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From: David Vrabel <david.vrabel@nutanix.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Gerd Hoffmann <kraxel@redhat.com>
Cc: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Zhao Liu <zhao1.liu@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH v2 1/4] hw/pci-bridge: Add generic PCIe switch upstream and downstream ports
Date: Tue, 8 Sep 2026 17:05:13 +0100	[thread overview]
Message-ID: <b20a4d64-1bae-4f11-8e18-1a8dbadda625@nutanix.com> (raw)
In-Reply-To: <20260908155223.164787-2-david.vrabel@nutanix.com>

On 08/09/2026 16:52, David Vrabel wrote:
> The TI XIO3130 PCIe switch is a vintage Gen1 device, so we add generic
> PCIe upstream and downstream port devices that are Gen6.
> 
> [...]
> 
> Instead of enhancing the existing switch and claiming it is more
> capable than the real hardware we add additional generic PCIe upstream
> and downstream port devices, which matches the existing generic PCIe
> root port device.

Hi Gerd,

These two new devices will require PCI Device IDs to be allocated. I 
have suggested (and used in this patch):

1b36:0015 QEMU PCIe Upstream Switch Port
1b36:0016 QEMU PCIe Downstream Switch Port

Matching the vendor ID and name with the existing QEMU PCIe Root Port 
(1b36:000c) device.

David



  reply	other threads:[~2026-09-08 16:06 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08 15:52 [PATCH v2 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology David Vrabel
2026-09-08 15:52 ` [PATCH v2 1/4] hw/pci-bridge: Add generic PCIe switch upstream and downstream ports David Vrabel
2026-09-08 16:05   ` David Vrabel [this message]
2026-09-09 15:14   ` Gerd Hoffmann
2026-09-08 15:52 ` [PATCH v2 2/4] hw/pci-bridge: Make speed and width for PCIe ports non-experimental David Vrabel
2026-09-08 15:52 ` [PATCH v2 3/4] hw/pci-bridge: Default the generic PCIe root port as Gen6 capable David Vrabel
2026-09-08 15:52 ` [PATCH v2 4/4] hw/pci: Ensure PCIe link speed/width is consistent between both ends David Vrabel

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