Re: [PATCH v3 1/5] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Wed, Sep 09, 2026 at 05:18:16PM +0530, Krishna Chaitanya Chundru wrote:
> Document the PCIe PHY found on the Qualcomm Nord platform.
> 
> Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple
> lane configurations using four PHY segments (A/B/C/D). The active
> topology is selected by firmware through a TCSR configuration
> register and may be configured as x16, x8+x8, x8+x4+x4, or
> x8+x4+x2+x2.
> 
> The binding describes the register regions, clocks, resets, power
> domains, regulators, PHY provider interface, clock provider interface,
> and the qcom,link-mode property used by the driver to discover the
> active lane configuration programmed by firmware.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
>  .../phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml        | 272 +++++++++++++++++++++
>  1 file changed, 272 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> new file mode 100644
> index 000000000000..624ad7e7d13e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> @@ -0,0 +1,272 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Nord QMP Quadfurcated PCIe multiple link-mode PHY
> +
> +maintainers:
> +  - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> +
> +description: |

Can we drop "|" like below?

@@ -9,7 +9,7 @@ title: Qualcomm Nord QMP Quadfurcated PCIe multiple link-mode PHY
 maintainers:
   - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

-description: |
+description:
   The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed
   of four PHY ports (A/B/C/D). The ports can be combined to support
   multiple lane topologies, including x16, x8+x8, x8+x4+x4 and
@@ -101,7 +101,7 @@ properties:
   vdda-pll-d-supply: true

   qcom,link-mode:
-    description: |
+    description:
       Reference to the TCSR syscon and the offset of the
       TCSR_PCIE_LINK_CONFIG_MODE register.
         0 (QMP_PCIE_NORD_MODE_X16)        — all ports ganged as x16
@@ -129,8 +129,8 @@ properties:

   "#phy-cells":
     const: 1
-    description: |
-      Selects the PHY instance by index:
+    description:
+      Selects the PHY instance by index.
         0 — port A (up to Gen5 x8; anchor in x16 mode)
         1 — port B (up to Gen5 x4)
         2 — port C (up to Gen5 x2)

Shawn