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From: Yao Zi <me@ziyao.cc>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Yixun Lan <dlan@kernel.org>, Alex Elder <elder@riscstar.com>,
	Inochi Amaoto <inochiama@outlook.com>,
	Haylen Chu <heylenay@4d2.org>
Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
	Yao Zi <me@ziyao.cc>
Subject: Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs
Date: Thu, 10 Sep 2026 13:31:30 +0000	[thread overview]
Message-ID: <aqKxMmgpFLE3CmQ8@pie> (raw)
In-Reply-To: <20260909-spacemit-pll-init-v1-4-b3065ad5a4ac@linux.spacemit.com>

On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote:
> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left
> running by firmware can have a zero prepare count, so this flag alone
> cannot prevent set_rate() from reprogramming a live PLL.

Would it be a better idea to simply turn off the PLL before reprogramming,
since protected by CLK_SET_RATE_GATE, re-programming never happens when
the PLL is required by downstream? This also seems to be simpler.

> Check the hardware state and reject set_rate() while either the enable
> or lock bit is set on K1 PLLs and K3 PLLAs. Propagate register read/write
> failures and reject rate requests with no table candidate. Callers must
> still move consumers away and stop the PLL before changing its rate.
> 
> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>

Best regards,
Yao Zi

WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <me@ziyao.cc>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Yixun Lan <dlan@kernel.org>, Alex Elder <elder@riscstar.com>,
	Inochi Amaoto <inochiama@outlook.com>,
	Haylen Chu <heylenay@4d2.org>
Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
	Yao Zi <me@ziyao.cc>
Subject: Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs
Date: Thu, 10 Sep 2026 13:31:30 +0000	[thread overview]
Message-ID: <aqKxMmgpFLE3CmQ8@pie> (raw)
In-Reply-To: <20260909-spacemit-pll-init-v1-4-b3065ad5a4ac@linux.spacemit.com>

On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote:
> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left
> running by firmware can have a zero prepare count, so this flag alone
> cannot prevent set_rate() from reprogramming a live PLL.

Would it be a better idea to simply turn off the PLL before reprogramming,
since protected by CLK_SET_RATE_GATE, re-programming never happens when
the PLL is required by downstream? This also seems to be simpler.

> Check the hardware state and reject set_rate() while either the enable
> or lock bit is set on K1 PLLs and K3 PLLAs. Propagate register read/write
> failures and reject rate requests with no table candidate. Callers must
> still move consumers away and stop the PLL before changing its rate.
> 
> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>

Best regards,
Yao Zi

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-09-10 13:32 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-09 14:07 [PATCH 0/5] clk: spacemit: preserve and safely synchronize firmware PLLs Troy Mitchell
2026-09-09 14:07 ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 1/5] clk: spacemit: derive PLL rates from hardware Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 2/5] clk: spacemit: make MIX rate selection consistent Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-10 13:01   ` Yao Zi
2026-09-10 13:01     ` Yao Zi
2026-09-10 14:19     ` Troy Mitchell
2026-09-10 14:19       ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 3/5] clk: spacemit: describe CPU clock dividers and shared PLL muxes Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:21   ` sashiko-bot
2026-09-10  3:23     ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:22   ` sashiko-bot
2026-09-10 13:31   ` Yao Zi [this message]
2026-09-10 13:31     ` Yao Zi
2026-09-11  2:02     ` Troy Mitchell
2026-09-11  2:02       ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 5/5] clk: spacemit: safely synchronize PLL parameters during init Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell

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