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From: Yao Zi <me@ziyao.cc>
To: "Troy Mitchell" <troy.mitchell@linux.spacemit.com>,
	"Yao Zi" <me@ziyao.cc>, "Stephen Boyd" <sboyd@kernel.org>,
	"Brian Masney" <bmasney+clk@redhat.com>,
	"Jerome Brunet" <jbrunet+clk@baylibre.com>,
	"Yixun Lan" <dlan@kernel.org>, "Alex Elder" <elder@riscstar.com>,
	"Inochi Amaoto" <inochiama@outlook.com>,
	"Haylen Chu" <heylenay@4d2.org>
Cc: <linux-clk@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<spacemit@lists.linux.dev>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs
Date: Fri, 11 Sep 2026 06:08:46 +0000	[thread overview]
Message-ID: <aqOa7jnonuXhUoy5@pie> (raw)
In-Reply-To: <DLC48RE9YAU6.1YO47FZILOUWJ@linux.spacemit.com>

On Fri, Sep 11, 2026 at 10:02:47AM +0800, Troy Mitchell wrote:
> On Thu Sep 10, 2026 at 9:31 PM +08, Yao Zi wrote:
> > On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote:
> >> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left
> >> running by firmware can have a zero prepare count, so this flag alone
> >> cannot prevent set_rate() from reprogramming a live PLL.
> >
> > Would it be a better idea to simply turn off the PLL before reprogramming,
> > since protected by CLK_SET_RATE_GATE, re-programming never happens when
> > the PLL is required by downstream? This also seems to be simpler.
> Then assigned-clock-rates on the PLL provider node?

Protecting PLL from rate-changing when it's enabled, and re-programming
the PLL to a recommended rate, are separate goals. This review comment
only focuses on the former (i.e. changes in this patch).

> I tested this
> on K3: .set_rate() was called during provider registration, with PLL3's
> prepare count still zero while the CPUs were running on it. Disabling
> PLL3 hung the board. CLK_SET_RATE_GATE therefore does not protect users
> that CCF has not yet accounted for.

I think it's caused by asynchronous probing. The APMU controller might
probe and register clocks after the PLL one, so the prepare/enable
counters of the PLLs might not match the reality during the gap.

> 
> -- 
> Troy Mitchell
> 

Best regards,
Yao Zi

WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <me@ziyao.cc>
To: "Troy Mitchell" <troy.mitchell@linux.spacemit.com>,
	"Yao Zi" <me@ziyao.cc>, "Stephen Boyd" <sboyd@kernel.org>,
	"Brian Masney" <bmasney+clk@redhat.com>,
	"Jerome Brunet" <jbrunet+clk@baylibre.com>,
	"Yixun Lan" <dlan@kernel.org>, "Alex Elder" <elder@riscstar.com>,
	"Inochi Amaoto" <inochiama@outlook.com>,
	"Haylen Chu" <heylenay@4d2.org>
Cc: <linux-clk@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<spacemit@lists.linux.dev>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs
Date: Fri, 11 Sep 2026 06:08:46 +0000	[thread overview]
Message-ID: <aqOa7jnonuXhUoy5@pie> (raw)
In-Reply-To: <DLC48RE9YAU6.1YO47FZILOUWJ@linux.spacemit.com>

On Fri, Sep 11, 2026 at 10:02:47AM +0800, Troy Mitchell wrote:
> On Thu Sep 10, 2026 at 9:31 PM +08, Yao Zi wrote:
> > On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote:
> >> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left
> >> running by firmware can have a zero prepare count, so this flag alone
> >> cannot prevent set_rate() from reprogramming a live PLL.
> >
> > Would it be a better idea to simply turn off the PLL before reprogramming,
> > since protected by CLK_SET_RATE_GATE, re-programming never happens when
> > the PLL is required by downstream? This also seems to be simpler.
> Then assigned-clock-rates on the PLL provider node?

Protecting PLL from rate-changing when it's enabled, and re-programming
the PLL to a recommended rate, are separate goals. This review comment
only focuses on the former (i.e. changes in this patch).

> I tested this
> on K3: .set_rate() was called during provider registration, with PLL3's
> prepare count still zero while the CPUs were running on it. Disabling
> PLL3 hung the board. CLK_SET_RATE_GATE therefore does not protect users
> that CCF has not yet accounted for.

I think it's caused by asynchronous probing. The APMU controller might
probe and register clocks after the PLL one, so the prepare/enable
counters of the PLLs might not match the reality during the gap.

> 
> -- 
> Troy Mitchell
> 

Best regards,
Yao Zi

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-09-11  6:09 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-09 14:07 [PATCH 0/5] clk: spacemit: preserve and safely synchronize firmware PLLs Troy Mitchell
2026-09-09 14:07 ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 1/5] clk: spacemit: derive PLL rates from hardware Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 2/5] clk: spacemit: make MIX rate selection consistent Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-10 13:01   ` Yao Zi
2026-09-10 13:01     ` Yao Zi
2026-09-10 14:19     ` Troy Mitchell
2026-09-10 14:19       ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 3/5] clk: spacemit: describe CPU clock dividers and shared PLL muxes Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:21   ` sashiko-bot
2026-09-10  3:23     ` Troy Mitchell
2026-09-09 14:07 ` [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell
2026-09-09 14:22   ` sashiko-bot
2026-09-10 13:31   ` Yao Zi
2026-09-10 13:31     ` Yao Zi
2026-09-11  2:02     ` Troy Mitchell
2026-09-11  2:02       ` Troy Mitchell
2026-09-11  6:08       ` Yao Zi [this message]
2026-09-11  6:08         ` Yao Zi
2026-09-09 14:07 ` [PATCH 5/5] clk: spacemit: safely synchronize PLL parameters during init Troy Mitchell
2026-09-09 14:07   ` Troy Mitchell

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