[PATCH 0/2] mtd: spi-nor: issi: add support for the IS25WX01G octal flash

[PATCH 0/2] mtd: spi-nor: issi: add support for the IS25WX01G octal flash

[Nuno Sá]

This series adds support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal
NOR flash.

The part is fully described by SFDP, so patch 2 only needs the flash ID
plus a small post_bfpt fixup:

 - The flash has no Status Register 2 and does not implement the 35h Read
   Configuration Register command, so the core's default assumption of a
   16-bit Write Status command does not hold and SNOR_F_HAS_16BIT_SR has
   to be cleared.

 - Its BFPT Quad Enable Requirement field carries a reserved value, which
   makes spi_nor_parse_bfpt() keep the manufacturer default quad enable
   method. As this is an octal-only part with no quad mode at all, the
   quad_enable hook is cleared.

Patch 1 is a prerequisite: the 4BAIT parser did not pick up the 1-1-8 and
1-8-8 page program opcodes, which we need since the IS25WX01G is beyond the
3-byte address range.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
Nuno Sá (2):
      mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 page programs from 4BAIT
      mtd: spi-nor: issi: Add support for is25wx01g

 drivers/mtd/spi-nor/issi.c | 27 +++++++++++++++++++++++++++
 drivers/mtd/spi-nor/sfdp.c | 10 ++++++++++
 2 files changed, 37 insertions(+)
---
base-commit: 700bf34058ca7cd792236b1ba5caad3770d66208
change-id: 20260911-mtd-spi-nor-new-issi-chip-ef3881bab60e
--

Thanks!
- Nuno Sá


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[PATCH 1/2] mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 page programs from 4BAIT

[Nuno Sá]

Commit af2792abd455 ("mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8
protocol from SFDP") taught the core to discover octal read support
from BFPT, but the 4-Byte Address Instruction Table parser was never
extended accordingly.

Parse the 1-1-8 and 1-8-8 page program bits of 4BAIT DWORD1 and set the
corresponding 4-byte opcodes, so that octal writes stay available once
the flash switches to the 4-byte address instruction set.

This is in preparation of adding support for the ISSI IS25WX01G, a
1 Gbit octal flash which is beyond the 3-byte address range and
advertises 4-byte 1-1-8 and 1-8-8 page program instructions.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
 drivers/mtd/spi-nor/sfdp.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index c21a6953db96..8e3989184435 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -1081,6 +1081,8 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
 		{ SNOR_HWCAPS_PP,		BIT(6) },
 		{ SNOR_HWCAPS_PP_1_1_4,		BIT(7) },
 		{ SNOR_HWCAPS_PP_1_4_4,		BIT(8) },
+		{ SNOR_HWCAPS_PP_1_1_8,		BIT(23) },
+		{ SNOR_HWCAPS_PP_1_8_8,		BIT(24) },
 	};
 	static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
 		{ 0u /* not used */,		BIT(9) },
@@ -1207,6 +1209,14 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
 		spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_4_4],
 					SPINOR_OP_PP_1_4_4_4B,
 					SNOR_PROTO_1_4_4);
+	if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_8)
+		spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_1_8],
+					SPINOR_OP_PP_1_1_8_4B,
+					SNOR_PROTO_1_1_8);
+	if (pp_hwcaps & SNOR_HWCAPS_PP_1_8_8)
+		spi_nor_set_pp_settings(&params_pp[SNOR_CMD_PP_1_8_8],
+					SPINOR_OP_PP_1_8_8_4B,
+					SNOR_PROTO_1_8_8);
 
 	for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
 		if (erase_mask & BIT(i))

-- 
2.55.0


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[PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g

[Nuno Sá]

Add support for the ISSI IS25WX01G, a 1 Gbit octal NOR flash. The part
is fully described by SFDP, so only the flash ID and two BFPT fixups are
needed.

The flash has no Status Register 2 and does not implement the 35h Read
Configuration Register command, so the default assumption of a 16-bit
Write Status command does not hold. Additionally, its BFPT Quad Enable
Requirement field carries a reserved value, which makes
spi_nor_parse_bfpt() keep the manufacturer default quad enable method;
clear it, since this is an octal-only part with no quad mode at all.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
 drivers/mtd/spi-nor/issi.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 2f057d731df2..aac9d19b90fc 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -29,6 +29,29 @@ static const struct spi_nor_fixups is25lp256_fixups = {
 	.post_bfpt = is25lp256_post_bfpt_fixups,
 };
 
+static int is25wx01g_post_bfpt_fixups(struct spi_nor *nor,
+				      const struct sfdp_parameter_header *bfpt_header,
+				      const struct sfdp_bfpt *bfpt)
+{
+	/*
+	 * There is no Status Register 2 and no 35h command. And WRITE STATUS
+	 * REGISTER takes a single data byte.
+	 */
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+
+	/*
+	 * The BFPT Quad Enable Requirement field is set to a reserved value, so
+	 * spi_nor_parse_bfpt() leaves the quad enable method at its default.
+	 * Make sure we disable it as there is no quad mode anyway.
+	 */
+	nor->params->quad_enable = NULL;
+	return 0;
+}
+
+static const struct spi_nor_fixups is25wx01g_fixups = {
+	.post_bfpt = is25wx01g_post_bfpt_fixups,
+};
+
 static int pm25lv_nor_late_init(struct spi_nor *nor)
 {
 	struct spi_nor_erase_map *map = &nor->params->erase_map;
@@ -120,6 +143,10 @@ static const struct flash_info issi_nor_parts[] = {
 		.id = SNOR_ID(0x9d, 0x70, 0x19),
 		.name = "is25wp256",
 		.flags = SPI_NOR_QUAD_PP,
+	}, {
+		.id = SNOR_ID(0x9d, 0x5b, 0x1b),
+		.name = "is25wx01g",
+		.fixups = &is25wx01g_fixups,
 	}
 };
 

-- 
2.55.0


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Re: [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch introduces multiple build failures due to an incomplete forward-port from an older kernel version. It references non-existent struct fields, uses an undeclared flag, and attempts an outdated method to disable 16-bit status register writes.
--

commit 2a2f93cf391e237e4b5b711cef68cc225e2bc2fe
Author: Nuno Sá <nuno.sa@analog.com>

mtd: spi-nor: issi: Add support for is25wx01g

This patch adds support for the ISSI IS25WX01G 1 Gbit octal NOR flash. It
relies on SFDP and provides BFPT fixups to handle the lack of a 35h command
and to disable the quad enable method.

> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 2f057d731df2a..aac9d19b90fcf 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -29,6 +29,29 @@ static const struct spi_nor_fixups is25lp256_fixups = {
>  	.post_bfpt = is25lp256_post_bfpt_fixups,
>  };
>  
> +static int is25wx01g_post_bfpt_fixups(struct spi_nor *nor,
> +				      const struct sfdp_parameter_header *bfpt_header,
> +				      const struct sfdp_bfpt *bfpt)
> +{
> +	/*
> +	 * There is no Status Register 2 and no 35h command. And WRITE STATUS
> +	 * REGISTER takes a single data byte.
> +	 */
> +	nor->flags &= ~SNOR_F_HAS_16BIT_SR;

[Severity: Low]
Does this code compile on the target tree? struct spi_nor does not appear
to have a flags member in the current API, and SNOR_F_HAS_16BIT_SR seems
to be undeclared.

> +
> +	/*
> +	 * The BFPT Quad Enable Requirement field is set to a reserved value, so
> +	 * spi_nor_parse_bfpt() leaves the quad enable method at its default.
> +	 * Make sure we disable it as there is no quad mode anyway.
> +	 */
> +	nor->params->quad_enable = NULL;
> +	return 0;
> +}
> +
> +static const struct spi_nor_fixups is25wx01g_fixups = {
> +	.post_bfpt = is25wx01g_post_bfpt_fixups,
> +};
> +

[ ... ]

> @@ -120,6 +143,10 @@ static const struct flash_info issi_nor_parts[] = {
>  		.id = SNOR_ID(0x9d, 0x70, 0x19),
>  		.name = "is25wp256",
>  		.flags = SPI_NOR_QUAD_PP,
> +	}, {
> +		.id = SNOR_ID(0x9d, 0x5b, 0x1b),
> +		.name = "is25wx01g",
> +		.fixups = &is25wx01g_fixups,

[Severity: Low]
Does struct flash_info have a fixups member in the current framework?
It looks like fixups might need to be registered via struct
spi_nor_manufacturer and its fixups array instead.

>  	}
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-mtd-spi-nor-new-issi-chip-v1-0-c54615f8c30f@analog.com?part=2

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Re: [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g

[Nuno Sá]

On Fri, Sep 11, 2026 at 03:44:12PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The patch introduces multiple build failures due to an incomplete forward-port from an older kernel version. It references non-existent struct fields, uses an undeclared flag, and attempts an outdated method to disable 16-bit status register writes.
> --
> 
> commit 2a2f93cf391e237e4b5b711cef68cc225e2bc2fe
> Author: Nuno Sá <nuno.sa@analog.com>
> 
> mtd: spi-nor: issi: Add support for is25wx01g
> 
> This patch adds support for the ISSI IS25WX01G 1 Gbit octal NOR flash. It
> relies on SFDP and provides BFPT fixups to handle the lack of a 35h command
> and to disable the quad enable method.
> 
> > diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> > index 2f057d731df2a..aac9d19b90fcf 100644
> > --- a/drivers/mtd/spi-nor/issi.c
> > +++ b/drivers/mtd/spi-nor/issi.c
> > @@ -29,6 +29,29 @@ static const struct spi_nor_fixups is25lp256_fixups = {
> >  	.post_bfpt = is25lp256_post_bfpt_fixups,
> >  };
> >  
> > +static int is25wx01g_post_bfpt_fixups(struct spi_nor *nor,
> > +				      const struct sfdp_parameter_header *bfpt_header,
> > +				      const struct sfdp_bfpt *bfpt)
> > +{
> > +	/*
> > +	 * There is no Status Register 2 and no 35h command. And WRITE STATUS
> > +	 * REGISTER takes a single data byte.
> > +	 */
> > +	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> 
> [Severity: Low]
> Does this code compile on the target tree? struct spi_nor does not appear
> to have a flags member in the current API, and SNOR_F_HAS_16BIT_SR seems
> to be undeclared.

Ok! It seems I was over confident and it seems things changes in
spi-nor/next! Will fix it and resend!!

- Nuno Sá
> 
> > +
> > +	/*
> > +	 * The BFPT Quad Enable Requirement field is set to a reserved value, so
> > +	 * spi_nor_parse_bfpt() leaves the quad enable method at its default.
> > +	 * Make sure we disable it as there is no quad mode anyway.
> > +	 */
> > +	nor->params->quad_enable = NULL;
> > +	return 0;
> > +}
> > +
> > +static const struct spi_nor_fixups is25wx01g_fixups = {
> > +	.post_bfpt = is25wx01g_post_bfpt_fixups,
> > +};
> > +
> 
> [ ... ]
> 
> > @@ -120,6 +143,10 @@ static const struct flash_info issi_nor_parts[] = {
> >  		.id = SNOR_ID(0x9d, 0x70, 0x19),
> >  		.name = "is25wp256",
> >  		.flags = SPI_NOR_QUAD_PP,
> > +	}, {
> > +		.id = SNOR_ID(0x9d, 0x5b, 0x1b),
> > +		.name = "is25wx01g",
> > +		.fixups = &is25wx01g_fixups,
> 
> [Severity: Low]
> Does struct flash_info have a fixups member in the current framework?
> It looks like fixups might need to be registered via struct
> spi_nor_manufacturer and its fixups array instead.
> 
> >  	}
> >  };
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260911-mtd-spi-nor-new-issi-chip-v1-0-c54615f8c30f@analog.com?part=2

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