From: Max Chou <max.chou@sifive.com>
To: Chao Liu <chao.liu@processmission.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
richard.henderson@linaro.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 3/6] tests/tcg/riscv64: Add vector masked fault-only-first PMP test
Date: Tue, 15 Sep 2026 17:34:58 +0800 [thread overview]
Message-ID: <aqkQqxqtRc0ypdbd@sifive.com> (raw)
In-Reply-To: <aqOSwMCX5UsGJA79@MacBook-Pro-4.local>
On 2026-09-11 13:49, Chao Liu wrote:
> Hi Max,
>
> On Wed, Sep 09, 2026 at 04:41:50PM +0800, Max Chou wrote:
> > Add a bare-metal test for masked vector fault-only-first loads across
> > locked NA4 PMP regions inside one page. The test covers masked-off
> > elements, a faulting active element 0, and later active faults that
> > shorten vl.
> >
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> > tests/tcg/riscv64/Makefile.softmmu-target | 13 ++
> > tests/tcg/riscv64/rvv-ldst.inc | 91 ++++++++
> > tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S | 259 ++++++++++++++++++++++
> > 3 files changed, 363 insertions(+)
> > create mode 100644 tests/tcg/riscv64/rvv-ldst.inc
> > create mode 100644 tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S
> >
> > diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
> > index f2c75abd57a..0fdf242f735 100644
> > --- a/tests/tcg/riscv64/Makefile.softmmu-target
> > +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> > @@ -85,5 +85,18 @@ run-test-vle32ff: test-vle32ff
> > $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true $(QEMU_OPTS)$<)
> > test-vle32ff: CFLAGS += -march=rv64gcv
> >
> > +RVV_LDST_MARCH = -march=rv64gcv
> > +RVV_LDST_TESTS = test-rvv-ldst-ff-pmp
> > +CLEANFILES += $(RVV_LDST_TESTS)
> > +
> > +$(RVV_LDST_TESTS): %: %.S rvv-ldst.inc $(LINK_SCRIPT)
> > + $(CC) $(CFLAGS) $(RVV_LDST_MARCH) $< -Wa,--noexecstack -c -o $@.o
> > + $(LD) $(LDFLAGS) $@.o -o $@
> > +
> > +EXTRA_RUNS += run-test-rvv-ldst-ff-pmp
> > +
> > +run-test-rvv-ldst-ff-pmp: test-rvv-ldst-ff-pmp
> > + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)vlen=128$(comma)elen=64$(comma)vext_spec=v1.0$(comma)rvv_ta_all_1s=true$(comma)rvv_ma_all_1s=true $(QEMU_OPTS)$<)
> > +
> Just a heads-up, TCG tests are moving to Meson build, so this needs to be
> based on:
>
> https://lore.kernel.org/qemu-devel/20260818192309.22169-1-pierrick.bouvier@oss.qualcomm.com/
>
> Thanks,
> Chao
Hi Chao,
Thanks for the information. Daniel also shared the same information to
me.I will send v2 for this TCG test build flow.
Thanks,
rnax
next prev parent reply other threads:[~2026-09-15 9:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 8:41 [PATCH 0/6] tests/tcg/riscv64: Add system mode rvv ld/st tests Max Chou
2026-09-09 8:41 ` [PATCH 1/6] target/riscv: Match PMP entries lying inside the checked range Max Chou
2026-09-09 8:41 ` [PATCH 2/6] target/riscv: rvv: Probe unit-stride accesses by the first element Max Chou
2026-09-09 8:41 ` [PATCH 3/6] tests/tcg/riscv64: Add vector masked fault-only-first PMP test Max Chou
2026-09-11 5:49 ` Chao Liu
2026-09-15 9:34 ` Max Chou [this message]
2026-09-09 8:41 ` [PATCH 4/6] tests/tcg/riscv64: Add vector unit-stride " Max Chou
2026-09-09 8:41 ` [PATCH 5/6] tests/tcg/riscv64: Add vector fault-only-first page probe test Max Chou
2026-09-09 8:41 ` [PATCH 6/6] tests/tcg/riscv64: Add vector segment PMP region spanning test Max Chou
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