Re: [PATCH v5 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board

From: Aurelien Jarno <aurelien@aurel32.net>
To: linux-kernel@vger.kernel.org, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: Aurelien Jarno <aurelien@aurel32.net>,
	Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	"open list:RISC-V SPACEMIT SoC Support"
	<linux-riscv@lists.infradead.org>,
	"open list:RISC-V SPACEMIT SoC Support"
	<spacemit@lists.linux.dev>
Subject: Re: [PATCH v5 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board
Date: Mon, 28 Sep 2026 23:10:44 +0200	[thread overview]
Message-ID: <arrX1KoS-ghNhTve@aurel32.net> (raw)
In-Reply-To: <20260928210216.7DCB41F000FF@smtp.kernel.org>

Hi,

On 2026-09-28 21:02, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] dt-bindings: missing required phys properties in usb3b and usb3c nodes
> --
> 
> commit 89b216baa5d6be0e4a7be800d568bba679087495
> Author: Aurelien Jarno <aurelien@aurel32.net>
> 
> riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board
> 
> This commit adds the USB3 controller nodes (B and C) to the SpacemiT K3 SoC
> device tree. It also enables them and adds the corresponding USB2 PHY nodes
> for the Pico-ITX board.
> 
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > index 1af47b7f1c8af..cf1c8b572c86b 100644
> > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> 
> [ ... ]
> 
> > @@ -441,6 +441,66 @@ soc: soc {
> >  		dma-noncoherent;
> >  		ranges;
> >  
> > +		usb3b: usb@81400000 {
> > +			compatible = "spacemit,k3-dwc3";
> > +			reg = <0x0 0x81400000 0x0 0x10000>;
> > +			interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
> 
> [Severity: Low]
> Does omitting the phys and phy-names properties here cause a devicetree
> validation regression?

No it doesn't, I checked that before the submitting the patch.

> The SoC devicetree fails dtbs_check validation against the binding schema
> (spacemit,k1-dwc3.yaml), which unconditionally requires the phys and
> phy-names properties.

No, as explained in patch 1, dtbs_check only check enabled nodes, so this is fine.

> Should this node define its hardwired connection to usb3b_u2phy via the
> phys and phy-names properties here, instead of omitting these SoC-internal
> hardwired connections from k3.dtsi and forcing downstream boards to
> redundantly define the SoC hardware topology?
> 
> > +			interrupt-parent = <&saplic>;
> > +			clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>;

No, this has already been discussed as part of the v3 review:
https://lore.kernel.org/spacemit/aomWjQGk_p84pPD2@inochi.infowork/

> [ ... ]
> 
> > +		usb3c: usb@81700000 {
> > +			compatible = "spacemit,k3-dwc3";
> > +			reg = <0x0 0x81700000 0x0 0x10000>;
> > +			interrupts = <148 IRQ_TYPE_LEVEL_HIGH>;
> 
> [Severity: Low]
> Similarly, does this node also need to define its hardwired connection to
> usb3c_u2phy via the phys and phy-names properties to avoid the same schema
> validation regression?
> 
> > +			interrupt-parent = <&saplic>;
> > +			clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>;

Ditto.

Regards
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv