Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream

Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream

[nick]

(Resent in plain text; the list rejected the HTML copy.)

On 2026-10-13 02:24, nick@detello.com wrote:
> Hi Chen, Inochi,
> 
> I have the SG2000 display path working on v7.2 with two small kernel
> patches: DISP, DSI MAC and D-PHY driven by a new DRM host driver,
> through the in-tree lontium-lt8912b bridge, to HDMI at 1280x720@60
> over
> two lanes. It's tested on both cores (RISC-V and ARM) on the Nix Badge
> 2.0,
> a custom board around the Milk-V Duo S module: console on HDMI and a
> 15 fps framebuffer animation.
> 
> Two questions before I prepare the submission:
> 
> 1. Is either of you, or anyone you know of, working on the VO/DSI
> block
>    for cv18xx/SG2000? I would rather join than duplicate.
> 2. Any preference on where the host driver lives
>    (drivers/gpu/drm/sophgo/?) and on compatibles before I write the
>    bindings? The branch uses sophgo,sg2000-dsi and a
>    sophgo,sg2000-vip-sys syscon, and adds one clock ID
>    (CLK_DSI_SYNTH_SRC) to the cv1800 binding header.
> 
> Code, as one reviewable PR against the board's NixOS repo:
>   https://github.com/NixVegas/BadgeOS/pull/8
>   Driver:  pkgs/video/sophgo-dsi/src/sophgo-dsi.c (~1,500 lines,
>            register provenance from sophgo/osdrv cited in place)
>   Patches: pkgs/kernel/patches/ (clk-cv18xx: poll DISPPLL's real lock
>            bit and expose the DSI source gate; lt8912b: do the bridge
>            setup in pre_enable, between the host's LP-11 and HS)
>   DT:      pkgs/firmware/dts/sg2000-milkv-duo-s-common.dtsi
> 
> Planned order: the clk fix; display nodes for sg2000.dtsi and for the
> Duo S DTS Joshua Milas's series added in July; the DSI host as an RFC
> to dri-devel; then the lt8912b change, which as written is specific to
> this host (fixed HDMI mode, LVDS and PM paths dropped) and will be
> rebased on Maxime's atomic-callback conversion on drm-misc-next before
> it goes anywhere. Known gaps before the RFC: fixed mode (no EDID, no
> hot-plug; HPD goes to the bridge on this board), no vblank interrupt,
> and register sequences reproduced from the vendor driver rather than
> modelled.
> 
> Happy to share a video, serial logs or register traces. The driver was
> developed with Claude Code assistance; I have read and tested every
> line and will carry the review.
> 
> Thanks,
> Nick DeTello

Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream

[Chen Wang]

Adding inochi's gmail address, which is the email address he currently uses.

Inochi, could you please help reply Nick on this?

Thanks,

Chen

On 10/13/2026 8:49 PM, nick@detello.com wrote:
> (Resent in plain text; the list rejected the HTML copy.)
>
> On 2026-10-13 02:24, nick@detello.com wrote:
>> Hi Chen, Inochi,
>>
>> I have the SG2000 display path working on v7.2 with two small kernel
>> patches: DISP, DSI MAC and D-PHY driven by a new DRM host driver,
>> through the in-tree lontium-lt8912b bridge, to HDMI at 1280x720@60
>> over
>> two lanes. It's tested on both cores (RISC-V and ARM) on the Nix Badge
>> 2.0,
>> a custom board around the Milk-V Duo S module: console on HDMI and a
>> 15 fps framebuffer animation.
>>
>> Two questions before I prepare the submission:
>>
>> 1. Is either of you, or anyone you know of, working on the VO/DSI
>> block
>>    for cv18xx/SG2000? I would rather join than duplicate.
>> 2. Any preference on where the host driver lives
>>    (drivers/gpu/drm/sophgo/?) and on compatibles before I write the
>>    bindings? The branch uses sophgo,sg2000-dsi and a
>>    sophgo,sg2000-vip-sys syscon, and adds one clock ID
>>    (CLK_DSI_SYNTH_SRC) to the cv1800 binding header.
>>
>> Code, as one reviewable PR against the board's NixOS repo:
>>   https://github.com/NixVegas/BadgeOS/pull/8
>>   Driver:  pkgs/video/sophgo-dsi/src/sophgo-dsi.c (~1,500 lines,
>>            register provenance from sophgo/osdrv cited in place)
>>   Patches: pkgs/kernel/patches/ (clk-cv18xx: poll DISPPLL's real lock
>>            bit and expose the DSI source gate; lt8912b: do the bridge
>>            setup in pre_enable, between the host's LP-11 and HS)
>>   DT:      pkgs/firmware/dts/sg2000-milkv-duo-s-common.dtsi
>>
>> Planned order: the clk fix; display nodes for sg2000.dtsi and for the
>> Duo S DTS Joshua Milas's series added in July; the DSI host as an RFC
>> to dri-devel; then the lt8912b change, which as written is specific to
>> this host (fixed HDMI mode, LVDS and PM paths dropped) and will be
>> rebased on Maxime's atomic-callback conversion on drm-misc-next before
>> it goes anywhere. Known gaps before the RFC: fixed mode (no EDID, no
>> hot-plug; HPD goes to the bridge on this board), no vblank interrupt,
>> and register sequences reproduced from the vendor driver rather than
>> modelled.
>>
>> Happy to share a video, serial logs or register traces. The driver was
>> developed with Claude Code assistance; I have read and tested every
>> line and will carry the review.
>>
>> Thanks,
>> Nick DeTello

Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream

[Inochi Amaoto]

On Wed, Oct 14, 2026 at 10:43:12AM +0800, Chen Wang wrote:
> Adding inochi's gmail address, which is the email address he currently uses.
> 
> Inochi, could you please help reply Nick on this?
> 
> Thanks,
> 
> Chen
> 
> On 10/13/2026 8:49 PM, nick@detello.com wrote:
> > (Resent in plain text; the list rejected the HTML copy.)
> > 
> > On 2026-10-13 02:24, nick@detello.com wrote:
> > > Hi Chen, Inochi,
> > > 
> > > I have the SG2000 display path working on v7.2 with two small kernel
> > > patches: DISP, DSI MAC and D-PHY driven by a new DRM host driver,
> > > through the in-tree lontium-lt8912b bridge, to HDMI at 1280x720@60
> > > over
> > > two lanes. It's tested on both cores (RISC-V and ARM) on the Nix Badge
> > > 2.0,
> > > a custom board around the Milk-V Duo S module: console on HDMI and a
> > > 15 fps framebuffer animation.
> > > 
> > > Two questions before I prepare the submission:
> > > 
> > > 1. Is either of you, or anyone you know of, working on the VO/DSI
> > > block
> > >    for cv18xx/SG2000? I would rather join than duplicate.

IIRC, there is no other ones, maybe someone has done similar, but they
are not opened and I am not sure why.
I already had a plan and finished bindings, but I am in bad health so
I have limit time on it (and this is why I may have a bad respond time
in LKML). The driver is a hard thing as I need to cover some SoCs with
simliar design.

> > > 2. Any preference on where the host driver lives
> > >    (drivers/gpu/drm/sophgo/?) and on compatibles before I write the
> > >    bindings? The branch uses sophgo,sg2000-dsi and a
> > >    sophgo,sg2000-vip-sys syscon, and adds one clock ID
> > >    (CLK_DSI_SYNTH_SRC) to the cv1800 binding header.
> > > 
> > > Code, as one reviewable PR against the board's NixOS repo:
> > >   https://github.com/NixVegas/BadgeOS/pull/8
> > >   Driver:  pkgs/video/sophgo-dsi/src/sophgo-dsi.c (~1,500 lines,
> > >            register provenance from sophgo/osdrv cited in place)
> > >   Patches: pkgs/kernel/patches/ (clk-cv18xx: poll DISPPLL's real lock
> > >            bit and expose the DSI source gate; lt8912b: do the bridge
> > >            setup in pre_enable, between the host's LP-11 and HS)
> > >   DT:      pkgs/firmware/dts/sg2000-milkv-duo-s-common.dtsi
> > > 

I have checked the PR and find it is very simple. I do not think it
reflect the real hardware, IIRC it will be divided into several parts with 
phy/dsi/vpu/isp/pinctrl/clk. And your driver only contains some of them.
If you take these thing with a whole view, you will see they are things
that work together.

I also disagree with the clk data fix. Although it should expose a new
div2 clock, the default configuration of DISP PLL should not be changed,
but If I did make a mistake, please send this patch directly and I am
happy with that. ^^.

Sorry for no detailed information, The detailed datasheet is not opened,
they are only opened to the trusted one, So I can not share you with the
detailed design and how the device is co-worked. But at least I can told
you, you may need pinctrl and clock-frequency properties to all display
node.

Regards,
Inochi

> > > Planned order: the clk fix; display nodes for sg2000.dtsi and for the
> > > Duo S DTS Joshua Milas's series added in July; the DSI host as an RFC
> > > to dri-devel; then the lt8912b change, which as written is specific to
> > > this host (fixed HDMI mode, LVDS and PM paths dropped) and will be
> > > rebased on Maxime's atomic-callback conversion on drm-misc-next before
> > > it goes anywhere. Known gaps before the RFC: fixed mode (no EDID, no
> > > hot-plug; HPD goes to the bridge on this board), no vblank interrupt,
> > > and register sequences reproduced from the vendor driver rather than
> > > modelled.
> > > 
> > > Happy to share a video, serial logs or register traces. The driver was
> > > developed with Claude Code assistance; I have read and tested every
> > > line and will carry the review.
> > > 
> > > Thanks,
> > > Nick DeTello

Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream

[nick]

Chen, thanks for the forward.

On 2026-10-13 23:06, Inochi Amaoto wrote:
> I already had a plan and finished bindings, [...] The driver is a
> hard thing as I need to cover some SoCs with simliar design.

Thanks for replying, and sorry to hear you are unwell. Would you be
willing to post your bindings, even as an RFC or an unfinished branch?
I will drop my own compatibles, write the drivers against your
bindings one block at a time, and handle the respins of what I send.
I'll start by submitting the independent clk patches.

I can test your patches on an SG2000 board with an LT8912B (RISC-V
and ARM) and, once it arrives, an SG2002 MaixCAM with a native DSI
panel, and reply with Tested-by. If the design needs coverage on other
variants, I can add those boards to my testing.

> I have checked the PR and find it is very simple. I do not think it
> reflect the real hardware, IIRC it will be divided into several parts
> with phy/dsi/vpu/isp/pinctrl/clk.

Agreed. I wrote it for one board and it does not model that split:
one file covers the display engine, the DSI controller and the D-PHY,
and takes its resets and clock bits from the VIP syscon. I would
rather build your design than a second one. Thanks for the pointers
on pinctrl and clock-frequency.

> I also disagree with the clk data fix. Although it should expose a
> new div2 clock, the default configuration of DISP PLL should not be
> changed, but If I did make a mistake, please send this patch directly
> and I am happy with that.

I will send it as you suggest, in two independent pieces. The first
exposes the DSI synthesizer source gate and reports its half or full
MIPIMPLL rate; it may not be the div2 clock you mean, so its commit
message will say exactly what it models. The second is a small RFC
that only moves the DISPPLL lock poll from bit 2 to bit 18 (the SG2000
TRM v1.0 table labels 18 lock and 2 updating). It leaves the PLL
programming unchanged, drops the 0 Hz-until-locked part of the PR, and
comes with results from testing that change alone. If you would rather
keep bit 2, I'll drop it.

Thanks,
Nick DeTello