* [PATCH v3 01/18] hmp: don't crash on invalid register
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 02/18] gdbstub: fix next register base after register gaps Marc-André Lureau
` (17 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
When printing an invalid/denied register, QEMU crashes with:
ERROR:include/qemu/bswap.h:488:ldn_le_p: code should not be reached
(ex: "p $sireg" when siselect=0 on riscv)
Return false instead.
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
monitor/hmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/monitor/hmp.c b/monitor/hmp.c
index 7b80d8480055..e97e0a9ff0d7 100644
--- a/monitor/hmp.c
+++ b/monitor/hmp.c
@@ -424,7 +424,7 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t *pval, const char *name)
buf = g_byte_array_new();
reg_size = gdb_read_register(cs, buf, reg->gdb_reg);
- if (reg_size > sizeof(*pval)) {
+ if (reg_size == 0 || reg_size > sizeof(*pval)) {
return false;
}
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 02/18] gdbstub: fix next register base after register gaps
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 01/18] hmp: don't crash on invalid register Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 03/18] gdbstub: set feature->base_reg for dynamic features Marc-André Lureau
` (16 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Commit b3e88abb200c ("gdbstub: Consider GDBFeature::base_reg in
gdb_register_coprocessor()") identified that register numbers may
have gaps. We also need to adjust the next base_reg correctly
to avoid overlapping registers. Rename the field to be more
explicit about its usage.
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
gdbstub/gdbstub.c | 13 ++++++-------
include/hw/core/cpu.h | 5 +++--
target/arm/gdbstub.c | 8 +++++---
target/arm/gdbstub64.c | 10 ++++++----
target/ppc/gdbstub.c | 2 +-
target/riscv/gdbstub.c | 9 ++++++---
target/xtensa/cpu.c | 2 +-
7 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 0a328b0dd488..0ce871d74929 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -605,13 +605,13 @@ void gdb_init_cpu(CPUState *cpu)
gdb_register_feature(cpu, 0,
cc->gdb_read_register, cc->gdb_write_register,
feature);
- cpu->gdb_num_regs = cpu->gdb_num_g_regs = feature->num_regs;
+ cpu->gdb_next_base_reg = cpu->gdb_num_g_regs = feature->num_regs;
} else {
- cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
+ cpu->gdb_next_base_reg = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
}
trace_gdbxml_init_cpu(object_get_typename(OBJECT(cpu)), cpu->cpu_index,
- cpu->gdb_num_regs, cpu->gdb_num_g_regs,
+ cpu->gdb_next_base_reg, cpu->gdb_num_g_regs,
cc->gdb_num_core_regs);
}
@@ -621,7 +621,7 @@ void gdb_register_coprocessor(CPUState *cpu,
{
GDBRegisterState *s;
guint i;
- int base_reg = cpu->gdb_num_regs;
+ int base_reg = cpu->gdb_next_base_reg;
for (i = 0; i < cpu->gdb_regs->len; i++) {
/* Check for duplicates. */
@@ -639,7 +639,7 @@ void gdb_register_coprocessor(CPUState *cpu,
gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature);
/* Add to end of list. */
- cpu->gdb_num_regs += feature->num_regs;
+ cpu->gdb_next_base_reg = base_reg + feature->num_regs;
}
void gdb_unregister_coprocessor_all(CPUState *cpu)
@@ -651,7 +651,7 @@ void gdb_unregister_coprocessor_all(CPUState *cpu)
g_array_free(cpu->gdb_regs, true);
cpu->gdb_regs = NULL;
- cpu->gdb_num_regs = 0;
+ cpu->gdb_next_base_reg = 0;
cpu->gdb_num_g_regs = 0;
}
@@ -2522,4 +2522,3 @@ void gdb_create_default_process(GDBState *s)
process->attached = false;
process->target_xml = NULL;
}
-
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 456154df6f69..04e0088ed5b6 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -455,7 +455,8 @@ struct qemu_work_item;
* @as: Pointer to the first AddressSpace, for the convenience of targets which
* only have a single AddressSpace
* @gdb_regs: Additional GDB registers.
- * @gdb_num_regs: Number of total registers accessible to GDB.
+ * @gdb_next_base_reg: Next register number after registered GDB features,
+ * including numbering gaps and internal registers.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
* @node: QTAILQ of CPUs sharing TB cache.
* @opaque: User data.
@@ -529,7 +530,7 @@ struct CPUState {
struct CPUJumpCache *tb_jmp_cache;
GArray *gdb_regs;
- int gdb_num_regs;
+ int gdb_next_base_reg;
int gdb_num_g_regs;
QTAILQ_ENTRY(CPUState) node;
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index d6e29c4cf467..e5cbe4d951ef 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -555,19 +555,21 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
gdb_find_static_feature("arm-m-profile-mve.xml"));
}
+ GDBFeature *feature =
+ arm_gen_dynamic_sysreg_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
- arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs));
+ feature);
#ifdef CONFIG_TCG
if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
- arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs));
+ arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_next_base_reg));
#ifndef CONFIG_USER_ONLY
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
gdb_register_coprocessor(cs,
arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
- arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs));
+ arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_next_base_reg));
}
#endif
}
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 0c3e5b30bd6a..cf5b95b54641 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -885,7 +885,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
CPUState *cs = CPU(cpu);
if (isar_feature_aa64_sve(&cpu->isar) ||
isar_feature_aa64_sme(&cpu->isar)) {
- GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);
+ GDBFeature *feature =
+ arm_gen_dynamic_svereg_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
aarch64_gdb_set_sve_reg, feature);
} else {
@@ -896,7 +897,7 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
if (isar_feature_aa64_sme(&cpu->isar)) {
GDBFeature *sme_feature =
- arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs);
+ arm_gen_dynamic_smereg_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,
aarch64_gdb_set_sme_reg, sme_feature);
if (isar_feature_aa64_sme2(&cpu->isar)) {
@@ -927,7 +928,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
#endif
/* All AArch64 CPUs have at least TPIDR */
+ GDBFeature *tls_feature =
+ arm_gen_dynamic_tls_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg,
- aarch64_gdb_set_tls_reg,
- arm_gen_dynamic_tls_feature(cs, cs->gdb_num_regs));
+ aarch64_gdb_set_tls_reg, tls_feature);
}
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 4d622c5cad59..ec25c541c685 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -206,7 +206,7 @@ static void gdb_gen_spr_feature(CPUState *cs)
gdb_feature_builder_init(&builder, &pcc->gdb_spr,
"org.qemu.power.spr", "power-spr.xml",
- cs->gdb_num_regs);
+ cs->gdb_next_base_reg);
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
ppc_spr_t *spr = &env->spr_cb[i];
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 9abbf5bcdf0e..f279f4ab2461 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -348,9 +348,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_find_static_feature("riscv-32bit-fpu.xml"));
}
if (cpu->cfg.ext_zve32x) {
+ GDBFeature *feature =
+ ricsv_gen_dynamic_vector_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
- riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs));
+ riscv_gdb_set_vector, feature);
}
#ifdef CONFIG_TCG
@@ -373,8 +374,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
if (cpu->cfg.ext_zicsr) {
+ GDBFeature *feature =
+ riscv_gen_dynamic_csr_feature(cs, cs->gdb_next_base_reg);
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs));
+ feature);
}
#endif
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7c25b9ab707a..48863a1859d4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -263,7 +263,7 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
+ cs->gdb_next_base_reg = xcc->config->gdb_regmap.num_regs;
qemu_init_vcpu(cs);
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 03/18] gdbstub: set feature->base_reg for dynamic features
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 01/18] hmp: don't crash on invalid register Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 02/18] gdbstub: fix next register base after register gaps Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 04/18] gdbstub: add gdb_register_internal_coprocessor() Marc-André Lureau
` (15 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
gdb_feature_builder_end() never propagated builder->base_reg into
feature->base_reg, leaving it at 0 for all dynamically-built features.
This made the trace log at gdb_get_register_list() report an incorrect
base_reg for dynamic features.
GDBRegisterState::base_reg was correctly set, so this doesn't fix
an actual issue.
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
gdbstub/gdbstub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 0ce871d74929..912e31b66744 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -476,6 +476,7 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *builder)
g_ptr_array_free(builder->xml, TRUE);
+ builder->feature->base_reg = builder->base_reg;
builder->feature->num_regs = builder->regs->len;
builder->feature->regs = (void *)g_ptr_array_free(builder->regs, FALSE);
trace_gdbxml_feature_builder_header(builder->feature->name,
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 04/18] gdbstub: add gdb_register_internal_coprocessor()
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (2 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 03/18] gdbstub: set feature->base_reg for dynamic features Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 21:51 ` Pierrick Bouvier
2026-10-22 10:56 ` [PATCH v3 05/18] MAINTAINERS: cover x86 GDB XML files Marc-André Lureau
` (14 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Add support for registering coprocessor features that are only visible
to QEMU's internal APIs (HMP monitor $register expressions, plugins) but
hidden from GDB's target description XML.
When a feature is registered as internal:
- It is excluded from the target.xml sent to GDB
- Its XML is not served via qXfer:features:read
- 'p'/'P' packets for internal register numbers return E14
This is useful for exposing system registers to the HMP monitor without
affecting GDB's register namespace. Exposing aliases or synthetic
registers through GDB's target description can cause problems: name
collisions with GDB's pseudo-registers, independent register caching,
and missing DWARF unwind rules.
Internal features must be registered after all GDB-visible features to
keep remote register numbering consistent. This ordering is enforced
with an assertion.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
gdbstub/gdbstub.c | 71 ++++++++++++++++++++++++++++++++++++++++++++------
include/exec/gdbstub.h | 21 +++++++++++++++
2 files changed, 84 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 912e31b66744..1675f4d6cd4a 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -54,6 +54,7 @@ typedef struct GDBRegisterState {
gdb_get_reg_cb get_reg;
gdb_set_reg_cb set_reg;
const GDBFeature *feature;
+ bool internal; /* hidden from GDB, accessible via API/monitor */
} GDBRegisterState;
GDBState gdbserver_state;
@@ -385,6 +386,11 @@ static const char *get_feature_xml(const char *p, const char **newp,
}
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ /* The core target.xml feature must never be internal. */
+ g_assert(i > 0 || !r->internal);
+ if (r->internal) {
+ continue;
+ }
g_ptr_array_add(
xml,
g_markup_printf_escaped("<xi:include href=\"%s\"/>",
@@ -400,6 +406,9 @@ static const char *get_feature_xml(const char *p, const char **newp,
/* Is it one of the features? */
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ if (r->internal) {
+ continue;
+ }
if (strncmp(p, r->feature->xmlname, len) == 0) {
return r->feature->xml;
}
@@ -563,13 +572,14 @@ int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
static void gdb_register_feature(CPUState *cpu, int base_reg,
gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
- const GDBFeature *feature)
+ const GDBFeature *feature, bool internal)
{
GDBRegisterState s = {
.base_reg = base_reg,
.get_reg = get_reg,
.set_reg = set_reg,
- .feature = feature
+ .feature = feature,
+ .internal = internal
};
trace_gdbxml_register_feature(feature->name, feature->xmlname,
@@ -605,7 +615,7 @@ void gdb_init_cpu(CPUState *cpu)
assert(feature->base_reg == 0);
gdb_register_feature(cpu, 0,
cc->gdb_read_register, cc->gdb_write_register,
- feature);
+ feature, false);
cpu->gdb_next_base_reg = cpu->gdb_num_g_regs = feature->num_regs;
} else {
cpu->gdb_next_base_reg = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
@@ -616,20 +626,26 @@ void gdb_init_cpu(CPUState *cpu)
cc->gdb_num_core_regs);
}
-void gdb_register_coprocessor(CPUState *cpu,
- gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
- const GDBFeature *feature)
+static void do_gdb_register_coprocessor(CPUState *cpu,
+ gdb_get_reg_cb get_reg,
+ gdb_set_reg_cb set_reg,
+ const GDBFeature *feature,
+ bool internal)
{
GDBRegisterState *s;
guint i;
int base_reg = cpu->gdb_next_base_reg;
for (i = 0; i < cpu->gdb_regs->len; i++) {
- /* Check for duplicates. */
s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+ /* Check for duplicates. */
if (s->feature == feature) {
return;
}
+ /* GDB-visible features must not follow internal ones. */
+ if (!internal) {
+ g_assert(!s->internal);
+ }
}
if (base_reg < feature->base_reg) {
@@ -637,12 +653,27 @@ void gdb_register_coprocessor(CPUState *cpu,
feature->base_reg);
base_reg = feature->base_reg;
}
- gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature);
+ gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature, internal);
/* Add to end of list. */
cpu->gdb_next_base_reg = base_reg + feature->num_regs;
}
+void gdb_register_coprocessor(CPUState *cpu,
+ gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
+ const GDBFeature *feature)
+{
+ do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, false);
+}
+
+void gdb_register_internal_coprocessor(CPUState *cpu,
+ gdb_get_reg_cb get_reg,
+ gdb_set_reg_cb set_reg,
+ const GDBFeature *feature)
+{
+ do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, true);
+}
+
void gdb_unregister_coprocessor_all(CPUState *cpu)
{
/*
@@ -1223,6 +1254,18 @@ static void handle_remove_bp(GArray *params, void *user_ctx)
* the remote gdb to fallback to older methods.
*/
+static bool gdb_register_is_internal(CPUState *cpu, int reg)
+{
+ for (guint i = 0; i < cpu->gdb_regs->len; i++) {
+ GDBRegisterState *r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
+
+ if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {
+ return r->internal;
+ }
+ }
+ return false;
+}
+
static void handle_set_reg(GArray *params, void *user_ctx)
{
int reg_size;
@@ -1232,6 +1275,12 @@ static void handle_set_reg(GArray *params, void *user_ctx)
return;
}
+ if (gdb_register_is_internal(gdbserver_state.g_cpu,
+ gdb_get_cmd_param(params, 0)->val_ull)) {
+ gdb_put_packet("E14");
+ return;
+ }
+
reg_size = strlen(gdb_get_cmd_param(params, 1)->data) / 2;
gdb_hextomem(gdbserver_state.mem_buf, gdb_get_cmd_param(params, 1)->data, reg_size);
gdb_write_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf->data,
@@ -1248,6 +1297,12 @@ static void handle_get_reg(GArray *params, void *user_ctx)
return;
}
+ if (gdb_register_is_internal(gdbserver_state.g_cpu,
+ gdb_get_cmd_param(params, 0)->val_ull)) {
+ gdb_put_packet("E14");
+ return;
+ }
+
reg_size = gdb_read_register(gdbserver_state.g_cpu,
gdbserver_state.mem_buf,
gdb_get_cmd_param(params, 0)->val_ull);
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 75eb4d9c365e..1bc778324758 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -40,6 +40,27 @@ void gdb_register_coprocessor(CPUState *cpu,
gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
const GDBFeature *feature);
+/**
+ * gdb_register_internal_coprocessor() - register internal registers
+ *
+ * Like gdb_register_coprocessor(), but the feature is NOT exposed to
+ * GDB via the target description XML. The registers are only
+ * accessible through QEMU's internal APIs (HMP monitor ``$register``
+ * expressions via gdb_get_register_list()).
+ *
+ * Internal features must be registered after all GDB-visible features
+ * to avoid register numbering mismatches with GDB.
+ *
+ * @cpu - the CPU associated with registers
+ * @get_reg - get function
+ * @set_reg - set function
+ * @feature - the GDBFeature describing the registers
+ */
+void gdb_register_internal_coprocessor(CPUState *cpu,
+ gdb_get_reg_cb get_reg,
+ gdb_set_reg_cb set_reg,
+ const GDBFeature *feature);
+
/**
* gdb_unregister_coprocessor_all() - unregisters supplemental set of registers
* @cpu - the CPU associated with registers
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 04/18] gdbstub: add gdb_register_internal_coprocessor()
2026-10-22 10:56 ` [PATCH v3 04/18] gdbstub: add gdb_register_internal_coprocessor() Marc-André Lureau
@ 2026-10-22 21:51 ` Pierrick Bouvier
0 siblings, 0 replies; 31+ messages in thread
From: Pierrick Bouvier @ 2026-10-22 21:51 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller, Warner Losh,
Kyle Evans
On 10/22/2026 3:56 AM, Marc-André Lureau wrote:
> Add support for registering coprocessor features that are only visible
> to QEMU's internal APIs (HMP monitor $register expressions, plugins) but
> hidden from GDB's target description XML.
>
> When a feature is registered as internal:
> - It is excluded from the target.xml sent to GDB
> - Its XML is not served via qXfer:features:read
> - 'p'/'P' packets for internal register numbers return E14
>
> This is useful for exposing system registers to the HMP monitor without
> affecting GDB's register namespace. Exposing aliases or synthetic
> registers through GDB's target description can cause problems: name
> collisions with GDB's pseudo-registers, independent register caching,
> and missing DWARF unwind rules.
>
> Internal features must be registered after all GDB-visible features to
> keep remote register numbering consistent. This ordering is enforced
> with an assertion.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> gdbstub/gdbstub.c | 71 ++++++++++++++++++++++++++++++++++++++++++++------
> include/exec/gdbstub.h | 21 +++++++++++++++
> 2 files changed, 84 insertions(+), 8 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 05/18] MAINTAINERS: cover x86 GDB XML files
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (3 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 04/18] gdbstub: add gdb_register_internal_coprocessor() Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 20:44 ` Pierrick Bouvier
2026-10-22 10:56 ` [PATCH v3 06/18] target/i386: expose segment limits register to monitors via gdbstub Marc-André Lureau
` (13 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Add entries so changes to these files are routed to the X86
maintainers.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d9209f043f0b..f22333fbf177 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -149,6 +149,7 @@ F: configs/targets/i386-softmmu.mak
F: configs/targets/x86_64-softmmu.mak
F: docs/system/i386/
F: docs/system/target-i386*
+F: gdbstub/gdb-xml/i386-*.xml
F: stubs/hmp-cmds-target-i386.c
F: target/i386/*.[ch]
F: target/i386/Kconfig
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 05/18] MAINTAINERS: cover x86 GDB XML files
2026-10-22 10:56 ` [PATCH v3 05/18] MAINTAINERS: cover x86 GDB XML files Marc-André Lureau
@ 2026-10-22 20:44 ` Pierrick Bouvier
0 siblings, 0 replies; 31+ messages in thread
From: Pierrick Bouvier @ 2026-10-22 20:44 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller, Warner Losh,
Kyle Evans
On 10/22/2026 3:56 AM, Marc-André Lureau wrote:
> Add entries so changes to these files are routed to the X86
> maintainers.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 06/18] target/i386: expose segment limits register to monitors via gdbstub
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (4 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 05/18] MAINTAINERS: cover x86 GDB XML files Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 07/18] target/i386: fix FPU tag word in GDB register read Marc-André Lureau
` (12 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Add an i386-system.xml GDB "internal" feature that exposes the six
segment limit registers (cs, ds, es, ss, fs, gs) as read-only system
registers through the GDB coprocessor interface. This makes them
accessible to HMP without relying on the legacy MonitorDef table, which
will be removed in a subsequent commit.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/i386-softmmu.mak | 2 +-
configs/targets/x86_64-softmmu.mak | 2 +-
gdbstub/gdb-xml/i386-system.xml | 14 ++++++++++++++
target/i386/cpu.c | 9 ---------
target/i386/gdbstub.c | 25 +++++++++++++++++++++++++
5 files changed, 41 insertions(+), 11 deletions(-)
diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak
index 38a8f85201f9..1424ab6f6834 100644
--- a/configs/targets/i386-softmmu.mak
+++ b/configs/targets/i386-softmmu.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-32bit.xml
+TARGET_XML_FILES= i386-32bit.xml i386-system.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak
index c7f8746b4f58..51e882b1c747 100644
--- a/configs/targets/x86_64-softmmu.mak
+++ b/configs/targets/x86_64-softmmu.mak
@@ -2,6 +2,6 @@ TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-apx.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-apx.xml i386-system.xml
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/gdbstub/gdb-xml/i386-system.xml b/gdbstub/gdb-xml/i386-system.xml
new file mode 100644
index 000000000000..9868b887eab8
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-system.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- Segment-cache values are read-only; writes are ignored. -->
+<feature name="org.qemu.gdb.i386.system">
+ <reg name="cs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ds.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="es.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ss.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="fs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="gs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+</feature>
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5da80ade70eb..37732b65e408 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10893,17 +10893,8 @@ static int64_t monitor_get_pc(MonitorHMP *hmp, const struct MonitorDef *md,
}
static const MonitorDef x86_monitor_defs[] = {
-#define SEG(name, seg) \
- { name ".limit", offsetof(CPUX86State, segs[seg].limit) },
- SEG("cs", R_CS)
- SEG("ds", R_DS)
- SEG("es", R_ES)
- SEG("ss", R_SS)
- SEG("fs", R_FS)
- SEG("gs", R_GS)
{ "pc", 0, monitor_get_pc, },
{ NULL },
-#undef SEG
};
#endif
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index e636ca0f4ae7..c0cde26d978c 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -496,6 +496,25 @@ static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_t *mem_buf, int n)
}
#endif
+#ifndef CONFIG_USER_ONLY
+static int x86_gdb_read_system(CPUState *cs, GByteArray *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+ static const int segments[] = { R_CS, R_DS, R_ES, R_SS, R_FS, R_GS };
+
+ if (n < 0 || n >= ARRAY_SIZE(segments)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->segs[segments[n]].limit);
+}
+
+static int x86_gdb_write_system(CPUState *cs, uint8_t *buf, int n)
+{
+ /* Segment caches are exposed for inspection only. Ignore writes. */
+ return 4;
+}
+#endif
+
void x86_cpu_gdb_init(CPUState *cs)
{
#ifdef TARGET_X86_64
@@ -517,4 +536,10 @@ void x86_cpu_gdb_init(CPUState *cs)
gdb_find_static_feature("i386-32bit-linux.xml"));
#endif
#endif
+#ifndef CONFIG_USER_ONLY
+ gdb_register_internal_coprocessor(
+ cs, x86_gdb_read_system,
+ x86_gdb_write_system,
+ gdb_find_static_feature("i386-system.xml"));
+#endif
}
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 07/18] target/i386: fix FPU tag word in GDB register read
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (5 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 06/18] target/i386: expose segment limits register to monitors via gdbstub Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 08/18] target/i386: split SSE registers into separate GDB feature Marc-André Lureau
` (11 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau,
Richard Henderson
The GDB stub was returning a hardcoded 0 for the x87 FPU tag word
register (ftag). Factor out cpu_compute_fptag() helper. Simplify a
little bit the code by dropping unnecessary CPU_LDoubleU
reinterpretation, building the value 0..7, avoiding signed-shifting.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/i386/cpu.c | 28 ++++++++++++++++++++++++++++
target/i386/cpu.h | 9 +++++++++
target/i386/gdbstub.c | 2 +-
target/i386/tcg/fpu_helper.c | 24 ++----------------------
4 files changed, 40 insertions(+), 23 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 37732b65e408..2f5ea4e51715 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9372,6 +9372,34 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
return false;
}
+uint16_t cpu_compute_fptag(CPUX86State *env)
+{
+ uint16_t fptag = 0;
+
+ for (int i = 0; i < 8; i++) {
+ unsigned tag;
+
+ if (env->fptags[i]) {
+ tag = 3; /* empty */
+ } else {
+ floatx80 f = env->fpregs[i].d;
+ uint16_t exponent = f.high & 0x7fff;
+ uint64_t mantissa = f.low;
+
+ if (exponent == 0 && mantissa == 0) {
+ tag = 1; /* zero */
+ } else if (exponent == 0 || exponent == 0x7fff ||
+ !(mantissa & (1ULL << 63))) {
+ tag = 2; /* NaNs, infinity, denormal */
+ } else {
+ tag = 0; /* valid */
+ }
+ }
+ fptag |= tag << (2 * i);
+ }
+ return fptag;
+}
+
static void x86_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e7a88074c071..116e28a59701 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2989,6 +2989,15 @@ static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
}
}
+/**
+ * cpu_compute_fptag - Compute the full 16-bit x87 FPU tag word.
+ *
+ * Reconstructs the 16-bit tag word from the fpregs and fptags arrays.
+ * Each of the 8 physical registers gets a 2-bit tag in bits [2*i+1 : 2*i]:
+ * 0 = valid, 1 = zero, 2 = special (NaN/Inf/denormal), 3 = empty.
+ */
+uint16_t cpu_compute_fptag(CPUX86State *env);
+
static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
{
env->fpuc = fpuc;
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index c0cde26d978c..420ce845eeae 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -186,7 +186,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
(env->fpstt & 0x7) << 11);
case IDX_FP_REGS + 10:
- return gdb_get_reg32(mem_buf, 0); /* ftag */
+ return gdb_get_reg32(mem_buf, cpu_compute_fptag(env));
case IDX_FP_REGS + 11:
return gdb_get_reg32(mem_buf, 0); /* fiseg */
case IDX_FP_REGS + 12:
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 4bbac996326e..81ae3d8f3d0f 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -2459,30 +2459,10 @@ void helper_fxam_ST0(CPUX86State *env)
static void do_fstenv(X86Access *ac, target_ulong ptr, int data32)
{
CPUX86State *env = ac->env;
- int fpus, fptag, exp, i;
- uint64_t mant;
- CPU_LDoubleU tmp;
+ int fpus, fptag;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
- fptag = 0;
- for (i = 7; i >= 0; i--) {
- fptag <<= 2;
- if (env->fptags[i]) {
- fptag |= 3;
- } else {
- tmp.d = env->fpregs[i].d;
- exp = EXPD(tmp);
- mant = MANTD(tmp);
- if (exp == 0 && mant == 0) {
- /* zero */
- fptag |= 1;
- } else if (exp == 0 || exp == MAXEXPD
- || (mant & (1LL << 63)) == 0) {
- /* NaNs, infinity, denormal */
- fptag |= 2;
- }
- }
- }
+ fptag = cpu_compute_fptag(env);
if (data32) {
/* 32 bit */
access_stl(ac, ptr, env->fpuc);
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 08/18] target/i386: split SSE registers into separate GDB feature
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (6 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 07/18] target/i386: fix FPU tag word in GDB register read Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 09/18] target/i386: expose system registers to monitors via gdbstub Marc-André Lureau
` (10 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Move XMM registers and mxcsr out of org.gnu.gdb.i386.core into a
separate org.gnu.gdb.i386.sse feature, matching GDB's expected target
description layout (gdb/features/i386/{32,64}bit-sse.xml). Previously,
SSE registers were embedded in the core feature with a commented-out
feature boundary.
GDB requires org.gnu.gdb.i386.sse as a prerequisite for the AVX
feature (org.gnu.gdb.i386.avx). Without this split, adding AVX support
causes GDB to reject the target description entirely.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/i386-bsd-user.mak | 2 +-
configs/targets/i386-linux-user.mak | 2 +-
configs/targets/i386-softmmu.mak | 2 +-
configs/targets/x86_64-bsd-user.mak | 2 +-
configs/targets/x86_64-linux-user.mak | 2 +-
configs/targets/x86_64-softmmu.mak | 2 +-
gdbstub/gdb-xml/i386-32bit-sse.xml | 54 +++++++++++++++++++++++++
gdbstub/gdb-xml/i386-32bit.xml | 46 +--------------------
gdbstub/gdb-xml/i386-64bit-sse.xml | 62 ++++++++++++++++++++++++++++
gdbstub/gdb-xml/i386-64bit.xml | 50 -----------------------
target/i386/gdbstub.c | 76 ++++++++++++++++++++++-------------
11 files changed, 172 insertions(+), 128 deletions(-)
diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-user.mak
index 485f571cb6cd..b2a8b0a42ad9 100644
--- a/configs/targets/i386-bsd-user.mak
+++ b/configs/targets/i386-bsd-user.mak
@@ -1,3 +1,3 @@
TARGET_ARCH=i386
-TARGET_XML_FILES= i386-32bit.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml
TARGET_LONG_BITS=32
diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-linux-user.mak
index a3ea4c39c520..234e600860a3 100644
--- a/configs/targets/i386-linux-user.mak
+++ b/configs/targets/i386-linux-user.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=i386
TARGET_SYSTBL_ABI=i386
TARGET_SYSTBL=syscall_32.tbl
-TARGET_XML_FILES= i386-32bit.xml i386-32bit-linux.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-32bit-linux.xml
TARGET_LONG_BITS=32
diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak
index 1424ab6f6834..a53ee07255b4 100644
--- a/configs/targets/i386-softmmu.mak
+++ b/configs/targets/i386-softmmu.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-32bit.xml i386-system.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-system.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-bsd-user.mak
index 26b7cfad4e23..f36a9ccbd60a 100644
--- a/configs/targets/x86_64-bsd-user.mak
+++ b/configs/targets/x86_64-bsd-user.mak
@@ -1,4 +1,4 @@
TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-apx.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64-linux-user.mak
index cad68746bdb2..77a035b7eb4c 100644
--- a/configs/targets/x86_64-linux-user.mak
+++ b/configs/targets/x86_64-linux-user.mak
@@ -2,5 +2,5 @@ TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall_64.tbl
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-linux.xml i386-64bit-apx.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-linux.xml i386-64bit-apx.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak
index 51e882b1c747..c04fdf2d3fe8 100644
--- a/configs/targets/x86_64-softmmu.mak
+++ b/configs/targets/x86_64-softmmu.mak
@@ -2,6 +2,6 @@ TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-apx.xml i386-system.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml i386-system.xml
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/gdbstub/gdb-xml/i386-32bit-sse.xml b/gdbstub/gdb-xml/i386-32bit-sse.xml
new file mode 100644
index 000000000000..3f8a8d2bc8c1
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-32bit-sse.xml
@@ -0,0 +1,54 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.sse">
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v2i64" type="int64" count="2"/>
+ <union id="vec128">
+ <field name="v4_float" type="v4f"/>
+ <field name="v2_double" type="v2d"/>
+ <field name="v16_int8" type="v16i8"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v2_int64" type="v2i64"/>
+ <field name="uint128" type="uint128"/>
+ </union>
+ <flags id="i386_mxcsr" size="4">
+ <field name="IE" start="0" end="0"/>
+ <field name="DE" start="1" end="1"/>
+ <field name="ZE" start="2" end="2"/>
+ <field name="OE" start="3" end="3"/>
+ <field name="UE" start="4" end="4"/>
+ <field name="PE" start="5" end="5"/>
+ <field name="DAZ" start="6" end="6"/>
+ <field name="IM" start="7" end="7"/>
+ <field name="DM" start="8" end="8"/>
+ <field name="ZM" start="9" end="9"/>
+ <field name="OM" start="10" end="10"/>
+ <field name="UM" start="11" end="11"/>
+ <field name="PM" start="12" end="12"/>
+ <field name="FZ" start="15" end="15"/>
+ </flags>
+
+ <reg name="xmm0" bitsize="128" type="vec128"/>
+ <reg name="xmm1" bitsize="128" type="vec128"/>
+ <reg name="xmm2" bitsize="128" type="vec128"/>
+ <reg name="xmm3" bitsize="128" type="vec128"/>
+ <reg name="xmm4" bitsize="128" type="vec128"/>
+ <reg name="xmm5" bitsize="128" type="vec128"/>
+ <reg name="xmm6" bitsize="128" type="vec128"/>
+ <reg name="xmm7" bitsize="128" type="vec128"/>
+
+ <reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
+</feature>
diff --git a/gdbstub/gdb-xml/i386-32bit.xml b/gdbstub/gdb-xml/i386-32bit.xml
index 1dec40e1d2c1..dd6b6e7b8481 100644
--- a/gdbstub/gdb-xml/i386-32bit.xml
+++ b/gdbstub/gdb-xml/i386-32bit.xml
@@ -5,7 +5,7 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-<!-- I386 with SSE -->
+<!-- I386 core -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.core">
@@ -152,48 +152,4 @@
<reg name="foseg" bitsize="32" type="int" group="float"/>
<reg name="fooff" bitsize="32" type="int" group="float"/>
<reg name="fop" bitsize="32" type="int" group="float"/>
-<!--/feature>
-<feature name="org.gnu.gdb.i386.32bit.sse"-->
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
- <vector id="v16i8" type="int8" count="16"/>
- <vector id="v8i16" type="int16" count="8"/>
- <vector id="v4i32" type="int32" count="4"/>
- <vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
- <field name="v16_int8" type="v16i8"/>
- <field name="v8_int16" type="v8i16"/>
- <field name="v4_int32" type="v4i32"/>
- <field name="v2_int64" type="v2i64"/>
- <field name="uint128" type="uint128"/>
- </union>
- <flags id="i386_mxcsr" size="4">
- <field name="IE" start="0" end="0"/>
- <field name="DE" start="1" end="1"/>
- <field name="ZE" start="2" end="2"/>
- <field name="OE" start="3" end="3"/>
- <field name="UE" start="4" end="4"/>
- <field name="PE" start="5" end="5"/>
- <field name="DAZ" start="6" end="6"/>
- <field name="IM" start="7" end="7"/>
- <field name="DM" start="8" end="8"/>
- <field name="ZM" start="9" end="9"/>
- <field name="OM" start="10" end="10"/>
- <field name="UM" start="11" end="11"/>
- <field name="PM" start="12" end="12"/>
- <field name="FZ" start="15" end="15"/>
- </flags>
-
- <reg name="xmm0" bitsize="128" type="vec128"/>
- <reg name="xmm1" bitsize="128" type="vec128"/>
- <reg name="xmm2" bitsize="128" type="vec128"/>
- <reg name="xmm3" bitsize="128" type="vec128"/>
- <reg name="xmm4" bitsize="128" type="vec128"/>
- <reg name="xmm5" bitsize="128" type="vec128"/>
- <reg name="xmm6" bitsize="128" type="vec128"/>
- <reg name="xmm7" bitsize="128" type="vec128"/>
-
- <reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
diff --git a/gdbstub/gdb-xml/i386-64bit-sse.xml b/gdbstub/gdb-xml/i386-64bit-sse.xml
new file mode 100644
index 000000000000..06a5f857d92c
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-64bit-sse.xml
@@ -0,0 +1,62 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.sse">
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v2i64" type="int64" count="2"/>
+ <union id="vec128">
+ <field name="v4_float" type="v4f"/>
+ <field name="v2_double" type="v2d"/>
+ <field name="v16_int8" type="v16i8"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v2_int64" type="v2i64"/>
+ <field name="uint128" type="uint128"/>
+ </union>
+ <flags id="x64_mxcsr" size="4">
+ <field name="IE" start="0" end="0"/>
+ <field name="DE" start="1" end="1"/>
+ <field name="ZE" start="2" end="2"/>
+ <field name="OE" start="3" end="3"/>
+ <field name="UE" start="4" end="4"/>
+ <field name="PE" start="5" end="5"/>
+ <field name="DAZ" start="6" end="6"/>
+ <field name="IM" start="7" end="7"/>
+ <field name="DM" start="8" end="8"/>
+ <field name="ZM" start="9" end="9"/>
+ <field name="OM" start="10" end="10"/>
+ <field name="UM" start="11" end="11"/>
+ <field name="PM" start="12" end="12"/>
+ <field name="FZ" start="15" end="15"/>
+ </flags>
+
+ <reg name="xmm0" bitsize="128" type="vec128"/>
+ <reg name="xmm1" bitsize="128" type="vec128"/>
+ <reg name="xmm2" bitsize="128" type="vec128"/>
+ <reg name="xmm3" bitsize="128" type="vec128"/>
+ <reg name="xmm4" bitsize="128" type="vec128"/>
+ <reg name="xmm5" bitsize="128" type="vec128"/>
+ <reg name="xmm6" bitsize="128" type="vec128"/>
+ <reg name="xmm7" bitsize="128" type="vec128"/>
+ <reg name="xmm8" bitsize="128" type="vec128"/>
+ <reg name="xmm9" bitsize="128" type="vec128"/>
+ <reg name="xmm10" bitsize="128" type="vec128"/>
+ <reg name="xmm11" bitsize="128" type="vec128"/>
+ <reg name="xmm12" bitsize="128" type="vec128"/>
+ <reg name="xmm13" bitsize="128" type="vec128"/>
+ <reg name="xmm14" bitsize="128" type="vec128"/>
+ <reg name="xmm15" bitsize="128" type="vec128"/>
+
+ <reg name="mxcsr" bitsize="32" type="x64_mxcsr" group="vector"/>
+</feature>
diff --git a/gdbstub/gdb-xml/i386-64bit.xml b/gdbstub/gdb-xml/i386-64bit.xml
index 9ac9164e6a99..a31c38aa8bd7 100644
--- a/gdbstub/gdb-xml/i386-64bit.xml
+++ b/gdbstub/gdb-xml/i386-64bit.xml
@@ -170,54 +170,4 @@
<reg name="fooff" bitsize="32" type="int" group="float"/>
<reg name="fop" bitsize="32" type="int" group="float"/>
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
- <vector id="v16i8" type="int8" count="16"/>
- <vector id="v8i16" type="int16" count="8"/>
- <vector id="v4i32" type="int32" count="4"/>
- <vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
- <field name="v16_int8" type="v16i8"/>
- <field name="v8_int16" type="v8i16"/>
- <field name="v4_int32" type="v4i32"/>
- <field name="v2_int64" type="v2i64"/>
- <field name="uint128" type="uint128"/>
- </union>
- <flags id="x64_mxcsr" size="4">
- <field name="IE" start="0" end="0"/>
- <field name="DE" start="1" end="1"/>
- <field name="ZE" start="2" end="2"/>
- <field name="OE" start="3" end="3"/>
- <field name="UE" start="4" end="4"/>
- <field name="PE" start="5" end="5"/>
- <field name="DAZ" start="6" end="6"/>
- <field name="IM" start="7" end="7"/>
- <field name="DM" start="8" end="8"/>
- <field name="ZM" start="9" end="9"/>
- <field name="OM" start="10" end="10"/>
- <field name="UM" start="11" end="11"/>
- <field name="PM" start="12" end="12"/>
- <field name="FZ" start="15" end="15"/>
- </flags>
-
- <reg name="xmm0" bitsize="128" type="vec128"/>
- <reg name="xmm1" bitsize="128" type="vec128"/>
- <reg name="xmm2" bitsize="128" type="vec128"/>
- <reg name="xmm3" bitsize="128" type="vec128"/>
- <reg name="xmm4" bitsize="128" type="vec128"/>
- <reg name="xmm5" bitsize="128" type="vec128"/>
- <reg name="xmm6" bitsize="128" type="vec128"/>
- <reg name="xmm7" bitsize="128" type="vec128"/>
- <reg name="xmm8" bitsize="128" type="vec128"/>
- <reg name="xmm9" bitsize="128" type="vec128"/>
- <reg name="xmm10" bitsize="128" type="vec128"/>
- <reg name="xmm11" bitsize="128" type="vec128"/>
- <reg name="xmm12" bitsize="128" type="vec128"/>
- <reg name="xmm13" bitsize="128" type="vec128"/>
- <reg name="xmm14" bitsize="128" type="vec128"/>
- <reg name="xmm15" bitsize="128" type="vec128"/>
-
- <reg name="mxcsr" bitsize="32" type="x64_mxcsr" group="vector"/>
</feature>
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 420ce845eeae..2b4c28aac162 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -57,9 +57,8 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
/*
* fpu regs ----------> 8 or 16
*/
-#define IDX_NB_MXCSR 1
/*
- * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
+ * total ----> 8+1+1+9+6+16=41 or 16+1+1+9+6+16=49
*/
#define IDX_IP_REG CPU_NB_REGS
@@ -67,8 +66,6 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
-#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
-#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
@@ -139,13 +136,6 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
return len;
- } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
- n -= IDX_XMM_REGS;
- if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
- return gdb_get_reg128(mem_buf,
- env->xmm_regs[n].ZMM_Q(1),
- env->xmm_regs[n].ZMM_Q(0));
- }
} else {
switch (n) {
case IDX_IP_REG:
@@ -198,10 +188,6 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
case IDX_FP_REGS + 15:
return gdb_get_reg32(mem_buf, 0); /* fop */
- case IDX_MXCSR_REG:
- update_mxcsr_from_sse_status(env);
- return gdb_get_reg32(mem_buf, env->mxcsr);
-
case IDX_CTL_CR0_REG:
return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]);
case IDX_CTL_CR2_REG:
@@ -300,13 +286,6 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
return 10;
- } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
- n -= IDX_XMM_REGS;
- if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
- env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
- env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
- return 16;
- }
} else {
switch (n) {
case IDX_IP_REG:
@@ -358,10 +337,6 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
case IDX_FP_REGS + 15: /* fop */
return 4;
- case IDX_MXCSR_REG:
- cpu_set_mxcsr(env, ldl_p(mem_buf));
- return 4;
-
case IDX_CTL_CR0_REG:
len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
@@ -409,6 +384,44 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 0;
}
+/*
+ * SSE feature (org.gnu.gdb.i386.sse) — XMM registers + mxcsr.
+ *
+ * Register layout: xmm0..xmm(N-1), mxcsr.
+ * N = CPU_NB_REGS (8 for 32-bit, 16 for 64-bit).
+ */
+static int x86_gdb_read_sse(CPUState *cs, GByteArray *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+
+ if (n < CPU_NB_REGS) {
+ return gdb_get_reg128(buf,
+ env->xmm_regs[n].ZMM_Q(1),
+ env->xmm_regs[n].ZMM_Q(0));
+ }
+ if (n == CPU_NB_REGS) {
+ update_mxcsr_from_sse_status(env);
+ return gdb_get_reg32(buf, env->mxcsr);
+ }
+ return 0;
+}
+
+static int x86_gdb_write_sse(CPUState *cs, uint8_t *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+
+ if (n < CPU_NB_REGS) {
+ env->xmm_regs[n].ZMM_Q(0) = ldq_p(buf);
+ env->xmm_regs[n].ZMM_Q(1) = ldq_p(buf + 8);
+ return 16;
+ }
+ if (n == CPU_NB_REGS) {
+ cpu_set_mxcsr(env, ldl_p(buf));
+ return 4;
+ }
+ return 0;
+}
+
#ifdef CONFIG_LINUX_USER
#define IDX_ORIG_AX 0
@@ -519,11 +532,20 @@ void x86_cpu_gdb_init(CPUState *cs)
{
#ifdef TARGET_X86_64
CPUX86State *env = &X86_CPU(cs)->env;
+ const char *sse_xml = "i386-64bit-sse.xml";
+#else
+ const char *sse_xml = "i386-32bit-sse.xml";
+#endif
+ gdb_register_coprocessor(cs, x86_gdb_read_sse, x86_gdb_write_sse,
+ gdb_find_static_feature(sse_xml));
+
+#ifdef TARGET_X86_64
if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) {
gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs,
i386_cpu_gdb_set_egprs,
- gdb_find_static_feature("i386-64bit-apx.xml"));
+ gdb_find_static_feature(
+ "i386-64bit-apx.xml"));
}
#endif
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 09/18] target/i386: expose system registers to monitors via gdbstub
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (7 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 08/18] target/i386: split SSE registers into separate GDB feature Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 10/18] target/i386: expose AVX/AVX-512 registers to GDB Marc-André Lureau
` (9 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Expand the org.qemu.gdb.i386.system feature to expose additional
read-only registers to HMP/monitor:
- segment cache bases and flags (cs/ds/es/ss/fs/gs)
- GDT/IDT base and limit
- LDT/TR selector, base, limit, and flags
- debug registers (dr0-dr3, dr6, dr7)
- CPU status fields: CPL, interrupt-inhibit, A20, SMM, HLT
- xcr0
- abridged x87 tag word (ftw)
This will allow to implement an HMP "info registers" (cpu dump)
equivalent based on QMP register query some day.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
gdbstub/gdb-xml/i386-system.xml | 41 ++++++++++++-
target/i386/cpu-dump.c | 5 +-
target/i386/cpu.h | 16 +++++
target/i386/gdbstub.c | 132 +++++++++++++++++++++++++++++++++++++---
4 files changed, 181 insertions(+), 13 deletions(-)
diff --git a/gdbstub/gdb-xml/i386-system.xml b/gdbstub/gdb-xml/i386-system.xml
index 9868b887eab8..7e7a5fb2e21f 100644
--- a/gdbstub/gdb-xml/i386-system.xml
+++ b/gdbstub/gdb-xml/i386-system.xml
@@ -3,7 +3,7 @@
SPDX-License-Identifier: GPL-2.0-or-later
-->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<!-- Segment-cache values are read-only; writes are ignored. -->
+<!-- System-register values are read-only; writes are ignored. -->
<feature name="org.qemu.gdb.i386.system">
<reg name="cs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
<reg name="ds.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
@@ -11,4 +11,43 @@
<reg name="ss.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
<reg name="fs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
<reg name="gs.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <!-- fs/gs in core regs -->
+ <reg name="cs.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="ds.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="es.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="ss.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="cs.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ds.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="es.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ss.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="fs.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="gs.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="gdt.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="gdt.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="idt.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="idt.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ldt.selector" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ldt.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="ldt.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="ldt.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="tr.selector" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="tr.base" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="tr.limit" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="tr.flags" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="dr0" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="dr1" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="dr2" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="dr3" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="dr6" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <reg name="dr7" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <!-- CPU status values, matching the fields printed by info registers. -->
+ <reg name="cpl" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <!-- ii: interrupt inhibit -->
+ <reg name="ii" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="a20" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="smm" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="hlt" bitsize="32" type="uint32" group="qemu-debug" save-restore="no"/>
+ <reg name="xcr0" bitsize="64" type="uint64" group="qemu-debug" save-restore="no"/>
+ <!-- Abridged x87 tag word: one bit per physical register, 1 = nonempty. -->
+ <reg name="ftw" bitsize="8" type="uint8" group="qemu-debug" save-restore="no"/>
</feature>
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
index 9e290c0b9b42..d8d7ebaf0e03 100644
--- a/target/i386/cpu-dump.c
+++ b/target/i386/cpu-dump.c
@@ -511,10 +511,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
XSTATE_Hi16_ZMM_MASK | \
XSTATE_YMM_MASK | XSTATE_SSE_MASK,
avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
- fptag = 0;
- for(i = 0; i < 8; i++) {
- fptag |= ((!env->fptags[i]) << i);
- }
+ fptag = x86_fptags_to_abridged(env);
update_mxcsr_from_sse_status(env);
qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
env->fpuc,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 116e28a59701..cc06f1fb7b68 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2998,6 +2998,22 @@ static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
*/
uint16_t cpu_compute_fptag(CPUX86State *env);
+/**
+ * x86_fptags_to_abridged - Pack fptags[] into the 8-bit abridged tag word.
+ *
+ * Returns the FXSAVE/XSAVE-style tag byte: bit i is 1 when ST(i) is
+ * nonempty (fptags[i] == 0) and 0 when empty (fptags[i] == 1).
+ */
+static inline uint8_t x86_fptags_to_abridged(const CPUX86State *env)
+{
+ uint8_t ftw = 0;
+
+ for (int i = 0; i < 8; i++) {
+ ftw |= (!env->fptags[i]) << i;
+ }
+ return ftw;
+}
+
static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
{
env->fpuc = fpuc;
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 2b4c28aac162..9a46c46ecff9 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -510,21 +510,135 @@ static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_t *mem_buf, int n)
#endif
#ifndef CONFIG_USER_ONLY
+enum {
+ /* Segment limits: cs, ds, es, ss, fs, gs (6 × 32-bit) */
+ X86_GDB_SEG_LIMIT_FIRST,
+ X86_GDB_SEG_LIMIT_LAST = X86_GDB_SEG_LIMIT_FIRST + 5,
+ /* Segment bases: cs, ds, es, ss (4 × 64-bit; fs/gs in core regs) */
+ X86_GDB_SEG_BASE_FIRST,
+ X86_GDB_SEG_BASE_LAST = X86_GDB_SEG_BASE_FIRST + 3,
+ /* Segment flags: cs, ds, es, ss, fs, gs (6 × 32-bit) */
+ X86_GDB_SEG_FLAGS_FIRST,
+ X86_GDB_SEG_FLAGS_LAST = X86_GDB_SEG_FLAGS_FIRST + 5,
+ /* Descriptor tables */
+ X86_GDB_GDT_BASE,
+ X86_GDB_GDT_LIMIT,
+ X86_GDB_IDT_BASE,
+ X86_GDB_IDT_LIMIT,
+ X86_GDB_LDT_SELECTOR,
+ X86_GDB_LDT_BASE,
+ X86_GDB_LDT_LIMIT,
+ X86_GDB_LDT_FLAGS,
+ X86_GDB_TR_SELECTOR,
+ X86_GDB_TR_BASE,
+ X86_GDB_TR_LIMIT,
+ X86_GDB_TR_FLAGS,
+ /* Debug registers: dr0-dr3, dr6, dr7 (6 × 64-bit) */
+ X86_GDB_DR0,
+ X86_GDB_DR1,
+ X86_GDB_DR2,
+ X86_GDB_DR3,
+ X86_GDB_DR6,
+ X86_GDB_DR7,
+ /* CPU status */
+ X86_GDB_CPL,
+ X86_GDB_II,
+ X86_GDB_A20,
+ X86_GDB_SMM,
+ X86_GDB_HLT,
+ X86_GDB_XCR0,
+ X86_GDB_FTW,
+ X86_GDB_SYSTEM_COUNT,
+};
+
static int x86_gdb_read_system(CPUState *cs, GByteArray *buf, int n)
{
CPUX86State *env = cpu_env(cs);
static const int segments[] = { R_CS, R_DS, R_ES, R_SS, R_FS, R_GS };
- if (n < 0 || n >= ARRAY_SIZE(segments)) {
+ switch (n) {
+ case X86_GDB_SEG_LIMIT_FIRST ... X86_GDB_SEG_LIMIT_LAST:
+ return gdb_get_reg32(buf,
+ env->segs[segments[n - X86_GDB_SEG_LIMIT_FIRST]].limit);
+ case X86_GDB_SEG_BASE_FIRST ... X86_GDB_SEG_BASE_LAST:
+ return gdb_get_reg64(buf,
+ env->segs[segments[n - X86_GDB_SEG_BASE_FIRST]].base);
+ case X86_GDB_SEG_FLAGS_FIRST ... X86_GDB_SEG_FLAGS_LAST:
+ return gdb_get_reg32(buf,
+ env->segs[segments[n - X86_GDB_SEG_FLAGS_FIRST]].flags);
+ case X86_GDB_GDT_BASE:
+ return gdb_get_reg64(buf, env->gdt.base);
+ case X86_GDB_GDT_LIMIT:
+ return gdb_get_reg32(buf, env->gdt.limit);
+ case X86_GDB_IDT_BASE:
+ return gdb_get_reg64(buf, env->idt.base);
+ case X86_GDB_IDT_LIMIT:
+ return gdb_get_reg32(buf, env->idt.limit);
+ case X86_GDB_LDT_SELECTOR:
+ return gdb_get_reg32(buf, env->ldt.selector);
+ case X86_GDB_LDT_BASE:
+ return gdb_get_reg64(buf, env->ldt.base);
+ case X86_GDB_LDT_LIMIT:
+ return gdb_get_reg32(buf, env->ldt.limit);
+ case X86_GDB_LDT_FLAGS:
+ return gdb_get_reg32(buf, env->ldt.flags);
+ case X86_GDB_TR_SELECTOR:
+ return gdb_get_reg32(buf, env->tr.selector);
+ case X86_GDB_TR_BASE:
+ return gdb_get_reg64(buf, env->tr.base);
+ case X86_GDB_TR_LIMIT:
+ return gdb_get_reg32(buf, env->tr.limit);
+ case X86_GDB_TR_FLAGS:
+ return gdb_get_reg32(buf, env->tr.flags);
+ case X86_GDB_DR0 ... X86_GDB_DR3:
+ return gdb_get_reg64(buf, env->dr[n - X86_GDB_DR0]);
+ case X86_GDB_DR6:
+ return gdb_get_reg64(buf, env->dr[6]);
+ case X86_GDB_DR7:
+ return gdb_get_reg64(buf, env->dr[7]);
+ case X86_GDB_CPL:
+ return gdb_get_reg32(buf, env->hflags & HF_CPL_MASK);
+ case X86_GDB_II:
+ return gdb_get_reg32(buf, !!(env->hflags & HF_INHIBIT_IRQ_MASK));
+ case X86_GDB_A20:
+ return gdb_get_reg32(buf, (env->a20_mask >> 20) & 1);
+ case X86_GDB_SMM:
+ return gdb_get_reg32(buf, !!(env->hflags & HF_SMM_MASK));
+ case X86_GDB_HLT:
+ return gdb_get_reg32(buf, cs->halted);
+ case X86_GDB_XCR0:
+ return gdb_get_reg64(buf, env->xcr0);
+ case X86_GDB_FTW:
+ return gdb_get_reg8(buf, x86_fptags_to_abridged(env));
+ default:
return 0;
}
- return gdb_get_reg32(buf, env->segs[segments[n]].limit);
}
static int x86_gdb_write_system(CPUState *cs, uint8_t *buf, int n)
{
- /* Segment caches are exposed for inspection only. Ignore writes. */
- return 4;
+ /* System registers are exposed for inspection only. Ignore writes. */
+ static const uint8_t sizes[X86_GDB_SYSTEM_COUNT] = {
+ [X86_GDB_SEG_LIMIT_FIRST ... X86_GDB_SEG_LIMIT_LAST] = 4,
+ [X86_GDB_SEG_BASE_FIRST ... X86_GDB_SEG_BASE_LAST] = 8,
+ [X86_GDB_SEG_FLAGS_FIRST ... X86_GDB_SEG_FLAGS_LAST] = 4,
+ [X86_GDB_GDT_BASE] = 8, [X86_GDB_GDT_LIMIT] = 4,
+ [X86_GDB_IDT_BASE] = 8, [X86_GDB_IDT_LIMIT] = 4,
+ [X86_GDB_LDT_SELECTOR] = 4, [X86_GDB_LDT_BASE] = 8,
+ [X86_GDB_LDT_LIMIT] = 4, [X86_GDB_LDT_FLAGS] = 4,
+ [X86_GDB_TR_SELECTOR] = 4, [X86_GDB_TR_BASE] = 8,
+ [X86_GDB_TR_LIMIT] = 4, [X86_GDB_TR_FLAGS] = 4,
+ [X86_GDB_DR0 ... X86_GDB_DR7] = 8,
+ [X86_GDB_CPL] = 4, [X86_GDB_II] = 4,
+ [X86_GDB_A20] = 4, [X86_GDB_SMM] = 4,
+ [X86_GDB_HLT] = 4, [X86_GDB_XCR0] = 8,
+ [X86_GDB_FTW] = 1,
+ };
+
+ if (n < 0 || n >= X86_GDB_SYSTEM_COUNT) {
+ return 0;
+ }
+ return sizes[n];
}
#endif
@@ -559,9 +673,11 @@ void x86_cpu_gdb_init(CPUState *cs)
#endif
#endif
#ifndef CONFIG_USER_ONLY
- gdb_register_internal_coprocessor(
- cs, x86_gdb_read_system,
- x86_gdb_write_system,
- gdb_find_static_feature("i386-system.xml"));
+ {
+ const GDBFeature *sysregs = gdb_find_static_feature("i386-system.xml");
+ g_assert(sysregs->num_regs == X86_GDB_SYSTEM_COUNT);
+ gdb_register_internal_coprocessor(cs, x86_gdb_read_system,
+ x86_gdb_write_system, sysregs);
+ }
#endif
}
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 10/18] target/i386: expose AVX/AVX-512 registers to GDB
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (8 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 09/18] target/i386: expose system registers to monitors via gdbstub Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 11/18] target/i386: drop HMP $pc Marc-André Lureau
` (8 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Register the standard GDB target description features for AVX and
AVX-512, so that GDB clients can inspect and modify vector state:
- org.gnu.gdb.i386.avx (requires CPUID_EXT_AVX):
YMM upper halves (ymm0h..ymm7h for 32-bit, ymm0h..ymm15h for
64-bit). GDB synthesizes full ymm0..ymm15 pseudo-registers by
concatenating xmm + ymmh.
- org.gnu.gdb.i386.avx512 (requires CPUID_7_0_EBX_AVX512F):
32-bit: k0..k7 opmask + zmm0h..zmm7h upper halves.
64-bit: xmm16..xmm31, ymm16h..ymm31h, k0..k7 opmask,
zmm0h..zmm31h upper halves.
GDB synthesizes full zmm0..zmm31 pseudo-registers from the
xmm + ymmh + zmmh components.
The XML descriptions and register layouts match the GDB feature
definitions from binutils-gdb (gdb/features/i386/).
Features are conditionally registered based on the CPU model's CPUID.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/i386-bsd-user.mak | 2 +-
configs/targets/i386-linux-user.mak | 2 +-
configs/targets/i386-softmmu.mak | 2 +-
configs/targets/x86_64-bsd-user.mak | 2 +-
configs/targets/x86_64-linux-user.mak | 2 +-
configs/targets/x86_64-softmmu.mak | 2 +-
gdbstub/gdb-xml/i386-32bit-avx.xml | 20 +++++
gdbstub/gdb-xml/i386-32bit-avx512.xml | 31 +++++++
gdbstub/gdb-xml/i386-64bit-avx.xml | 28 +++++++
gdbstub/gdb-xml/i386-64bit-avx512.xml | 108 ++++++++++++++++++++++++
target/i386/gdbstub.c | 154 +++++++++++++++++++++++++++++++++-
11 files changed, 346 insertions(+), 7 deletions(-)
diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-user.mak
index b2a8b0a42ad9..18e618258cc6 100644
--- a/configs/targets/i386-bsd-user.mak
+++ b/configs/targets/i386-bsd-user.mak
@@ -1,3 +1,3 @@
TARGET_ARCH=i386
-TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i386-32bit-avx512.xml
TARGET_LONG_BITS=32
diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-linux-user.mak
index 234e600860a3..6b9869a6d253 100644
--- a/configs/targets/i386-linux-user.mak
+++ b/configs/targets/i386-linux-user.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=i386
TARGET_SYSTBL_ABI=i386
TARGET_SYSTBL=syscall_32.tbl
-TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-32bit-linux.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i386-32bit-avx512.xml i386-32bit-linux.xml
TARGET_LONG_BITS=32
diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak
index a53ee07255b4..05cc0bf29716 100644
--- a/configs/targets/i386-softmmu.mak
+++ b/configs/targets/i386-softmmu.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-system.xml
+TARGET_XML_FILES= i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i386-32bit-avx512.xml i386-system.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-bsd-user.mak
index f36a9ccbd60a..e157dd9935bd 100644
--- a/configs/targets/x86_64-bsd-user.mak
+++ b/configs/targets/x86_64-bsd-user.mak
@@ -1,4 +1,4 @@
TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i386-64bit-avx512.xml i386-64bit-apx.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64-linux-user.mak
index 77a035b7eb4c..cc65f1333c3e 100644
--- a/configs/targets/x86_64-linux-user.mak
+++ b/configs/targets/x86_64-linux-user.mak
@@ -2,5 +2,5 @@ TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall_64.tbl
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-linux.xml i386-64bit-apx.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i386-64bit-avx512.xml i386-64bit-linux.xml i386-64bit-apx.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak
index c04fdf2d3fe8..725db9e4cdb4 100644
--- a/configs/targets/x86_64-softmmu.mak
+++ b/configs/targets/x86_64-softmmu.mak
@@ -2,6 +2,6 @@ TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
-TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml i386-system.xml
+TARGET_XML_FILES= i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i386-64bit-avx512.xml i386-64bit-apx.xml i386-system.xml
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
diff --git a/gdbstub/gdb-xml/i386-32bit-avx.xml b/gdbstub/gdb-xml/i386-32bit-avx.xml
new file mode 100644
index 000000000000..bc6bc28ff19c
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-32bit-avx.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx">
+ <reg name="ymm0h" bitsize="128" type="uint128"/>
+ <reg name="ymm1h" bitsize="128" type="uint128"/>
+ <reg name="ymm2h" bitsize="128" type="uint128"/>
+ <reg name="ymm3h" bitsize="128" type="uint128"/>
+ <reg name="ymm4h" bitsize="128" type="uint128"/>
+ <reg name="ymm5h" bitsize="128" type="uint128"/>
+ <reg name="ymm6h" bitsize="128" type="uint128"/>
+ <reg name="ymm7h" bitsize="128" type="uint128"/>
+</feature>
diff --git a/gdbstub/gdb-xml/i386-32bit-avx512.xml b/gdbstub/gdb-xml/i386-32bit-avx512.xml
new file mode 100644
index 000000000000..764f74f86d6c
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-32bit-avx512.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2014-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx512">
+ <vector id="v2ui128" type="uint128" count="2"/>
+
+ <reg name="k0" bitsize="64" type="uint64"/>
+ <reg name="k1" bitsize="64" type="uint64"/>
+ <reg name="k2" bitsize="64" type="uint64"/>
+ <reg name="k3" bitsize="64" type="uint64"/>
+ <reg name="k4" bitsize="64" type="uint64"/>
+ <reg name="k5" bitsize="64" type="uint64"/>
+ <reg name="k6" bitsize="64" type="uint64"/>
+ <reg name="k7" bitsize="64" type="uint64"/>
+
+ <reg name="zmm0h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm1h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm2h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm3h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm4h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm5h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm6h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm7h" bitsize="256" type="v2ui128"/>
+</feature>
diff --git a/gdbstub/gdb-xml/i386-64bit-avx.xml b/gdbstub/gdb-xml/i386-64bit-avx.xml
new file mode 100644
index 000000000000..d470ee08af30
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-64bit-avx.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx">
+ <reg name="ymm0h" bitsize="128" type="uint128"/>
+ <reg name="ymm1h" bitsize="128" type="uint128"/>
+ <reg name="ymm2h" bitsize="128" type="uint128"/>
+ <reg name="ymm3h" bitsize="128" type="uint128"/>
+ <reg name="ymm4h" bitsize="128" type="uint128"/>
+ <reg name="ymm5h" bitsize="128" type="uint128"/>
+ <reg name="ymm6h" bitsize="128" type="uint128"/>
+ <reg name="ymm7h" bitsize="128" type="uint128"/>
+ <reg name="ymm8h" bitsize="128" type="uint128"/>
+ <reg name="ymm9h" bitsize="128" type="uint128"/>
+ <reg name="ymm10h" bitsize="128" type="uint128"/>
+ <reg name="ymm11h" bitsize="128" type="uint128"/>
+ <reg name="ymm12h" bitsize="128" type="uint128"/>
+ <reg name="ymm13h" bitsize="128" type="uint128"/>
+ <reg name="ymm14h" bitsize="128" type="uint128"/>
+ <reg name="ymm15h" bitsize="128" type="uint128"/>
+</feature>
diff --git a/gdbstub/gdb-xml/i386-64bit-avx512.xml b/gdbstub/gdb-xml/i386-64bit-avx512.xml
new file mode 100644
index 000000000000..79156c561db8
--- /dev/null
+++ b/gdbstub/gdb-xml/i386-64bit-avx512.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2014-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx512">
+ <vector id="v8bf16" type="bfloat16" count="8"/>
+ <vector id="v8h" type="ieee_half" count="8"/>
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v2i64" type="int64" count="2"/>
+ <union id="vec128">
+ <field name="v8_bfloat16" type="v8bf16"/>
+ <field name="v8_half" type="v8h"/>
+ <field name="v4_float" type="v4f"/>
+ <field name="v2_double" type="v2d"/>
+ <field name="v16_int8" type="v16i8"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v2_int64" type="v2i64"/>
+ <field name="uint128" type="uint128"/>
+ </union>
+ <vector id="v2ui128" type="uint128" count="2"/>
+
+ <reg name="xmm16" bitsize="128" type="vec128"/>
+ <reg name="xmm17" bitsize="128" type="vec128"/>
+ <reg name="xmm18" bitsize="128" type="vec128"/>
+ <reg name="xmm19" bitsize="128" type="vec128"/>
+ <reg name="xmm20" bitsize="128" type="vec128"/>
+ <reg name="xmm21" bitsize="128" type="vec128"/>
+ <reg name="xmm22" bitsize="128" type="vec128"/>
+ <reg name="xmm23" bitsize="128" type="vec128"/>
+ <reg name="xmm24" bitsize="128" type="vec128"/>
+ <reg name="xmm25" bitsize="128" type="vec128"/>
+ <reg name="xmm26" bitsize="128" type="vec128"/>
+ <reg name="xmm27" bitsize="128" type="vec128"/>
+ <reg name="xmm28" bitsize="128" type="vec128"/>
+ <reg name="xmm29" bitsize="128" type="vec128"/>
+ <reg name="xmm30" bitsize="128" type="vec128"/>
+ <reg name="xmm31" bitsize="128" type="vec128"/>
+
+ <reg name="ymm16h" bitsize="128" type="uint128"/>
+ <reg name="ymm17h" bitsize="128" type="uint128"/>
+ <reg name="ymm18h" bitsize="128" type="uint128"/>
+ <reg name="ymm19h" bitsize="128" type="uint128"/>
+ <reg name="ymm20h" bitsize="128" type="uint128"/>
+ <reg name="ymm21h" bitsize="128" type="uint128"/>
+ <reg name="ymm22h" bitsize="128" type="uint128"/>
+ <reg name="ymm23h" bitsize="128" type="uint128"/>
+ <reg name="ymm24h" bitsize="128" type="uint128"/>
+ <reg name="ymm25h" bitsize="128" type="uint128"/>
+ <reg name="ymm26h" bitsize="128" type="uint128"/>
+ <reg name="ymm27h" bitsize="128" type="uint128"/>
+ <reg name="ymm28h" bitsize="128" type="uint128"/>
+ <reg name="ymm29h" bitsize="128" type="uint128"/>
+ <reg name="ymm30h" bitsize="128" type="uint128"/>
+ <reg name="ymm31h" bitsize="128" type="uint128"/>
+
+ <reg name="k0" bitsize="64" type="uint64"/>
+ <reg name="k1" bitsize="64" type="uint64"/>
+ <reg name="k2" bitsize="64" type="uint64"/>
+ <reg name="k3" bitsize="64" type="uint64"/>
+ <reg name="k4" bitsize="64" type="uint64"/>
+ <reg name="k5" bitsize="64" type="uint64"/>
+ <reg name="k6" bitsize="64" type="uint64"/>
+ <reg name="k7" bitsize="64" type="uint64"/>
+
+ <reg name="zmm0h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm1h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm2h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm3h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm4h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm5h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm6h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm7h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm8h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm9h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm10h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm11h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm12h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm13h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm14h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm15h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm16h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm17h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm18h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm19h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm20h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm21h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm22h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm23h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm24h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm25h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm26h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm27h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm28h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm29h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm30h" bitsize="256" type="v2ui128"/>
+ <reg name="zmm31h" bitsize="256" type="v2ui128"/>
+</feature>
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 9a46c46ecff9..8b89f2260a4c 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -422,6 +422,141 @@ static int x86_gdb_write_sse(CPUState *cs, uint8_t *buf, int n)
return 0;
}
+/*
+ * AVX feature (org.gnu.gdb.i386.avx) — YMM upper halves.
+ *
+ * Register layout: ymm0h..ymm(N-1)h, each 128-bit.
+ * N = CPU_NB_REGS (8 for 32-bit, 16 for 64-bit).
+ */
+static int x86_gdb_read_avx(CPUState *cs, GByteArray *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+
+ if (n < 0 || n >= CPU_NB_REGS) {
+ return 0;
+ }
+ return gdb_get_reg128(buf,
+ env->xmm_regs[n].ZMM_Q(3),
+ env->xmm_regs[n].ZMM_Q(2));
+}
+
+static int x86_gdb_write_avx(CPUState *cs, uint8_t *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+
+ if (n < 0 || n >= CPU_NB_REGS) {
+ return 0;
+ }
+ env->xmm_regs[n].ZMM_Q(2) = ldq_p(buf);
+ env->xmm_regs[n].ZMM_Q(3) = ldq_p(buf + 8);
+ return 16;
+}
+
+/*
+ * AVX-512 feature (org.gnu.gdb.i386.avx512).
+ *
+ * 32-bit layout (CPU_NB_REGS == 8):
+ * n = 0..7 k0..k7 (64-bit opmask)
+ * n = 8..15 zmm0h..zmm7h (256-bit ZMM upper halves)
+ *
+ * 64-bit layout (CPU_NB_REGS == 16):
+ * n = 0..15 xmm16..xmm31 (128-bit)
+ * n = 16..31 ymm16h..ymm31h (128-bit)
+ * n = 32..39 k0..k7 (64-bit opmask)
+ * n = 40..71 zmm0h..zmm31h (256-bit ZMM upper halves)
+ */
+#ifdef TARGET_X86_64
+enum {
+ X86_GDB_AVX512_XMM16_FIRST = 0,
+ X86_GDB_AVX512_YMM16H_FIRST = 16,
+ X86_GDB_AVX512_OPMASK_FIRST = 32,
+ X86_GDB_AVX512_ZMM_FIRST = 40,
+ X86_GDB_AVX512_COUNT = 72,
+};
+#else
+enum {
+ X86_GDB_AVX512_OPMASK_FIRST = 0,
+ X86_GDB_AVX512_ZMM_FIRST = NB_OPMASK_REGS,
+ X86_GDB_AVX512_COUNT = NB_OPMASK_REGS + CPU_NB_REGS,
+};
+#endif
+
+static int x86_gdb_read_avx512(CPUState *cs, GByteArray *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+ int reg;
+
+ if (n < 0 || n >= X86_GDB_AVX512_COUNT) {
+ return 0;
+ }
+
+#ifdef TARGET_X86_64
+ if (n < X86_GDB_AVX512_YMM16H_FIRST) {
+ /* xmm16..xmm31: lower 128 bits */
+ reg = 16 + n;
+ return gdb_get_reg128(buf,
+ env->xmm_regs[reg].ZMM_Q(1),
+ env->xmm_regs[reg].ZMM_Q(0));
+ }
+ if (n < X86_GDB_AVX512_OPMASK_FIRST) {
+ /* ymm16h..ymm31h: upper 128 bits of YMM */
+ reg = 16 + (n - X86_GDB_AVX512_YMM16H_FIRST);
+ return gdb_get_reg128(buf,
+ env->xmm_regs[reg].ZMM_Q(3),
+ env->xmm_regs[reg].ZMM_Q(2));
+ }
+#endif
+ if (n < X86_GDB_AVX512_ZMM_FIRST) {
+ /* k0..k7: opmask registers */
+ return gdb_get_reg64(buf,
+ env->opmask_regs[n - X86_GDB_AVX512_OPMASK_FIRST]);
+ }
+ /* zmm0h..zmm(N-1)h: upper 256 bits of ZMM */
+ reg = n - X86_GDB_AVX512_ZMM_FIRST;
+ for (int i = 4; i < 8; i++) {
+ gdb_get_reg64(buf, env->xmm_regs[reg].ZMM_Q(i));
+ }
+ return 32;
+}
+
+static int x86_gdb_write_avx512(CPUState *cs, uint8_t *buf, int n)
+{
+ CPUX86State *env = cpu_env(cs);
+ int reg;
+
+ if (n < 0 || n >= X86_GDB_AVX512_COUNT) {
+ return 0;
+ }
+
+#ifdef TARGET_X86_64
+ if (n < X86_GDB_AVX512_YMM16H_FIRST) {
+ /* xmm16..xmm31 */
+ reg = 16 + n;
+ env->xmm_regs[reg].ZMM_Q(0) = ldq_p(buf);
+ env->xmm_regs[reg].ZMM_Q(1) = ldq_p(buf + 8);
+ return 16;
+ }
+ if (n < X86_GDB_AVX512_OPMASK_FIRST) {
+ /* ymm16h..ymm31h */
+ reg = 16 + (n - X86_GDB_AVX512_YMM16H_FIRST);
+ env->xmm_regs[reg].ZMM_Q(2) = ldq_p(buf);
+ env->xmm_regs[reg].ZMM_Q(3) = ldq_p(buf + 8);
+ return 16;
+ }
+#endif
+ if (n < X86_GDB_AVX512_ZMM_FIRST) {
+ /* k0..k7 */
+ env->opmask_regs[n - X86_GDB_AVX512_OPMASK_FIRST] = ldq_p(buf);
+ return 8;
+ }
+ /* zmm0h..zmm(N-1)h */
+ reg = n - X86_GDB_AVX512_ZMM_FIRST;
+ for (int i = 0; i < 4; i++) {
+ env->xmm_regs[reg].ZMM_Q(4 + i) = ldq_p(buf + i * 8);
+ }
+ return 32;
+}
+
#ifdef CONFIG_LINUX_USER
#define IDX_ORIG_AX 0
@@ -644,16 +779,33 @@ static int x86_gdb_write_system(CPUState *cs, uint8_t *buf, int n)
void x86_cpu_gdb_init(CPUState *cs)
{
+ CPUX86State *env = cpu_env(cs);
#ifdef TARGET_X86_64
- CPUX86State *env = &X86_CPU(cs)->env;
const char *sse_xml = "i386-64bit-sse.xml";
+ const char *avx_xml = "i386-64bit-avx.xml";
+ const char *avx512_xml = "i386-64bit-avx512.xml";
#else
const char *sse_xml = "i386-32bit-sse.xml";
+ const char *avx_xml = "i386-32bit-avx.xml";
+ const char *avx512_xml = "i386-32bit-avx512.xml";
#endif
gdb_register_coprocessor(cs, x86_gdb_read_sse, x86_gdb_write_sse,
gdb_find_static_feature(sse_xml));
+ if (env->features[FEAT_1_ECX] & CPUID_EXT_AVX) {
+ const GDBFeature *avx = gdb_find_static_feature(avx_xml);
+ g_assert(avx->num_regs == CPU_NB_REGS);
+ gdb_register_coprocessor(cs, x86_gdb_read_avx,
+ x86_gdb_write_avx, avx);
+ }
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_AVX512F) {
+ const GDBFeature *avx512 = gdb_find_static_feature(avx512_xml);
+ g_assert(avx512->num_regs == X86_GDB_AVX512_COUNT);
+ gdb_register_coprocessor(cs, x86_gdb_read_avx512,
+ x86_gdb_write_avx512, avx512);
+ }
+
#ifdef TARGET_X86_64
if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) {
gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs,
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 11/18] target/i386: drop HMP $pc
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (9 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 10/18] target/i386: expose AVX/AVX-512 registers to GDB Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 23:34 ` Dr. David Alan Gilbert
2026-10-22 10:56 ` [PATCH v3 12/18] MAINTAINERS: cover m68k GDB XML files Marc-André Lureau
` (7 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau,
Fabiano Rosas, Laurent Vivier
The to be deprecated MonitorDef provided a synthetic $pc alias on
x86 (which begin as an $eip alias). Preserving it requires x86-specific
semantics (CPUClass::get_pc() omits the historical truncation).
Use $eip or $rip instead, adding $cs.base as required.
It was never a documented feature, HMP is not a stable API, x86-only,
and the replacement ($rip/$eip + $cs.base) is arguably more correct.
Nobody asked for a deprecation window on ML either.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
docs/about/removed-features.rst | 8 ++++++++
target/i386/cpu.c | 23 -----------------------
tests/qtest/test-hmp.c | 1 -
3 files changed, 8 insertions(+), 24 deletions(-)
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index 6a9944a0c794..444169b5b718 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -908,6 +908,14 @@ Use ``multifd-channels`` instead.
Use ``multifd-compression`` instead.
+``$pc`` register alias on x86 (removed in 11.2)
+'''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``$pc`` alias (the linear instruction pointer) is no longer
+recognized in HMP expressions. Use ``$rip`` or ``$eip`` (depending
+on the target) instead, adding ``$cs.base`` when the linear address
+is needed.
+
Host Architectures
------------------
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2f5ea4e51715..a28c3033ba6d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -42,7 +42,6 @@
#include "exec/watchpoint.h"
#ifndef CONFIG_USER_ONLY
#include "confidential-guest.h"
-#include "monitor/hmp.h"
#include "system/reset.h"
#include "qapi/qapi-commands-machine.h"
#include "system/qmp-cpu.h"
@@ -10907,25 +10906,6 @@ static const Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
-#ifdef CONFIG_HMP
-static int64_t monitor_get_pc(MonitorHMP *hmp, const struct MonitorDef *md,
- int offset)
-{
- CPUArchState *env = monitor_hmp_get_cpu_env(hmp);
- int64_t ret = env->eip + env->segs[R_CS].base;
-
- if (!(env->hflags & HF_CS64_MASK)) {
- ret = (int32_t)ret;
- }
- return ret;
-}
-
-static const MonitorDef x86_monitor_defs[] = {
- { "pc", 0, monitor_get_pc, },
- { NULL },
-};
-#endif
-
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
@@ -10939,9 +10919,6 @@ static const struct SysemuCPUOps i386_sysemu_ops = {
.write_elf64_note = x86_cpu_write_elf64_note,
.write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
.write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
-#ifdef CONFIG_HMP
- .monitor_defs = x86_monitor_defs,
-#endif
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
index a523dbb446ce..b3f8fd58612d 100644
--- a/tests/qtest/test-hmp.c
+++ b/tests/qtest/test-hmp.c
@@ -58,7 +58,6 @@ static const char *hmp_cmds[] = {
"object_del mem1",
"one-insn-per-tb on",
"pmemsave 0 4096 \"/dev/null\"",
- "p $pc + 8",
"qom-list /",
"qom-set /machine initrd test",
"qom-get /machine initrd",
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 11/18] target/i386: drop HMP $pc
2026-10-22 10:56 ` [PATCH v3 11/18] target/i386: drop HMP $pc Marc-André Lureau
@ 2026-10-22 23:34 ` Dr. David Alan Gilbert
2026-10-23 20:45 ` Marc-André Lureau
0 siblings, 1 reply; 31+ messages in thread
From: Dr. David Alan Gilbert @ 2026-10-22 23:34 UTC (permalink / raw)
To: Marc-André Lureau
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Fabiano Rosas,
Laurent Vivier
* Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> The to be deprecated MonitorDef provided a synthetic $pc alias on
> x86 (which begin as an $eip alias). Preserving it requires x86-specific
> semantics (CPUClass::get_pc() omits the historical truncation).
> Use $eip or $rip instead, adding $cs.base as required.
>
> It was never a documented feature, HMP is not a stable API, x86-only,
> and the replacement ($rip/$eip + $cs.base) is arguably more correct.
> Nobody asked for a deprecation window on ML either.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
<snip>
> diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
> index a523dbb446ce..b3f8fd58612d 100644
> --- a/tests/qtest/test-hmp.c
> +++ b/tests/qtest/test-hmp.c
> @@ -58,7 +58,6 @@ static const char *hmp_cmds[] = {
> "object_del mem1",
> "one-insn-per-tb on",
> "pmemsave 0 4096 \"/dev/null\"",
> - "p $pc + 8",
That leaves us with no test of the 'p' command, and no test of reading
a register.
Given how much you're changing accessing the registers you
should still have a basic test by the end.
How does this test work on S390 where 'info registers' shows
NIP but 'p $pc' works but 'p $nip' doesn't?
I assume gdb also has some concept of a 'pc' at it's end?
Dave
> "qom-list /",
> "qom-set /machine initrd test",
> "qom-get /machine initrd",
>
> --
> 2.56.0.116.g6de20f6092dc
>
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 11/18] target/i386: drop HMP $pc
2026-10-22 23:34 ` Dr. David Alan Gilbert
@ 2026-10-23 20:45 ` Marc-André Lureau
2026-10-23 22:51 ` Dr. David Alan Gilbert
0 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-23 20:45 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Fabiano Rosas,
Laurent Vivier
Hi
On Fri, Oct 23, 2026 at 3:35 AM Dr. David Alan Gilbert <dave@treblig.org> wrote:
>
> * Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> > The to be deprecated MonitorDef provided a synthetic $pc alias on
> > x86 (which begin as an $eip alias). Preserving it requires x86-specific
> > semantics (CPUClass::get_pc() omits the historical truncation).
> > Use $eip or $rip instead, adding $cs.base as required.
> >
> > It was never a documented feature, HMP is not a stable API, x86-only,
> > and the replacement ($rip/$eip + $cs.base) is arguably more correct.
> > Nobody asked for a deprecation window on ML either.
> >
> > Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
>
> <snip>
>
> > diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
> > index a523dbb446ce..b3f8fd58612d 100644
> > --- a/tests/qtest/test-hmp.c
> > +++ b/tests/qtest/test-hmp.c
> > @@ -58,7 +58,6 @@ static const char *hmp_cmds[] = {
> > "object_del mem1",
> > "one-insn-per-tb on",
> > "pmemsave 0 4096 \"/dev/null\"",
> > - "p $pc + 8",
>
> That leaves us with no test of the 'p' command, and no test of reading
> a register.
> Given how much you're changing accessing the registers you
> should still have a basic test by the end.
The existing test doesn't really do much though, it just checks we
don't crash basically. I can try addressing this as a followup
>
> How does this test work on S390 where 'info registers' shows
> NIP but 'p $pc' works but 'p $nip' doesn't?
I assume you are talking about gdb, since $pc doesn't work with HMP-S390.
>
> I assume gdb also has some concept of a 'pc' at it's end?
GDB has extra synthetic pseudo-registers. We have a bunch in QEMU (and
this series add more). We can add extra as necessary. But $pc for x86
is currently ill-defined, so we decided to drop it earlier.
> Dave
>
>
> > "qom-list /",
> > "qom-set /machine initrd test",
> > "qom-get /machine initrd",
> >
> > --
> > 2.56.0.116.g6de20f6092dc
> >
> --
> -----Open up your eyes, open up your mind, open up your code -------
> / Dr. David Alan Gilbert | Running GNU/Linux | Happy \
> \ dave @ treblig.org | | In Hex /
> \ _________________________|_____ http://www.treblig.org |_______/
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 11/18] target/i386: drop HMP $pc
2026-10-23 20:45 ` Marc-André Lureau
@ 2026-10-23 22:51 ` Dr. David Alan Gilbert
0 siblings, 0 replies; 31+ messages in thread
From: Dr. David Alan Gilbert @ 2026-10-23 22:51 UTC (permalink / raw)
To: Marc-André Lureau
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Fabiano Rosas,
Laurent Vivier
* Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> Hi
>
> On Fri, Oct 23, 2026 at 3:35 AM Dr. David Alan Gilbert <dave@treblig.org> wrote:
> >
> > * Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> > > The to be deprecated MonitorDef provided a synthetic $pc alias on
> > > x86 (which begin as an $eip alias). Preserving it requires x86-specific
> > > semantics (CPUClass::get_pc() omits the historical truncation).
> > > Use $eip or $rip instead, adding $cs.base as required.
> > >
> > > It was never a documented feature, HMP is not a stable API, x86-only,
> > > and the replacement ($rip/$eip + $cs.base) is arguably more correct.
> > > Nobody asked for a deprecation window on ML either.
> > >
> > > Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> >
> > <snip>
> >
> > > diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
> > > index a523dbb446ce..b3f8fd58612d 100644
> > > --- a/tests/qtest/test-hmp.c
> > > +++ b/tests/qtest/test-hmp.c
> > > @@ -58,7 +58,6 @@ static const char *hmp_cmds[] = {
> > > "object_del mem1",
> > > "one-insn-per-tb on",
> > > "pmemsave 0 4096 \"/dev/null\"",
> > > - "p $pc + 8",
> >
> > That leaves us with no test of the 'p' command, and no test of reading
> > a register.
> > Given how much you're changing accessing the registers you
> > should still have a basic test by the end.
>
> The existing test doesn't really do much though, it just checks we
> don't crash basically. I can try addressing this as a followup
>
> >
> > How does this test work on S390 where 'info registers' shows
> > NIP but 'p $pc' works but 'p $nip' doesn't?
>
> I assume you are talking about gdb, since $pc doesn't work with HMP-S390.
Oh! It was that test I was worried about, so that 'p $pc + 8' fails
on s390 - with an 'unknown register'; so yes, removing the x86 one doesn't
make any difference then.
> > I assume gdb also has some concept of a 'pc' at it's end?
>
> GDB has extra synthetic pseudo-registers. We have a bunch in QEMU (and
> this series add more). We can add extra as necessary. But $pc for x86
> is currently ill-defined, so we decided to drop it earlier.
OK, it was just that loss of the test for reading $pc which worried me;
hmm it would be great if we could find a way to add a test back in the future
for register reading.
Given that it already silently fails on s390, you could actually leave
that test line in and when run on any non-(x86, s390) it would test the
reading still.
Dave
> > Dave
> >
> >
> > > "qom-list /",
> > > "qom-set /machine initrd test",
> > > "qom-get /machine initrd",
> > >
> > > --
> > > 2.56.0.116.g6de20f6092dc
> > >
> > --
> > -----Open up your eyes, open up your mind, open up your code -------
> > / Dr. David Alan Gilbert | Running GNU/Linux | Happy \
> > \ dave @ treblig.org | | In Hex /
> > \ _________________________|_____ http://www.treblig.org |_______/
> >
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 12/18] MAINTAINERS: cover m68k GDB XML files
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (10 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 11/18] target/i386: drop HMP $pc Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 21:51 ` Pierrick Bouvier
2026-10-22 10:56 ` [PATCH v3 13/18] target/m68k: expose system registers to monitors via gdbstub Marc-André Lureau
` (6 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Add entries so changes to these files are routed to the m68k
maintainers.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f22333fbf177..de3cb9dcaf25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -303,6 +303,8 @@ M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
F: target/m68k/
F: disas/m68k.c
+F: gdbstub/gdb-xml/cf*.xml
+F: gdbstub/gdb-xml/m68k*.xml
F: tests/functional/m68k/meson.build
F: tests/tcg/m68k/
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 12/18] MAINTAINERS: cover m68k GDB XML files
2026-10-22 10:56 ` [PATCH v3 12/18] MAINTAINERS: cover m68k GDB XML files Marc-André Lureau
@ 2026-10-22 21:51 ` Pierrick Bouvier
0 siblings, 0 replies; 31+ messages in thread
From: Pierrick Bouvier @ 2026-10-22 21:51 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller, Warner Losh,
Kyle Evans
On 10/22/2026 3:56 AM, Marc-André Lureau wrote:
> Add entries so changes to these files are routed to the m68k
> maintainers.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 13/18] target/m68k: expose system registers to monitors via gdbstub
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (11 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 12/18] MAINTAINERS: cover m68k GDB XML files Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 14/18] target/sparc64: " Marc-André Lureau
` (5 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Replace the HMP-specific MonitorDef with a GDB feature that exposes
supervisor stack pointers (ssp, usp, isp), function code registers (sfc,
dfc), MMU registers (urp, srp, dttr0/1, ittr0/1, mmusr) as read-only
system registers through the internal GDB coprocessor interface.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/m68k-softmmu.mak | 2 +-
gdbstub/gdb-xml/m68k-system.xml | 32 ++++++++++++++++++++++++++
target/m68k/cpu.c | 22 ------------------
target/m68k/helper.c | 49 +++++++++++++++++++++++++++++++++++++++-
4 files changed, 81 insertions(+), 24 deletions(-)
diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmmu.mak
index 0bc889f326e3..f3ac9b74c862 100644
--- a/configs/targets/m68k-softmmu.mak
+++ b/configs/targets/m68k-softmmu.mak
@@ -1,4 +1,4 @@
TARGET_ARCH=m68k
TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml
+TARGET_XML_FILES= cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml m68k-system.xml
TARGET_LONG_BITS=32
diff --git a/gdbstub/gdb-xml/m68k-system.xml b/gdbstub/gdb-xml/m68k-system.xml
new file mode 100644
index 000000000000..0a91be0edc00
--- /dev/null
+++ b/gdbstub/gdb-xml/m68k-system.xml
@@ -0,0 +1,32 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- System-register values are read-only; writes are ignored. -->
+<feature name="org.qemu.gdb.m68k.system">
+ <reg name="ssp" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="usp" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="isp" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="sfc" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="dfc" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="urp" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="srp" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="dttr0" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="dttr1" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="ittr0" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="ittr1" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="mmusr" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+</feature>
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 9b52ad5fc234..ad7303305848 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -25,7 +25,6 @@
#include "disas/capstone.h"
#ifndef CONFIG_USER_ONLY
#include "migration/vmstate.h"
-#include "monitor/hmp.h"
#endif
#include "cpu.h"
@@ -666,32 +665,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
},
};
-#ifdef CONFIG_HMP
-static const MonitorDef m68k_monitor_defs[] = {
- { "ssp", offsetof(CPUM68KState, sp[0]) },
- { "usp", offsetof(CPUM68KState, sp[1]) },
- { "isp", offsetof(CPUM68KState, sp[2]) },
- { "sfc", offsetof(CPUM68KState, sfc) },
- { "dfc", offsetof(CPUM68KState, dfc) },
- { "urp", offsetof(CPUM68KState, mmu.urp) },
- { "srp", offsetof(CPUM68KState, mmu.srp) },
- { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) },
- { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) },
- { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) },
- { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) },
- { "mmusr", offsetof(CPUM68KState, mmu.mmusr) },
- { NULL },
-};
-#endif
-
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps m68k_sysemu_ops = {
.has_work = m68k_cpu_has_work,
.get_phys_addr_debug = m68k_cpu_get_phys_addr_debug,
-#ifdef CONFIG_HMP
- .monitor_defs = m68k_monitor_defs,
-#endif
};
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 5f91d206f596..1a29eaaf37f6 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -123,6 +123,48 @@ static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
return 0;
}
+#ifndef CONFIG_USER_ONLY
+static int m68k_gdb_read_system_register(CPUState *cs, GByteArray *buf, int n)
+{
+ CPUM68KState *env = cpu_env(cs);
+ static const int stacks[] = { M68K_SSP, M68K_USP, M68K_ISP };
+
+ if (n >= 0 && n < ARRAY_SIZE(stacks)) {
+ int sp = stacks[n];
+
+ return gdb_get_reg32(buf, env->sp[sp]);
+ }
+ switch (n) {
+ case 3:
+ return gdb_get_reg32(buf, env->sfc);
+ case 4:
+ return gdb_get_reg32(buf, env->dfc);
+ case 5:
+ return gdb_get_reg32(buf, env->mmu.urp);
+ case 6:
+ return gdb_get_reg32(buf, env->mmu.srp);
+ case 7:
+ return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR0]);
+ case 8:
+ return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR1]);
+ case 9:
+ return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR0]);
+ case 10:
+ return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR1]);
+ case 11:
+ return gdb_get_reg32(buf, env->mmu.mmusr);
+ default:
+ return 0;
+ }
+}
+
+static int m68k_gdb_write_system_register(CPUState *cs, uint8_t *buf, int n)
+{
+ /* These registers are exposed for inspection only. Ignore writes. */
+ return 4;
+}
+#endif
+
void m68k_cpu_init_gdb(M68kCPU *cpu)
{
CPUState *cs = CPU(cpu);
@@ -135,7 +177,12 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_set_reg,
gdb_find_static_feature("m68k-fp.xml"));
}
- /* TODO: Add [E]MAC registers. */
+ /* TODO: Add [E]MAC registers. */
+#ifndef CONFIG_USER_ONLY
+ gdb_register_internal_coprocessor(cs, m68k_gdb_read_system_register,
+ m68k_gdb_write_system_register,
+ gdb_find_static_feature("m68k-system.xml"));
+#endif
}
void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 14/18] target/sparc64: expose system registers to monitors via gdbstub
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (12 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 13/18] target/m68k: expose system registers to monitors via gdbstub Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 15/18] target/riscv: bypass smstateen check in debugger mode Marc-André Lureau
` (4 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Replace the HMP-specific MonitorDef with a GDB feature that exposes
asi, pstate, cansave, canrestore, otherwin, wstate, and cleanwin as
read-only system registers through the internal GDB coprocessor
interface.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/sparc64-softmmu.mak | 2 +-
gdbstub/gdb-xml/sparc64-system.xml | 22 +++++++++++++++++++++
target/sparc/cpu.c | 19 -------------------
target/sparc/gdbstub.c | 38 +++++++++++++++++++++++++++++++++++++
4 files changed, 61 insertions(+), 20 deletions(-)
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index 4e621fb8e39e..7f2789136653 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES=sparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml
+TARGET_XML_FILES=sparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml sparc64-system.xml
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/gdbstub/gdb-xml/sparc64-system.xml b/gdbstub/gdb-xml/sparc64-system.xml
new file mode 100644
index 000000000000..e00baedb467e
--- /dev/null
+++ b/gdbstub/gdb-xml/sparc64-system.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- System-register values are read-only; writes are ignored. -->
+<feature name="org.qemu.gdb.sparc.system">
+ <reg name="asi" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="pstate" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="cansave" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="canrestore" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="otherwin" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="wstate" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+ <reg name="cleanwin" bitsize="32" type="uint32"
+ group="qemu-debug" save-restore="no"/>
+</feature>
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ae9bdca9df82..89dfb091ca87 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -995,31 +995,12 @@ static const Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
-#ifdef TARGET_SPARC64
-#include "monitor/hmp.h"
-#ifdef CONFIG_HMP
-static const MonitorDef sparc64_monitor_defs[] = {
- { "asi", offsetof(CPUSPARCState, asi) },
- { "pstate", offsetof(CPUSPARCState, pstate) },
- { "cansave", offsetof(CPUSPARCState, cansave) },
- { "canrestore", offsetof(CPUSPARCState, canrestore) },
- { "otherwin", offsetof(CPUSPARCState, otherwin) },
- { "wstate", offsetof(CPUSPARCState, wstate) },
- { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
- { NULL },
-};
-#endif
-#endif
-
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps sparc_sysemu_ops = {
.has_work = sparc_cpu_has_work,
.get_phys_addr_debug = sparc_cpu_get_phys_addr_debug,
.legacy_vmsd = &vmstate_sparc_cpu,
-#if defined(TARGET_SPARC64) && defined(CONFIG_HMP)
- .monitor_defs = sparc64_monitor_defs,
-#endif
};
#endif
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index 2874ce1b3501..c8aa74a4a8b7 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -266,6 +266,39 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
#endif
}
+#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+static int sparc64_gdb_read_system_register(CPUState *cs, GByteArray *buf,
+ int n)
+{
+ CPUSPARCState *env = cpu_env(cs);
+
+ switch (n) {
+ case 0:
+ return gdb_get_reg32(buf, env->asi);
+ case 1:
+ return gdb_get_reg32(buf, env->pstate);
+ case 2:
+ return gdb_get_reg32(buf, env->cansave);
+ case 3:
+ return gdb_get_reg32(buf, env->canrestore);
+ case 4:
+ return gdb_get_reg32(buf, env->otherwin);
+ case 5:
+ return gdb_get_reg32(buf, env->wstate);
+ case 6:
+ return gdb_get_reg32(buf, env->cleanwin);
+ default:
+ return 0;
+ }
+}
+
+static int sparc64_gdb_write_system_register(CPUState *cs, uint8_t *buf, int n)
+{
+ /* These registers are exposed for inspection only. Ignore writes. */
+ return 4;
+}
+#endif
+
void sparc_cpu_register_gdb_regs(CPUState *cs)
{
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
@@ -282,5 +315,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs)
gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,
sparc_cp0_gdb_write_register,
gdb_find_static_feature("sparc64-cp0.xml"));
+#ifndef CONFIG_USER_ONLY
+ gdb_register_internal_coprocessor(cs, sparc64_gdb_read_system_register,
+ sparc64_gdb_write_system_register,
+ gdb_find_static_feature("sparc64-system.xml"));
+#endif
#endif
}
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 15/18] target/riscv: bypass smstateen check in debugger mode
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (13 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 14/18] target/sparc64: " Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 10:56 ` [PATCH v3 16/18] MAINTAINERS: cover riscv GDB XML files Marc-André Lureau
` (3 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Allow to read CSRs gated by Smstateen extension when env->debugger.
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/riscv/tcg/csr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 063590f56a79..aff5b54d37b1 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -53,7 +53,8 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
{
bool virt = env->virt_enabled;
- if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
+ if (env->debugger || env->priv == PRV_M ||
+ !riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_NONE;
}
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v3 16/18] MAINTAINERS: cover riscv GDB XML files
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (14 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 15/18] target/riscv: bypass smstateen check in debugger mode Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 21:51 ` Pierrick Bouvier
2026-10-22 10:56 ` [PATCH v3 17/18] target/riscv: expose register aliases to monitors via gdbstub Marc-André Lureau
` (2 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Add an entry so changes to these files are routed to the RISC-V
maintainers.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index de3cb9dcaf25..010539dd3588 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -372,6 +372,7 @@ F: configs/targets/riscv*
F: docs/system/target-riscv.rst
F: docs/specs/riscv-iommu.rst
F: target/riscv/
+F: gdbstub/gdb-xml/riscv*.xml
F: hw/char/riscv_htif.c
F: hw/riscv/
F: hw/intc/riscv*
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 16/18] MAINTAINERS: cover riscv GDB XML files
2026-10-22 10:56 ` [PATCH v3 16/18] MAINTAINERS: cover riscv GDB XML files Marc-André Lureau
@ 2026-10-22 21:51 ` Pierrick Bouvier
0 siblings, 0 replies; 31+ messages in thread
From: Pierrick Bouvier @ 2026-10-22 21:51 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller, Warner Losh,
Kyle Evans
On 10/22/2026 3:56 AM, Marc-André Lureau wrote:
> Add an entry so changes to these files are routed to the RISC-V
> maintainers.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 17/18] target/riscv: expose register aliases to monitors via gdbstub
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (15 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 16/18] MAINTAINERS: cover riscv GDB XML files Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-23 19:50 ` Daniel Henrique Barboza
2026-10-22 10:56 ` [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure Marc-André Lureau
2026-10-24 15:51 ` [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Dr. David Alan Gilbert
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.)
but users also refer to registers by their numeric names (x0-x31,
f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism
supported both via split "x0/zero" name matching.
Register a feature that maps:
- x0-x31 and s0 to the corresponding core integer registers
- x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[]
- f0-f31 to the corresponding FPU registers (when FPU is present)
CSR-by-name lookups ($mstatus, $sstatus, ...) keep working, through
the existing GDB CSR feature rather than the removed csr_ops loop.
Lookup is now case-sensitive (consistent with all other targets),
including for the CSR names. Vector registers report "unknown
register" instead of the target-specific "Unable to print the value
of vector vreg" message.
RV32 numeric and high-half aliases now zero-extend into HMP’s 64-bit
expression value (for example, $x1 containing 0xffffffff evaluates to
4294967295, whereas the legacy fallback returned -1). This makes aliases
consistent with the existing GDB-backed names.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
configs/targets/riscv32-linux-user.mak | 2 +-
configs/targets/riscv32-softmmu.mak | 2 +-
configs/targets/riscv64-bsd-user.mak | 2 +-
configs/targets/riscv64-linux-user.mak | 2 +-
configs/targets/riscv64-softmmu.mak | 2 +-
gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++
gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 +++++++++
gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++
gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++++++++
target/riscv/cpu.c | 1 -
target/riscv/gdbstub.c | 48 ++++++++++
target/riscv/internals.h | 3 -
target/riscv/monitor.c | 140 ------------------------------
13 files changed, 349 insertions(+), 149 deletions(-)
diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak
index d88fdf5e1b2f..8ee14fa14383 100644
--- a/configs/targets/riscv32-linux-user.mak
+++ b/configs/targets/riscv32-linux-user.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
-TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml
+TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
TARGET_SYSTBL_ABI=32
diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak
index 5d5016d00832..c717940344f0 100644
--- a/configs/targets/riscv32-softmmu.mak
+++ b/configs/targets/riscv32-softmmu.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
-TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml
+TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
# needed by boot.c
TARGET_NEED_FDT=y
TARGET_LONG_BITS=32
diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak
index 5b4e138099fc..1d37e018c871 100644
--- a/configs/targets/riscv64-bsd-user.mak
+++ b/configs/targets/riscv64-bsd-user.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
-TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
+TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak
index 35621520c560..564d15aaca8c 100644
--- a/configs/targets/riscv64-linux-user.mak
+++ b/configs/targets/riscv64-linux-user.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
-TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
+TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
TARGET_SYSTBL_ABI=64
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index a10dc03c04c8..28bfcdc575fb 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_KVM_HAVE_GUEST_DEBUG=y
-TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml
+TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
# needed by boot.c
TARGET_NEED_FDT=y
TARGET_LONG_BITS=64
diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-32bit-alias.xml
new file mode 100644
index 000000000000..a00a86ebdf95
--- /dev/null
+++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.qemu.gdb.riscv.alias">
+ <reg name="x0" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x1" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x2" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x3" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x4" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x5" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x6" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x7" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x8" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x9" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x10" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x11" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x12" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x13" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x14" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x15" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x16" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x17" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x18" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x19" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x20" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x21" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x22" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x23" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x24" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x25" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x26" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x27" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x28" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x29" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x30" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x31" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s0" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x0h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="zeroh" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x1h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="rah" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x2h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="sph" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x3h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="gph" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x4h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="tph" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x5h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t0h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x6h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t1h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x7h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t2h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x8h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s0h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x9h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s1h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x10h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a0h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x11h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a1h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x12h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a2h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x13h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a3h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x14h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a4h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x15h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a5h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x16h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a6h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x17h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="a7h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x18h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s2h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x19h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s3h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x20h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s4h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x21h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s5h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x22h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s6h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x23h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s7h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x24h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s8h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x25h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s9h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x26h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s10h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x27h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="s11h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x28h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t3h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x29h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t4h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x30h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t5h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="x31h" bitsize="32" type="int" group="qemu-debug"/>
+ <reg name="t6h" bitsize="32" type="int" group="qemu-debug"/>
+</feature>
diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml
new file mode 100644
index 000000000000..3935f72ea289
--- /dev/null
+++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.qemu.gdb.riscv.fpu-alias">
+ <reg name="f0" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f1" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f2" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f3" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f4" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f5" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f6" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f7" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f8" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f9" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f10" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f11" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f12" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f13" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f14" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f15" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f16" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f17" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f18" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f19" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f20" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f21" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f22" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f23" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f24" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f25" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f26" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f27" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f28" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f29" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f30" bitsize="32" type="ieee_single" group="qemu-debug"/>
+ <reg name="f31" bitsize="32" type="ieee_single" group="qemu-debug"/>
+</feature>
diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-64bit-alias.xml
new file mode 100644
index 000000000000..28781b230226
--- /dev/null
+++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.qemu.gdb.riscv.alias">
+ <reg name="x0" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x1" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x2" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x3" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x4" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x5" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x6" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x7" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x8" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x9" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x10" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x11" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x12" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x13" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x14" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x15" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x16" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x17" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x18" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x19" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x20" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x21" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x22" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x23" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x24" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x25" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x26" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x27" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x28" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x29" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x30" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x31" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s0" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x0h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="zeroh" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x1h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="rah" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x2h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="sph" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x3h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="gph" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x4h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="tph" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x5h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t0h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x6h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t1h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x7h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t2h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x8h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s0h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x9h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s1h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x10h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a0h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x11h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a1h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x12h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a2h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x13h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a3h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x14h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a4h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x15h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a5h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x16h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a6h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x17h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="a7h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x18h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s2h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x19h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s3h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x20h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s4h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x21h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s5h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x22h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s6h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x23h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s7h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x24h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s8h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x25h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s9h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x26h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s10h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x27h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="s11h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x28h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t3h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x29h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t4h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x30h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t5h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="x31h" bitsize="64" type="int" group="qemu-debug"/>
+ <reg name="t6h" bitsize="64" type="int" group="qemu-debug"/>
+</feature>
diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml
new file mode 100644
index 000000000000..13e6b341a0f8
--- /dev/null
+++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!--
+ SPDX-License-Identifier: GPL-2.0-or-later
+-->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.qemu.gdb.riscv.fpu-alias">
+
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+
+ <reg name="f0" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f1" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f2" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f3" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f4" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f5" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f6" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f7" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f8" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f9" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f10" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f11" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f12" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f13" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f14" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f15" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f16" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f17" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f18" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f19" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f20" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f21" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f22" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f23" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f24" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f25" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f26" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f27" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f28" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f29" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f30" bitsize="64" type="riscv_double" group="qemu-debug"/>
+ <reg name="f31" bitsize="64" type="riscv_double" group="qemu-debug"/>
+</feature>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 08a4d14ea1f6..7b052da6d8b4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3107,7 +3107,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
.legacy_vmsd = &vmstate_riscv_cpu,
#ifdef CONFIG_TCG
.translate_for_debug = riscv_cpu_translate_for_debug,
- .monitor_get_register = riscv_monitor_get_register_legacy,
#endif
};
#endif
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f279f4ab2461..0d89caf8ba36 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -336,10 +336,42 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
return &cpu->dyn_vreg_feature;
}
+/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */
+static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ uint64_t val;
+
+ if (n < 33) {
+ return riscv_cpu_gdb_read_register(cs, buf, n == 32 ? 8 : n);
+ }
+
+ val = cpu->env.gprh[(n - 33) / 2];
+ if (riscv_cpu_is_32bit(cpu)) {
+ return gdb_get_reg32(buf, val);
+ }
+ return gdb_get_reg64(buf, val);
+}
+
+static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
+
+ if (n < 33) {
+ return riscv_cpu_gdb_write_register(cs, buf, n == 32 ? 8 : n);
+ }
+
+ env->gprh[(n - 33) / 2] = ldn(env, buf, regsz);
+ return regsz;
+}
+
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+
if (env->misa_ext & RVD) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
gdb_find_static_feature("riscv-64bit-fpu.xml"));
@@ -380,4 +412,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
feature);
}
#endif
+
+ gdb_register_internal_coprocessor(
+ cs, riscv_gdb_get_alias, riscv_gdb_set_alias,
+ gdb_find_static_feature(riscv_cpu_is_32bit(cpu) ?
+ "riscv-32bit-alias.xml" :
+ "riscv-64bit-alias.xml"));
+
+ if (env->misa_ext & RVD) {
+ gdb_register_internal_coprocessor(
+ cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ gdb_find_static_feature("riscv-64bit-fpu-alias.xml"));
+ } else if (env->misa_ext & RVF) {
+ gdb_register_internal_coprocessor(
+ cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ gdb_find_static_feature("riscv-32bit-fpu-alias.xml"));
+ }
}
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f17d011d22fb..f4af4636c6ca 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -265,7 +265,4 @@ static inline int insn_len(uint16_t first_word)
return (first_word & 3) == 3 ? 4 : 2;
}
-int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
- int64_t *pval);
-
#endif
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 7e61ae2a4717..20f3ba57ae57 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -19,10 +19,7 @@
*/
#include "qemu/osdep.h"
-#include "qemu/ctype.h"
-#include "qemu/qemu-print.h"
#include "cpu.h"
-#include "target/riscv/tcg/csr.h"
#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp.h"
@@ -247,140 +244,3 @@ void hmp_info_mem(MonitorHMP *hmp, const QDict *qdict)
mem_info_svxx(hmp, env);
}
#endif /* CONFIG_HMP */
-
-#ifdef CONFIG_TCG
-static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
- target_ulong *val, bool is_gprh)
-{
- const char * const *reg_names;
- uint64_t *vals;
-
- if (is_gprh) {
- reg_names = riscv_int_regnamesh;
- vals = env->gprh;
- } else {
- reg_names = riscv_int_regnames;
- vals = env->gpr;
- }
-
- for (int i = 0; i < 32; i++) {
- g_auto(GStrv) reg_name = g_strsplit(reg_names[i], "/", 2);
-
- g_assert(reg_name[0]);
- g_assert(reg_name[1]);
-
- if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||
- g_ascii_strcasecmp(reg_name[1], name) == 0) {
- *val = vals[i];
- return true;
- }
- }
-
- return false;
-}
-
-static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t *val)
-{
- if (qemu_tolower(name[0]) != 'f') {
- return false;
- }
-
- for (int i = 0; i < 32; i++) {
- g_auto(GStrv) reg_name = g_strsplit(riscv_fpr_regnames[i], "/", 2);
-
- g_assert(reg_name[0]);
- g_assert(reg_name[1]);
-
- if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||
- g_ascii_strcasecmp(reg_name[1], name) == 0) {
- *val = env->fpr[i];
- return true;
- }
- }
-
- return false;
-}
-
-static bool reg_is_vreg(const char *name)
-{
- if (qemu_tolower(name[0]) != 'v' || strlen(name) > 3) {
- return false;
- }
-
- for (int i = 0; i < 32; i++) {
- if (g_ascii_strcasecmp(name, riscv_rvv_regnames[i]) == 0) {
- return true;
- }
- }
-
- return false;
-}
-
-int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
- int64_t *pval)
-{
- RISCVCPU *hart = RISCV_CPU(cs);
- CPURISCVState *env = cpu_env(cs);
- target_ulong val = 0;
- uint64_t val64 = 0;
- int i;
-
- if (reg_is_ulong_integer(env, name, &val, false) ||
- reg_is_ulong_integer(env, name, &val, true)) {
- *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
- return 0;
- }
-
- if (reg_is_u64_fpu(env, name, &val64)) {
- *pval = val64;
- return 0;
- }
-
- if (reg_is_vreg(name)) {
- if (!riscv_cpu_cfg(env)->ext_zve32x) {
- return -EINVAL;
- }
-
- qemu_printf("Unable to print the value of vector "
- "vreg '%s' from this API\n", name);
-
- /*
- * We're returning 0 because returning -EINVAL triggers
- * an 'unknown register' message in exp_unary() later,
- * which feels ankward after our own error message.
- */
- *pval = 0;
- return 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
- RISCVException res;
- int csrno = i;
-
- /*
- * Early skip when possible since we're going
- * through a lot of NULL entries.
- */
- if (csr_ops[csrno].predicate == NULL) {
- continue;
- }
-
- if (g_ascii_strcasecmp(csr_ops[csrno].name, name) != 0) {
- continue;
- }
-
- res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
-
- /*
- * Rely on the smode, hmode, etc, predicates within csr.c
- * to do the filtering of the registers that are present.
- */
- if (res == RISCV_EXCP_NONE) {
- *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-#endif
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 17/18] target/riscv: expose register aliases to monitors via gdbstub
2026-10-22 10:56 ` [PATCH v3 17/18] target/riscv: expose register aliases to monitors via gdbstub Marc-André Lureau
@ 2026-10-23 19:50 ` Daniel Henrique Barboza
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Henrique Barboza @ 2026-10-23 19:50 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans
On 10/22/2026 7:56 AM, Marc-André Lureau wrote:
> The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.)
> but users also refer to registers by their numeric names (x0-x31,
> f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism
> supported both via split "x0/zero" name matching.
>
> Register a feature that maps:
> - x0-x31 and s0 to the corresponding core integer registers
> - x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[]
> - f0-f31 to the corresponding FPU registers (when FPU is present)
>
> CSR-by-name lookups ($mstatus, $sstatus, ...) keep working, through
> the existing GDB CSR feature rather than the removed csr_ops loop.
>
> Lookup is now case-sensitive (consistent with all other targets),
> including for the CSR names. Vector registers report "unknown
> register" instead of the target-specific "Unable to print the value
> of vector vreg" message.
>
> RV32 numeric and high-half aliases now zero-extend into HMP’s 64-bit
> expression value (for example, $x1 containing 0xffffffff evaluates to
> 4294967295, whereas the legacy fallback returned -1). This makes aliases
> consistent with the existing GDB-backed names.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> configs/targets/riscv32-linux-user.mak | 2 +-
> configs/targets/riscv32-softmmu.mak | 2 +-
> configs/targets/riscv64-bsd-user.mak | 2 +-
> configs/targets/riscv64-linux-user.mak | 2 +-
> configs/targets/riscv64-softmmu.mak | 2 +-
> gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++
> gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 +++++++++
> gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++
> gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++++++++
> target/riscv/cpu.c | 1 -
> target/riscv/gdbstub.c | 48 ++++++++++
> target/riscv/internals.h | 3 -
> target/riscv/monitor.c | 140 ------------------------------
> 13 files changed, 349 insertions(+), 149 deletions(-)
>
> diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak
> index d88fdf5e1b2f..8ee14fa14383 100644
> --- a/configs/targets/riscv32-linux-user.mak
> +++ b/configs/targets/riscv32-linux-user.mak
> @@ -1,7 +1,7 @@
> TARGET_ARCH=riscv32
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml
> +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
> CONFIG_SEMIHOSTING=y
> CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
> TARGET_SYSTBL_ABI=32
> diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak
> index 5d5016d00832..c717940344f0 100644
> --- a/configs/targets/riscv32-softmmu.mak
> +++ b/configs/targets/riscv32-softmmu.mak
> @@ -1,6 +1,6 @@
> TARGET_ARCH=riscv32
> TARGET_BASE_ARCH=riscv
> -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml
> +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
> # needed by boot.c
> TARGET_NEED_FDT=y
> TARGET_LONG_BITS=32
> diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak
> index 5b4e138099fc..1d37e018c871 100644
> --- a/configs/targets/riscv64-bsd-user.mak
> +++ b/configs/targets/riscv64-bsd-user.mak
> @@ -1,6 +1,6 @@
> TARGET_ARCH=riscv64
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
> +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
> TARGET_LONG_BITS=64
> TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak
> index 35621520c560..564d15aaca8c 100644
> --- a/configs/targets/riscv64-linux-user.mak
> +++ b/configs/targets/riscv64-linux-user.mak
> @@ -1,7 +1,7 @@
> TARGET_ARCH=riscv64
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
> +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
> CONFIG_SEMIHOSTING=y
> CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
> TARGET_SYSTBL_ABI=64
> diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
> index a10dc03c04c8..28bfcdc575fb 100644
> --- a/configs/targets/riscv64-softmmu.mak
> +++ b/configs/targets/riscv64-softmmu.mak
> @@ -1,7 +1,7 @@
> TARGET_ARCH=riscv64
> TARGET_BASE_ARCH=riscv
> TARGET_KVM_HAVE_GUEST_DEBUG=y
> -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml
> +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml
> # needed by boot.c
> TARGET_NEED_FDT=y
> TARGET_LONG_BITS=64
> diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-32bit-alias.xml
> new file mode 100644
> index 000000000000..a00a86ebdf95
> --- /dev/null
> +++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml
> @@ -0,0 +1,105 @@
> +<?xml version="1.0"?>
> +<!--
> + SPDX-License-Identifier: GPL-2.0-or-later
> +-->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.qemu.gdb.riscv.alias">
> + <reg name="x0" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x1" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x2" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x3" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x4" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x5" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x6" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x7" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x8" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x9" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x10" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x11" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x12" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x13" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x14" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x15" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x16" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x17" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x18" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x19" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x20" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x21" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x22" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x23" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x24" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x25" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x26" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x27" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x28" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x29" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x30" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x31" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s0" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x0h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="zeroh" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x1h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="rah" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x2h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="sph" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x3h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="gph" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x4h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="tph" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x5h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t0h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x6h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t1h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x7h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t2h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x8h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s0h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x9h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s1h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x10h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a0h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x11h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a1h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x12h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a2h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x13h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a3h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x14h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a4h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x15h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a5h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x16h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a6h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x17h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="a7h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x18h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s2h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x19h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s3h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x20h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s4h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x21h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s5h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x22h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s6h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x23h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s7h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x24h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s8h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x25h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s9h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x26h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s10h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x27h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="s11h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x28h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t3h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x29h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t4h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x30h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t5h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="x31h" bitsize="32" type="int" group="qemu-debug"/>
> + <reg name="t6h" bitsize="32" type="int" group="qemu-debug"/>
> +</feature>
> diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml
> new file mode 100644
> index 000000000000..3935f72ea289
> --- /dev/null
> +++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml
> @@ -0,0 +1,40 @@
> +<?xml version="1.0"?>
> +<!--
> + SPDX-License-Identifier: GPL-2.0-or-later
> +-->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.qemu.gdb.riscv.fpu-alias">
> + <reg name="f0" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f1" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f2" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f3" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f4" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f5" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f6" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f7" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f8" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f9" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f10" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f11" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f12" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f13" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f14" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f15" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f16" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f17" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f18" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f19" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f20" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f21" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f22" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f23" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f24" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f25" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f26" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f27" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f28" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f29" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f30" bitsize="32" type="ieee_single" group="qemu-debug"/>
> + <reg name="f31" bitsize="32" type="ieee_single" group="qemu-debug"/>
> +</feature>
> diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-64bit-alias.xml
> new file mode 100644
> index 000000000000..28781b230226
> --- /dev/null
> +++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml
> @@ -0,0 +1,105 @@
> +<?xml version="1.0"?>
> +<!--
> + SPDX-License-Identifier: GPL-2.0-or-later
> +-->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.qemu.gdb.riscv.alias">
> + <reg name="x0" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x1" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x2" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x3" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x4" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x5" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x6" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x7" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x8" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x9" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x10" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x11" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x12" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x13" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x14" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x15" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x16" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x17" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x18" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x19" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x20" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x21" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x22" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x23" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x24" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x25" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x26" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x27" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x28" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x29" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x30" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x31" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s0" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x0h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="zeroh" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x1h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="rah" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x2h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="sph" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x3h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="gph" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x4h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="tph" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x5h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t0h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x6h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t1h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x7h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t2h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x8h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s0h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x9h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s1h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x10h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a0h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x11h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a1h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x12h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a2h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x13h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a3h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x14h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a4h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x15h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a5h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x16h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a6h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x17h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="a7h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x18h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s2h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x19h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s3h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x20h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s4h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x21h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s5h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x22h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s6h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x23h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s7h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x24h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s8h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x25h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s9h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x26h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s10h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x27h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="s11h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x28h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t3h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x29h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t4h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x30h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t5h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="x31h" bitsize="64" type="int" group="qemu-debug"/>
> + <reg name="t6h" bitsize="64" type="int" group="qemu-debug"/>
> +</feature>
> diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml
> new file mode 100644
> index 000000000000..13e6b341a0f8
> --- /dev/null
> +++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml
> @@ -0,0 +1,46 @@
> +<?xml version="1.0"?>
> +<!--
> + SPDX-License-Identifier: GPL-2.0-or-later
> +-->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.qemu.gdb.riscv.fpu-alias">
> +
> + <union id="riscv_double">
> + <field name="float" type="ieee_single"/>
> + <field name="double" type="ieee_double"/>
> + </union>
> +
> + <reg name="f0" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f1" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f2" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f3" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f4" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f5" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f6" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f7" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f8" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f9" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f10" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f11" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f12" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f13" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f14" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f15" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f16" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f17" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f18" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f19" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f20" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f21" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f22" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f23" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f24" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f25" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f26" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f27" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f28" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f29" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f30" bitsize="64" type="riscv_double" group="qemu-debug"/>
> + <reg name="f31" bitsize="64" type="riscv_double" group="qemu-debug"/>
> +</feature>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 08a4d14ea1f6..7b052da6d8b4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3107,7 +3107,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> .legacy_vmsd = &vmstate_riscv_cpu,
> #ifdef CONFIG_TCG
> .translate_for_debug = riscv_cpu_translate_for_debug,
> - .monitor_get_register = riscv_monitor_get_register_legacy,
> #endif
> };
> #endif
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index f279f4ab2461..0d89caf8ba36 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -336,10 +336,42 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
> return &cpu->dyn_vreg_feature;
> }
>
> +/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */
> +static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + uint64_t val;
> +
> + if (n < 33) {
> + return riscv_cpu_gdb_read_register(cs, buf, n == 32 ? 8 : n);
> + }
> +
> + val = cpu->env.gprh[(n - 33) / 2];
> + if (riscv_cpu_is_32bit(cpu)) {
> + return gdb_get_reg32(buf, val);
> + }
> + return gdb_get_reg64(buf, val);
> +}
> +
> +static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
> +
> + if (n < 33) {
> + return riscv_cpu_gdb_write_register(cs, buf, n == 32 ? 8 : n);
> + }
> +
> + env->gprh[(n - 33) / 2] = ldn(env, buf, regsz);
> + return regsz;
> +}
> +
> void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> +
> if (env->misa_ext & RVD) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> gdb_find_static_feature("riscv-64bit-fpu.xml"));
> @@ -380,4 +412,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> feature);
> }
> #endif
> +
> + gdb_register_internal_coprocessor(
> + cs, riscv_gdb_get_alias, riscv_gdb_set_alias,
> + gdb_find_static_feature(riscv_cpu_is_32bit(cpu) ?
> + "riscv-32bit-alias.xml" :
> + "riscv-64bit-alias.xml"));
> +
> + if (env->misa_ext & RVD) {
> + gdb_register_internal_coprocessor(
> + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + gdb_find_static_feature("riscv-64bit-fpu-alias.xml"));
> + } else if (env->misa_ext & RVF) {
> + gdb_register_internal_coprocessor(
> + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + gdb_find_static_feature("riscv-32bit-fpu-alias.xml"));
> + }
> }
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index f17d011d22fb..f4af4636c6ca 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -265,7 +265,4 @@ static inline int insn_len(uint16_t first_word)
> return (first_word & 3) == 3 ? 4 : 2;
> }
>
> -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
> - int64_t *pval);
> -
> #endif
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index 7e61ae2a4717..20f3ba57ae57 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -19,10 +19,7 @@
> */
>
> #include "qemu/osdep.h"
> -#include "qemu/ctype.h"
> -#include "qemu/qemu-print.h"
> #include "cpu.h"
> -#include "target/riscv/tcg/csr.h"
> #include "cpu_bits.h"
> #include "monitor/monitor.h"
> #include "monitor/hmp.h"
> @@ -247,140 +244,3 @@ void hmp_info_mem(MonitorHMP *hmp, const QDict *qdict)
> mem_info_svxx(hmp, env);
> }
> #endif /* CONFIG_HMP */
> -
> -#ifdef CONFIG_TCG
> -static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
> - target_ulong *val, bool is_gprh)
> -{
> - const char * const *reg_names;
> - uint64_t *vals;
> -
> - if (is_gprh) {
> - reg_names = riscv_int_regnamesh;
> - vals = env->gprh;
> - } else {
> - reg_names = riscv_int_regnames;
> - vals = env->gpr;
> - }
> -
> - for (int i = 0; i < 32; i++) {
> - g_auto(GStrv) reg_name = g_strsplit(reg_names[i], "/", 2);
> -
> - g_assert(reg_name[0]);
> - g_assert(reg_name[1]);
> -
> - if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||
> - g_ascii_strcasecmp(reg_name[1], name) == 0) {
> - *val = vals[i];
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> -static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t *val)
> -{
> - if (qemu_tolower(name[0]) != 'f') {
> - return false;
> - }
> -
> - for (int i = 0; i < 32; i++) {
> - g_auto(GStrv) reg_name = g_strsplit(riscv_fpr_regnames[i], "/", 2);
> -
> - g_assert(reg_name[0]);
> - g_assert(reg_name[1]);
> -
> - if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||
> - g_ascii_strcasecmp(reg_name[1], name) == 0) {
> - *val = env->fpr[i];
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> -static bool reg_is_vreg(const char *name)
> -{
> - if (qemu_tolower(name[0]) != 'v' || strlen(name) > 3) {
> - return false;
> - }
> -
> - for (int i = 0; i < 32; i++) {
> - if (g_ascii_strcasecmp(name, riscv_rvv_regnames[i]) == 0) {
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
> - int64_t *pval)
> -{
> - RISCVCPU *hart = RISCV_CPU(cs);
> - CPURISCVState *env = cpu_env(cs);
> - target_ulong val = 0;
> - uint64_t val64 = 0;
> - int i;
> -
> - if (reg_is_ulong_integer(env, name, &val, false) ||
> - reg_is_ulong_integer(env, name, &val, true)) {
> - *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
> - return 0;
> - }
> -
> - if (reg_is_u64_fpu(env, name, &val64)) {
> - *pval = val64;
> - return 0;
> - }
> -
> - if (reg_is_vreg(name)) {
> - if (!riscv_cpu_cfg(env)->ext_zve32x) {
> - return -EINVAL;
> - }
> -
> - qemu_printf("Unable to print the value of vector "
> - "vreg '%s' from this API\n", name);
> -
> - /*
> - * We're returning 0 because returning -EINVAL triggers
> - * an 'unknown register' message in exp_unary() later,
> - * which feels ankward after our own error message.
> - */
> - *pval = 0;
> - return 0;
> - }
> -
> - for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
> - RISCVException res;
> - int csrno = i;
> -
> - /*
> - * Early skip when possible since we're going
> - * through a lot of NULL entries.
> - */
> - if (csr_ops[csrno].predicate == NULL) {
> - continue;
> - }
> -
> - if (g_ascii_strcasecmp(csr_ops[csrno].name, name) != 0) {
> - continue;
> - }
> -
> - res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> -
> - /*
> - * Rely on the smode, hmode, etc, predicates within csr.c
> - * to do the filtering of the registers that are present.
> - */
> - if (res == RISCV_EXCP_NONE) {
> - *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
> - return 0;
> - }
> - }
> -
> - return -EINVAL;
> -}
> -#endif
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (16 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 17/18] target/riscv: expose register aliases to monitors via gdbstub Marc-André Lureau
@ 2026-10-22 10:56 ` Marc-André Lureau
2026-10-22 21:52 ` Pierrick Bouvier
2026-10-24 15:51 ` [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Dr. David Alan Gilbert
18 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-22 10:56 UTC (permalink / raw)
To: qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans, Marc-André Lureau
Now that all targets expose their system registers via internal GDB
register descriptions (i386 segment limits, m68k, sparc64, RISC-V
aliases), the legacy MonitorDef table and
SysemuCPUOps::monitor_get_register callback are no longer needed.
HMP $register expressions now use gdb_get_register_list() exclusively.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
include/hw/core/sysemu-cpu-ops.h | 16 ---------------
include/monitor/hmp.h | 6 ------
include/qemu/typedefs.h | 1 -
monitor/hmp.c | 43 +---------------------------------------
4 files changed, 1 insertion(+), 65 deletions(-)
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index d125540262d2..daac2a3b13b1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -103,22 +103,6 @@ typedef struct SysemuCPUOps {
*/
bool (*internal_is_big_endian)(CPUState *cpu);
- /**
- * @monitor_get_register: Callback to fill @pval with register @name value.
- * This field is legacy, use @gdb_core_xml_file
- * to dump registers instead.
- * Returns: 0 on success or negative errno on failure.
- */
- int (*monitor_get_register)(CPUState *cs, const char *name, int64_t *pval);
-
-#ifdef CONFIG_HMP
- /**
- * @monitor_defs: Array of MonitorDef entries. This field is legacy,
- * use @gdb_core_xml_file to dump registers instead.
- */
- const MonitorDef *monitor_defs;
-#endif
-
/**
* @legacy_vmsd: Legacy state for migration.
* Do not use in new targets, use #DeviceClass::vmsd instead.
diff --git a/include/monitor/hmp.h b/include/monitor/hmp.h
index ef53e87f7608..950dd931d452 100644
--- a/include/monitor/hmp.h
+++ b/include/monitor/hmp.h
@@ -31,12 +31,6 @@ MonitorHMP *monitor_cur_hmp(void);
g_assert_not_reached(); \
}
-struct MonitorDef {
- const char *name;
- int offset;
- int64_t (*get_value)(MonitorHMP *hmp, const MonitorDef *md, int offset);
-};
-
void monitor_new_hmp(const char *id, const char *chardev_id,
bool use_readline, Error **errp);
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 2344c92182ea..5580e1fc4aba 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -72,7 +72,6 @@ typedef struct MemoryRegionSection MemoryRegionSection;
typedef struct MigrationIncomingState MigrationIncomingState;
typedef struct MigrationState MigrationState;
typedef struct Monitor Monitor;
-typedef struct MonitorDef MonitorDef;
typedef struct MSIMessage MSIMessage;
typedef struct NetClientState NetClientState;
typedef struct NetFilterState NetFilterState;
diff --git a/monitor/hmp.c b/monitor/hmp.c
index e97e0a9ff0d7..feb604da27f2 100644
--- a/monitor/hmp.c
+++ b/monitor/hmp.c
@@ -25,7 +25,6 @@
#include "qemu/osdep.h"
#include <dirent.h>
#include "hw/core/qdev.h"
-#include "hw/core/sysemu-cpu-ops.h"
#include "monitor-internal.h"
#include "monitor-hmp-internal.h"
#include "monitor/hmp.h"
@@ -443,8 +442,6 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t *pval, const char *name)
static const char *pch;
static sigjmp_buf expr_env;
-static int get_monitor_def(MonitorHMP *mon, int64_t *pval, const char *name);
-
static G_NORETURN G_GNUC_PRINTF(2, 3)
void expr_error(MonitorHMP *mon, const char *fmt, ...)
{
@@ -526,8 +523,7 @@ static int64_t expr_unary(MonitorHMP *mon)
pch++;
}
*q = 0;
- if (!gdb_get_register(mon, ®, buf)
- && get_monitor_def(mon, ®, buf) < 0) {
+ if (!gdb_get_register(mon, ®, buf)) {
expr_error(mon, "unknown register");
}
n = reg;
@@ -1720,43 +1716,6 @@ void monitor_register_hmp_info_hrt(const char *name,
g_assert_not_reached();
}
-/*
- * Set @pval to the value in the register identified by @name.
- * return 0 if OK, -1 if not found
- */
-static int get_monitor_def(MonitorHMP *hmp, int64_t *pval, const char *name)
-{
- CPUState *cs = monitor_hmp_get_cpu(hmp);
- const MonitorDef *md = NULL;
- void *ptr;
-
- if (cs == NULL) {
- return -1;
- }
- md = cs->cc->sysemu_ops->monitor_defs;
- if (md == NULL) {
- return -1;
- }
-
- for (; md->name != NULL; md++) {
- if (hmp_compare_cmd(name, md->name)) {
- if (md->get_value) {
- *pval = md->get_value(hmp, md, md->offset);
- } else {
- CPUArchState *env = monitor_hmp_get_cpu_env(hmp);
- ptr = (uint8_t *)env + md->offset;
- *pval = *(int32_t *)ptr;
- }
- return 0;
- }
- }
-
- if (!cs->cc->sysemu_ops->monitor_get_register) {
- return -1;
- }
- return cs->cc->sysemu_ops->monitor_get_register(cs, name, pval);
-}
-
int monitor_hmp_vprintf(MonitorHMP *hmp, const char *fmt, va_list ap)
{
g_autofree char *buf = g_strdup_vprintf(fmt, ap);
--
2.56.0.116.g6de20f6092dc
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure
2026-10-22 10:56 ` [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure Marc-André Lureau
@ 2026-10-22 21:52 ` Pierrick Bouvier
0 siblings, 0 replies; 31+ messages in thread
From: Pierrick Bouvier @ 2026-10-22 21:52 UTC (permalink / raw)
To: Marc-André Lureau, qemu-devel
Cc: Dr. David Alan Gilbert, Alex Bennée,
Philippe Mathieu-Daudé, Zhao Liu, Peter Maydell,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Max Filippov,
qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini, Laurent Vivier,
Mark Cave-Ayland, Artyom Tarasenko, Helge Deller, Warner Losh,
Kyle Evans
On 10/22/2026 3:56 AM, Marc-André Lureau wrote:
> Now that all targets expose their system registers via internal GDB
> register descriptions (i386 segment limits, m68k, sparc64, RISC-V
> aliases), the legacy MonitorDef table and
> SysemuCPUOps::monitor_get_register callback are no longer needed.
>
> HMP $register expressions now use gdb_get_register_list() exclusively.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> include/hw/core/sysemu-cpu-ops.h | 16 ---------------
> include/monitor/hmp.h | 6 ------
> include/qemu/typedefs.h | 1 -
> monitor/hmp.c | 43 +---------------------------------------
> 4 files changed, 1 insertion(+), 65 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers
2026-10-22 10:56 [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Marc-André Lureau
` (17 preceding siblings ...)
2026-10-22 10:56 ` [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure Marc-André Lureau
@ 2026-10-24 15:51 ` Dr. David Alan Gilbert
2026-10-25 8:26 ` Marc-André Lureau
18 siblings, 1 reply; 31+ messages in thread
From: Dr. David Alan Gilbert @ 2026-10-24 15:51 UTC (permalink / raw)
To: Marc-André Lureau
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans
* Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> Hi,
>
> HMP monitor supports printing $register expression. The lookup
> was done via GDB stub registers, and supplementary MonitorDef
> HMP-specific tables.
Why don't you get the first ~3 of these merged and then you can take the
others through the individual targets at their own pace.
Dave
> Migrate HMP registers to use the GDB infrastructure and remove the
> legacy HMP MonitorDef. Internal registers aren't exposed to GDB.
> This also drops HMP $pc x86 fallback (use $eip/$rip instead).
>
> Known behavioural changes on RISC-V: CSR lookup is now case-sensitive
> and vector registers now report "unkown register" instead of a
> target-specific message ("Unable to print the value of vector vreg 'v0'
> from this API")
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> Changes in v3:
> - added x86 GDB register patches
> - fix the x87 FPU tag word returned by the GDB stub
> - split SSE registers into a separate org.gnu.gdb.i386.sse feature
> - expose AVX/AVX-512 registers (ymm/zmm upper halves and opmask)
> - expose more system registers to HMP
> - renamed i386-segments.xml to i386-system.xml and registered it as an
> internal feature, like the other targets
> - moved the HMP $pc removal to its own patch and documented it in
> removed-features.rst
> - moved each target's MonitorDef removal into its target patch; the final
> patch now only removes the generic MonitorDef infrastructure
> - added MAINTAINERS entries
> - rebased onto current master
> - Link to v2: https://lore.kernel.org/qemu-devel/20261013-query-reg-v2-0-6f95a2e139a9@redhat.com
>
> Changes in v2:
> - dropped v1 patch 5 (CPUClass::get_pc fallback for $pc)
> - new patch gdb_register_internal_coprocessor() to hide registers from GDB
> - SPARC64, m68k, RISC-V aliases now use internal registration
> - pickup trailer tags
> - Link to v1: https://lore.kernel.org/qemu-devel/20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com
>
> ---
> Marc-André Lureau (18):
> hmp: don't crash on invalid register
> gdbstub: fix next register base after register gaps
> gdbstub: set feature->base_reg for dynamic features
> gdbstub: add gdb_register_internal_coprocessor()
> MAINTAINERS: cover x86 GDB XML files
> target/i386: expose segment limits register to monitors via gdbstub
> target/i386: fix FPU tag word in GDB register read
> target/i386: split SSE registers into separate GDB feature
> target/i386: expose system registers to monitors via gdbstub
> target/i386: expose AVX/AVX-512 registers to GDB
> target/i386: drop HMP $pc
> MAINTAINERS: cover m68k GDB XML files
> target/m68k: expose system registers to monitors via gdbstub
> target/sparc64: expose system registers to monitors via gdbstub
> target/riscv: bypass smstateen check in debugger mode
> MAINTAINERS: cover riscv GDB XML files
> target/riscv: expose register aliases to monitors via gdbstub
> monitor/hmp: remove legacy MonitorDef infrastructure
>
> MAINTAINERS | 4 +
> configs/targets/i386-bsd-user.mak | 2 +-
> configs/targets/i386-linux-user.mak | 2 +-
> configs/targets/i386-softmmu.mak | 2 +-
> configs/targets/m68k-softmmu.mak | 2 +-
> configs/targets/riscv32-linux-user.mak | 2 +-
> configs/targets/riscv32-softmmu.mak | 2 +-
> configs/targets/riscv64-bsd-user.mak | 2 +-
> configs/targets/riscv64-linux-user.mak | 2 +-
> configs/targets/riscv64-softmmu.mak | 2 +-
> configs/targets/sparc64-softmmu.mak | 2 +-
> configs/targets/x86_64-bsd-user.mak | 2 +-
> configs/targets/x86_64-linux-user.mak | 2 +-
> configs/targets/x86_64-softmmu.mak | 2 +-
> docs/about/removed-features.rst | 8 +
> gdbstub/gdb-xml/i386-32bit-avx.xml | 20 ++
> gdbstub/gdb-xml/i386-32bit-avx512.xml | 31 +++
> gdbstub/gdb-xml/i386-32bit-sse.xml | 54 +++++
> gdbstub/gdb-xml/i386-32bit.xml | 46 +---
> gdbstub/gdb-xml/i386-64bit-avx.xml | 28 +++
> gdbstub/gdb-xml/i386-64bit-avx512.xml | 108 +++++++++
> gdbstub/gdb-xml/i386-64bit-sse.xml | 62 +++++
> gdbstub/gdb-xml/i386-64bit.xml | 50 ----
> gdbstub/gdb-xml/i386-system.xml | 53 +++++
> gdbstub/gdb-xml/m68k-system.xml | 32 +++
> gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 +++++++++
> gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 ++++
> gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 +++++++++
> gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++
> gdbstub/gdb-xml/sparc64-system.xml | 22 ++
> gdbstub/gdbstub.c | 85 +++++--
> include/exec/gdbstub.h | 21 ++
> include/hw/core/cpu.h | 5 +-
> include/hw/core/sysemu-cpu-ops.h | 16 --
> include/monitor/hmp.h | 6 -
> include/qemu/typedefs.h | 1 -
> monitor/hmp.c | 45 +---
> target/arm/gdbstub.c | 8 +-
> target/arm/gdbstub64.c | 10 +-
> target/i386/cpu-dump.c | 5 +-
> target/i386/cpu.c | 60 +++--
> target/i386/cpu.h | 25 ++
> target/i386/gdbstub.c | 373 +++++++++++++++++++++++++++---
> target/i386/tcg/fpu_helper.c | 24 +-
> target/m68k/cpu.c | 22 --
> target/m68k/helper.c | 49 +++-
> target/ppc/gdbstub.c | 2 +-
> target/riscv/cpu.c | 1 -
> target/riscv/gdbstub.c | 57 ++++-
> target/riscv/internals.h | 3 -
> target/riscv/monitor.c | 140 -----------
> target/riscv/tcg/csr.c | 3 +-
> target/sparc/cpu.c | 19 --
> target/sparc/gdbstub.c | 38 +++
> target/xtensa/cpu.c | 2 +-
> tests/qtest/test-hmp.c | 1 -
> 56 files changed, 1383 insertions(+), 478 deletions(-)
> ---
> base-commit: 8967b2fe1b2aaae3c29e207d85fab901d580a2dc
> change-id: 20260910-query-reg-80cd59cf4707
>
> Best regards,
> --
> Marc-André Lureau <marcandre.lureau@redhat.com>
>
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers
2026-10-24 15:51 ` [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers Dr. David Alan Gilbert
@ 2026-10-25 8:26 ` Marc-André Lureau
2026-10-25 16:06 ` Dr. David Alan Gilbert
0 siblings, 1 reply; 31+ messages in thread
From: Marc-André Lureau @ 2026-10-25 8:26 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans
Hi
On Sat, Oct 24, 2026 at 7:52 PM Dr. David Alan Gilbert <dave@treblig.org> wrote:
>
> * Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> > Hi,
> >
> > HMP monitor supports printing $register expression. The lookup
> > was done via GDB stub registers, and supplementary MonitorDef
> > HMP-specific tables.
>
> Why don't you get the first ~3 of these merged and then you can take the
> others through the individual targets at their own pace.
Because I am not a GDB stub or HMP maintainer. Should I send a PR
regardless for those? they can be reviewed & applied at a maintainer
pace. If you think it's too slow, I can agree :)
>
> Dave
>
> > Migrate HMP registers to use the GDB infrastructure and remove the
> > legacy HMP MonitorDef. Internal registers aren't exposed to GDB.
> > This also drops HMP $pc x86 fallback (use $eip/$rip instead).
> >
> > Known behavioural changes on RISC-V: CSR lookup is now case-sensitive
> > and vector registers now report "unkown register" instead of a
> > target-specific message ("Unable to print the value of vector vreg 'v0'
> > from this API")
> >
> > Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> > ---
> > Changes in v3:
> > - added x86 GDB register patches
> > - fix the x87 FPU tag word returned by the GDB stub
> > - split SSE registers into a separate org.gnu.gdb.i386.sse feature
> > - expose AVX/AVX-512 registers (ymm/zmm upper halves and opmask)
> > - expose more system registers to HMP
> > - renamed i386-segments.xml to i386-system.xml and registered it as an
> > internal feature, like the other targets
> > - moved the HMP $pc removal to its own patch and documented it in
> > removed-features.rst
> > - moved each target's MonitorDef removal into its target patch; the final
> > patch now only removes the generic MonitorDef infrastructure
> > - added MAINTAINERS entries
> > - rebased onto current master
> > - Link to v2: https://lore.kernel.org/qemu-devel/20261013-query-reg-v2-0-6f95a2e139a9@redhat.com
> >
> > Changes in v2:
> > - dropped v1 patch 5 (CPUClass::get_pc fallback for $pc)
> > - new patch gdb_register_internal_coprocessor() to hide registers from GDB
> > - SPARC64, m68k, RISC-V aliases now use internal registration
> > - pickup trailer tags
> > - Link to v1: https://lore.kernel.org/qemu-devel/20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com
> >
> > ---
> > Marc-André Lureau (18):
> > hmp: don't crash on invalid register
> > gdbstub: fix next register base after register gaps
> > gdbstub: set feature->base_reg for dynamic features
> > gdbstub: add gdb_register_internal_coprocessor()
> > MAINTAINERS: cover x86 GDB XML files
> > target/i386: expose segment limits register to monitors via gdbstub
> > target/i386: fix FPU tag word in GDB register read
> > target/i386: split SSE registers into separate GDB feature
> > target/i386: expose system registers to monitors via gdbstub
> > target/i386: expose AVX/AVX-512 registers to GDB
> > target/i386: drop HMP $pc
> > MAINTAINERS: cover m68k GDB XML files
> > target/m68k: expose system registers to monitors via gdbstub
> > target/sparc64: expose system registers to monitors via gdbstub
> > target/riscv: bypass smstateen check in debugger mode
> > MAINTAINERS: cover riscv GDB XML files
> > target/riscv: expose register aliases to monitors via gdbstub
> > monitor/hmp: remove legacy MonitorDef infrastructure
> >
> > MAINTAINERS | 4 +
> > configs/targets/i386-bsd-user.mak | 2 +-
> > configs/targets/i386-linux-user.mak | 2 +-
> > configs/targets/i386-softmmu.mak | 2 +-
> > configs/targets/m68k-softmmu.mak | 2 +-
> > configs/targets/riscv32-linux-user.mak | 2 +-
> > configs/targets/riscv32-softmmu.mak | 2 +-
> > configs/targets/riscv64-bsd-user.mak | 2 +-
> > configs/targets/riscv64-linux-user.mak | 2 +-
> > configs/targets/riscv64-softmmu.mak | 2 +-
> > configs/targets/sparc64-softmmu.mak | 2 +-
> > configs/targets/x86_64-bsd-user.mak | 2 +-
> > configs/targets/x86_64-linux-user.mak | 2 +-
> > configs/targets/x86_64-softmmu.mak | 2 +-
> > docs/about/removed-features.rst | 8 +
> > gdbstub/gdb-xml/i386-32bit-avx.xml | 20 ++
> > gdbstub/gdb-xml/i386-32bit-avx512.xml | 31 +++
> > gdbstub/gdb-xml/i386-32bit-sse.xml | 54 +++++
> > gdbstub/gdb-xml/i386-32bit.xml | 46 +---
> > gdbstub/gdb-xml/i386-64bit-avx.xml | 28 +++
> > gdbstub/gdb-xml/i386-64bit-avx512.xml | 108 +++++++++
> > gdbstub/gdb-xml/i386-64bit-sse.xml | 62 +++++
> > gdbstub/gdb-xml/i386-64bit.xml | 50 ----
> > gdbstub/gdb-xml/i386-system.xml | 53 +++++
> > gdbstub/gdb-xml/m68k-system.xml | 32 +++
> > gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 +++++++++
> > gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 ++++
> > gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 +++++++++
> > gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++
> > gdbstub/gdb-xml/sparc64-system.xml | 22 ++
> > gdbstub/gdbstub.c | 85 +++++--
> > include/exec/gdbstub.h | 21 ++
> > include/hw/core/cpu.h | 5 +-
> > include/hw/core/sysemu-cpu-ops.h | 16 --
> > include/monitor/hmp.h | 6 -
> > include/qemu/typedefs.h | 1 -
> > monitor/hmp.c | 45 +---
> > target/arm/gdbstub.c | 8 +-
> > target/arm/gdbstub64.c | 10 +-
> > target/i386/cpu-dump.c | 5 +-
> > target/i386/cpu.c | 60 +++--
> > target/i386/cpu.h | 25 ++
> > target/i386/gdbstub.c | 373 +++++++++++++++++++++++++++---
> > target/i386/tcg/fpu_helper.c | 24 +-
> > target/m68k/cpu.c | 22 --
> > target/m68k/helper.c | 49 +++-
> > target/ppc/gdbstub.c | 2 +-
> > target/riscv/cpu.c | 1 -
> > target/riscv/gdbstub.c | 57 ++++-
> > target/riscv/internals.h | 3 -
> > target/riscv/monitor.c | 140 -----------
> > target/riscv/tcg/csr.c | 3 +-
> > target/sparc/cpu.c | 19 --
> > target/sparc/gdbstub.c | 38 +++
> > target/xtensa/cpu.c | 2 +-
> > tests/qtest/test-hmp.c | 1 -
> > 56 files changed, 1383 insertions(+), 478 deletions(-)
> > ---
> > base-commit: 8967b2fe1b2aaae3c29e207d85fab901d580a2dc
> > change-id: 20260910-query-reg-80cd59cf4707
> >
> > Best regards,
> > --
> > Marc-André Lureau <marcandre.lureau@redhat.com>
> >
> --
> -----Open up your eyes, open up your mind, open up your code -------
> / Dr. David Alan Gilbert | Running GNU/Linux | Happy \
> \ dave @ treblig.org | | In Hex /
> \ _________________________|_____ http://www.treblig.org |_______/
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v3 00/18] monitor/hmp: replace MonitorDef with GDB registers
2026-10-25 8:26 ` Marc-André Lureau
@ 2026-10-25 16:06 ` Dr. David Alan Gilbert
0 siblings, 0 replies; 31+ messages in thread
From: Dr. David Alan Gilbert @ 2026-10-25 16:06 UTC (permalink / raw)
To: Marc-André Lureau
Cc: qemu-devel, Alex Bennée, Philippe Mathieu-Daudé,
Zhao Liu, Peter Maydell, Chinmay Rath, Nicholas Piggin,
Glenn Miles, Harsh Prateek Bora, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Chao Liu,
Max Filippov, qemu-arm, qemu-ppc, qemu-riscv, Paolo Bonzini,
Laurent Vivier, Mark Cave-Ayland, Artyom Tarasenko, Helge Deller,
Pierrick Bouvier, Warner Losh, Kyle Evans
* Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> Hi
>
> On Sat, Oct 24, 2026 at 7:52 PM Dr. David Alan Gilbert <dave@treblig.org> wrote:
> >
> > * Marc-André Lureau (marcandre.lureau@redhat.com) wrote:
> > > Hi,
> > >
> > > HMP monitor supports printing $register expression. The lookup
> > > was done via GDB stub registers, and supplementary MonitorDef
> > > HMP-specific tables.
> >
> > Why don't you get the first ~3 of these merged and then you can take the
> > others through the individual targets at their own pace.
>
> Because I am not a GDB stub or HMP maintainer. Should I send a PR
> regardless for those? they can be reviewed & applied at a maintainer
> pace.
The first one looks trivial to me.
> If you think it's too slow, I can agree :)
It's not the 'slow', it just would avoid needing to keep big patchsets
running around and everyone having to check them again each time.
Dave
> >
> > Dave
> >
> > > Migrate HMP registers to use the GDB infrastructure and remove the
> > > legacy HMP MonitorDef. Internal registers aren't exposed to GDB.
> > > This also drops HMP $pc x86 fallback (use $eip/$rip instead).
> > >
> > > Known behavioural changes on RISC-V: CSR lookup is now case-sensitive
> > > and vector registers now report "unkown register" instead of a
> > > target-specific message ("Unable to print the value of vector vreg 'v0'
> > > from this API")
> > >
> > > Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> > > ---
> > > Changes in v3:
> > > - added x86 GDB register patches
> > > - fix the x87 FPU tag word returned by the GDB stub
> > > - split SSE registers into a separate org.gnu.gdb.i386.sse feature
> > > - expose AVX/AVX-512 registers (ymm/zmm upper halves and opmask)
> > > - expose more system registers to HMP
> > > - renamed i386-segments.xml to i386-system.xml and registered it as an
> > > internal feature, like the other targets
> > > - moved the HMP $pc removal to its own patch and documented it in
> > > removed-features.rst
> > > - moved each target's MonitorDef removal into its target patch; the final
> > > patch now only removes the generic MonitorDef infrastructure
> > > - added MAINTAINERS entries
> > > - rebased onto current master
> > > - Link to v2: https://lore.kernel.org/qemu-devel/20261013-query-reg-v2-0-6f95a2e139a9@redhat.com
> > >
> > > Changes in v2:
> > > - dropped v1 patch 5 (CPUClass::get_pc fallback for $pc)
> > > - new patch gdb_register_internal_coprocessor() to hide registers from GDB
> > > - SPARC64, m68k, RISC-V aliases now use internal registration
> > > - pickup trailer tags
> > > - Link to v1: https://lore.kernel.org/qemu-devel/20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com
> > >
> > > ---
> > > Marc-André Lureau (18):
> > > hmp: don't crash on invalid register
> > > gdbstub: fix next register base after register gaps
> > > gdbstub: set feature->base_reg for dynamic features
> > > gdbstub: add gdb_register_internal_coprocessor()
> > > MAINTAINERS: cover x86 GDB XML files
> > > target/i386: expose segment limits register to monitors via gdbstub
> > > target/i386: fix FPU tag word in GDB register read
> > > target/i386: split SSE registers into separate GDB feature
> > > target/i386: expose system registers to monitors via gdbstub
> > > target/i386: expose AVX/AVX-512 registers to GDB
> > > target/i386: drop HMP $pc
> > > MAINTAINERS: cover m68k GDB XML files
> > > target/m68k: expose system registers to monitors via gdbstub
> > > target/sparc64: expose system registers to monitors via gdbstub
> > > target/riscv: bypass smstateen check in debugger mode
> > > MAINTAINERS: cover riscv GDB XML files
> > > target/riscv: expose register aliases to monitors via gdbstub
> > > monitor/hmp: remove legacy MonitorDef infrastructure
> > >
> > > MAINTAINERS | 4 +
> > > configs/targets/i386-bsd-user.mak | 2 +-
> > > configs/targets/i386-linux-user.mak | 2 +-
> > > configs/targets/i386-softmmu.mak | 2 +-
> > > configs/targets/m68k-softmmu.mak | 2 +-
> > > configs/targets/riscv32-linux-user.mak | 2 +-
> > > configs/targets/riscv32-softmmu.mak | 2 +-
> > > configs/targets/riscv64-bsd-user.mak | 2 +-
> > > configs/targets/riscv64-linux-user.mak | 2 +-
> > > configs/targets/riscv64-softmmu.mak | 2 +-
> > > configs/targets/sparc64-softmmu.mak | 2 +-
> > > configs/targets/x86_64-bsd-user.mak | 2 +-
> > > configs/targets/x86_64-linux-user.mak | 2 +-
> > > configs/targets/x86_64-softmmu.mak | 2 +-
> > > docs/about/removed-features.rst | 8 +
> > > gdbstub/gdb-xml/i386-32bit-avx.xml | 20 ++
> > > gdbstub/gdb-xml/i386-32bit-avx512.xml | 31 +++
> > > gdbstub/gdb-xml/i386-32bit-sse.xml | 54 +++++
> > > gdbstub/gdb-xml/i386-32bit.xml | 46 +---
> > > gdbstub/gdb-xml/i386-64bit-avx.xml | 28 +++
> > > gdbstub/gdb-xml/i386-64bit-avx512.xml | 108 +++++++++
> > > gdbstub/gdb-xml/i386-64bit-sse.xml | 62 +++++
> > > gdbstub/gdb-xml/i386-64bit.xml | 50 ----
> > > gdbstub/gdb-xml/i386-system.xml | 53 +++++
> > > gdbstub/gdb-xml/m68k-system.xml | 32 +++
> > > gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 +++++++++
> > > gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 ++++
> > > gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 +++++++++
> > > gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++
> > > gdbstub/gdb-xml/sparc64-system.xml | 22 ++
> > > gdbstub/gdbstub.c | 85 +++++--
> > > include/exec/gdbstub.h | 21 ++
> > > include/hw/core/cpu.h | 5 +-
> > > include/hw/core/sysemu-cpu-ops.h | 16 --
> > > include/monitor/hmp.h | 6 -
> > > include/qemu/typedefs.h | 1 -
> > > monitor/hmp.c | 45 +---
> > > target/arm/gdbstub.c | 8 +-
> > > target/arm/gdbstub64.c | 10 +-
> > > target/i386/cpu-dump.c | 5 +-
> > > target/i386/cpu.c | 60 +++--
> > > target/i386/cpu.h | 25 ++
> > > target/i386/gdbstub.c | 373 +++++++++++++++++++++++++++---
> > > target/i386/tcg/fpu_helper.c | 24 +-
> > > target/m68k/cpu.c | 22 --
> > > target/m68k/helper.c | 49 +++-
> > > target/ppc/gdbstub.c | 2 +-
> > > target/riscv/cpu.c | 1 -
> > > target/riscv/gdbstub.c | 57 ++++-
> > > target/riscv/internals.h | 3 -
> > > target/riscv/monitor.c | 140 -----------
> > > target/riscv/tcg/csr.c | 3 +-
> > > target/sparc/cpu.c | 19 --
> > > target/sparc/gdbstub.c | 38 +++
> > > target/xtensa/cpu.c | 2 +-
> > > tests/qtest/test-hmp.c | 1 -
> > > 56 files changed, 1383 insertions(+), 478 deletions(-)
> > > ---
> > > base-commit: 8967b2fe1b2aaae3c29e207d85fab901d580a2dc
> > > change-id: 20260910-query-reg-80cd59cf4707
> > >
> > > Best regards,
> > > --
> > > Marc-André Lureau <marcandre.lureau@redhat.com>
> > >
> > --
> > -----Open up your eyes, open up your mind, open up your code -------
> > / Dr. David Alan Gilbert | Running GNU/Linux | Happy \
> > \ dave @ treblig.org | | In Hex /
> > \ _________________________|_____ http://www.treblig.org |_______/
> >
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
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