[PATCH v2 0/2] drm/panthor: Consistently delegate shader power

[PATCH v2 0/2] drm/panthor: Consistently delegate shader power

[Daniel Stone]

Hi,
When trying to bring up a v14 platform, one trap I fell into was
inconsistent power-domain delegation. When delegating a domain, all of
its child domains need to be already delegated, so the firmware can
exercise effective control.

We unconditionally delegate the L2 domain to firmware power management,
along with the tiler and shader domains, however the neural-engine power
domain is also a child of L2 and not delegated. Failing to do this
results in the firmware going into a loop when attempting to power up
the shader cores for the first time.

Changes in v2:
  - send the patches from the right tree so they actually compile

Cheers,
Daniel

[PATCH v2 1/2] drm/panthor: Add neural-engine presence and power bits for v14+

[Daniel Stone]

Mali v14+ can optionally feature a neural engine. This is not currently
used by Panthor, but add the bare-minimum bits required to detect the
engine's presence and control its power.

Signed-off-by: Daniel Stone <daniels@collabora.com>
---
 drivers/gpu/drm/panthor/panthor_gpu_regs.h | 1 +
 drivers/gpu/drm/panthor/panthor_hw.h       | 6 ++++++
 drivers/gpu/drm/panthor/panthor_pwr_regs.h | 7 +++++++
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 4c5b953796e4f..5340966caef37 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -67,6 +67,7 @@
 
 #define GPU_FEATURES					0x60
 #define   GPU_FEATURES_RAY_INTERSECTION			BIT(2)
+#define   GPU_FEATURES_NEURAL_ENGINE			BIT(4)
 #define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
 
 #define GPU_TIMESTAMP_OFFSET				0x88
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index f797663893b2d..924faea27061a 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -61,4 +61,10 @@ static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
 	return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14;
 }
 
+static inline bool panthor_hw_has_neural(struct panthor_device *ptdev)
+{
+	return (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14 &&
+	        ptdev->gpu_info.gpu_features & GPU_FEATURES_NEURAL_ENGINE);
+}
+
 #endif /* __PANTHOR_HW_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
index 9cf7a715066f8..80d8e1e522298 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
@@ -20,12 +20,14 @@
 #define   PWR_STATUS_ALLOW_L2				BIT_U64(0)
 #define   PWR_STATUS_ALLOW_TILER			BIT_U64(1)
 #define   PWR_STATUS_ALLOW_SHADER			BIT_U64(8)
+#define   PWR_STATUS_ALLOW_NEURAL			BIT_U64(9)
 #define   PWR_STATUS_ALLOW_BASE				BIT_U64(14)
 #define   PWR_STATUS_ALLOW_STACK			BIT_U64(15)
 #define   PWR_STATUS_DOMAIN_ALLOWED(x)			BIT_U64(x)
 #define   PWR_STATUS_DELEGATED_L2			BIT_U64(16)
 #define   PWR_STATUS_DELEGATED_TILER			BIT_U64(17)
 #define   PWR_STATUS_DELEGATED_SHADER			BIT_U64(24)
+#define   PWR_STATUS_DELEGATED_NEURAL			BIT_U64(25)
 #define   PWR_STATUS_DELEGATED_BASE			BIT_U64(30)
 #define   PWR_STATUS_DELEGATED_STACK			BIT_U64(31)
 #define   PWR_STATUS_DELEGATED_SHIFT			16
@@ -48,6 +50,7 @@
 #define   PWR_COMMAND_DOMAIN_L2				0
 #define   PWR_COMMAND_DOMAIN_TILER			1
 #define   PWR_COMMAND_DOMAIN_SHADER			8
+#define   PWR_COMMAND_DOMAIN_NEURAL			9
 #define   PWR_COMMAND_DOMAIN_BASE			14
 #define   PWR_COMMAND_DOMAIN_STACK			15
 #define   PWR_COMMAND_SUBDOMAIN_RTU			BIT(0)
@@ -68,6 +71,10 @@
 #define PWR_SHADER_READY				0x208
 #define PWR_SHADER_PWRTRANS				0x210
 #define PWR_SHADER_PWRACTIVE				0x218
+#define PWR_NEURAL_PRESENT				0x240
+#define PWR_NEURAL_READY				0x248
+#define PWR_NEURAL_PWRTRANS				0x250
+#define PWR_NEURAL_PWRACTIVE				0x258
 #define PWR_BASE_PRESENT				0x380
 #define PWR_BASE_READY					0x388
 #define PWR_BASE_PWRTRANS				0x390
-- 
2.47.3

[PATCH v2 2/2] drm/panthor: Delegate neural power domain to CSF when present

[Daniel Stone]

As the neural power domain is a child of the L2 power domain, control
over the L2 domain cannot be delegated to CSF unless the neural domain
has first been delegated. Given that we delegate all power control on
v14+, this eventually causes a hard lock-up and/or firmware OOPS when we
try to power on anything due to the inconsistent delegation state.

Fixes: ee4f9af07933 ("drm/panthor: Implement L2 power on/off via PWR_CONTROL")
Signed-off-by: Daniel Stone <daniels@collabora.com>
---
 drivers/gpu/drm/panthor/panthor_pwr.c | 28 ++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index dd7b6ef8ea209..7a841cfa86fd5 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -146,6 +146,8 @@ static const char *get_domain_name(u8 domain)
 		return "Base";
 	case PWR_COMMAND_DOMAIN_STACK:
 		return "Stack";
+	case PWR_COMMAND_DOMAIN_NEURAL:
+		return "Neural";
 	}
 	return "Unknown";
 }
@@ -163,6 +165,8 @@ static u32 get_domain_base(u8 domain)
 		return PWR_BASE_PRESENT;
 	case PWR_COMMAND_DOMAIN_STACK:
 		return PWR_STACK_PRESENT;
+	case PWR_COMMAND_DOMAIN_NEURAL:
+		return PWR_NEURAL_PRESENT;
 	}
 	return 0;
 }
@@ -229,6 +233,15 @@ static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
 	drm_info(&ptdev->base, "SHADER_PRESENT:  0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
 	drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
 	drm_info(&ptdev->base, "SHADER_READY:    0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
+
+	if (panthor_hw_has_neural(ptdev)) {
+		drm_info(&ptdev->base, "NEURAL_PRESENT:  0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_PRESENT));
+		drm_info(&ptdev->base, "NEURAL_PWRTRANS: 0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_PWRTRANS));
+		drm_info(&ptdev->base, "NEURAL_READY:    0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_READY));
+	}
 }
 
 static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
@@ -405,9 +418,15 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
 	if (!ptdev->pwr)
 		return 0;
 
+	if (panthor_hw_has_neural(ptdev)) {
+		ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
+		if (ret)
+			return ret;
+	}
+
 	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
 	if (ret)
-		return ret;
+		goto err_retract_neural;
 
 	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER);
 	if (ret)
@@ -415,6 +434,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
 
 	return 0;
 
+err_retract_neural:
+	retract_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
 err_retract_shader:
 	retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
 
@@ -517,6 +538,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
 	struct panthor_pwr *pwr = ptdev->pwr;
 	const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
 	const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
+	const bool has_neural = panthor_hw_has_neural(ptdev);
 
 	/* Abort if L2 power off constraints are not satisfied */
 	if (!(pwr_status & l2_allow_mask)) {
@@ -530,6 +552,10 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
 	 * host control to be powered down in the right order before powering
 	 * down the L2.
 	 */
+	if (has_neural &&
+	    panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_NEURAL))
+		return;
+
 	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
 		return;
 
-- 
2.47.3

Re: [PATCH v2 2/2] drm/panthor: Delegate neural power domain to CSF when present

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/panthor: resource leak due to inverted error labels in delegate_domains
- [High] drm/panthor: incorrect error cleanup and teardown order violates LIFO
--

commit c290abd8b3c0e64a66dafb547bc7c789688cb8df
Author: Daniel Stone <daniels@collabora.com>

    drm/panthor: Delegate neural power domain to CSF when present

This commit delegates the neural power domain to the CSF before delegating
other domains to prevent a hard lock-up or firmware OOPS on v14+.
It also updates power state transitions and debugging output for the
neural domain.

> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index dd7b6ef8ea209..7a841cfa86fd5 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c
[ ... ]
> @@ -405,9 +418,15 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  	if (!ptdev->pwr)
>  		return 0;
>  
> +	if (panthor_hw_has_neural(ptdev)) {
> +		ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
>  	if (ret)
> -		return ret;
> +		goto err_retract_neural;
>  
>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER);
>  	if (ret)
> @@ -415,6 +434,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  
>  	return 0;
>  
> +err_retract_neural:
> +	retract_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
>  err_retract_shader:
>  	retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);

[Severity: High]
Does this skip retracting the NEURAL domain on a TILER delegation failure?

If delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER) fails, the code jumps to
err_retract_shader. Because the err_retract_shader label is placed below
err_retract_neural, it skips retracting the NEURAL domain.

Since the commit message notes that an inconsistent delegation state causes a
hard lock-up or firmware OOPS, shouldn't the labels be placed in LIFO order
so err_retract_shader can fall through to err_retract_neural?

>  
> @@ -530,6 +552,10 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>  	 * host control to be powered down in the right order before powering
>  	 * down the L2.
>  	 */
> +	if (has_neural &&
> +	    panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_NEURAL))
> +		return;
> +
>  	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
>  		return;
>  

[Severity: High]
Does this violate the LIFO teardown order for the power domains?

In panthor_pwr_delegate_domains(), the domains are delegated in the order:
NEURAL, SHADER, TILER.

Here in panthor_pwr_l2_power_off(), the NEURAL domain is forced off before
TILER and SHADER. Should the teardown order be TILER, SHADER, then NEURAL
to safely unwind the delegation?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261015135116.713461-1-daniels@collabora.com?part=2

Re: [PATCH v2 1/2] drm/panthor: Add neural-engine presence and power bits for v14+

[Liviu Dudau]

On Thu, Oct 15, 2026 at 02:50:26PM +0100, Daniel Stone wrote:
> Mali v14+ can optionally feature a neural engine. This is not currently
> used by Panthor, but add the bare-minimum bits required to detect the
> engine's presence and control its power.
> 
> Signed-off-by: Daniel Stone <daniels@collabora.com>

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>

Best regards,
Liviu

> ---
>  drivers/gpu/drm/panthor/panthor_gpu_regs.h | 1 +
>  drivers/gpu/drm/panthor/panthor_hw.h       | 6 ++++++
>  drivers/gpu/drm/panthor/panthor_pwr_regs.h | 7 +++++++
>  3 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> index 4c5b953796e4f..5340966caef37 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> @@ -67,6 +67,7 @@
>  
>  #define GPU_FEATURES					0x60
>  #define   GPU_FEATURES_RAY_INTERSECTION			BIT(2)
> +#define   GPU_FEATURES_NEURAL_ENGINE			BIT(4)
>  #define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
>  
>  #define GPU_TIMESTAMP_OFFSET				0x88
> diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
> index f797663893b2d..924faea27061a 100644
> --- a/drivers/gpu/drm/panthor/panthor_hw.h
> +++ b/drivers/gpu/drm/panthor/panthor_hw.h
> @@ -61,4 +61,10 @@ static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
>  	return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14;
>  }
>  
> +static inline bool panthor_hw_has_neural(struct panthor_device *ptdev)
> +{
> +	return (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14 &&
> +	        ptdev->gpu_info.gpu_features & GPU_FEATURES_NEURAL_ENGINE);
> +}
> +
>  #endif /* __PANTHOR_HW_H__ */
> diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> index 9cf7a715066f8..80d8e1e522298 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> @@ -20,12 +20,14 @@
>  #define   PWR_STATUS_ALLOW_L2				BIT_U64(0)
>  #define   PWR_STATUS_ALLOW_TILER			BIT_U64(1)
>  #define   PWR_STATUS_ALLOW_SHADER			BIT_U64(8)
> +#define   PWR_STATUS_ALLOW_NEURAL			BIT_U64(9)
>  #define   PWR_STATUS_ALLOW_BASE				BIT_U64(14)
>  #define   PWR_STATUS_ALLOW_STACK			BIT_U64(15)
>  #define   PWR_STATUS_DOMAIN_ALLOWED(x)			BIT_U64(x)
>  #define   PWR_STATUS_DELEGATED_L2			BIT_U64(16)
>  #define   PWR_STATUS_DELEGATED_TILER			BIT_U64(17)
>  #define   PWR_STATUS_DELEGATED_SHADER			BIT_U64(24)
> +#define   PWR_STATUS_DELEGATED_NEURAL			BIT_U64(25)
>  #define   PWR_STATUS_DELEGATED_BASE			BIT_U64(30)
>  #define   PWR_STATUS_DELEGATED_STACK			BIT_U64(31)
>  #define   PWR_STATUS_DELEGATED_SHIFT			16
> @@ -48,6 +50,7 @@
>  #define   PWR_COMMAND_DOMAIN_L2				0
>  #define   PWR_COMMAND_DOMAIN_TILER			1
>  #define   PWR_COMMAND_DOMAIN_SHADER			8
> +#define   PWR_COMMAND_DOMAIN_NEURAL			9
>  #define   PWR_COMMAND_DOMAIN_BASE			14
>  #define   PWR_COMMAND_DOMAIN_STACK			15
>  #define   PWR_COMMAND_SUBDOMAIN_RTU			BIT(0)
> @@ -68,6 +71,10 @@
>  #define PWR_SHADER_READY				0x208
>  #define PWR_SHADER_PWRTRANS				0x210
>  #define PWR_SHADER_PWRACTIVE				0x218
> +#define PWR_NEURAL_PRESENT				0x240
> +#define PWR_NEURAL_READY				0x248
> +#define PWR_NEURAL_PWRTRANS				0x250
> +#define PWR_NEURAL_PWRACTIVE				0x258
>  #define PWR_BASE_PRESENT				0x380
>  #define PWR_BASE_READY					0x388
>  #define PWR_BASE_PWRTRANS				0x390
> -- 
> 2.47.3
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

Re: [PATCH v2 2/2] drm/panthor: Delegate neural power domain to CSF when present

[Liviu Dudau]

On Thu, Oct 15, 2026 at 02:50:27PM +0100, Daniel Stone wrote:
> As the neural power domain is a child of the L2 power domain, control
> over the L2 domain cannot be delegated to CSF unless the neural domain
> has first been delegated. Given that we delegate all power control on
> v14+, this eventually causes a hard lock-up and/or firmware OOPS when we
> try to power on anything due to the inconsistent delegation state.
> 
> Fixes: ee4f9af07933 ("drm/panthor: Implement L2 power on/off via PWR_CONTROL")
> Signed-off-by: Daniel Stone <daniels@collabora.com>

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>

Best regards,
Liviu

> ---
>  drivers/gpu/drm/panthor/panthor_pwr.c | 28 ++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index dd7b6ef8ea209..7a841cfa86fd5 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c
> @@ -146,6 +146,8 @@ static const char *get_domain_name(u8 domain)
>  		return "Base";
>  	case PWR_COMMAND_DOMAIN_STACK:
>  		return "Stack";
> +	case PWR_COMMAND_DOMAIN_NEURAL:
> +		return "Neural";
>  	}
>  	return "Unknown";
>  }
> @@ -163,6 +165,8 @@ static u32 get_domain_base(u8 domain)
>  		return PWR_BASE_PRESENT;
>  	case PWR_COMMAND_DOMAIN_STACK:
>  		return PWR_STACK_PRESENT;
> +	case PWR_COMMAND_DOMAIN_NEURAL:
> +		return PWR_NEURAL_PRESENT;
>  	}
>  	return 0;
>  }
> @@ -229,6 +233,15 @@ static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
>  	drm_info(&ptdev->base, "SHADER_PRESENT:  0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
>  	drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
>  	drm_info(&ptdev->base, "SHADER_READY:    0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
> +
> +	if (panthor_hw_has_neural(ptdev)) {
> +		drm_info(&ptdev->base, "NEURAL_PRESENT:  0x%016llx",
> +			 gpu_read64(pwr->iomem, PWR_NEURAL_PRESENT));
> +		drm_info(&ptdev->base, "NEURAL_PWRTRANS: 0x%016llx",
> +			 gpu_read64(pwr->iomem, PWR_NEURAL_PWRTRANS));
> +		drm_info(&ptdev->base, "NEURAL_READY:    0x%016llx",
> +			 gpu_read64(pwr->iomem, PWR_NEURAL_READY));
> +	}
>  }
>  
>  static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
> @@ -405,9 +418,15 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  	if (!ptdev->pwr)
>  		return 0;
>  
> +	if (panthor_hw_has_neural(ptdev)) {
> +		ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
>  	if (ret)
> -		return ret;
> +		goto err_retract_neural;
>  
>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER);
>  	if (ret)
> @@ -415,6 +434,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  
>  	return 0;
>  
> +err_retract_neural:
> +	retract_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
>  err_retract_shader:
>  	retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
>  
> @@ -517,6 +538,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>  	struct panthor_pwr *pwr = ptdev->pwr;
>  	const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
>  	const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
> +	const bool has_neural = panthor_hw_has_neural(ptdev);
>  
>  	/* Abort if L2 power off constraints are not satisfied */
>  	if (!(pwr_status & l2_allow_mask)) {
> @@ -530,6 +552,10 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>  	 * host control to be powered down in the right order before powering
>  	 * down the L2.
>  	 */
> +	if (has_neural &&
> +	    panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_NEURAL))
> +		return;
> +
>  	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
>  		return;
>  
> -- 
> 2.47.3
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯