* [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches
@ 2026-10-30 8:57 Steffen Dirkwinkel
2026-10-30 8:57 ` [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Steffen Dirkwinkel
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Steffen Dirkwinkel @ 2026-10-30 8:57 UTC (permalink / raw)
To: GSS_MTK_Uboot_upstream, u-boot
Cc: Tom Rini, Ilias Apalodimas, Ryder Lee, Weijie Gao, Chunfeng Yun,
Igor Belwon, David Lechner, Julien Stephan, Steffen Dirkwinkel,
Carlo Caione, Chris Chen
Running u-boot without caches is slow, especially if using rsa
signatures. This series turns the caches in u-boot spl and proper on
early.
Measured on an MT8370 module (Beckhoff SM0101, not upstream yet) with TF-A
BL2 as DDR loader and SPL loading a 2.7 MB FIT (BL31, OP-TEE, U-Boot,
SHA-256 hashes) from SPI NOR:
SPL, from its banner and from selecting the FIT to the first BL31
output:
caches signature SPL total FIT -> BL31
off - 864.0 / 864.3 ms 808.1 / 808.3 ms
on - 95.8 / 95.8 ms 95.8 / 95.8 ms
off RSA-3072 1903.3 / 1903.8 ms 1836.7 / 1836.8 ms
on RSA-3072 142.0 / 142.0 ms 142.0 / 142.0 ms
U-Boot proper, from bootstage marks before each initcall:
initcall caches off caches on
initf_dm 349.8 / 349.7 4.6 / 4.6 ms
serial_init 204.7 / 204.7 3.0 / 3.0 ms
dram_init 162.2 / 162.1 2.3 / 2.3 ms
relocation copy 22.0 / 22.0 0.4 / 0.4 ms
board_init_f() to main_loop()
819 / 819 87 / 87 ms
Autoboot prompt after power-on, which includes a 5 s USB download wait
in the BootROM:
unsigned FIT RSA-3072 signed FIT
without series 8412 / 8411 ms 9436 / 9437 ms
patch 1 7650 / 7651 ms 7660 / 7657 ms
both patches 6902 / 6906 / 6894 ms 6928 / 6924 ms
The module tests used a v2026.10 based tree with the Genio SPL support
cherry picked.
On v2027.01-rc1 the Genio 510 and 700 EVK configurations build with both
patches, but I didn't test on the evk.
I used an LLM to help write and test the patches.
---
Steffen Dirkwinkel (2):
arm: mediatek: mt8188: enable the caches in SPL
arm: mediatek: mt8188: run board_init_f() with the caches on
arch/arm/mach-mediatek/cpu.c | 14 ++++++++++++++
arch/arm/mach-mediatek/mt8188/init.c | 31 +++++++++++++++++++++++++++++++
arch/arm/mach-mediatek/spl.c | 7 +++++++
3 files changed, 52 insertions(+)
---
base-commit: dfcfc4c9f78d1743f490a497082a4ec8e058aae8
change-id: 20261027-std-upstream-mt8188-spl-caches-2f4271625329
Best regards,
--
Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL
2026-10-30 8:57 [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Steffen Dirkwinkel
@ 2026-10-30 8:57 ` Steffen Dirkwinkel
2026-10-30 14:21 ` Carlo Caione
2026-10-30 8:57 ` [PATCH 2/2] arm: mediatek: mt8188: run board_init_f() with the caches on Steffen Dirkwinkel
2026-10-30 14:10 ` [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Carlo Caione
2 siblings, 1 reply; 6+ messages in thread
From: Steffen Dirkwinkel @ 2026-10-30 8:57 UTC (permalink / raw)
To: GSS_MTK_Uboot_upstream, u-boot
Cc: Tom Rini, Ilias Apalodimas, Ryder Lee, Weijie Gao, Chunfeng Yun,
Igor Belwon, David Lechner, Julien Stephan, Steffen Dirkwinkel,
Carlo Caione, Chris Chen
From: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Running through spl without the dcache is very slow, especially when
hashing or checking signatures.
Time from the SPL banner to entering BL31 on an MT8370 module loading a
2.7 MB FIT with SHA-256 hashes from SPI NOR, two boots each:
FIT caches off caches on
unsigned 864.0 / 864.3 ms 95.8 / 95.8 ms
RSA-3072 signature 1903.3 / 1903.8 ms 142.0 / 142.0 ms
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
---
arch/arm/mach-mediatek/mt8188/init.c | 14 ++++++++++++++
arch/arm/mach-mediatek/spl.c | 7 +++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c
index b2cdec8c2189..2e6aa041c38f 100644
--- a/arch/arm/mach-mediatek/mt8188/init.c
+++ b/arch/arm/mach-mediatek/mt8188/init.c
@@ -6,6 +6,7 @@
* Chris-QJ Chen <chris-qj.chen@mediatek.com>
*/
+#include <cpu_func.h>
#include <asm/global_data.h>
#include <asm/system.h>
#include <dm/uclass.h>
@@ -47,3 +48,16 @@ int print_cpuinfo(void)
printf("CPU: MediaTek MT8188\n");
return 0;
}
+
+#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+/* Early page tables, in DRAM unused by SPL and by U-Boot before relocation */
+#define MT8188_EARLY_TLB_ADDR 0x4e000000
+
+/* Initialize the MMU and activate the data cache in SPL */
+void mtk_spl_enable_caches(void)
+{
+ gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR;
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c
index 125ebcd784fe..8073101e3ef6 100644
--- a/arch/arm/mach-mediatek/spl.c
+++ b/arch/arm/mach-mediatek/spl.c
@@ -14,10 +14,17 @@ __weak int mtk_soc_early_init(void)
return 0;
}
+__weak void mtk_spl_enable_caches(void)
+{
+}
+
void board_init_f(ulong dummy)
{
int ret;
+ /* enable caches early */
+ mtk_spl_enable_caches();
+
ret = spl_early_init();
if (ret)
hang();
--
2.56.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm: mediatek: mt8188: run board_init_f() with the caches on
2026-10-30 8:57 [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Steffen Dirkwinkel
2026-10-30 8:57 ` [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Steffen Dirkwinkel
@ 2026-10-30 8:57 ` Steffen Dirkwinkel
2026-10-30 14:10 ` [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Carlo Caione
2 siblings, 0 replies; 6+ messages in thread
From: Steffen Dirkwinkel @ 2026-10-30 8:57 UTC (permalink / raw)
To: GSS_MTK_Uboot_upstream, u-boot
Cc: Tom Rini, Ilias Apalodimas, Ryder Lee, Weijie Gao, Chunfeng Yun,
Igor Belwon, David Lechner, Julien Stephan, Steffen Dirkwinkel,
Carlo Caione, Chris Chen
From: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Device tree walks and other setup is very slow without caches, so turn
them on before relocation.
On an MT8370 module, from bootstage marks before each initcall, two
boots each:
step caches off caches on
initf_dm 349.8 / 349.7 4.6 / 4.6 ms
serial_init 204.7 / 204.7 3.0 / 3.0 ms
dram_init 162.2 / 162.1 2.3 / 2.3 ms
relocate_code 22.0 / 22.0 0.4 / 0.4 ms
board_init_f() to main_loop() 819 / 819 87 / 87 ms
and from the serial console, after power-on (includes 5s debug usb wait):
U-Boot banner 7346 / 7346 ms 6772 / 6777 / 6765 ms
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
---
arch/arm/mach-mediatek/cpu.c | 14 ++++++++++++++
arch/arm/mach-mediatek/mt8188/init.c | 23 ++++++++++++++++++++---
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c
index 04ede8823b07..484a50f0a25c 100644
--- a/arch/arm/mach-mediatek/cpu.c
+++ b/arch/arm/mach-mediatek/cpu.c
@@ -7,10 +7,13 @@
#include <dm.h>
#include <init.h>
#include <wdt.h>
+#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <linux/arm-smccc.h>
#include <linux/types.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define MTK_SIP_PLAT_BINFO ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
ARM_SMCCC_OWNER_SIP, 0x529)
@@ -23,6 +26,17 @@ int arch_cpu_init(void)
void enable_caches(void)
{
+#if IS_ENABLED(CONFIG_TARGET_MT8188) && !IS_ENABLED(CONFIG_XPL_BUILD) && \
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+ /* Deactivate the data cache, enabled before relocation in mach_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing
+ * tlb_fillptr, to use the page tables reserved by arch_reserve_mmu()
+ */
+ gd->arch.tlb_fillptr = 0;
+#endif
+
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c
index 2e6aa041c38f..139412071131 100644
--- a/arch/arm/mach-mediatek/mt8188/init.c
+++ b/arch/arm/mach-mediatek/mt8188/init.c
@@ -49,15 +49,32 @@ int print_cpuinfo(void)
return 0;
}
-#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Early page tables, in DRAM unused by SPL and by U-Boot before relocation */
#define MT8188_EARLY_TLB_ADDR 0x4e000000
-/* Initialize the MMU and activate the data cache in SPL */
-void mtk_spl_enable_caches(void)
+/*
+ * Initialize the MMU and activate the data cache in SPL and in the U-Boot
+ * pre-reloc stage. The MMU/TLB is updated in enable_caches() after relocation.
+ */
+static void mt8188_enable_early_caches(void)
{
gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR;
gd->arch.tlb_size = PGTABLE_SIZE;
dcache_enable();
}
+
+#if IS_ENABLED(CONFIG_XPL_BUILD)
+void mtk_spl_enable_caches(void)
+{
+ mt8188_enable_early_caches();
+}
+#else
+int mach_cpu_init(void)
+{
+ mt8188_enable_early_caches();
+
+ return 0;
+}
+#endif
#endif
--
2.56.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches
2026-10-30 8:57 [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Steffen Dirkwinkel
2026-10-30 8:57 ` [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Steffen Dirkwinkel
2026-10-30 8:57 ` [PATCH 2/2] arm: mediatek: mt8188: run board_init_f() with the caches on Steffen Dirkwinkel
@ 2026-10-30 14:10 ` Carlo Caione
2 siblings, 0 replies; 6+ messages in thread
From: Carlo Caione @ 2026-10-30 14:10 UTC (permalink / raw)
To: Steffen Dirkwinkel
Cc: GSS_MTK_Uboot_upstream, u-boot, Tom Rini, Ilias Apalodimas,
Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon, David Lechner,
Julien Stephan, Steffen Dirkwinkel, Chris Chen
On Fri, Oct 30, 2026 at 09:57:40 +0100, Steffen Dirkwinkel wrote:
> Running u-boot without caches is slow, especially if using rsa
> signatures. This series turns the caches in u-boot spl and proper on
> early.
Hi Steffen,
interestingly this is going to conflict with my work at [0] but mine
was specific to DA so I welcome this effort to expand the fix to SPL as
well :)
[0] https://lore.kernel.org/all/20261022-ccaione-upstream-mt8390-da-v5-4-58982fe11312@baylibre.com/
--
Carlo Caione
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL
2026-10-30 8:57 ` [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Steffen Dirkwinkel
@ 2026-10-30 14:21 ` Carlo Caione
2026-10-30 14:27 ` Carlo Caione
0 siblings, 1 reply; 6+ messages in thread
From: Carlo Caione @ 2026-10-30 14:21 UTC (permalink / raw)
To: Steffen Dirkwinkel
Cc: GSS_MTK_Uboot_upstream, u-boot, Tom Rini, Ilias Apalodimas,
Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon, David Lechner,
Julien Stephan, Steffen Dirkwinkel, Chris Chen
On Fri, Oct 30, 2026 at 09:57:41 +0100, Steffen Dirkwinkel wrote:
> From: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
>
> Running through spl without the dcache is very slow, especially when
> hashing or checking signatures.
>
> Time from the SPL banner to entering BL31 on an MT8370 module loading a
> 2.7 MB FIT with SHA-256 hashes from SPI NOR, two boots each:
>
> FIT caches off caches on
> unsigned 864.0 / 864.3 ms 95.8 / 95.8 ms
> RSA-3072 signature 1903.3 / 1903.8 ms 142.0 / 142.0 ms
>
> Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
> ---
> arch/arm/mach-mediatek/mt8188/init.c | 14 ++++++++++++++
> arch/arm/mach-mediatek/spl.c | 7 +++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c
> index b2cdec8c2189..2e6aa041c38f 100644
> --- a/arch/arm/mach-mediatek/mt8188/init.c
> +++ b/arch/arm/mach-mediatek/mt8188/init.c
> @@ -6,6 +6,7 @@
> * Chris-QJ Chen <chris-qj.chen@mediatek.com>
> */
>
> +#include <cpu_func.h>
> #include <asm/global_data.h>
> #include <asm/system.h>
> #include <dm/uclass.h>
> @@ -47,3 +48,16 @@ int print_cpuinfo(void)
> printf("CPU: MediaTek MT8188\n");
> return 0;
> }
> +
> +#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> +/* Early page tables, in DRAM unused by SPL and by U-Boot before relocation */
> +#define MT8188_EARLY_TLB_ADDR 0x4e000000
Could we use an explicitly allocated/aligned buffer for the early tables
instead of 0x4e000000? That address works with the current layout, but
nothing reserves it against other image loads.
> +
> +/* Initialize the MMU and activate the data cache in SPL */
> +void mtk_spl_enable_caches(void)
> +{
> + gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR;
> + gd->arch.tlb_size = PGTABLE_SIZE;
> + dcache_enable();
> +}
> +#endif
With CONFIG_CMO_BY_VA_ONLY=y, the baseline reaches the console, but
this patch stops before BL31. SPL leaves gd->ram_base/ram_size unset, so
VA-based cache flushing skips RAM. Could we handle this mode, or leave
early caching disabled for it?
> diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c
> index 125ebcd784fe..8073101e3ef6 100644
> --- a/arch/arm/mach-mediatek/spl.c
> +++ b/arch/arm/mach-mediatek/spl.c
> @@ -14,10 +14,17 @@ __weak int mtk_soc_early_init(void)
> return 0;
> }
>
> +__weak void mtk_spl_enable_caches(void)
> +{
> +}
> +
> void board_init_f(ulong dummy)
> {
> int ret;
>
> + /* enable caches early */
> + mtk_spl_enable_caches();
> +
The BL31 path already disables D-cache/MMU, but jump_to_image() does
not, so this patch is in general fine if we are jumping to BL31 but it
is not if we directly jump to BL33 for example.
I tried a direct jump to a proper U-Boot from SPL and indeed both remain
enabled with this patch, whereas the baseline hands over with both
disabled. Could we cover the direct handoff too?
> ret = spl_early_init();
> if (ret)
> hang();
>
> --
> 2.56.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL
2026-10-30 14:21 ` Carlo Caione
@ 2026-10-30 14:27 ` Carlo Caione
0 siblings, 0 replies; 6+ messages in thread
From: Carlo Caione @ 2026-10-30 14:27 UTC (permalink / raw)
To: Steffen Dirkwinkel
Cc: GSS_MTK_Uboot_upstream, u-boot, Tom Rini, Ilias Apalodimas,
Ryder Lee, Weijie Gao, Chunfeng Yun, Igor Belwon, David Lechner,
Julien Stephan, Steffen Dirkwinkel, Chris Chen
On Fri, Oct 30, 2026 at 15:21:30 +0100, Carlo Caione wrote:
> On Fri, Oct 30, 2026 at 09:57:41 +0100, Steffen Dirkwinkel wrote:
[...]
> With CONFIG_CMO_BY_VA_ONLY=y, the baseline reaches the console, but
> this patch stops before BL31. SPL leaves gd->ram_base/ram_size unset, so
> VA-based cache flushing skips RAM. Could we handle this mode, or leave
> early caching disabled for it?
On a second thought, forget about this. This is very unlikely to be
an issue and I honestly caught it only by accident, so this is just
nitpicking on my side. All the other problems still stand though.
Thanks!
--
Carlo Caione
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-30 14:27 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-10-30 8:57 [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Steffen Dirkwinkel
2026-10-30 8:57 ` [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Steffen Dirkwinkel
2026-10-30 14:21 ` Carlo Caione
2026-10-30 14:27 ` Carlo Caione
2026-10-30 8:57 ` [PATCH 2/2] arm: mediatek: mt8188: run board_init_f() with the caches on Steffen Dirkwinkel
2026-10-30 14:10 ` [PATCH 0/2] arm: mediatek: mt8188: run SPL and pre-relocation U-Boot with caches Carlo Caione
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