From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: Aastha Rawat <aastharawat@linux.microsoft.com>
Cc: qemu-devel@nongnu.org,
"Magnus Kulke" <magnuskulke@linux.microsoft.com>,
"Wei Liu" <wei.liu@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Anirudh Rayabharam" <anirudh@anirudhrb.com>,
qemu-arm@nongnu.org, "Alexander Graf" <agraf@csgraf.de>,
"Pedro Barbuda" <pbarbuda@microsoft.com>,
"Mohamed Mediouni" <mohamed@unpredictable.fr>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
Subject: Re: [PATCH v6 05/14] target/arm/mshv: implement vcpu state operations for ARM64
Date: Fri, 13 Nov 2026 17:05:21 +0200 [thread overview]
Message-ID: <avcnMV0isGvRNhyE@linux.microsoft.com> (raw)
In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-5-aefe5e76a0e3@linux.microsoft.com>
On Thu, Oct 01, 2026 at 10:52:50AM +0000, Aastha Rawat wrote:
> Add support for reading and writing ARM64 CPU registers in the MSHV
> accelerator. This includes functions to set and get registers,
> initialize and destroy VCPU state, and manage register state
> synchronization between QEMU and hypervisor.
>
> Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
> ---
> include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++++
> target/arm/mshv/mshv-all.c | 119 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 161 insertions(+)
>
> diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
> index a5527d49cf..b5bcea353a 100644
> --- a/include/hw/hyperv/hvgdk_mini.h
> +++ b/include/hw/hyperv/hvgdk_mini.h
> @@ -32,6 +32,46 @@ typedef enum hv_register_name {
> HV_REGISTER_PENDING_EVENT0 = 0x00010004,
> HV_REGISTER_PENDING_EVENT1 = 0x00010005,
>
> +#if defined(__aarch64__)
> + HV_ARM64_REGISTER_XZR = 0x0002FFFE,
> + HV_ARM64_REGISTER_X0 = 0x00020000,
> + HV_ARM64_REGISTER_X1 = 0x00020001,
> + HV_ARM64_REGISTER_X2 = 0x00020002,
> + HV_ARM64_REGISTER_X3 = 0x00020003,
> + HV_ARM64_REGISTER_X4 = 0x00020004,
> + HV_ARM64_REGISTER_X5 = 0x00020005,
> + HV_ARM64_REGISTER_X6 = 0x00020006,
> + HV_ARM64_REGISTER_X7 = 0x00020007,
> + HV_ARM64_REGISTER_X8 = 0x00020008,
> + HV_ARM64_REGISTER_X9 = 0x00020009,
> + HV_ARM64_REGISTER_X10 = 0x0002000A,
> + HV_ARM64_REGISTER_X11 = 0x0002000B,
> + HV_ARM64_REGISTER_X12 = 0x0002000C,
> + HV_ARM64_REGISTER_X13 = 0x0002000D,
> + HV_ARM64_REGISTER_X14 = 0x0002000E,
> + HV_ARM64_REGISTER_X15 = 0x0002000F,
> + HV_ARM64_REGISTER_X16 = 0x00020010,
> + HV_ARM64_REGISTER_X17 = 0x00020011,
> + HV_ARM64_REGISTER_X18 = 0x00020012,
> + HV_ARM64_REGISTER_X19 = 0x00020013,
> + HV_ARM64_REGISTER_X20 = 0x00020014,
> + HV_ARM64_REGISTER_X21 = 0x00020015,
> + HV_ARM64_REGISTER_X22 = 0x00020016,
> + HV_ARM64_REGISTER_X23 = 0x00020017,
> + HV_ARM64_REGISTER_X24 = 0x00020018,
> + HV_ARM64_REGISTER_X25 = 0x00020019,
> + HV_ARM64_REGISTER_X26 = 0x0002001A,
> + HV_ARM64_REGISTER_X27 = 0x0002001B,
> + HV_ARM64_REGISTER_X28 = 0x0002001C,
> + HV_ARM64_REGISTER_FP = 0x0002001D,
> + HV_ARM64_REGISTER_LR = 0x0002001E,
> + HV_ARM64_REGISTER_PC = 0x00020022,
> +
> + /* AArch64 System Register Descriptions: General system control registers */
> + HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,
> + HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,
> +
> +#elif defined(__x86_64__)
> /* X64 User-Mode Registers */
> HV_X64_REGISTER_RAX = 0x00020000,
> HV_X64_REGISTER_RCX = 0x00020001,
> @@ -188,6 +228,8 @@ typedef enum hv_register_name {
> /* Other MSRs */
> HV_X64_REGISTER_MSR_IA32_MISC_ENABLE = 0x000800A0,
>
> +#endif
> +
> /* Misc */
> HV_X64_REGISTER_HYPERCALL = 0x00090001,
> HV_REGISTER_GUEST_OS_ID = 0x00090002,
> diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
> index 00c54f5d66..29dd45a123 100644
> --- a/target/arm/mshv/mshv-all.c
> +++ b/target/arm/mshv/mshv-all.c
> @@ -10,17 +10,128 @@
> */
>
> #include "qemu/osdep.h"
> +#include <sys/ioctl.h>
> +
> +#include "qemu/error-report.h"
> +#include "qemu/memalign.h"
> #include "hw/arm/virt.h"
> +
> +#include "system/cpus.h"
> +#include "target/arm/cpu.h"
> +
> #include "system/mshv.h"
> #include "system/mshv_int.h"
> +#include "hw/hyperv/hvgdk_mini.h"
> +
> +static const enum hv_register_name STANDARD_REGISTER_NAMES[32] = {
> + HV_ARM64_REGISTER_X0,
> + HV_ARM64_REGISTER_X1,
> + HV_ARM64_REGISTER_X2,
> + HV_ARM64_REGISTER_X3,
> + HV_ARM64_REGISTER_X4,
> + HV_ARM64_REGISTER_X5,
> + HV_ARM64_REGISTER_X6,
> + HV_ARM64_REGISTER_X7,
> + HV_ARM64_REGISTER_X8,
> + HV_ARM64_REGISTER_X9,
> + HV_ARM64_REGISTER_X10,
> + HV_ARM64_REGISTER_X11,
> + HV_ARM64_REGISTER_X12,
> + HV_ARM64_REGISTER_X13,
> + HV_ARM64_REGISTER_X14,
> + HV_ARM64_REGISTER_X15,
> + HV_ARM64_REGISTER_X16,
> + HV_ARM64_REGISTER_X17,
> + HV_ARM64_REGISTER_X18,
> + HV_ARM64_REGISTER_X19,
> + HV_ARM64_REGISTER_X20,
> + HV_ARM64_REGISTER_X21,
> + HV_ARM64_REGISTER_X22,
> + HV_ARM64_REGISTER_X23,
> + HV_ARM64_REGISTER_X24,
> + HV_ARM64_REGISTER_X25,
> + HV_ARM64_REGISTER_X26,
> + HV_ARM64_REGISTER_X27,
> + HV_ARM64_REGISTER_X28,
> + HV_ARM64_REGISTER_FP,
> + HV_ARM64_REGISTER_LR,
> + HV_ARM64_REGISTER_PC,
> +};
> +
> +static int set_standard_regs(const CPUState *cpu)
> +{
> + size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);
> + struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = {};
> + int ret;
> + ARMCPU *arm_cpu = ARM_CPU(cpu);
> + CPUARMState *env = &arm_cpu->env;
> +
> + for (size_t i = 0; i < n_regs - 1; i++) {
> + assocs[i].name = STANDARD_REGISTER_NAMES[i];
> + assocs[i].value.reg64 = env->xregs[i];
> + }
> +
> + /* Last register is the program counter */
> + assocs[n_regs - 1].name = STANDARD_REGISTER_NAMES[n_regs - 1];
> + assocs[n_regs - 1].value.reg64 = env->pc;
> +
> + ret = mshv_set_generic_regs(cpu, assocs, n_regs);
> + if (ret < 0) {
> + error_report("failed to set standard registers");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> +static int get_standard_regs(CPUState *cpu)
> +{
> + size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);
> + struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = {};
> + int ret;
> + ARMCPU *arm_cpu = ARM_CPU(cpu);
> + CPUARMState *env = &arm_cpu->env;
> +
> + for (size_t i = 0; i < n_regs; i++) {
> + assocs[i].name = STANDARD_REGISTER_NAMES[i];
> + }
> + ret = mshv_get_generic_regs(cpu, assocs, n_regs);
> + if (ret < 0) {
> + error_report("failed to get standard registers");
> + return -1;
> + }
> +
> + for (size_t i = 0; i < n_regs - 1; i++) {
> + env->xregs[i] = assocs[i].value.reg64;
> + }
> + env->pc = assocs[n_regs - 1].value.reg64;
> +
> + return 0;
> +}
>
> static int load_regs(CPUState *cpu)
> {
> + int ret;
> +
> + ret = get_standard_regs(cpu);
> + if (ret < 0) {
> + error_report("Failed to load standard registers");
> + return -1;
> + }
> +
> return 0;
> }
>
I see that only these general purpose registers are synchronized after an exit,
reset or init.
At a glance, KVM also handles registers such as PSTATE and SP_EL0/SP_EL1.
Should this implementation handle those as well?
> static int store_regs(const CPUState *cpu)
> {
> + int ret;
> +
> + ret = set_standard_regs(cpu);
> + if (ret < 0) {
> + error_report("Failed to store standard registers");
> + return -1;
> + }
> +
> return 0;
> }
>
> @@ -41,12 +152,20 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)
>
> void mshv_arch_init_vcpu(CPUState *cpu)
> {
> + AccelCPUState *state = cpu->accel;
>
> + mshv_setup_hvcall_args(state);
> }
>
> void mshv_arch_destroy_vcpu(CPUState *cpu)
> {
> + AccelCPUState *state = cpu->accel;
> +
> + if (state->hvcall_args.base) {
> + qemu_vfree(state->hvcall_args.base);
> + }
>
> + state->hvcall_args = (MshvHvCallArgs){0};
> }
>
> int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
>
> --
> 2.45.4
next prev parent reply other threads:[~2026-11-13 15:05 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 10:52 [PATCH v6 00/14] Add ARM64 support for MSHV accelerator Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 01/14] accel/mshv: extract common CPU register helpers Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 02/14] accel/mshv: add arch-specific accelerator init hook Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 03/14] accel/mshv: make MSHV migration initialization arch-specific Aastha Rawat
2026-11-13 11:37 ` Doru Blânzeanu
2026-10-01 10:52 ` [PATCH v6 04/14] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support Aastha Rawat
2026-10-13 16:48 ` Peter Maydell
2026-11-13 12:23 ` Doru Blânzeanu
2026-11-13 12:56 ` Doru Blânzeanu
2026-10-01 10:52 ` [PATCH v6 05/14] target/arm/mshv: implement vcpu state operations for ARM64 Aastha Rawat
2026-11-13 15:05 ` Doru Blânzeanu [this message]
2026-10-01 10:52 ` [PATCH v6 06/14] target/arm: convert host CPU feature ifdef ladder to runtime checks Aastha Rawat
2026-10-13 16:46 ` Peter Maydell
2026-10-23 14:37 ` Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 07/14] target/arm/mshv: implement -cpu host for MSHV Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 08/14] accel/mshv: Add access_vp_regs synthetic proc features Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 09/14] target/arm: cpu: Mark MSHV supporting PSCI 1.3 Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 10/14] target/arm: extract MMIO emulation logic for HVF & WHPX Aastha Rawat
2026-10-13 16:40 ` Peter Maydell
2026-10-22 10:27 ` Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 11/14] target/arm/mshv: add vCPU run loop Aastha Rawat
2026-10-13 16:50 ` Peter Maydell
2026-10-16 9:56 ` Anirudh Rayabharam
2026-10-01 10:52 ` [PATCH v6 12/14] include/hw/hyperv: adjust hv_interrupt_control structure for arm64 Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 13/14] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation Aastha Rawat
2026-10-01 10:52 ` [PATCH v6 14/14] MAINTAINERS: updates for MSHV arm64 code Aastha Rawat
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