* [PULL 00/38] tcg patch queue
@ 2026-08-18 17:01 Richard Henderson
2026-08-18 17:01 ` [PULL 01/38] tcg/optimize: INDEX_op_mul is commutative Richard Henderson
` (38 more replies)
0 siblings, 39 replies; 44+ messages in thread
From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw)
To: qemu-devel
The following changes since commit fa19879df1658f96ac07365fca8835b7decd6995:
Merge tag 'pull-block-jobs-2026-08-17' of https://gitlab.com/vsementsov/qemu into staging (2026-08-17 15:37:53 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20260818
for you to fetch changes up to ff90861d1c4a1eda23d83cdb18c3647f2e2b0128:
target/mips: Enable disassembly via capstone (2026-08-18 09:06:53 -0700)
----------------------------------------------------------------
accel/tcg: Allow overlapping reads in record_save
tcg/optimize: INDEX_op_mul is commutative
tcg/optimize: Fix s_mask computation for shifts
tcg: Defer tb_flush when initial thread region alloc fails
tcg: Add revbit{8,32,64} opcodes
tcg: Add integer min/max opcodes
disas: Updates for capstone v6
----------------------------------------------------------------
Ilya Chichkov (1):
accel/tcg: Allow overlapping reads in record_save
Richard Henderson (37):
tcg/optimize: INDEX_op_mul is commutative
tcg/optimize: Fix s_mask computation for shifts
tcg: Return success from tcg_region_alloc__locked
tcg: Return success from tcg_region_alloc
tcg: Defer tb_flush when initial thread region alloc fails
tcg: Fix opcode dump for bswap
tcg: Add tcg_gen_revbit{8,32,64}
tcg: Simplify bswap/hswap expansion using bitswap
target/arm: Use generic tcg_gen_revbit*
target/loongarch: Use generic tcg_gen_revbit*
target/mips: Expand octeon reflections inline
target/riscv: Use generic tcg_gen_revbit8
tcg: Add revbit{8,32,64} opcodes
tcg/optimize: Handle revbit{8,32,64}
tcg/aarch64: Implement revbit{32,64}
tcg/loongarch64: Import REVBIT insns
tcg/loongarch64: Implement revbit{8,32,64}
util/cpuinfo-riscv: Detect Zbkb
tcg/riscv64: Implement revbit8
tests/tcg/loongarch64: Tidy test_bit.c
tests/tcg/loongarch64: Add bitrev smoke tests
tcg: Add integer min/max opcodes
tcg/optimize: Handle min/max opcodes
util/cpuinfo-aarch64: Detect FEAT_CSSC
tcg/aarch64: Implement min/max with FEAT_CSSC
target/riscv64: Implement min/max with Zbb
tcg/aarch64: Implement ctpop with FEAT_CSSC
tcg/aarch64: Use CTZ from FEAT_CSSC
target/riscv: Improve riscv_has_ext
disas/capstone: Allow for cap_insn_unit > length
target/riscv: Enable disassembly via capstone
target/sh4: Enable disassembly via capstone
target/tricore: Enable disassembly via capstone
target/loongarch: Enable disassembly via capstone
target/s390x: Update capstone disassembly to v6
target/m68k: Enable disassembly via capstone
target/mips: Enable disassembly via capstone
host/include/aarch64/host/cpuinfo.h | 1 +
host/include/riscv64/host/cpuinfo.h | 1 +
include/disas/capstone.h | 115 ++-
include/tcg/tcg-op-common.h | 5 +
include/tcg/tcg-op.h | 7 +
include/tcg/tcg-opc.h | 7 +
target/arm/tcg/helper-a64-defs.h | 1 -
target/arm/tcg/helper-defs.h | 1 -
target/loongarch/tcg/helper.h | 4 -
target/mips/helper.h | 7 -
target/riscv/cpu.h | 2 +-
target/riscv/helper.h | 1 -
tcg/aarch64/tcg-target-con-set.h | 2 +
tcg/aarch64/tcg-target-con-str.h | 2 +
tcg/tcg-internal.h | 2 +-
accel/tcg/translator.c | 14 +-
disas/capstone.c | 29 +-
target/arm/tcg/helper-a64.c | 5 -
target/arm/tcg/op_helper.c | 5 -
target/arm/tcg/translate-a64.c | 4 +-
target/arm/tcg/translate.c | 2 +-
target/loongarch/cpu.c | 8 +
target/loongarch/tcg/op_helper.c | 21 -
target/m68k/cpu.c | 65 +-
target/mips/cpu.c | 60 +-
target/mips/tcg/octeon_crypto.c | 35 -
target/mips/tcg/octeon_translate.c | 49 +-
target/riscv/cpu.c | 81 +-
target/riscv/tcg/bitmanip_helper.c | 15 -
target/s390x/cpu.c | 4 +-
target/sh4/cpu.c | 14 +
target/tricore/cpu.c | 31 +
tcg/optimize.c | 142 +++-
tcg/region.c | 40 +-
tcg/tcg-op.c | 234 ++++--
tcg/tcg.c | 41 +-
tests/tcg/i386/test-i386-opt-shr.c | 21 +
tests/tcg/loongarch64/test_bit.c | 77 +-
util/cpuinfo-aarch64.c | 2 +
util/cpuinfo-riscv.c | 17 +-
docs/devel/tcg-ops.rst | 28 +
target/loongarch/tcg/insn_trans/trans_bit.c.inc | 13 +-
target/riscv/tcg/insn_trans/trans_rvb.c.inc | 2 +-
tcg/aarch64/tcg-target.c.inc | 197 ++++-
tcg/loongarch64/tcg-insn-defs.c.inc | 960 +++++++++++++-----------
tcg/loongarch64/tcg-target.c.inc | 56 ++
tcg/ppc64/tcg-target.c.inc | 28 +
tcg/riscv64/tcg-target.c.inc | 79 ++
tcg/s390x/tcg-target.c.inc | 28 +
tcg/sparc64/tcg-target.c.inc | 28 +
tcg/tci/tcg-target.c.inc | 28 +
tcg/x86_64/tcg-target.c.inc | 28 +
52 files changed, 1869 insertions(+), 780 deletions(-)
create mode 100644 tests/tcg/i386/test-i386-opt-shr.c
^ permalink raw reply [flat|nested] 44+ messages in thread* [PULL 01/38] tcg/optimize: INDEX_op_mul is commutative 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts Richard Henderson ` (37 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-stable, Philippe Mathieu-Daudé Cc: qemu-stable@nongnu.org Fixes: 7a2f7084525 ("tcg/optimize: Sink commutative operand swapping into fold functions") Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index fcdef25bee..ed2ff32ed2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2152,7 +2152,7 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) static bool fold_mul(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, 1)) { return true; -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson 2026-08-18 17:01 ` [PULL 01/38] tcg/optimize: INDEX_op_mul is commutative Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-21 16:51 ` Michael Tokarev 2026-08-18 17:01 ` [PULL 03/38] accel/tcg: Allow overlapping reads in record_save Richard Henderson ` (36 subsequent siblings) 38 siblings, 1 reply; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-stable, Jacob Young Skip s_mask computation for logical right shift. Cc: qemu-stable@nongnu.org Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") Reported-by: Jacob Young <jacobly@ziglang.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/optimize.c | 11 ++++++++++- tests/tcg/i386/test-i386-opt-shr.c | 21 +++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/i386/test-i386-opt-shr.c diff --git a/tcg/optimize.c b/tcg/optimize.c index ed2ff32ed2..d12babad88 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2656,8 +2656,17 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); o_mask = do_constant_folding(op->opc, ctx->type, o_mask, sh); - s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); + if (op->opc == INDEX_op_shr) { + /* + * Logical right shift will force the sign bit zero. + * Don't bother computing s_mask and let fold_masks + * recompute from z_mask. + */ + return fold_masks_zo(ctx, op, z_mask, o_mask); + } + + s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); return fold_masks_zos(ctx, op, z_mask, o_mask, s_mask); } diff --git a/tests/tcg/i386/test-i386-opt-shr.c b/tests/tcg/i386/test-i386-opt-shr.c new file mode 100644 index 0000000000..9fb8d42022 --- /dev/null +++ b/tests/tcg/i386/test-i386-opt-shr.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Regression test for tcg optimize vs sign bit repetition counting. */ + +#include <assert.h> + +int main() +{ +#ifndef __x86_64__ + char test; + + asm("movw $0x4000, %%ax\n\t" + "addw %%ax, %%ax\n\t" + "cwtl\n\t" + "shrl %%eax\n\t" + "cmpw $-0x3fff, %%ax\n\t" + "setnl %%al" + : "=a"(test)); + assert(!test); +#endif + return 0; +} -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts 2026-08-18 17:01 ` [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts Richard Henderson @ 2026-08-21 16:51 ` Michael Tokarev 2026-08-21 17:33 ` Richard Henderson 0 siblings, 1 reply; 44+ messages in thread From: Michael Tokarev @ 2026-08-21 16:51 UTC (permalink / raw) To: Richard Henderson, qemu-devel; +Cc: qemu-stable, Jacob Young, QEMU Stable On 8/18/26 20:01, Richard Henderson wrote: > Skip s_mask computation for logical right shift. > > Cc: qemu-stable@nongnu.org > Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") > Reported-by: Jacob Young <jacobly@ziglang.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/optimize.c | 11 ++++++++++- > tests/tcg/i386/test-i386-opt-shr.c | 21 +++++++++++++++++++++ > 2 files changed, 31 insertions(+), 1 deletion(-) > create mode 100644 tests/tcg/i386/test-i386-opt-shr.c > > diff --git a/tcg/optimize.c b/tcg/optimize.c > index ed2ff32ed2..d12babad88 100644 > --- a/tcg/optimize.c > +++ b/tcg/optimize.c > @@ -2656,8 +2656,17 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) > > z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); > o_mask = do_constant_folding(op->opc, ctx->type, o_mask, sh); > - s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); > > + if (op->opc == INDEX_op_shr) { > + /* > + * Logical right shift will force the sign bit zero. > + * Don't bother computing s_mask and let fold_masks > + * recompute from z_mask. > + */ > + return fold_masks_zo(ctx, op, z_mask, o_mask); > + } > + > + s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); In 10.0.x, things are (were) a bit different. Does this back-port look sane? -- https://gitlab.com/mjt0k/qemu/-/commit/77ad6491326b4d0b2907f0ed9d504d6f490e245c Thanks, /mjt ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts 2026-08-21 16:51 ` Michael Tokarev @ 2026-08-21 17:33 ` Richard Henderson 0 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-21 17:33 UTC (permalink / raw) To: Michael Tokarev, qemu-devel; +Cc: qemu-stable, Jacob Young On 8/21/26 09:51, Michael Tokarev wrote: > On 8/18/26 20:01, Richard Henderson wrote: >> Skip s_mask computation for logical right shift. >> >> Cc: qemu-stable@nongnu.org >> Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") >> Reported-by: Jacob Young <jacobly@ziglang.org> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/optimize.c | 11 ++++++++++- >> tests/tcg/i386/test-i386-opt-shr.c | 21 +++++++++++++++++++++ >> 2 files changed, 31 insertions(+), 1 deletion(-) >> create mode 100644 tests/tcg/i386/test-i386-opt-shr.c >> >> diff --git a/tcg/optimize.c b/tcg/optimize.c >> index ed2ff32ed2..d12babad88 100644 >> --- a/tcg/optimize.c >> +++ b/tcg/optimize.c >> @@ -2656,8 +2656,17 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) >> z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); >> o_mask = do_constant_folding(op->opc, ctx->type, o_mask, sh); >> - s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); >> + if (op->opc == INDEX_op_shr) { >> + /* >> + * Logical right shift will force the sign bit zero. >> + * Don't bother computing s_mask and let fold_masks >> + * recompute from z_mask. >> + */ >> + return fold_masks_zo(ctx, op, z_mask, o_mask); >> + } >> + >> + s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); > > In 10.0.x, things are (were) a bit different. Does this back-port look sane? -- > https://gitlab.com/mjt0k/qemu/-/commit/77ad6491326b4d0b2907f0ed9d504d6f490e245c Perfect, thanks. r~ ^ permalink raw reply [flat|nested] 44+ messages in thread
* [PULL 03/38] accel/tcg: Allow overlapping reads in record_save 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson 2026-08-18 17:01 ` [PULL 01/38] tcg/optimize: INDEX_op_mul is commutative Richard Henderson 2026-08-18 17:01 ` [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 04/38] tcg: Return success from tcg_region_alloc__locked Richard Henderson ` (35 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Ilya Chichkov, qemu-stable From: Ilya Chichkov <ilya.chichkov.dev@gmail.com> record_save() assumed that a target reads the bytes of an insn as a strictly ascending sequence of adjacent chunks, and asserted that each read begins exactly where the previous one ended. That assumption no longer holds for riscv. Since f9eaa1542b ("target/riscv: support atomic instruction fetch (Ziccif)"), decode_opc() loads a full aligned word whenever pc is 4-byte aligned, even when the insn turns out to be a 2-byte compressed one, so the record may already hold bytes past the end of the insn being translated. When such a compressed insn sits at page offset 0xffc, pc_next becomes 0xffe, which is within MAX_INSN_LEN of the end of the page, and riscv_tr_translate_insn() probes the next insn to decide whether it would cross the page boundary. That probe reads at offset 2 while the record already covers [0,4), and the assert fires: qemu-system-riscv32: accel/tcg/translator.c:395: record_save: Assertion `offset == db->record_start + db->record_len' failed. record_save() is only reached when the insn is fetched from MMIO, so this is visible on boards that execute code from a region created with memory_region_init_io(), such as an XIP flash window mapped over a serial flash controller. Both sides of the collision are correct: the wide fetch is required for Ziccif atomicity, and the probe is required for correct fault reporting at a page boundary, per 00c07344fa ("target/riscv: Make translator stop before the end of a page"). Unlike a86d3352ab ("target/riscv: do not use translator_ldl in opcode_at"), where a non-translation caller had no business using translator_ld*, the probe here is a genuine translation read whose bytes must be recorded. Relax the invariant instead. Keep requiring that a read neither moves backwards nor leaves a gap, but let a read overlapping the recorded range extend it only by the bytes past its end. Cc: qemu-stable@nongnu.org Fixes: f9eaa1542b ("target/riscv: support atomic instruction fetch (Ziccif)") Signed-off-by: Ilya Chichkov <ilya.chichkov.dev@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260814142159.3800744-1-ilya.chichkov.dev@gmail.com> --- accel/tcg/translator.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index cd7d079fe0..57daded60f 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -387,14 +387,22 @@ static void record_save(DisasContextBase *db, vaddr pc, * Either the first or second page may be I/O. If it is the second, * then the first byte we need to record will be at a non-zero offset. * In either case, we should not need to record but a single insn. + * + * A read may re-read bytes that are already recorded: a target may + * fetch a whole aligned word to decode an insn (e.g. riscv Ziccif), + * then probe the following insn, which lies within that same word. + * Such a read extends the record only by the bytes past its end. */ if (db->record_len == 0) { db->record_start = offset; db->record_len = size; } else { - assert(offset == db->record_start + db->record_len); - assert(db->record_len + size <= sizeof(db->record)); - db->record_len += size; + int end = offset - db->record_start + size; + + assert(offset >= db->record_start); + assert(offset <= db->record_start + db->record_len); + assert(end <= sizeof(db->record)); + db->record_len = MAX(db->record_len, end); } memcpy(db->record + (offset - db->record_start), from, size); -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 04/38] tcg: Return success from tcg_region_alloc__locked 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (2 preceding siblings ...) 2026-08-18 17:01 ` [PULL 03/38] accel/tcg: Allow overlapping reads in record_save Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 05/38] tcg: Return success from tcg_region_alloc Richard Henderson ` (34 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Invert the sense of the boolean result from 'error' to 'success'. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/region.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index 5d4be1453b..2161d961d9 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -360,11 +360,11 @@ static void tcg_region_assign(TCGContext *s, size_t curr_region) static bool tcg_region_alloc__locked(TCGContext *s) { if (region.current == region.n) { - return true; + return false; } tcg_region_assign(s, region.current); region.current++; - return false; + return true; } /* @@ -373,17 +373,17 @@ static bool tcg_region_alloc__locked(TCGContext *s) */ bool tcg_region_alloc(TCGContext *s) { - bool err; + bool ok; /* read the region size now; alloc__locked will overwrite it on success */ size_t size_full = s->code_gen_buffer_size; qemu_mutex_lock(®ion.lock); - err = tcg_region_alloc__locked(s); - if (!err) { + ok = tcg_region_alloc__locked(s); + if (ok) { region.agg_size_full += size_full - TCG_HIGHWATER; } qemu_mutex_unlock(®ion.lock); - return err; + return !ok; } /* @@ -392,8 +392,8 @@ bool tcg_region_alloc(TCGContext *s) */ static void tcg_region_initial_alloc__locked(TCGContext *s) { - bool err = tcg_region_alloc__locked(s); - g_assert(!err); + bool ok = tcg_region_alloc__locked(s); + g_assert(ok); } void tcg_region_initial_alloc(TCGContext *s) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 05/38] tcg: Return success from tcg_region_alloc 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (3 preceding siblings ...) 2026-08-18 17:01 ` [PULL 04/38] tcg: Return success from tcg_region_alloc__locked Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 06/38] tcg: Defer tb_flush when initial thread region alloc fails Richard Henderson ` (33 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Invert the sense of the boolean result from 'error' to 'success'. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/region.c | 2 +- tcg/tcg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index 2161d961d9..8ee8c39c43 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -383,7 +383,7 @@ bool tcg_region_alloc(TCGContext *s) region.agg_size_full += size_full - TCG_HIGHWATER; } qemu_mutex_unlock(®ion.lock); - return !ok; + return ok; } /* diff --git a/tcg/tcg.c b/tcg/tcg.c index 1e77f2365a..af15c3d63e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1835,7 +1835,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); if (unlikely(next > s->code_gen_highwater)) { - if (tcg_region_alloc(s)) { + if (!tcg_region_alloc(s)) { return NULL; } goto retry; -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 06/38] tcg: Defer tb_flush when initial thread region alloc fails 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (4 preceding siblings ...) 2026-08-18 17:01 ` [PULL 05/38] tcg: Return success from tcg_region_alloc Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 07/38] tcg: Fix opcode dump for bswap Richard Henderson ` (32 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Anushree Mathur A vCPU hotplug may happen at any time. When the new thread is started, the region pool may be exhausted. Do not abort. Rename tcg_region_thread_initial_alloc to differentiate it from tcg_region_initial_alloc__locked. The renamed function now uses tcg_region_alloc__locked and is prepared for failure. In tcg_tb_alloc, allow code_gen_ptr to be NULL. Treat that as any other region exhaustion. Reorg with while instead of goto. Reported-by: Anushree Mathur <anushree.mathur@linux.ibm.com> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2984 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg-internal.h | 2 +- tcg/region.c | 24 ++++++++++++++++++++++-- tcg/tcg.c | 22 ++++++++++++++-------- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index c0997ab224..e35440dc8c 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -42,7 +42,7 @@ extern unsigned int tcg_max_ctxs; void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); bool tcg_region_alloc(TCGContext *s); -void tcg_region_initial_alloc(TCGContext *s); +void tcg_region_thread_initial_alloc(TCGContext *s); void tcg_region_prologue_set(TCGContext *s); static inline void *tcg_call_func(TCGOp *op) diff --git a/tcg/region.c b/tcg/region.c index 8ee8c39c43..8bd378b212 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -396,11 +396,31 @@ static void tcg_region_initial_alloc__locked(TCGContext *s) g_assert(ok); } -void tcg_region_initial_alloc(TCGContext *s) +void tcg_region_thread_initial_alloc(TCGContext *s) { + bool ok; + qemu_mutex_lock(®ion.lock); - tcg_region_initial_alloc__locked(s); + ok = tcg_region_alloc__locked(s); qemu_mutex_unlock(®ion.lock); + + /* + * A vCPU hotplug may happen at any time. When the new thread is + * started, the region pool may be exhausted. At this point in + * the new thread call stack, we are not in a position to fix this. + * Leave code_gen_ptr NULL, so that this thread's first call to + * tcg_tb_alloc() returns NULL, so that the translator performs + * a tb_flush() and retry. + * + * During the tb_flush(), tcg_region_reset_all() will assign a + * new region to all contexts, including this one. + */ + if (!ok) { + s->code_gen_buffer = NULL; + s->code_gen_ptr = NULL; + s->code_gen_buffer_size = 0; + s->code_gen_highwater = NULL; + } } /* Call from a safe-work context */ diff --git a/tcg/tcg.c b/tcg/tcg.c index af15c3d63e..db43589fa2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1279,7 +1279,7 @@ void tcg_register_thread(void) qatomic_set(&tcg_ctxs[n], s); if (n > 0) { - tcg_region_initial_alloc(s); + tcg_region_thread_initial_alloc(s); } tcg_ctx = s; @@ -1830,18 +1830,24 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) TranslationBlock *tb; void *next; - retry: - tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); - next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); + while (1) { + tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); - if (unlikely(next > s->code_gen_highwater)) { + /* + * Note that code_gen_ptr can be NULL after vCPU hotplug. + * See tcg_region_thread_initial_alloc. + */ + if (tb) { + next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); + if (next <= s->code_gen_highwater) { + qatomic_set(&s->code_gen_ptr, next); + return tb; + } + } if (!tcg_region_alloc(s)) { return NULL; } - goto retry; } - qatomic_set(&s->code_gen_ptr, next); - return tb; } void tcg_prologue_init(void) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 07/38] tcg: Fix opcode dump for bswap 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (5 preceding siblings ...) 2026-08-18 17:01 ` [PULL 06/38] tcg: Defer tb_flush when initial thread region alloc fails Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 08/38] tcg: Add tcg_gen_revbit{8,32,64} Richard Henderson ` (31 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé We use an array of char for bswap_flag_name, so some entries in the array are non-null but empty. Check that. Fixes: 587195bd590 ("tcg: Add flags argument to bswap opcodes") Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index db43589fa2..937d0c8fd7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2957,7 +2957,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) if (flags < ARRAY_SIZE(bswap_flag_name)) { name = bswap_flag_name[flags]; } - if (name) { + if (name && name[0]) { col += ne_fprintf(f, ",%s", name); } else { col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 08/38] tcg: Add tcg_gen_revbit{8,32,64} 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (6 preceding siblings ...) 2026-08-18 17:01 ` [PULL 07/38] tcg: Fix opcode dump for bswap Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap Richard Henderson ` (30 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Add generic expanders for reversing bits within a word. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-op-common.h | 5 +++ include/tcg/tcg-op.h | 7 ++++ tcg/tcg-op.c | 76 +++++++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 1fe342db0d..f7b6aadb50 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -164,6 +164,8 @@ void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); +void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); @@ -275,6 +277,9 @@ void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); +void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 96a5af1a29..568b78fe81 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -115,6 +115,10 @@ typedef TCGv_i64 TCGv; #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 #define tcg_gen_hswap_tl tcg_gen_hswap_i64 #define tcg_gen_wswap_tl tcg_gen_wswap_i64 +#define tcg_gen_revbit8_tl tcg_gen_revbit8_i64 +#define tcg_gen_revbit32_tl tcg_gen_revbit32_i64 +#define tcg_gen_revbit64_tl tcg_gen_revbit64_i64 +#define tcg_gen_revbit_tl tcg_gen_revbit64_i64 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 #define tcg_gen_andc_tl tcg_gen_andc_i64 @@ -234,6 +238,9 @@ typedef TCGv_i64 TCGv; #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 #define tcg_gen_hswap_tl tcg_gen_hswap_i32 +#define tcg_gen_revbit8_tl tcg_gen_revbit8_i32 +#define tcg_gen_revbit32_tl(D, S, F) tcg_gen_revbit32_i32(D, S) +#define tcg_gen_revbit_tl tcg_gen_revbit32_i32 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 #define tcg_gen_andc_tl tcg_gen_andc_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bbcb510c76..3d28280785 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1160,6 +1160,45 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_gen_extract_i32(ret, arg, 0, 16); } +/* + * Internal helper for bit and byte reversal. + * Given a repeating matched block of 1's and 0's, swap the bits within + * those two blocks. E.g. mask=00ff00ff, shift the input bits left and + * right 8 bits. + */ +static void gen_bitswap_i32(TCGv_i32 ret, TCGv_i32 arg, uint32_t mask) +{ + TCGv_i32 t0 = tcg_temp_ebb_new_i32(); + TCGv_i32 t1 = tcg_temp_ebb_new_i32(); + int sh = cto32(mask); + + tcg_gen_andi_i32(t0, arg, mask); + tcg_gen_shri_i32(t1, arg, sh); + tcg_gen_shli_i32(t0, t0, sh); + tcg_gen_andi_i32(t1, t1, mask); + tcg_gen_or_i32(ret, t0, t1); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); +} + +/* Similarly for 64-bit operands. */ +static void gen_bitswap_i64(TCGv_i64 ret, TCGv_i64 arg, uint64_t mask) +{ + TCGv_i64 t0 = tcg_temp_ebb_new_i64(); + TCGv_i64 t1 = tcg_temp_ebb_new_i64(); + int sh = cto64(mask); + + tcg_gen_andi_i64(t0, arg, mask); + tcg_gen_shri_i64(t1, arg, sh); + tcg_gen_shli_i64(t0, t0, sh); + tcg_gen_andi_i64(t1, t1, mask); + tcg_gen_or_i64(ret, t0, t1); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + /* * bswap16_i32: 16-bit byte swap on the low bits of a 32-bit value. * @@ -1244,6 +1283,19 @@ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_gen_rotli_i32(ret, arg, 16); } +void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + gen_bitswap_i32(ret, arg, 0x55555555u); + gen_bitswap_i32(ret, ret, 0x33333333u); + gen_bitswap_i32(ret, ret, 0x0f0f0f0fu); +} + +void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + tcg_gen_revbit8_i32(ret, arg); + tcg_gen_bswap32_i32(ret, ret); +} + void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); @@ -1869,6 +1921,30 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_rotli_i64(ret, arg, 32); } +void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) +{ + /* Only one extension flag may be present. */ + tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); + + gen_bitswap_i64(ret, arg, 0x55555555ull); + gen_bitswap_i64(ret, ret, 0x33333333ull); + gen_bitswap_i64(ret, ret, 0x0f0f0f0full); + tcg_gen_bswap32_i64(ret, ret, flags | TCG_BSWAP_IZ); +} + +void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + gen_bitswap_i64(ret, arg, 0x5555555555555555ull); + gen_bitswap_i64(ret, ret, 0x3333333333333333ull); + gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full); +} + +void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + tcg_gen_revbit8_i64(ret, arg); + tcg_gen_bswap64_i64(ret, ret); +} + void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) { if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (7 preceding siblings ...) 2026-08-18 17:01 ` [PULL 08/38] tcg: Add tcg_gen_revbit{8,32,64} Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-24 9:05 ` Peter Maydell 2026-08-18 17:01 ` [PULL 10/38] target/arm: Use generic tcg_gen_revbit* Richard Henderson ` (29 subsequent siblings) 38 siblings, 1 reply; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg-op.c | 72 ++++++---------------------------------------------- 1 file changed, 8 insertions(+), 64 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3d28280785..c24a7962fc 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1252,23 +1252,8 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I32, 0)) { tcg_gen_op3i_i32(INDEX_op_bswap32, ret, arg, 0); } else { - TCGv_i32 t0 = tcg_temp_ebb_new_i32(); - TCGv_i32 t1 = tcg_temp_ebb_new_i32(); - TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff); - - /* arg = abcd */ - tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ - tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */ - tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */ - tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */ - tcg_gen_or_i32(ret, t0, t1); /* ret = badc */ - - tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */ - tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */ - tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */ - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + gen_bitswap_i32(ret, arg, 0x00ff00ff); + tcg_gen_hswap_i32(ret, ret); } } @@ -1823,14 +1808,9 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff); - /* arg = xxxxabcd */ - tcg_gen_shri_i64(t0, arg, 8); /* t0 = .xxxxabc */ - tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */ - tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */ + /* arg = xxxxabcd */ + gen_bitswap_i64(ret, arg, 0x00ff00ff); /* ret = ....badc */ tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */ tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */ @@ -1857,32 +1837,8 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) { tcg_gen_op3i_i64(INDEX_op_bswap64, ret, arg, 0); } else { - TCGv_i64 t0 = tcg_temp_ebb_new_i64(); - TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - TCGv_i64 t2 = tcg_temp_ebb_new_i64(); - - /* arg = abcdefgh */ - tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull); - tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */ - tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */ - tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */ - - tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull); - tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */ - tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */ - tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */ - tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */ - tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */ - - tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */ - tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */ - tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); + gen_bitswap_i64(ret, arg, 0x00ff00ff00ff00ffull); + tcg_gen_hswap_i64(ret, ret); } } @@ -1894,20 +1850,8 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) */ void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg) { - uint64_t m = 0x0000ffff0000ffffull; - TCGv_i64 t0 = tcg_temp_ebb_new_i64(); - TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - - /* arg = abcdefgh */ - tcg_gen_rotli_i64(t1, arg, 32); /* t1 = efghabcd */ - tcg_gen_andi_i64(t0, t1, m); /* t0 = ..gh..cd */ - tcg_gen_shli_i64(t0, t0, 16); /* t0 = gh..cd.. */ - tcg_gen_shri_i64(t1, t1, 16); /* t1 = ..efghab */ - tcg_gen_andi_i64(t1, t1, m); /* t1 = ..ef..ab */ - tcg_gen_or_i64(ret, t0, t1); /* ret = ghefcdab */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); + gen_bitswap_i64(ret, ret, 0x0000ffff0000ffffull); + tcg_gen_wswap_i64(ret, ret); } /* -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap 2026-08-18 17:01 ` [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap Richard Henderson @ 2026-08-24 9:05 ` Peter Maydell 2026-08-24 9:30 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 44+ messages in thread From: Peter Maydell @ 2026-08-24 9:05 UTC (permalink / raw) To: Richard Henderson; +Cc: qemu-devel, Philippe Mathieu-Daudé On Tue, 18 Aug 2026 at 18:07, Richard Henderson <richard.henderson@linaro.org> wrote: > > Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Hi -- this commit is reported to cause a regression where an aarch64 rev64 can now trigger a TCG assertion: https://gitlab.com/qemu-project/qemu/-/work_items/4229 Could you have a look at that, please? thanks -- PMM ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap 2026-08-24 9:05 ` Peter Maydell @ 2026-08-24 9:30 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 44+ messages in thread From: Philippe Mathieu-Daudé @ 2026-08-24 9:30 UTC (permalink / raw) To: Peter Maydell, Richard Henderson; +Cc: qemu-devel On 24/8/26 11:05, Peter Maydell wrote: > On Tue, 18 Aug 2026 at 18:07, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > Hi -- this commit is reported to cause a regression where an > aarch64 rev64 can now trigger a TCG assertion: > https://gitlab.com/qemu-project/qemu/-/work_items/4229 > > Could you have a look at that, please? If so I'd expect the culprit to be either the previous one, "tcg: Add tcg_gen_revbit{8,32,64}" or later "tcg/aarch64: Implement revbit{32,64}". Richard you'll likely beat me at finding the issue, otherwise I can have a look in 3 days. ^ permalink raw reply [flat|nested] 44+ messages in thread
* [PULL 10/38] target/arm: Use generic tcg_gen_revbit* 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (8 preceding siblings ...) 2026-08-18 17:01 ` [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 11/38] target/loongarch: " Richard Henderson ` (28 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/helper-a64-defs.h | 1 - target/arm/tcg/helper-defs.h | 1 - target/arm/tcg/helper-a64.c | 5 ----- target/arm/tcg/op_helper.c | 5 ----- target/arm/tcg/translate-a64.c | 4 ++-- target/arm/tcg/translate.c | 2 +- 6 files changed, 3 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h index 0e56e00f45..12f58c6a44 100644 --- a/target/arm/tcg/helper-a64-defs.h +++ b/target/arm/tcg/helper-a64-defs.h @@ -18,7 +18,6 @@ */ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) -DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(msr_i_spsel, void, env, i32) DEF_HELPER_2(msr_i_daifset, void, env, i32) DEF_HELPER_2(msr_i_daifclear, void, env, i32) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 0077aeb4e2..42376af2c6 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -10,7 +10,6 @@ DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) #define PAS_OP(pfx) \ DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 05ab9ab6d3..9d805231a0 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -69,11 +69,6 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den) return num / den; } -uint64_t HELPER(rbit64)(uint64_t x) -{ - return revbit64(x); -} - void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) { update_spsel(env, imm); diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c4433be2ed..857e897a48 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -172,11 +172,6 @@ uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) return num / den; } -uint32_t HELPER(rbit)(uint32_t x) -{ - return revbit32(x); -} - uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res = a + b; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1780490065..4f9a93950b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8963,7 +8963,7 @@ static void gen_wrap2_i32(TCGv_i64 d, TCGv_i64 n, NeonGenOneOpFn fn) static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn) { - gen_wrap2_i32(tcg_rd, tcg_rn, gen_helper_rbit); + tcg_gen_revbit32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ); } static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask) @@ -8998,7 +8998,7 @@ static void gen_rev32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn) tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32); } -TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? gen_helper_rbit64 : gen_rbit32) +TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_revbit64_i64 : gen_rbit32) TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32) TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32) TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 055f3c5b40..1770428d3c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4835,7 +4835,7 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) if (!ENABLE_ARCH_6T2) { return false; } - return op_rr(s, a, gen_helper_rbit); + return op_rr(s, a, tcg_gen_revbit32_i32); } /* -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 11/38] target/loongarch: Use generic tcg_gen_revbit* 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (9 preceding siblings ...) 2026-08-18 17:01 ` [PULL 10/38] target/arm: Use generic tcg_gen_revbit* Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 12/38] target/mips: Expand octeon reflections inline Richard Henderson ` (27 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Song Gao, Philippe Mathieu-Daudé Reviewed-by: Song Gao <17746591750@163.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/loongarch/tcg/helper.h | 4 ---- target/loongarch/tcg/op_helper.c | 21 ------------------- .../loongarch/tcg/insn_trans/trans_bit.c.inc | 13 ++++++++---- 3 files changed, 9 insertions(+), 29 deletions(-) diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index 8a6c62f116..e76c73c775 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -5,10 +5,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) -DEF_HELPER_FLAGS_1(bitrev_w, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(bitrev_d, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) - DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c index e63ac66daa..f41f0cb1e6 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -22,27 +22,6 @@ void helper_raise_exception(CPULoongArchState *env, uint32_t exception) do_raise_exception(env, exception, GETPC()); } -target_ulong helper_bitrev_w(target_ulong rj) -{ - return (int32_t)revbit32(rj); -} - -target_ulong helper_bitrev_d(target_ulong rj) -{ - return revbit64(rj); -} - -target_ulong helper_bitswap(target_ulong v) -{ - v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) | - ((v & (target_ulong)0x5555555555555555ULL) << 1); - v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) | - ((v & (target_ulong)0x3333333333333333ULL) << 2); - v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) | - ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4); - return v; -} - /* loongarch assert op */ void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) { diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc index ee5fa003ce..b91bb7eaa6 100644 --- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc @@ -178,6 +178,11 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2) tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1); } +static void gen_bitrev_w(TCGv dest, TCGv src) +{ + tcg_gen_revbit32_tl(dest, src, TCG_BSWAP_OS); +} + TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl) TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl) TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w) @@ -194,10 +199,10 @@ TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w) TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64) TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w) TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d) -TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap) -TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap) -TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w) -TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d) +TRANS(bitrev_4b, ALL, gen_rr, EXT_NONE, EXT_SIGN, tcg_gen_revbit8_i64) +TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit8_i64) +TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_w) +TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit64_i64) TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz) TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez) TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 12/38] target/mips: Expand octeon reflections inline 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (10 preceding siblings ...) 2026-08-18 17:01 ` [PULL 11/38] target/loongarch: " Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 13/38] target/riscv: Use generic tcg_gen_revbit8 Richard Henderson ` (26 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Anton Johansson Use tcg_gen_revbit64_i64 instead of out-of-line helpers. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/mips/helper.h | 7 ----- target/mips/tcg/octeon_crypto.c | 35 --------------------- target/mips/tcg/octeon_translate.c | 49 ++++++++++++++++++++++++++---- 3 files changed, 43 insertions(+), 48 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 786117813a..779b87101d 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -27,10 +27,6 @@ DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) /* Octeon COP2 selector operation helpers. */ DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env) -DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env) -DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env) -DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env) -DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env) DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_polynomial_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64) @@ -43,9 +39,6 @@ DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64) -DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect0, void, env, i64) -DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect1, void, env, i64) -DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64) DEF_HELPER_1(octeon_cp2_mt_sha3_startop, void, env) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c index fbf80be2a5..118397e632 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -2127,41 +2127,6 @@ uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); } -uint64_t helper_octeon_cp2_mf_gfm_mul_reflect0(CPUMIPSState *env) -{ - return revbit64(env->octeon_crypto.gfm_mul[0]); -} - -uint64_t helper_octeon_cp2_mf_gfm_mul_reflect1(CPUMIPSState *env) -{ - return revbit64(env->octeon_crypto.gfm_mul[1]); -} - -uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect0(CPUMIPSState *env) -{ - return revbit64(env->octeon_crypto.gfm_resinp[0]); -} - -uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect1(CPUMIPSState *env) -{ - return revbit64(env->octeon_crypto.gfm_resinp[1]); -} - -void helper_octeon_cp2_mt_gfm_mul_reflect0(CPUMIPSState *env, uint64_t value) -{ - env->octeon_crypto.gfm_mul[0] = revbit64(value); -} - -void helper_octeon_cp2_mt_gfm_mul_reflect1(CPUMIPSState *env, uint64_t value) -{ - env->octeon_crypto.gfm_mul[1] = revbit64(value); -} - -void helper_octeon_cp2_mt_gfm_xor0_reflect(CPUMIPSState *env, uint64_t value) -{ - env->octeon_crypto.gfm_resinp[0] ^= revbit64(value); -} - static void octeon_gfm_xormul1_common(MIPSOcteonCryptoState *crypto, uint64_t value) { diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index a0db6630c7..b689adb46b 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -28,6 +28,8 @@ TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) +#define CP2_MF_REFLECT(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mf_reflect, OCTEON_CRYPTO_OFFSET(FIELD)) #define CP2_MF_HELPER(NAME, SUFFIX) \ TRANS(NAME, trans_octeon_cp2_mf_helper, \ gen_helper_octeon_cp2_mf_ ## SUFFIX) @@ -44,6 +46,8 @@ TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) +#define CP2_MT_REFLECT(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mt_reflect, OCTEON_CRYPTO_OFFSET(FIELD)) #define CP2_MT_HELPER(NAME, SUFFIX) \ TRANS(NAME, trans_octeon_cp2_mt_helper, \ gen_helper_octeon_cp2_mt_ ## SUFFIX) @@ -110,6 +114,17 @@ static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *ctx, arg_cp2 *a, return true; } +static bool trans_octeon_cp2_mf_reflect(DisasContext *ctx, arg_cp2 *a, + int offset) +{ + TCGv_i64 value = tcg_temp_new_i64(); + + tcg_gen_ld_i64(value, tcg_env, offset); + tcg_gen_revbit64_i64(value, value); + gen_store_gpr(value, a->rt); + return true; +} + static bool trans_octeon_cp2_mf_helper(DisasContext *ctx, arg_cp2 *a, void (*gen_helper)(TCGv_i64, TCGv_env)) { @@ -183,6 +198,17 @@ static bool trans_octeon_cp2_mt_xor_i64(DisasContext *ctx, arg_cp2 *a, return true; } +static bool trans_octeon_cp2_mt_reflect(DisasContext *ctx, arg_cp2 *a, + int offset) +{ + TCGv_i64 value = tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_revbit64_i64(value, value); + tcg_gen_st_i64(value, tcg_env, offset); + return true; +} + static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a, void (*gen_helper)(TCGv_env, TCGv_i64)) { @@ -200,6 +226,17 @@ static bool trans_octeon_cp2_mt_helper_env(DisasContext *ctx, arg_cp2 *a, return true; } +static void gen_helper_octeon_cp2_mt_gfm_xor0_reflect(TCGv_env t_env, + TCGv_i64 value) +{ + TCGv_i64 resinp = tcg_temp_new_i64(); + + tcg_gen_revbit64_i64(value, value); + tcg_gen_ld_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0])); + tcg_gen_xor_i64(resinp, resinp, value); + tcg_gen_st_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0])); +} + CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0); CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1); CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2); @@ -241,10 +278,10 @@ CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]); CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24); -CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0); -CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1); -CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0); -CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1); +CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT0, gfm_mul[0]) +CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT1, gfm_mul[1]) +CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp[0]) +CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp[1]) CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]); CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]); CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]); @@ -281,8 +318,8 @@ CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3); -CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT0, gfm_mul_reflect0); -CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT1, gfm_mul_reflect1); +CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT0, gfm_mul[0]); +CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT1, gfm_mul[1]); CP2_MT_HELPER(CVM_MT_GFM_XOR0_REFLECT, gfm_xor0_reflect); CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]); CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]); -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 13/38] target/riscv: Use generic tcg_gen_revbit8 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (11 preceding siblings ...) 2026-08-18 17:01 ` [PULL 12/38] target/mips: Expand octeon reflections inline Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 14/38] tcg: Add revbit{8,32,64} opcodes Richard Henderson ` (25 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/helper.h | 1 - target/riscv/tcg/bitmanip_helper.c | 15 --------------- target/riscv/tcg/insn_trans/trans_rvb.c.inc | 2 +- 3 files changed, 1 insertion(+), 17 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 542b7c264f..4fc2d3a155 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -79,7 +79,6 @@ DEF_HELPER_FLAGS_2(froundnx_d, TCG_CALL_NO_RWG_SE, i64, env, i64) /* Bitmanip */ DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) diff --git a/target/riscv/tcg/bitmanip_helper.c b/target/riscv/tcg/bitmanip_helper.c index 1156a87dd3..d8d94bca7b 100644 --- a/target/riscv/tcg/bitmanip_helper.c +++ b/target/riscv/tcg/bitmanip_helper.c @@ -52,21 +52,6 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) return result; } -static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift) -{ - return ((x & mask) << shift) | ((x & ~mask) >> shift); -} - -target_ulong HELPER(brev8)(target_ulong rs1) -{ - target_ulong x = rs1; - - x = do_swap(x, 0x5555555555555555ull, 1); - x = do_swap(x, 0x3333333333333333ull, 2); - x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4); - return x; -} - static const uint64_t shuf_masks[] = { dup_const(MO_8, 0x44), dup_const(MO_8, 0x30), diff --git a/target/riscv/tcg/insn_trans/trans_rvb.c.inc b/target/riscv/tcg/insn_trans/trans_rvb.c.inc index e4dcc7c991..3e74be223b 100644 --- a/target/riscv/tcg/insn_trans/trans_rvb.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvb.c.inc @@ -522,7 +522,7 @@ static void gen_packw(TCGv ret, TCGv src1, TCGv src2) static bool trans_brev8(DisasContext *ctx, arg_brev8 *a) { REQUIRE_ZBKB(ctx); - return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_revbit8_tl); } static bool trans_pack(DisasContext *ctx, arg_pack *a) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 14/38] tcg: Add revbit{8,32,64} opcodes 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (12 preceding siblings ...) 2026-08-18 17:01 ` [PULL 13/38] target/riscv: Use generic tcg_gen_revbit8 Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 15/38] tcg/optimize: Handle revbit{8,32,64} Richard Henderson ` (24 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Add the plumbing, but not yet implemented for any host. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-opc.h | 3 ++ tcg/tcg-op.c | 66 +++++++++++++++++++++++++------- tcg/tcg.c | 7 ++++ docs/devel/tcg-ops.rst | 16 ++++++++ tcg/aarch64/tcg-target.c.inc | 12 ++++++ tcg/loongarch64/tcg-target.c.inc | 12 ++++++ tcg/ppc64/tcg-target.c.inc | 12 ++++++ tcg/riscv64/tcg-target.c.inc | 12 ++++++ tcg/s390x/tcg-target.c.inc | 12 ++++++ tcg/sparc64/tcg-target.c.inc | 12 ++++++ tcg/tci/tcg-target.c.inc | 12 ++++++ tcg/x86_64/tcg-target.c.inc | 12 ++++++ 12 files changed, 174 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 61f1c28858..13c7f17f76 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -79,6 +79,9 @@ DEF(or, 1, 2, 0, TCG_OPF_INT) DEF(orc, 1, 2, 0, TCG_OPF_INT) DEF(rems, 1, 2, 0, TCG_OPF_INT) DEF(remu, 1, 2, 0, TCG_OPF_INT) +DEF(revbit8, 1, 1, 0, TCG_OPF_INT) +DEF(revbit32, 1, 1, 1, TCG_OPF_INT) +DEF(revbit64, 1, 1, 0, TCG_OPF_INT) DEF(rotl, 1, 2, 0, TCG_OPF_INT) DEF(rotr, 1, 2, 0, TCG_OPF_INT) DEF(sar, 1, 2, 0, TCG_OPF_INT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c24a7962fc..c302a484cd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1270,15 +1270,26 @@ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg) { - gen_bitswap_i32(ret, arg, 0x55555555u); - gen_bitswap_i32(ret, ret, 0x33333333u); - gen_bitswap_i32(ret, ret, 0x0f0f0f0fu); + if (tcg_op_supported(INDEX_op_revbit8, TCG_TYPE_I32, 0)) { + tcg_gen_op2_i32(INDEX_op_revbit8, ret, arg); + } else if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I32, 0)) { + tcg_gen_op2_i32(INDEX_op_revbit32, ret, arg); + tcg_gen_bswap32_i32(ret, ret); + } else { + gen_bitswap_i32(ret, arg, 0x55555555u); + gen_bitswap_i32(ret, ret, 0x33333333u); + gen_bitswap_i32(ret, ret, 0x0f0f0f0fu); + } } void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) { - tcg_gen_revbit8_i32(ret, arg); - tcg_gen_bswap32_i32(ret, ret); + if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I32, 0)) { + tcg_gen_op3i_i32(INDEX_op_revbit32, ret, arg, 0); + } else { + tcg_gen_revbit8_i32(ret, arg); + tcg_gen_bswap32_i32(ret, ret); + } } void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) @@ -1870,23 +1881,50 @@ void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); - gen_bitswap_i64(ret, arg, 0x55555555ull); - gen_bitswap_i64(ret, ret, 0x33333333ull); - gen_bitswap_i64(ret, ret, 0x0f0f0f0full); - tcg_gen_bswap32_i64(ret, ret, flags | TCG_BSWAP_IZ); + if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I64, 0)) { + tcg_gen_op3i_i64(INDEX_op_revbit32, ret, arg, flags); + } else if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_revbit64, ret, arg); + if (flags & TCG_BSWAP_OS) { + tcg_gen_sari_i64(ret, ret, 32); + } else { + tcg_gen_shri_i64(ret, ret, 32); + } + } else { + if (tcg_op_supported(INDEX_op_revbit8, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_revbit8, ret, arg); + } else { + gen_bitswap_i64(ret, arg, 0x55555555ull); + gen_bitswap_i64(ret, ret, 0x33333333ull); + gen_bitswap_i64(ret, ret, 0x0f0f0f0full); + flags |= TCG_BSWAP_IZ; + } + tcg_gen_bswap32_i64(ret, ret, flags); + } } void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg) { - gen_bitswap_i64(ret, arg, 0x5555555555555555ull); - gen_bitswap_i64(ret, ret, 0x3333333333333333ull); - gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full); + if (tcg_op_supported(INDEX_op_revbit8, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_revbit8, ret, arg); + } else if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_revbit64, ret, arg); + tcg_gen_bswap64_i64(ret, ret); + } else { + gen_bitswap_i64(ret, arg, 0x5555555555555555ull); + gen_bitswap_i64(ret, ret, 0x3333333333333333ull); + gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full); + } } void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) { - tcg_gen_revbit8_i64(ret, arg); - tcg_gen_bswap64_i64(ret, ret); + if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_revbit64, ret, arg); + } else { + tcg_gen_revbit8_i64(ret, arg); + tcg_gen_bswap64_i64(ret, ret); + } } void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 937d0c8fd7..8a324ce885 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1203,6 +1203,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2), OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), + OUTOP(INDEX_op_revbit32, TCGOutOpBswap, outop_revbit32), OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl), OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr), OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar), @@ -1230,6 +1231,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), + OUTOP(INDEX_op_revbit8, TCGOutOpUnary, outop_revbit8), + OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64), OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), }; @@ -2950,6 +2953,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) case INDEX_op_bswap16: case INDEX_op_bswap32: case INDEX_op_bswap64: + case INDEX_op_revbit32: { TCGArg flags = op->args[k]; const char *name = NULL; @@ -5581,6 +5585,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_ctpop: case INDEX_op_neg: case INDEX_op_not: + case INDEX_op_revbit8: + case INDEX_op_revbit64: { const TCGOutOpUnary *out = container_of(all_outop[op->opc], TCGOutOpUnary, base); @@ -5593,6 +5599,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_bswap16: case INDEX_op_bswap32: + case INDEX_op_revbit32: { const TCGOutOpBswap *out = container_of(all_outop[op->opc], TCGOutOpBswap, base); diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 92ef127c80..f2e9255dd9 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -495,6 +495,22 @@ Misc into 32-bit output *t0*. Depending on the host, this may be a simple shift, or may require additional canonicalization. + * - revbit8 *dest*, *t1* + + - | Reverse the 8 bits within each byte of input *t1* with + | output in *dest*; the byte order is unchanged. + + * - revbit32 *dest*, *t1*, *flags* + + - | Reverse the 32 bits of the lower 32 bits of input *t1* + | with output in *dest*. On TCG_TYPE_I64, *flags* control + | any required sign or zero extension of the result in + | the same way as for bswap32. + | On TCG_TYPE_I32, *flags* should be zero. + + * - revbit64 *dest*, *t1* + + - | Reverse the 64 bits of input *t1* with output in *dest*. Conditional moves ----------------- diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index cc9c2a5158..0afa988087 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2652,6 +2652,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tgen_sub(s, type, a0, TCG_REG_XZR, a1); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 182dcfd5eb..97ed51d99c 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1866,6 +1866,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tgen_sub(s, type, a0, TCG_REG_ZERO, a1); diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index b54afa0b6d..07dff67e84 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -3421,6 +3421,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tcg_out32(s, NEG | RT(a0) | RA(a1)); diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 76dd4fca97..687146e0b0 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2469,6 +2469,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tgen_sub(s, type, a0, TCG_REG_ZERO, a1); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 84a9e73a46..c481745c3f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3020,6 +3020,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { if (type == TCG_TYPE_I32) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 5e5c3f1cda..d6ed9d3362 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1947,6 +1947,18 @@ static const TCGOutOpUnary outop_bswap64 = { .base.static_constraint = C_NotImplemented, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tgen_sub(s, type, a0, TCG_REG_G0, a1); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1b22c70616..1b61668517 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -959,6 +959,18 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tcg_out_op_rr(s, INDEX_op_neg, a0, a1); diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 1fc45e4ec6..37acba9045 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -1290,6 +1290,18 @@ static inline void tcg_out_bswap64(TCGContext *s, int reg) tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); } +static const TCGOutOpUnary outop_revbit8 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBswap outop_revbit32 = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpUnary outop_revbit64 = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_arithi(TCGContext *s, int c, int r0, tcg_target_long val, int cf) { -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 15/38] tcg/optimize: Handle revbit{8,32,64} 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (13 preceding siblings ...) 2026-08-18 17:01 ` [PULL 14/38] tcg: Add revbit{8,32,64} opcodes Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 16/38] tcg/aarch64: Implement revbit{32,64} Richard Henderson ` (23 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé These are nearly identical to bswap, so reuse fold_bswap. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/optimize.c | 77 +++++++++++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 32 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d12babad88..facf4c1e0f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -534,6 +534,20 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type, case INDEX_op_bswap64: return bswap64(x); + case INDEX_op_revbit8: + /* Note the host-utils.h revbit8 operates on uint8_t. */ + if (type == TCG_TYPE_I32) { + return bswap32(revbit32(x)); + } + return bswap64(revbit64(x)); + + case INDEX_op_revbit32: + x = revbit32(x); + return y & TCG_BSWAP_OS ? (int32_t)x : x; + + case INDEX_op_revbit64: + return revbit64(x); + case INDEX_op_ext_i32_i64: return (int32_t)x; @@ -1483,7 +1497,26 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask; TempOptInfo *t1 = arg_info(op->args[1]); - int flags = op->args[2]; + int flags = 0; + + switch (op->opc) { + case INDEX_op_bswap16: + flags = op->args[2]; + s_mask = INT16_MIN; + break; + case INDEX_op_bswap32: + case INDEX_op_revbit32: + flags = op->args[2]; + s_mask = INT32_MIN; + break; + case INDEX_op_bswap64: + case INDEX_op_revbit8: + case INDEX_op_revbit64: + s_mask = 0; + break; + default: + g_assert_not_reached(); + } if (ti_is_const(t1)) { return tcg_opt_gen_movi(ctx, op, op->args[0], @@ -1491,39 +1524,16 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) ti_const_val(t1), flags)); } - z_mask = t1->z_mask; - o_mask = t1->o_mask; - s_mask = 0; + z_mask = do_constant_folding(op->opc, ctx->type, t1->z_mask, flags); + o_mask = do_constant_folding(op->opc, ctx->type, t1->o_mask, flags); - switch (op->opc) { - case INDEX_op_bswap16: - z_mask = bswap16(z_mask); - o_mask = bswap16(o_mask); - if (flags & TCG_BSWAP_OS) { - z_mask = (int16_t)z_mask; - o_mask = (int16_t)o_mask; - s_mask = INT16_MIN; - } else if (!(flags & TCG_BSWAP_OZ)) { - z_mask |= MAKE_64BIT_MASK(16, 48); + if (flags & TCG_BSWAP_OS) { + /* s_mask set */ + } else { + if (!(flags & TCG_BSWAP_OZ)) { + z_mask |= s_mask << 1; } - break; - case INDEX_op_bswap32: - z_mask = bswap32(z_mask); - o_mask = bswap32(o_mask); - if (flags & TCG_BSWAP_OS) { - z_mask = (int32_t)z_mask; - o_mask = (int32_t)o_mask; - s_mask = INT32_MIN; - } else if (!(flags & TCG_BSWAP_OZ)) { - z_mask |= MAKE_64BIT_MASK(32, 32); - } - break; - case INDEX_op_bswap64: - z_mask = bswap64(z_mask); - o_mask = bswap64(o_mask); - break; - default: - g_assert_not_reached(); + s_mask = 0; } return fold_masks_zos(ctx, op, z_mask, o_mask, s_mask); @@ -3104,6 +3114,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_bswap16: case INDEX_op_bswap32: case INDEX_op_bswap64: + case INDEX_op_revbit8: + case INDEX_op_revbit32: + case INDEX_op_revbit64: done = fold_bswap(&ctx, op); break; case INDEX_op_clz: -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 16/38] tcg/aarch64: Implement revbit{32,64} 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (14 preceding siblings ...) 2026-08-18 17:01 ` [PULL 15/38] tcg/optimize: Handle revbit{8,32,64} Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 17/38] tcg/loongarch64: Import REVBIT insns Richard Henderson ` (22 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 0afa988087..80995403e4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2656,12 +2656,28 @@ static const TCGOutOpUnary outop_revbit8 = { .base.static_constraint = C_NotImplemented, }; +static void tgen_revbit32(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, unsigned flags) +{ + tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I32, a0, a1); + if (flags & TCG_BSWAP_OS) { + tcg_out_ext32s(s, a0, a0); + } +} + static const TCGOutOpBswap outop_revbit32 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit32, }; +static void tgen_revbit64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I64, a0, a1); +} + static const TCGOutOpUnary outop_revbit64 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit64, }; static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 17/38] tcg/loongarch64: Import REVBIT insns 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (15 preceding siblings ...) 2026-08-18 17:01 ` [PULL 16/38] tcg/aarch64: Implement revbit{32,64} Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 18/38] tcg/loongarch64: Implement revbit{8,32,64} Richard Henderson ` (21 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/loongarch64/tcg-insn-defs.c.inc | 960 +++++++++++++++------------- 1 file changed, 503 insertions(+), 457 deletions(-) diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc index 6bb8656fd8..e907fc755f 100644 --- a/tcg/loongarch64/tcg-insn-defs.c.inc +++ b/tcg/loongarch64/tcg-insn-defs.c.inc @@ -4,7 +4,7 @@ * * This file is auto-generated by genqemutcgdefs from * https://github.com/loongson-community/loongarch-opcodes, - * from commit 7f353fb69bd99ce6edfad7ad63948c4bb526f0bf. + * from commit 1b95bb8c443ad71e266120fd97bd227df2d8ecfc. * DO NOT EDIT. */ @@ -18,6 +18,10 @@ typedef enum { OPC_REVB_2H = 0x00003000, OPC_REVB_2W = 0x00003800, OPC_REVB_D = 0x00003c00, + OPC_REVBIT_4B = 0x00004800, + OPC_REVBIT_8B = 0x00004c00, + OPC_REVBIT_W = 0x00005000, + OPC_REVBIT_D = 0x00005400, OPC_SEXT_H = 0x00005800, OPC_SEXT_B = 0x00005c00, OPC_ADD_W = 0x00100000, @@ -545,14 +549,14 @@ typedef enum { OPC_XVLDI = 0x77e00000, } LoongArchInsn; -static int32_t __attribute__((unused)) -encode_d_slot(LoongArchInsn opc, uint32_t d) +static int32_t __attribute__((unused)) encode_d_slot(LoongArchInsn opc, + uint32_t d) { return opc | d; } -static int32_t __attribute__((unused)) -encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j) +static int32_t __attribute__((unused)) encode_dj_slots(LoongArchInsn opc, + uint32_t d, uint32_t j) { return opc | d | j << 5; } @@ -563,43 +567,43 @@ encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k) return opc | d | j << 5 | k << 10; } -static int32_t __attribute__((unused)) -encode_djka_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k, - uint32_t a) +static int32_t __attribute__((unused)) encode_djka_slots(LoongArchInsn opc, + uint32_t d, uint32_t j, + uint32_t k, uint32_t a) { return opc | d | j << 5 | k << 10 | a << 15; } -static int32_t __attribute__((unused)) -encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k, - uint32_t m) +static int32_t __attribute__((unused)) encode_djkm_slots(LoongArchInsn opc, + uint32_t d, uint32_t j, + uint32_t k, uint32_t m) { return opc | d | j << 5 | k << 10 | m << 16; } -static int32_t __attribute__((unused)) -encode_djkn_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k, - uint32_t n) +static int32_t __attribute__((unused)) encode_djkn_slots(LoongArchInsn opc, + uint32_t d, uint32_t j, + uint32_t k, uint32_t n) { return opc | d | j << 5 | k << 10 | n << 18; } -static int32_t __attribute__((unused)) -encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k) +static int32_t __attribute__((unused)) encode_dk_slots(LoongArchInsn opc, + uint32_t d, uint32_t k) { return opc | d | k << 10; } -static int32_t __attribute__((unused)) -encode_dfj_insn(LoongArchInsn opc, TCGReg d, TCGReg fj) +static int32_t __attribute__((unused)) encode_dfj_insn(LoongArchInsn opc, + TCGReg d, TCGReg fj) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(fj >= 0x20 && fj <= 0x3f); return encode_dj_slots(opc, d, fj & 0x1f); } -static int32_t __attribute__((unused)) -encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j) +static int32_t __attribute__((unused)) encode_dj_insn(LoongArchInsn opc, + TCGReg d, TCGReg j) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -669,9 +673,10 @@ encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5) return encode_djk_slots(opc, d, j, uk5); } -static int32_t __attribute__((unused)) -encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5, - uint32_t um5) +static int32_t __attribute__((unused)) encode_djuk5um5_insn(LoongArchInsn opc, + TCGReg d, TCGReg j, + uint32_t uk5, + uint32_t um5) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -689,9 +694,10 @@ encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6) return encode_djk_slots(opc, d, j, uk6); } -static int32_t __attribute__((unused)) -encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6, - uint32_t um6) +static int32_t __attribute__((unused)) encode_djuk6um6_insn(LoongArchInsn opc, + TCGReg d, TCGReg j, + uint32_t uk6, + uint32_t um6) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -700,16 +706,16 @@ encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6, return encode_djkm_slots(opc, d, j, uk6, um6); } -static int32_t __attribute__((unused)) -encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20) +static int32_t __attribute__((unused)) encode_dsj20_insn(LoongArchInsn opc, + TCGReg d, int32_t sj20) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(sj20 >= -0x80000 && sj20 <= 0x7ffff); return encode_dj_slots(opc, d, sj20 & 0xfffff); } -static int32_t __attribute__((unused)) -encode_dtj_insn(LoongArchInsn opc, TCGReg d, TCGReg tj) +static int32_t __attribute__((unused)) encode_dtj_insn(LoongArchInsn opc, + TCGReg d, TCGReg tj) { tcg_debug_assert(d >= 0 && d <= 0x1f); tcg_debug_assert(tj >= 0 && tj <= 0x3); @@ -770,16 +776,16 @@ encode_dxjuk3_insn(LoongArchInsn opc, TCGReg d, TCGReg xj, uint32_t uk3) return encode_djk_slots(opc, d, xj & 0x1f, uk3); } -static int32_t __attribute__((unused)) -encode_fdfj_insn(LoongArchInsn opc, TCGReg fd, TCGReg fj) +static int32_t __attribute__((unused)) encode_fdfj_insn(LoongArchInsn opc, + TCGReg fd, TCGReg fj) { tcg_debug_assert(fd >= 0x20 && fd <= 0x3f); tcg_debug_assert(fj >= 0x20 && fj <= 0x3f); return encode_dj_slots(opc, fd & 0x1f, fj & 0x1f); } -static int32_t __attribute__((unused)) -encode_fdj_insn(LoongArchInsn opc, TCGReg fd, TCGReg j) +static int32_t __attribute__((unused)) encode_fdj_insn(LoongArchInsn opc, + TCGReg fd, TCGReg j) { tcg_debug_assert(fd >= 0x20 && fd <= 0x3f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -804,37 +810,37 @@ encode_fdjsk12_insn(LoongArchInsn opc, TCGReg fd, TCGReg j, int32_t sk12) return encode_djk_slots(opc, fd & 0x1f, j, sk12 & 0xfff); } -static int32_t __attribute__((unused)) -encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16) +static int32_t __attribute__((unused)) encode_sd10k16_insn(LoongArchInsn opc, + int32_t sd10k16) { tcg_debug_assert(sd10k16 >= -0x2000000 && sd10k16 <= 0x1ffffff); return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff); } -static int32_t __attribute__((unused)) -encode_sd5k16_insn(LoongArchInsn opc, int32_t sd5k16) +static int32_t __attribute__((unused)) encode_sd5k16_insn(LoongArchInsn opc, + int32_t sd5k16) { tcg_debug_assert(sd5k16 >= -0x100000 && sd5k16 <= 0xfffff); return encode_dk_slots(opc, (sd5k16 >> 16) & 0x1f, sd5k16 & 0xffff); } -static int32_t __attribute__((unused)) -encode_tdj_insn(LoongArchInsn opc, TCGReg td, TCGReg j) +static int32_t __attribute__((unused)) encode_tdj_insn(LoongArchInsn opc, + TCGReg td, TCGReg j) { tcg_debug_assert(td >= 0 && td <= 0x3); tcg_debug_assert(j >= 0 && j <= 0x1f); return encode_dj_slots(opc, td, j); } -static int32_t __attribute__((unused)) -encode_ud15_insn(LoongArchInsn opc, uint32_t ud15) +static int32_t __attribute__((unused)) encode_ud15_insn(LoongArchInsn opc, + uint32_t ud15) { tcg_debug_assert(ud15 <= 0x7fff); return encode_d_slot(opc, ud15); } -static int32_t __attribute__((unused)) -encode_vdj_insn(LoongArchInsn opc, TCGReg vd, TCGReg j) +static int32_t __attribute__((unused)) encode_vdj_insn(LoongArchInsn opc, + TCGReg vd, TCGReg j) { tcg_debug_assert(vd >= 0x20 && vd <= 0x3f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -974,8 +980,8 @@ encode_vdsj13_insn(LoongArchInsn opc, TCGReg vd, int32_t sj13) return encode_dj_slots(opc, vd & 0x1f, sj13 & 0x1fff); } -static int32_t __attribute__((unused)) -encode_vdvj_insn(LoongArchInsn opc, TCGReg vd, TCGReg vj) +static int32_t __attribute__((unused)) encode_vdvj_insn(LoongArchInsn opc, + TCGReg vd, TCGReg vj) { tcg_debug_assert(vd >= 0x20 && vd <= 0x3f); tcg_debug_assert(vj >= 0x20 && vj <= 0x3f); @@ -1083,8 +1089,8 @@ encode_vdvjvkva_insn(LoongArchInsn opc, TCGReg vd, TCGReg vj, TCGReg vk, return encode_djka_slots(opc, vd & 0x1f, vj & 0x1f, vk & 0x1f, va & 0x1f); } -static int32_t __attribute__((unused)) -encode_xdj_insn(LoongArchInsn opc, TCGReg xd, TCGReg j) +static int32_t __attribute__((unused)) encode_xdj_insn(LoongArchInsn opc, + TCGReg xd, TCGReg j) { tcg_debug_assert(xd >= 0x20 && xd <= 0x3f); tcg_debug_assert(j >= 0 && j <= 0x1f); @@ -1206,8 +1212,8 @@ encode_xdsj13_insn(LoongArchInsn opc, TCGReg xd, int32_t sj13) return encode_dj_slots(opc, xd & 0x1f, sj13 & 0x1fff); } -static int32_t __attribute__((unused)) -encode_xdxj_insn(LoongArchInsn opc, TCGReg xd, TCGReg xj) +static int32_t __attribute__((unused)) encode_xdxj_insn(LoongArchInsn opc, + TCGReg xd, TCGReg xj) { tcg_debug_assert(xd >= 0x20 && xd <= 0x3f); tcg_debug_assert(xj >= 0x20 && xj <= 0x3f); @@ -1316,523 +1322,555 @@ encode_xdxjxkxa_insn(LoongArchInsn opc, TCGReg xd, TCGReg xj, TCGReg xk, } /* Emits the `movgr2scr td, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_movgr2scr(TCGContext *s, TCGReg td, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_movgr2scr(TCGContext *s, + TCGReg td, TCGReg j) { tcg_out32(s, encode_tdj_insn(OPC_MOVGR2SCR, td, j)); } /* Emits the `movscr2gr d, tj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_movscr2gr(TCGContext *s, TCGReg d, TCGReg tj) +static void __attribute__((unused)) tcg_out_opc_movscr2gr(TCGContext *s, + TCGReg d, TCGReg tj) { tcg_out32(s, encode_dtj_insn(OPC_MOVSCR2GR, d, tj)); } /* Emits the `clz.w d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_clz_w(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_CLZ_W, d, j)); } /* Emits the `ctz.w d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_CTZ_W, d, j)); } /* Emits the `clz.d d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_clz_d(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_CLZ_D, d, j)); } /* Emits the `ctz.d d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_CTZ_D, d, j)); } /* Emits the `revb.2h d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_REVB_2H, d, j)); } /* Emits the `revb.2w d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_revb_2w(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_revb_2w(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_REVB_2W, d, j)); } /* Emits the `revb.d d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_revb_d(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_REVB_D, d, j)); } +/* Emits the `revbit.4b d, j` instruction. */ +static void __attribute__((unused)) tcg_out_opc_revbit_4b(TCGContext *s, + TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVBIT_4B, d, j)); +} + +/* Emits the `revbit.8b d, j` instruction. */ +static void __attribute__((unused)) tcg_out_opc_revbit_8b(TCGContext *s, + TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVBIT_8B, d, j)); +} + +/* Emits the `revbit.w d, j` instruction. */ +static void __attribute__((unused)) tcg_out_opc_revbit_w(TCGContext *s, + TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVBIT_W, d, j)); +} + +/* Emits the `revbit.d d, j` instruction. */ +static void __attribute__((unused)) tcg_out_opc_revbit_d(TCGContext *s, + TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVBIT_D, d, j)); +} + /* Emits the `sext.h d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_sext_h(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_SEXT_H, d, j)); } /* Emits the `sext.b d, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_sext_b(TCGContext *s, TCGReg d, + TCGReg j) { tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j)); } /* Emits the `add.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_add_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ADD_W, d, j, k)); } /* Emits the `add.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_add_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ADD_D, d, j, k)); } /* Emits the `sub.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sub_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SUB_W, d, j, k)); } /* Emits the `sub.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sub_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SUB_D, d, j, k)); } /* Emits the `slt d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_slt(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SLT, d, j, k)); } /* Emits the `sltu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sltu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SLTU, d, j, k)); } /* Emits the `maskeqz d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MASKEQZ, d, j, k)); } /* Emits the `masknez d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_masknez(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MASKNEZ, d, j, k)); } /* Emits the `nor d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_nor(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_NOR, d, j, k)); } /* Emits the `and d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_and(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_AND, d, j, k)); } /* Emits the `or d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_or(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_OR, d, j, k)); } /* Emits the `xor d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_xor(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_XOR, d, j, k)); } /* Emits the `orn d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_orn(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ORN, d, j, k)); } /* Emits the `andn d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_andn(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ANDN, d, j, k)); } /* Emits the `sll.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sll_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SLL_W, d, j, k)); } /* Emits the `srl.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_srl_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SRL_W, d, j, k)); } /* Emits the `sra.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sra_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SRA_W, d, j, k)); } /* Emits the `sll.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sll_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SLL_D, d, j, k)); } /* Emits the `srl.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_srl_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SRL_D, d, j, k)); } /* Emits the `sra.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_sra_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_SRA_D, d, j, k)); } /* Emits the `rotr.b d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotr_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_rotr_b(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ROTR_B, d, j, k)); } /* Emits the `rotr.h d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotr_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_rotr_h(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ROTR_H, d, j, k)); } /* Emits the `rotr.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ROTR_W, d, j, k)); } /* Emits the `rotr.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_ROTR_D, d, j, k)); } /* Emits the `mul.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mul_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MUL_W, d, j, k)); } /* Emits the `mulh.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MULH_W, d, j, k)); } /* Emits the `mulh.wu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MULH_WU, d, j, k)); } /* Emits the `mul.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mul_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MUL_D, d, j, k)); } /* Emits the `mulh.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MULH_D, d, j, k)); } /* Emits the `mulh.du d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MULH_DU, d, j, k)); } /* Emits the `div.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_div_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_DIV_W, d, j, k)); } /* Emits the `mod.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mod_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MOD_W, d, j, k)); } /* Emits the `div.wu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_div_wu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_DIV_WU, d, j, k)); } /* Emits the `mod.wu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MOD_WU, d, j, k)); } /* Emits the `div.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_div_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_DIV_D, d, j, k)); } /* Emits the `mod.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mod_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MOD_D, d, j, k)); } /* Emits the `div.du d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_div_du(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_DIV_DU, d, j, k)); } /* Emits the `mod.du d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_mod_du(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k)); } /* Emits the `slli.w d, j, uk5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +static void __attribute__((unused)) tcg_out_opc_slli_w(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk5) { tcg_out32(s, encode_djuk5_insn(OPC_SLLI_W, d, j, uk5)); } /* Emits the `slli.d d, j, uk6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +static void __attribute__((unused)) tcg_out_opc_slli_d(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk6) { tcg_out32(s, encode_djuk6_insn(OPC_SLLI_D, d, j, uk6)); } /* Emits the `srli.w d, j, uk5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +static void __attribute__((unused)) tcg_out_opc_srli_w(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk5) { tcg_out32(s, encode_djuk5_insn(OPC_SRLI_W, d, j, uk5)); } /* Emits the `srli.d d, j, uk6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +static void __attribute__((unused)) tcg_out_opc_srli_d(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk6) { tcg_out32(s, encode_djuk6_insn(OPC_SRLI_D, d, j, uk6)); } /* Emits the `srai.w d, j, uk5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +static void __attribute__((unused)) tcg_out_opc_srai_w(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk5) { tcg_out32(s, encode_djuk5_insn(OPC_SRAI_W, d, j, uk5)); } /* Emits the `srai.d d, j, uk6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +static void __attribute__((unused)) tcg_out_opc_srai_d(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk6) { tcg_out32(s, encode_djuk6_insn(OPC_SRAI_D, d, j, uk6)); } /* Emits the `rotri.b d, j, uk3` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotri_b(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk3) +static void __attribute__((unused)) tcg_out_opc_rotri_b(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk3) { tcg_out32(s, encode_djuk3_insn(OPC_ROTRI_B, d, j, uk3)); } /* Emits the `rotri.h d, j, uk4` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotri_h(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk4) +static void __attribute__((unused)) tcg_out_opc_rotri_h(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk4) { tcg_out32(s, encode_djuk4_insn(OPC_ROTRI_H, d, j, uk4)); } /* Emits the `rotri.w d, j, uk5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +static void __attribute__((unused)) tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk5) { tcg_out32(s, encode_djuk5_insn(OPC_ROTRI_W, d, j, uk5)); } /* Emits the `rotri.d d, j, uk6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +static void __attribute__((unused)) tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk6) { tcg_out32(s, encode_djuk6_insn(OPC_ROTRI_D, d, j, uk6)); } /* Emits the `bstrins.w d, j, uk5, um5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5, - uint32_t um5) +static void __attribute__((unused)) tcg_out_opc_bstrins_w(TCGContext *s, + TCGReg d, TCGReg j, + uint32_t uk5, + uint32_t um5) { tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRINS_W, d, j, uk5, um5)); } /* Emits the `bstrpick.w d, j, uk5, um5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5, - uint32_t um5) +static void __attribute__((unused)) tcg_out_opc_bstrpick_w(TCGContext *s, + TCGReg d, TCGReg j, + uint32_t uk5, + uint32_t um5) { tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRPICK_W, d, j, uk5, um5)); } /* Emits the `bstrins.d d, j, uk6, um6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6, - uint32_t um6) +static void __attribute__((unused)) tcg_out_opc_bstrins_d(TCGContext *s, + TCGReg d, TCGReg j, + uint32_t uk6, + uint32_t um6) { tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRINS_D, d, j, uk6, um6)); } /* Emits the `bstrpick.d d, j, uk6, um6` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6, - uint32_t um6) +static void __attribute__((unused)) tcg_out_opc_bstrpick_d(TCGContext *s, + TCGReg d, TCGReg j, + uint32_t uk6, + uint32_t um6) { tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRPICK_D, d, j, uk6, um6)); } /* Emits the `fmov.d fd, fj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fmov_d(TCGContext *s, TCGReg fd, TCGReg fj) +static void __attribute__((unused)) tcg_out_opc_fmov_d(TCGContext *s, TCGReg fd, + TCGReg fj) { tcg_out32(s, encode_fdfj_insn(OPC_FMOV_D, fd, fj)); } /* Emits the `movgr2fr.d fd, j` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_movgr2fr_d(TCGContext *s, TCGReg fd, TCGReg j) +static void __attribute__((unused)) tcg_out_opc_movgr2fr_d(TCGContext *s, + TCGReg fd, TCGReg j) { tcg_out32(s, encode_fdj_insn(OPC_MOVGR2FR_D, fd, j)); } /* Emits the `movfr2gr.d d, fj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_movfr2gr_d(TCGContext *s, TCGReg d, TCGReg fj) +static void __attribute__((unused)) tcg_out_opc_movfr2gr_d(TCGContext *s, + TCGReg d, TCGReg fj) { tcg_out32(s, encode_dfj_insn(OPC_MOVFR2GR_D, d, fj)); } /* Emits the `slti d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_slti(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_SLTI, d, j, sk12)); } /* Emits the `sltui d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_sltui(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_SLTUI, d, j, sk12)); } /* Emits the `addi.w d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_addi_w(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ADDI_W, d, j, sk12)); } /* Emits the `addi.d d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_addi_d(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ADDI_D, d, j, sk12)); } /* Emits the `cu52i.d d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_CU52I_D, d, j, sk12)); } /* Emits the `andi d, j, uk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +static void __attribute__((unused)) tcg_out_opc_andi(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk12) { tcg_out32(s, encode_djuk12_insn(OPC_ANDI, d, j, uk12)); } /* Emits the `ori d, j, uk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +static void __attribute__((unused)) tcg_out_opc_ori(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk12) { tcg_out32(s, encode_djuk12_insn(OPC_ORI, d, j, uk12)); } /* Emits the `xori d, j, uk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +static void __attribute__((unused)) tcg_out_opc_xori(TCGContext *s, TCGReg d, + TCGReg j, uint32_t uk12) { tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12)); } @@ -1845,9 +1883,9 @@ tcg_out_opc_vbitsel_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk, TCGReg va) } /* Emits the `xvbitsel.v xd, xj, xk, xa` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvbitsel_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk, - TCGReg xa) +static void __attribute__((unused)) tcg_out_opc_xvbitsel_v(TCGContext *s, + TCGReg xd, TCGReg xj, + TCGReg xk, TCGReg xa) { tcg_out32(s, encode_xdxjxkxa_insn(OPC_XVBITSEL_V, xd, xj, xk, xa)); } @@ -1874,22 +1912,22 @@ tcg_out_opc_addu16i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) } /* Emits the `lu12i.w d, sj20` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20) +static void __attribute__((unused)) tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, + int32_t sj20) { tcg_out32(s, encode_dsj20_insn(OPC_LU12I_W, d, sj20)); } /* Emits the `cu32i.d d, sj20` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20) +static void __attribute__((unused)) tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, + int32_t sj20) { tcg_out32(s, encode_dsj20_insn(OPC_CU32I_D, d, sj20)); } /* Emits the `pcaddu2i d, sj20` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_pcaddu2i(TCGContext *s, TCGReg d, int32_t sj20) +static void __attribute__((unused)) tcg_out_opc_pcaddu2i(TCGContext *s, + TCGReg d, int32_t sj20) { tcg_out32(s, encode_dsj20_insn(OPC_PCADDU2I, d, sj20)); } @@ -1916,134 +1954,134 @@ tcg_out_opc_pcaddu18i(TCGContext *s, TCGReg d, int32_t sj20) } /* Emits the `ld.b d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_b(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_B, d, j, sk12)); } /* Emits the `ld.h d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_h(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_H, d, j, sk12)); } /* Emits the `ld.w d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_w(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_W, d, j, sk12)); } /* Emits the `ld.d d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_d(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_D, d, j, sk12)); } /* Emits the `st.b d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_st_b(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ST_B, d, j, sk12)); } /* Emits the `st.h d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_st_h(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ST_H, d, j, sk12)); } /* Emits the `st.w d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_st_w(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ST_W, d, j, sk12)); } /* Emits the `st.d d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_st_d(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_ST_D, d, j, sk12)); } /* Emits the `ld.bu d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_BU, d, j, sk12)); } /* Emits the `ld.hu d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_HU, d, j, sk12)); } /* Emits the `ld.wu d, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_djsk12_insn(OPC_LD_WU, d, j, sk12)); } /* Emits the `fld.s fd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fld_s(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_fld_s(TCGContext *s, TCGReg fd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_fdjsk12_insn(OPC_FLD_S, fd, j, sk12)); } /* Emits the `fst.s fd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fst_s(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_fst_s(TCGContext *s, TCGReg fd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_fdjsk12_insn(OPC_FST_S, fd, j, sk12)); } /* Emits the `fld.d fd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fld_d(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_fld_d(TCGContext *s, TCGReg fd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_fdjsk12_insn(OPC_FLD_D, fd, j, sk12)); } /* Emits the `fst.d fd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fst_d(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_fst_d(TCGContext *s, TCGReg fd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_fdjsk12_insn(OPC_FST_D, fd, j, sk12)); } /* Emits the `vld vd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vld(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_vld(TCGContext *s, TCGReg vd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_vdjsk12_insn(OPC_VLD, vd, j, sk12)); } /* Emits the `vst vd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vst(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_vst(TCGContext *s, TCGReg vd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_vdjsk12_insn(OPC_VST, vd, j, sk12)); } /* Emits the `xvld xd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvld(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_xvld(TCGContext *s, TCGReg xd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_xdjsk12_insn(OPC_XVLD, xd, j, sk12)); } /* Emits the `xvst xd, j, sk12` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvst(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12) +static void __attribute__((unused)) tcg_out_opc_xvst(TCGContext *s, TCGReg xd, + TCGReg j, int32_t sk12) { tcg_out32(s, encode_xdjsk12_insn(OPC_XVST, xd, j, sk12)); } @@ -2077,33 +2115,37 @@ tcg_out_opc_vldrepl_b(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12) } /* Emits the `vstelm.d vd, j, sk8, un1` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vstelm_d(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8, - uint32_t un1) +static void __attribute__((unused)) tcg_out_opc_vstelm_d(TCGContext *s, + TCGReg vd, TCGReg j, + int32_t sk8, + uint32_t un1) { tcg_out32(s, encode_vdjsk8un1_insn(OPC_VSTELM_D, vd, j, sk8, un1)); } /* Emits the `vstelm.w vd, j, sk8, un2` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vstelm_w(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8, - uint32_t un2) +static void __attribute__((unused)) tcg_out_opc_vstelm_w(TCGContext *s, + TCGReg vd, TCGReg j, + int32_t sk8, + uint32_t un2) { tcg_out32(s, encode_vdjsk8un2_insn(OPC_VSTELM_W, vd, j, sk8, un2)); } /* Emits the `vstelm.h vd, j, sk8, un3` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vstelm_h(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8, - uint32_t un3) +static void __attribute__((unused)) tcg_out_opc_vstelm_h(TCGContext *s, + TCGReg vd, TCGReg j, + int32_t sk8, + uint32_t un3) { tcg_out32(s, encode_vdjsk8un3_insn(OPC_VSTELM_H, vd, j, sk8, un3)); } /* Emits the `vstelm.b vd, j, sk8, un4` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vstelm_b(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8, - uint32_t un4) +static void __attribute__((unused)) tcg_out_opc_vstelm_b(TCGContext *s, + TCGReg vd, TCGReg j, + int32_t sk8, + uint32_t un4) { tcg_out32(s, encode_vdjsk8un4_insn(OPC_VSTELM_B, vd, j, sk8, un4)); } @@ -2137,306 +2179,310 @@ tcg_out_opc_xvldrepl_b(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12) } /* Emits the `xvstelm.d xd, j, sk8, un2` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvstelm_d(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8, - uint32_t un2) +static void __attribute__((unused)) tcg_out_opc_xvstelm_d(TCGContext *s, + TCGReg xd, TCGReg j, + int32_t sk8, + uint32_t un2) { tcg_out32(s, encode_xdjsk8un2_insn(OPC_XVSTELM_D, xd, j, sk8, un2)); } /* Emits the `xvstelm.w xd, j, sk8, un3` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvstelm_w(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8, - uint32_t un3) +static void __attribute__((unused)) tcg_out_opc_xvstelm_w(TCGContext *s, + TCGReg xd, TCGReg j, + int32_t sk8, + uint32_t un3) { tcg_out32(s, encode_xdjsk8un3_insn(OPC_XVSTELM_W, xd, j, sk8, un3)); } /* Emits the `xvstelm.h xd, j, sk8, un4` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvstelm_h(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8, - uint32_t un4) +static void __attribute__((unused)) tcg_out_opc_xvstelm_h(TCGContext *s, + TCGReg xd, TCGReg j, + int32_t sk8, + uint32_t un4) { tcg_out32(s, encode_xdjsk8un4_insn(OPC_XVSTELM_H, xd, j, sk8, un4)); } /* Emits the `xvstelm.b xd, j, sk8, un5` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvstelm_b(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8, - uint32_t un5) +static void __attribute__((unused)) tcg_out_opc_xvstelm_b(TCGContext *s, + TCGReg xd, TCGReg j, + int32_t sk8, + uint32_t un5) { tcg_out32(s, encode_xdjsk8un5_insn(OPC_XVSTELM_B, xd, j, sk8, un5)); } /* Emits the `ldx.b d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_b(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_B, d, j, k)); } /* Emits the `ldx.h d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_h(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_H, d, j, k)); } /* Emits the `ldx.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_W, d, j, k)); } /* Emits the `ldx.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_D, d, j, k)); } /* Emits the `stx.b d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_stx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_stx_b(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_STX_B, d, j, k)); } /* Emits the `stx.h d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_stx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_stx_h(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_STX_H, d, j, k)); } /* Emits the `stx.w d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_stx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_stx_w(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_STX_W, d, j, k)); } /* Emits the `stx.d d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_stx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_stx_d(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_STX_D, d, j, k)); } /* Emits the `ldx.bu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_BU, d, j, k)); } /* Emits the `ldx.hu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_HU, d, j, k)); } /* Emits the `ldx.wu d, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d, + TCGReg j, TCGReg k) { tcg_out32(s, encode_djk_insn(OPC_LDX_WU, d, j, k)); } /* Emits the `fldx.s fd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fldx_s(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_fldx_s(TCGContext *s, TCGReg fd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_fdjk_insn(OPC_FLDX_S, fd, j, k)); } /* Emits the `fldx.d fd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fldx_d(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_fldx_d(TCGContext *s, TCGReg fd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_fdjk_insn(OPC_FLDX_D, fd, j, k)); } /* Emits the `fstx.s fd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fstx_s(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_fstx_s(TCGContext *s, TCGReg fd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_fdjk_insn(OPC_FSTX_S, fd, j, k)); } /* Emits the `fstx.d fd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_fstx_d(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_fstx_d(TCGContext *s, TCGReg fd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_fdjk_insn(OPC_FSTX_D, fd, j, k)); } /* Emits the `vldx vd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vldx(TCGContext *s, TCGReg vd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_vldx(TCGContext *s, TCGReg vd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_vdjk_insn(OPC_VLDX, vd, j, k)); } /* Emits the `vstx vd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vstx(TCGContext *s, TCGReg vd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_vstx(TCGContext *s, TCGReg vd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_vdjk_insn(OPC_VSTX, vd, j, k)); } /* Emits the `xvldx xd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvldx(TCGContext *s, TCGReg xd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_xvldx(TCGContext *s, TCGReg xd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_xdjk_insn(OPC_XVLDX, xd, j, k)); } /* Emits the `xvstx xd, j, k` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvstx(TCGContext *s, TCGReg xd, TCGReg j, TCGReg k) +static void __attribute__((unused)) tcg_out_opc_xvstx(TCGContext *s, TCGReg xd, + TCGReg j, TCGReg k) { tcg_out32(s, encode_xdjk_insn(OPC_XVSTX, xd, j, k)); } /* Emits the `dbar ud15` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_dbar(TCGContext *s, uint32_t ud15) +static void __attribute__((unused)) tcg_out_opc_dbar(TCGContext *s, + uint32_t ud15) { tcg_out32(s, encode_ud15_insn(OPC_DBAR, ud15)); } /* Emits the `jiscr0 sd5k16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_jiscr0(TCGContext *s, int32_t sd5k16) +static void __attribute__((unused)) tcg_out_opc_jiscr0(TCGContext *s, + int32_t sd5k16) { tcg_out32(s, encode_sd5k16_insn(OPC_JISCR0, sd5k16)); } /* Emits the `jiscr1 sd5k16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_jiscr1(TCGContext *s, int32_t sd5k16) +static void __attribute__((unused)) tcg_out_opc_jiscr1(TCGContext *s, + int32_t sd5k16) { tcg_out32(s, encode_sd5k16_insn(OPC_JISCR1, sd5k16)); } /* Emits the `jirl d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_jirl(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_JIRL, d, j, sk16)); } /* Emits the `b sd10k16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_b(TCGContext *s, int32_t sd10k16) +static void __attribute__((unused)) tcg_out_opc_b(TCGContext *s, + int32_t sd10k16) { tcg_out32(s, encode_sd10k16_insn(OPC_B, sd10k16)); } /* Emits the `bl sd10k16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bl(TCGContext *s, int32_t sd10k16) +static void __attribute__((unused)) tcg_out_opc_bl(TCGContext *s, + int32_t sd10k16) { tcg_out32(s, encode_sd10k16_insn(OPC_BL, sd10k16)); } /* Emits the `beq d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_beq(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BEQ, d, j, sk16)); } /* Emits the `bne d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_bne(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BNE, d, j, sk16)); } /* Emits the `bgt d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_bgt(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BGT, d, j, sk16)); } /* Emits the `ble d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_ble(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BLE, d, j, sk16)); } /* Emits the `bgtu d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_bgtu(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BGTU, d, j, sk16)); } /* Emits the `bleu d, j, sk16` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +static void __attribute__((unused)) tcg_out_opc_bleu(TCGContext *s, TCGReg d, + TCGReg j, int32_t sk16) { tcg_out32(s, encode_djsk16_insn(OPC_BLEU, d, j, sk16)); } /* Emits the `vseq.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vseq_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vseq_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_B, vd, vj, vk)); } /* Emits the `vseq.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vseq_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vseq_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_H, vd, vj, vk)); } /* Emits the `vseq.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vseq_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vseq_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_W, vd, vj, vk)); } /* Emits the `vseq.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vseq_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vseq_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_D, vd, vj, vk)); } /* Emits the `vsle.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsle_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsle_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_B, vd, vj, vk)); } /* Emits the `vsle.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsle_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsle_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_H, vd, vj, vk)); } /* Emits the `vsle.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsle_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsle_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_W, vd, vj, vk)); } /* Emits the `vsle.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsle_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsle_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_D, vd, vj, vk)); } @@ -2470,29 +2516,29 @@ tcg_out_opc_vsle_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) } /* Emits the `vslt.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vslt_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vslt_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_B, vd, vj, vk)); } /* Emits the `vslt.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vslt_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vslt_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_H, vd, vj, vk)); } /* Emits the `vslt.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vslt_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vslt_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_W, vd, vj, vk)); } /* Emits the `vslt.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vslt_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vslt_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_D, vd, vj, vk)); } @@ -2526,57 +2572,57 @@ tcg_out_opc_vslt_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) } /* Emits the `vadd.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vadd_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vadd_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_B, vd, vj, vk)); } /* Emits the `vadd.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vadd_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vadd_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_H, vd, vj, vk)); } /* Emits the `vadd.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vadd_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vadd_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_W, vd, vj, vk)); } /* Emits the `vadd.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vadd_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vadd_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_D, vd, vj, vk)); } /* Emits the `vsub.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsub_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsub_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_B, vd, vj, vk)); } /* Emits the `vsub.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsub_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsub_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_H, vd, vj, vk)); } /* Emits the `vsub.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsub_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsub_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_W, vd, vj, vk)); } /* Emits the `vsub.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsub_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsub_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_D, vd, vj, vk)); } @@ -2694,57 +2740,57 @@ tcg_out_opc_vssub_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) } /* Emits the `vmax.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmax_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmax_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_B, vd, vj, vk)); } /* Emits the `vmax.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmax_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmax_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_H, vd, vj, vk)); } /* Emits the `vmax.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmax_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmax_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_W, vd, vj, vk)); } /* Emits the `vmax.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmax_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmax_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_D, vd, vj, vk)); } /* Emits the `vmin.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmin_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmin_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_B, vd, vj, vk)); } /* Emits the `vmin.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmin_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmin_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_H, vd, vj, vk)); } /* Emits the `vmin.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmin_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmin_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_W, vd, vj, vk)); } /* Emits the `vmin.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmin_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmin_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_D, vd, vj, vk)); } @@ -2806,113 +2852,113 @@ tcg_out_opc_vmin_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) } /* Emits the `vmul.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmul_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmul_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_B, vd, vj, vk)); } /* Emits the `vmul.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmul_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmul_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_H, vd, vj, vk)); } /* Emits the `vmul.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmul_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmul_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_W, vd, vj, vk)); } /* Emits the `vmul.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vmul_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vmul_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_D, vd, vj, vk)); } /* Emits the `vsll.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsll_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsll_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_B, vd, vj, vk)); } /* Emits the `vsll.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsll_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsll_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_H, vd, vj, vk)); } /* Emits the `vsll.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsll_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsll_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_W, vd, vj, vk)); } /* Emits the `vsll.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsll_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsll_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_D, vd, vj, vk)); } /* Emits the `vsrl.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsrl_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsrl_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_B, vd, vj, vk)); } /* Emits the `vsrl.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsrl_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsrl_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_H, vd, vj, vk)); } /* Emits the `vsrl.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsrl_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsrl_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_W, vd, vj, vk)); } /* Emits the `vsrl.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsrl_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsrl_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_D, vd, vj, vk)); } /* Emits the `vsra.b vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsra_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsra_b(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_B, vd, vj, vk)); } /* Emits the `vsra.h vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsra_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsra_h(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_H, vd, vj, vk)); } /* Emits the `vsra.w vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsra_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsra_w(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_W, vd, vj, vk)); } /* Emits the `vsra.d vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vsra_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vsra_d(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_D, vd, vj, vk)); } @@ -2974,29 +3020,29 @@ tcg_out_opc_vreplve_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg k) } /* Emits the `vand.v vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vand_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vand_v(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VAND_V, vd, vj, vk)); } /* Emits the `vor.v vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vor_v(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VOR_V, vd, vj, vk)); } /* Emits the `vxor.v vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vxor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vxor_v(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VXOR_V, vd, vj, vk)); } /* Emits the `vnor.v vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vnor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vnor_v(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VNOR_V, vd, vj, vk)); } @@ -3009,8 +3055,8 @@ tcg_out_opc_vandn_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) } /* Emits the `vorn.v vd, vj, vk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vorn_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk) +static void __attribute__((unused)) tcg_out_opc_vorn_v(TCGContext *s, TCGReg vd, + TCGReg vj, TCGReg vk) { tcg_out32(s, encode_vdvjvk_insn(OPC_VORN_V, vd, vj, vk)); } @@ -3324,29 +3370,29 @@ tcg_out_opc_vmini_du(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk5) } /* Emits the `vneg.b vd, vj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vneg_b(TCGContext *s, TCGReg vd, TCGReg vj) +static void __attribute__((unused)) tcg_out_opc_vneg_b(TCGContext *s, TCGReg vd, + TCGReg vj) { tcg_out32(s, encode_vdvj_insn(OPC_VNEG_B, vd, vj)); } /* Emits the `vneg.h vd, vj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vneg_h(TCGContext *s, TCGReg vd, TCGReg vj) +static void __attribute__((unused)) tcg_out_opc_vneg_h(TCGContext *s, TCGReg vd, + TCGReg vj) { tcg_out32(s, encode_vdvj_insn(OPC_VNEG_H, vd, vj)); } /* Emits the `vneg.w vd, vj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vneg_w(TCGContext *s, TCGReg vd, TCGReg vj) +static void __attribute__((unused)) tcg_out_opc_vneg_w(TCGContext *s, TCGReg vd, + TCGReg vj) { tcg_out32(s, encode_vdvj_insn(OPC_VNEG_W, vd, vj)); } /* Emits the `vneg.d vd, vj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vneg_d(TCGContext *s, TCGReg vd, TCGReg vj) +static void __attribute__((unused)) tcg_out_opc_vneg_d(TCGContext *s, TCGReg vd, + TCGReg vj) { tcg_out32(s, encode_vdvj_insn(OPC_VNEG_D, vd, vj)); } @@ -3702,8 +3748,8 @@ tcg_out_opc_vandi_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8) } /* Emits the `vori.b vd, vj, uk8` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vori_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8) +static void __attribute__((unused)) tcg_out_opc_vori_b(TCGContext *s, TCGReg vd, + TCGReg vj, uint32_t uk8) { tcg_out32(s, encode_vdvjuk8_insn(OPC_VORI_B, vd, vj, uk8)); } @@ -3723,8 +3769,8 @@ tcg_out_opc_vnori_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8) } /* Emits the `vldi vd, sj13` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_vldi(TCGContext *s, TCGReg vd, int32_t sj13) +static void __attribute__((unused)) tcg_out_opc_vldi(TCGContext *s, TCGReg vd, + int32_t sj13) { tcg_out32(s, encode_vdsj13_insn(OPC_VLDI, vd, sj13)); } @@ -4325,8 +4371,8 @@ tcg_out_opc_xvand_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk) } /* Emits the `xvor.v xd, xj, xk` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvor_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk) +static void __attribute__((unused)) tcg_out_opc_xvor_v(TCGContext *s, TCGReg xd, + TCGReg xj, TCGReg xk) { tcg_out32(s, encode_xdxjxk_insn(OPC_XVOR_V, xd, xj, xk)); } @@ -4668,29 +4714,29 @@ tcg_out_opc_xvmini_du(TCGContext *s, TCGReg xd, TCGReg xj, uint32_t uk5) } /* Emits the `xvneg.b xd, xj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvneg_b(TCGContext *s, TCGReg xd, TCGReg xj) +static void __attribute__((unused)) tcg_out_opc_xvneg_b(TCGContext *s, + TCGReg xd, TCGReg xj) { tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_B, xd, xj)); } /* Emits the `xvneg.h xd, xj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvneg_h(TCGContext *s, TCGReg xd, TCGReg xj) +static void __attribute__((unused)) tcg_out_opc_xvneg_h(TCGContext *s, + TCGReg xd, TCGReg xj) { tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_H, xd, xj)); } /* Emits the `xvneg.w xd, xj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvneg_w(TCGContext *s, TCGReg xd, TCGReg xj) +static void __attribute__((unused)) tcg_out_opc_xvneg_w(TCGContext *s, + TCGReg xd, TCGReg xj) { tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_W, xd, xj)); } /* Emits the `xvneg.d xd, xj` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvneg_d(TCGContext *s, TCGReg xd, TCGReg xj) +static void __attribute__((unused)) tcg_out_opc_xvneg_d(TCGContext *s, + TCGReg xd, TCGReg xj) { tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_D, xd, xj)); } @@ -5060,8 +5106,8 @@ tcg_out_opc_xvnori_b(TCGContext *s, TCGReg xd, TCGReg xj, uint32_t uk8) } /* Emits the `xvldi xd, sj13` instruction. */ -static void __attribute__((unused)) -tcg_out_opc_xvldi(TCGContext *s, TCGReg xd, int32_t sj13) +static void __attribute__((unused)) tcg_out_opc_xvldi(TCGContext *s, TCGReg xd, + int32_t sj13) { tcg_out32(s, encode_xdsj13_insn(OPC_XVLDI, xd, sj13)); } -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 18/38] tcg/loongarch64: Implement revbit{8,32,64} 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (16 preceding siblings ...) 2026-08-18 17:01 ` [PULL 17/38] tcg/loongarch64: Import REVBIT insns Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 19/38] util/cpuinfo-riscv: Detect Zbkb Richard Henderson ` (20 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Anton Johansson, Philippe Mathieu-Daudé Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/loongarch64/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 97ed51d99c..7d89e80886 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1866,16 +1866,44 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static void tgen_revbit8(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + if (type == TCG_TYPE_I32) { + tcg_out_opc_revbit_4b(s, a0, a1); + } else { + tcg_out_opc_revbit_8b(s, a0, a1); + } +} + static const TCGOutOpUnary outop_revbit8 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit8; }; +static void tgen_revbit32(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, unsigned flags) +{ + tcg_out_opc_revbit_w(s, a0, a1); + + /* All 32-bit values are computed sign-extended in the register. */ + if (type == TCG_TYPE_I64 && (flags & TCG_BSWAP_OZ)) { + tcg_out_ext32u(s, a0, a0); + } +} + static const TCGOutOpBswap outop_revbit32 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit32, }; +static void tgen_revbit64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_opc_revbit_d(s, a0, a1); +} + static const TCGOutOpUnary outop_revbit64 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit64, }; static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 19/38] util/cpuinfo-riscv: Detect Zbkb 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (17 preceding siblings ...) 2026-08-18 17:01 ` [PULL 18/38] tcg/loongarch64: Implement revbit{8,32,64} Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 20/38] tcg/riscv64: Implement revbit8 Richard Henderson ` (19 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Alistair Francis, Philippe Mathieu-Daudé RISCV_HWPROBE_EXT_ZBKB was introduced in linux 6.10 with the rest of the hwprobe api. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- host/include/riscv64/host/cpuinfo.h | 1 + util/cpuinfo-riscv.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/host/include/riscv64/host/cpuinfo.h b/host/include/riscv64/host/cpuinfo.h index b2b53dbf62..1f047051a3 100644 --- a/host/include/riscv64/host/cpuinfo.h +++ b/host/include/riscv64/host/cpuinfo.h @@ -12,6 +12,7 @@ #define CPUINFO_ZBS (1u << 3) #define CPUINFO_ZICOND (1u << 4) #define CPUINFO_ZVE64X (1u << 5) +#define CPUINFO_ZBKB (1u << 6) /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 0291b7218a..8c48b1ea91 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -36,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS | CPUINFO_ZBKB | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; @@ -60,6 +60,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #if defined(__riscv_arch_test) && \ (defined(__riscv_vector) || defined(__riscv_zve64x)) info |= CPUINFO_ZVE64X; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zbkb) + info |= CPUINFO_ZBKB; #endif left &= ~info; @@ -76,7 +79,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBS ? CPUINFO_ZBS : 0; - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS); + info |= pair.value & RISCV_HWPROBE_EXT_ZBKB ? CPUINFO_ZBKB : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS | CPUINFO_ZBKB); #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; @@ -131,6 +135,15 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) left &= ~CPUINFO_ZBS; } + if (left & CPUINFO_ZBKB) { + /* Probe for Zbkb: brev8 zero,zero. */ + got_sigill = 0; + asm volatile(".insn i 0x13, 5, zero, zero, 0x687" + : : : "memory"); + info |= got_sigill ? 0 : CPUINFO_ZBKB; + left &= ~CPUINFO_ZBKB; + } + if (left & CPUINFO_ZICOND) { /* Probe for Zicond: czero.eqz zero,zero,zero. */ got_sigill = 0; -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 20/38] tcg/riscv64: Implement revbit8 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (18 preceding siblings ...) 2026-08-18 17:01 ` [PULL 19/38] util/cpuinfo-riscv: Detect Zbkb Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 21/38] tests/tcg/loongarch64: Tidy test_bit.c Richard Henderson ` (18 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Alistair Francis Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv64/tcg-target.c.inc | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 687146e0b0..8fd32644fe 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -246,6 +246,9 @@ typedef enum { OPC_XNOR = 0x40004033, OPC_ZEXT_H = 0x0800403b, + /* Zbkb: Bit Manipulation for Cryptography */ + OPC_BREV8 = 0x68705013, + /* Zicond: integer conditional operations */ OPC_CZERO_EQZ = 0x0e005033, OPC_CZERO_NEZ = 0x0e007033, @@ -2469,8 +2472,20 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static TCGConstraintSetIndex cset_revbit8(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_ZBKB ? C_O1_I1(r, r) : C_NotImplemented; +} + +static void tgen_revbit8(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_opc_imm(s, OPC_BREV8, a0, a1, 0); +} + static const TCGOutOpUnary outop_revbit8 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_revbit8, + .out_rr = tgen_revbit8, }; static const TCGOutOpBswap outop_revbit32 = { -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 21/38] tests/tcg/loongarch64: Tidy test_bit.c 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (19 preceding siblings ...) 2026-08-18 17:01 ` [PULL 20/38] tcg/riscv64: Implement revbit8 Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 22/38] tests/tcg/loongarch64: Add bitrev smoke tests Richard Henderson ` (17 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Use one macro for all test templates. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tests/tcg/loongarch64/test_bit.c | 69 +++++++------------------------- 1 file changed, 15 insertions(+), 54 deletions(-) diff --git a/tests/tcg/loongarch64/test_bit.c b/tests/tcg/loongarch64/test_bit.c index a6d9904909..69b2eaac78 100644 --- a/tests/tcg/loongarch64/test_bit.c +++ b/tests/tcg/loongarch64/test_bit.c @@ -2,62 +2,23 @@ #include <inttypes.h> #define ARRAY_SIZE(X) (sizeof(X) / sizeof(*(X))) -#define TEST_CLO(N) \ -static uint64_t test_clo_##N(uint64_t rj) \ -{ \ - uint64_t rd = 0; \ - \ - asm volatile("clo."#N" %0, %1\n\t" \ - : "=r"(rd) \ - : "r"(rj) \ - : ); \ - return rd; \ + +#define TEST(C, I) \ +static uint64_t test_##C(uint64_t rj) \ +{ \ + uint64_t rd; \ + asm volatile(I " %0, %1\n\t" : "=r"(rd) : "r"(rj)); \ + return rd; \ } -#define TEST_CLZ(N) \ -static uint64_t test_clz_##N(uint64_t rj) \ -{ \ - uint64_t rd = 0; \ - \ - asm volatile("clz."#N" %0, %1\n\t" \ - : "=r"(rd) \ - : "r"(rj) \ - : ); \ - return rd; \ -} - -#define TEST_CTO(N) \ -static uint64_t test_cto_##N(uint64_t rj) \ -{ \ - uint64_t rd = 0; \ - \ - asm volatile("cto."#N" %0, %1\n\t" \ - : "=r"(rd) \ - : "r"(rj) \ - : ); \ - return rd; \ -} - -#define TEST_CTZ(N) \ -static uint64_t test_ctz_##N(uint64_t rj) \ -{ \ - uint64_t rd = 0; \ - \ - asm volatile("ctz."#N" %0, %1\n\t" \ - : "=r"(rd) \ - : "r"(rj) \ - : ); \ - return rd; \ -} - -TEST_CLO(w) -TEST_CLO(d) -TEST_CLZ(w) -TEST_CLZ(d) -TEST_CTO(w) -TEST_CTO(d) -TEST_CTZ(w) -TEST_CTZ(d) +TEST(clo_w, "clo.w") +TEST(clo_d, "clo.d") +TEST(clz_w, "clz.w") +TEST(clz_d, "clz.d") +TEST(cto_w, "cto.w") +TEST(cto_d, "cto.d") +TEST(ctz_w, "ctz.w") +TEST(ctz_d, "ctz.d") struct vector { uint64_t (*func)(uint64_t); -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 22/38] tests/tcg/loongarch64: Add bitrev smoke tests 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (20 preceding siblings ...) 2026-08-18 17:01 ` [PULL 21/38] tests/tcg/loongarch64: Tidy test_bit.c Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 23/38] tcg: Add integer min/max opcodes Richard Henderson ` (16 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tests/tcg/loongarch64/test_bit.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/tcg/loongarch64/test_bit.c b/tests/tcg/loongarch64/test_bit.c index 69b2eaac78..65cd6598c9 100644 --- a/tests/tcg/loongarch64/test_bit.c +++ b/tests/tcg/loongarch64/test_bit.c @@ -19,6 +19,10 @@ TEST(cto_w, "cto.w") TEST(cto_d, "cto.d") TEST(ctz_w, "ctz.w") TEST(ctz_d, "ctz.d") +TEST(bitrev_4b, "bitrev.4b") +TEST(bitrev_8b, "bitrev.8b") +TEST(bitrev_w, "bitrev.w") +TEST(bitrev_d, "bitrev.d") struct vector { uint64_t (*func)(uint64_t); @@ -35,6 +39,10 @@ static struct vector vectors[] = { {test_cto_d, 0xabd28a64000000, 0}, {test_ctz_w, 0xfaffff42392476ab, 0}, {test_ctz_d, 0xabd28a64000000, 26}, + {test_bitrev_4b, 0xdeadbeef11223344, 0xffffffff8844cc22}, + {test_bitrev_8b, 0x1122334455667788, 0x8844cc22aa66ee11}, + {test_bitrev_w, 0xdeadbeef89abcdef, 0xfffffffff7b3d591}, + {test_bitrev_d, 0x0123456789abcdef, 0xf7b3d591e6a2c480}, }; int main() -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 23/38] tcg: Add integer min/max opcodes 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (21 preceding siblings ...) 2026-08-18 17:01 ` [PULL 22/38] tests/tcg/loongarch64: Add bitrev smoke tests Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 24/38] tcg/optimize: Handle " Richard Henderson ` (15 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Alex Bennée We already have these for vectors; replicate for integers. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-opc.h | 4 +++ tcg/tcg-op.c | 48 ++++++++++++++++++++++++++------ tcg/tcg.c | 8 ++++++ docs/devel/tcg-ops.rst | 12 ++++++++ tcg/aarch64/tcg-target.c.inc | 16 +++++++++++ tcg/loongarch64/tcg-target.c.inc | 16 +++++++++++ tcg/ppc64/tcg-target.c.inc | 16 +++++++++++ tcg/riscv64/tcg-target.c.inc | 16 +++++++++++ tcg/s390x/tcg-target.c.inc | 16 +++++++++++ tcg/sparc64/tcg-target.c.inc | 16 +++++++++++ tcg/tci/tcg-target.c.inc | 16 +++++++++++ tcg/x86_64/tcg-target.c.inc | 16 +++++++++++ 12 files changed, 192 insertions(+), 8 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 13c7f17f76..f3a81d5d7f 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -89,11 +89,15 @@ DEF(setcond, 1, 2, 1, TCG_OPF_INT) DEF(sextract, 1, 1, 2, TCG_OPF_INT) DEF(shl, 1, 2, 0, TCG_OPF_INT) DEF(shr, 1, 2, 0, TCG_OPF_INT) +DEF(smax, 1, 2, 0, TCG_OPF_INT) +DEF(smin, 1, 2, 0, TCG_OPF_INT) DEF(st8, 0, 2, 1, TCG_OPF_INT) DEF(st16, 0, 2, 1, TCG_OPF_INT) DEF(st32, 0, 2, 1, TCG_OPF_INT) DEF(st, 0, 2, 1, TCG_OPF_INT) DEF(sub, 1, 2, 0, TCG_OPF_INT) +DEF(umax, 1, 2, 0, TCG_OPF_INT) +DEF(umin, 1, 2, 0, TCG_OPF_INT) DEF(xor, 1, 2, 0, TCG_OPF_INT) DEF(addco, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c302a484cd..e28944cf72 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1294,22 +1294,38 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); + if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i32(INDEX_op_smin, ret, a, b); + } else { + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); + } } void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); + if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i32(INDEX_op_umin, ret, a, b); + } else { + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); + } } void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); + if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i32(INDEX_op_smax, ret, a, b); + } else { + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); + } } void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); + if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i32(INDEX_op_umax, ret, a, b); + } else { + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); + } } void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) @@ -2473,22 +2489,38 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); + if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_smin, ret, a, b); + } else { + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); + } } void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); + if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_umin, ret, a, b); + } else { + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); + } } void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); + if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_smax, ret, a, b); + } else { + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); + } } void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); + if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_umax, ret, a, b); + } else { + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); + } } void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) diff --git a/tcg/tcg.c b/tcg/tcg.c index 8a324ce885..489df0e738 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1211,6 +1211,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_sextract, TCGOutOpExtract, outop_sextract), OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl), OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr), + OUTOP(INDEX_op_smax, TCGOutOpBinary, outop_smax), + OUTOP(INDEX_op_smin, TCGOutOpBinary, outop_smin), OUTOP(INDEX_op_st, TCGOutOpStore, outop_st), OUTOP(INDEX_op_st8, TCGOutOpStore, outop_st8), OUTOP(INDEX_op_st16, TCGOutOpStore, outop_st16), @@ -1220,6 +1222,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_subbo, TCGOutOpAddSubCarry, outop_subbo), /* subb1o is implemented with set_borrow + subbio */ OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), + OUTOP(INDEX_op_umax, TCGOutOpBinary, outop_umax), + OUTOP(INDEX_op_umin, TCGOutOpBinary, outop_umin), OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), [INDEX_op_goto_ptr] = &outop_goto_ptr, @@ -5518,6 +5522,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_sar: case INDEX_op_shl: case INDEX_op_shr: + case INDEX_op_smax: + case INDEX_op_smin: + case INDEX_op_umax: + case INDEX_op_umin: case INDEX_op_xor: { const TCGOutOpBinary *out = diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index f2e9255dd9..88d48a1f99 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -317,6 +317,18 @@ Arithmetic pass 0 to *nh* to make a simple zero-extension of *nl*, so overflow should never occur. + * - smax *t0*, *t1*, *t2* + + umax *t0*, *t1*, *t2* + + - | *t0* = MAX(*t1*, *t2*), for signed and unsigned integers. + + * - smin *t0*, *t1*, *t2* + + umin *t0*, *t1*, *t2* + + - | *t0* = MIN(*t1*, *t2*), for signed and unsigned integers. + Logical ------- diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 80995403e4..f5c185bbf4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2592,6 +2592,22 @@ static void tcg_out_set_borrow(TCGContext *s) TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR); } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 7d89e80886..f65496a040 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1804,6 +1804,22 @@ static void tcg_out_set_borrow(TCGContext *s) g_assert_not_reached(); } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index 07dff67e84..cd1c234367 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -3281,6 +3281,22 @@ static void tcg_out_set_borrow(TCGContext *s) tcg_out32(s, ADDIC | TAI(TCG_REG_R0, TCG_REG_R0, 0)); } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 8fd32644fe..723c21b3da 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2404,6 +2404,22 @@ static void tcg_out_set_borrow(TCGContext *s) g_assert_not_reached(); } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c481745c3f..4d1a779c47 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2950,6 +2950,22 @@ static void tcg_out_set_borrow(TCGContext *s) tcg_out_insn(s, RR, CLR, TCG_REG_R0, TCG_REG_R0); /* cc = 0 */ } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index d6ed9d3362..35cd14a5b6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1917,6 +1917,22 @@ static void tcg_out_set_borrow(TCGContext *s) tcg_out_set_carry(s); /* borrow == carry */ } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1b61668517..4cd1c1431c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -894,6 +894,22 @@ static void tcg_out_set_borrow(TCGContext *s) tcg_out_op_v(s, INDEX_op_tci_setcarry); /* borrow == carry */ } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 37acba9045..2c8f1f3e58 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -2977,6 +2977,22 @@ static void tcg_out_set_borrow(TCGContext *s) tcg_out8(s, OPC_STC); } +static const TCGOutOpBinary outop_smax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_smin = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umax = { + .base.static_constraint = C_NotImplemented, +}; + +static const TCGOutOpBinary outop_umin = { + .base.static_constraint = C_NotImplemented, +}; + static void tgen_xor(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 24/38] tcg/optimize: Handle min/max opcodes 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (22 preceding siblings ...) 2026-08-18 17:01 ` [PULL 23/38] tcg: Add integer min/max opcodes Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 25/38] util/cpuinfo-aarch64: Detect FEAT_CSSC Richard Henderson ` (14 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Alex Bennée, Philippe Mathieu-Daudé Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/optimize.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index facf4c1e0f..d291c844ca 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -597,6 +597,30 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type, } return (uint64_t)x % ((uint64_t)y ? : 1); + case INDEX_op_smax: + if (type == TCG_TYPE_I32) { + return MAX((int32_t)x, (int32_t)y); + } + return MAX((int64_t)x, (int64_t)y); + + case INDEX_op_smin: + if (type == TCG_TYPE_I32) { + return MIN((int32_t)x, (int32_t)y); + } + return MIN((int64_t)x, (int64_t)y); + + case INDEX_op_umax: + if (type == TCG_TYPE_I32) { + return MAX((uint32_t)x, (uint32_t)y); + } + return MAX((uint64_t)x, (uint64_t)y); + + case INDEX_op_umin: + if (type == TCG_TYPE_I32) { + return MIN((uint32_t)x, (uint32_t)y); + } + return MIN((uint64_t)x, (uint64_t)y); + default: g_assert_not_reached(); } @@ -2101,6 +2125,16 @@ static bool fold_mb(OptContext *ctx, TCGOp *op) return true; } +static bool fold_minmax(OptContext *ctx, TCGOp *op, uint64_t bound) +{ + if (fold_const2_commutative(ctx, op) || + fold_xi_to_i(ctx, op, bound) || + fold_xx_to_x(ctx, op)) { + return true; + } + return finish_folding(ctx, op); +} + static bool fold_mov(OptContext *ctx, TCGOp *op) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); @@ -3258,6 +3292,14 @@ void tcg_optimize(TCGContext *s) case INDEX_op_sextract: done = fold_sextract(&ctx, op); break; + case INDEX_op_smax: + done = fold_minmax(&ctx, op, (ctx.type == TCG_TYPE_I32 + ? INT32_MAX : INT64_MAX)); + break; + case INDEX_op_smin: + done = fold_minmax(&ctx, op, (ctx.type == TCG_TYPE_I32 + ? INT32_MIN : INT64_MIN)); + break; case INDEX_op_sub: done = fold_sub(&ctx, op); break; @@ -3273,6 +3315,16 @@ void tcg_optimize(TCGContext *s) case INDEX_op_sub_vec: done = fold_sub_vec(&ctx, op); break; + case INDEX_op_umax: + /* + * Note that 32-bit constants are stored sign extended, + * so (int32_t)UINT32_MAX == -1. + */ + done = fold_minmax(&ctx, op, -1); + break; + case INDEX_op_umin: + done = fold_minmax(&ctx, op, 0); + break; case INDEX_op_xor: case INDEX_op_xor_vec: done = fold_xor(&ctx, op); -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 25/38] util/cpuinfo-aarch64: Detect FEAT_CSSC 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (23 preceding siblings ...) 2026-08-18 17:01 ` [PULL 24/38] tcg/optimize: Handle " Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 26/38] tcg/aarch64: Implement min/max with FEAT_CSSC Richard Henderson ` (13 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- host/include/aarch64/host/cpuinfo.h | 1 + util/cpuinfo-aarch64.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/host/cpuinfo.h index fe671534e4..c32c04dade 100644 --- a/host/include/aarch64/host/cpuinfo.h +++ b/host/include/aarch64/host/cpuinfo.h @@ -12,6 +12,7 @@ #define CPUINFO_AES (1u << 3) #define CPUINFO_PMULL (1u << 4) #define CPUINFO_BTI (1u << 5) +#define CPUINFO_CSSC (1u << 6) /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index 288074c08f..4ce6deb7c8 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -72,6 +72,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); info |= (hwcap2 & HWCAP2_BTI ? CPUINFO_BTI : 0); + info |= (hwcap2 & HWCAP2_CSSC ? CPUINFO_CSSC : 0); #endif #ifdef CONFIG_DARWIN info |= sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE; @@ -79,6 +80,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) info |= sysctl_for_bool("hw.optional.arm.FEAT_AES") * CPUINFO_AES; info |= sysctl_for_bool("hw.optional.arm.FEAT_PMULL") * CPUINFO_PMULL; info |= sysctl_for_bool("hw.optional.arm.FEAT_BTI") * CPUINFO_BTI; + info |= sysctl_for_bool("hw.optional.arm.FEAT_CSSC") * CPUINFO_CSSC; #endif #if defined(__OpenBSD__) && !defined(CONFIG_ELF_AUX_INFO) int mib[2]; -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 26/38] tcg/aarch64: Implement min/max with FEAT_CSSC 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (24 preceding siblings ...) 2026-08-18 17:01 ` [PULL 25/38] util/cpuinfo-aarch64: Detect FEAT_CSSC Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 27/38] target/riscv64: Implement min/max with Zbb Richard Henderson ` (12 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target-con-set.h | 2 + tcg/aarch64/tcg-target-con-str.h | 2 + tcg/aarch64/tcg-target.c.inc | 103 +++++++++++++++++++++++++++++-- 3 files changed, 103 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h index d0622e65fb..dd84a9af58 100644 --- a/tcg/aarch64/tcg-target-con-set.h +++ b/tcg/aarch64/tcg-target-con-set.h @@ -24,6 +24,8 @@ C_O1_I2(r, r, rAL) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rL) +C_O1_I2(r, r, rS) +C_O1_I2(r, r, rU) C_O1_I2(r, rZ, rA) C_O1_I2(r, rz, rMZ) C_O1_I2(r, rz, rz) diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h index 48e1722c68..fef75e8a76 100644 --- a/tcg/aarch64/tcg-target-con-str.h +++ b/tcg/aarch64/tcg-target-con-str.h @@ -21,4 +21,6 @@ CONST('L', TCG_CT_CONST_LIMM) CONST('M', TCG_CT_CONST_MONE) CONST('O', TCG_CT_CONST_ORRI) CONST('N', TCG_CT_CONST_ANDI) +CONST('S', TCG_CT_CONST_S8) +CONST('U', TCG_CT_CONST_U8) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f5c185bbf4..55b3be0b96 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -152,6 +152,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, #define TCG_CT_CONST_ORRI 0x1000 #define TCG_CT_CONST_ANDI 0x2000 #define TCG_CT_CONST_CMP 0x4000 +#define TCG_CT_CONST_S8 0x8000 +#define TCG_CT_CONST_U8 0x10000 #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull @@ -320,6 +322,12 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { return 1; } + if ((ct & TCG_CT_CONST_S8) && val == (int8_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_U8) && val == (uint8_t)val) { + return 1; + } if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; } @@ -472,6 +480,12 @@ typedef enum { Iaddsub_imm_SUBI = 0x51000000, Iaddsub_imm_SUBSI = 0x71000000, + /* Min/max immediate instructions. */ + Iminmax_imm_SMAXI = 0x11c00000, + Iminmax_imm_UMAXI = 0x11c40000, + Iminmax_imm_SMINI = 0x11c80000, + Iminmax_imm_UMINI = 0x11cc0000, + /* Bitfield instructions. */ Ibitfield_BFM = 0x33000000, Ibitfield_SBFM = 0x13000000, @@ -533,6 +547,10 @@ typedef enum { Irrr_UMULH = 0x9bc07c00, Irrr_UDIV = 0x1ac00800, Irrr_SDIV = 0x1ac00c00, + Irrr_SMAX = 0x1ac00600, + Irrr_UMAX = 0x1ac00640, + Irrr_SMIN = 0x1ac00680, + Irrr_UMIN = 0x1ac006c0, /* Data-processing (3 source) instructions. */ Irrrr_MADD = 0x1b000000, @@ -737,6 +755,13 @@ static void tcg_out_insn_addsub_imm(TCGContext *s, AArch64Insn insn, tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd); } +static void tcg_out_insn_minmax_imm(TCGContext *s, AArch64Insn insn, + TCGType ext, TCGReg rd, TCGReg rn, + uint8_t imm) +{ + tcg_out32(s, insn | ext << 31 | imm << 10 | rn << 5 | rd); +} + /* This function can be used for both 3.4.2 (Bitfield) and 3.4.4 (Logical immediate). Both insn groups have N, IMMR and IMMS fields that feed the DecodeBitMasks pseudo function. */ @@ -2592,20 +2617,90 @@ static void tcg_out_set_borrow(TCGContext *s) TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR); } +static TCGConstraintSetIndex cset_sminmax(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_CSSC ? C_O1_I2(r, r, rS) : C_NotImplemented; +} + +static void tgen_smax(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_insn(s, rrr, SMAX, type, a0, a1, a2); +} + +static void tgen_smaxi(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, tcg_target_long a2) +{ + tcg_out_insn(s, minmax_imm, SMAXI, type, a0, a1, a2); +} + static const TCGOutOpBinary outop_smax = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_sminmax, + .out_rrr = tgen_smax, + .out_rri = tgen_smaxi, }; +static void tgen_smin(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_insn(s, rrr, SMIN, type, a0, a1, a2); +} + +static void tgen_smini(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, tcg_target_long a2) +{ + tcg_out_insn(s, minmax_imm, SMINI, type, a0, a1, a2); +} + static const TCGOutOpBinary outop_smin = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_sminmax, + .out_rrr = tgen_smin, + .out_rri = tgen_smini, }; +static TCGConstraintSetIndex cset_uminmax(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_CSSC ? C_O1_I2(r, r, rU) : C_NotImplemented; +} + +static void tgen_umax(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_insn(s, rrr, UMAX, type, a0, a1, a2); +} + +static void tgen_umaxi(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, tcg_target_long a2) +{ + tcg_out_insn(s, minmax_imm, UMAXI, type, a0, a1, a2); +} + static const TCGOutOpBinary outop_umax = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_uminmax, + .out_rrr = tgen_umax, + .out_rri = tgen_umaxi, }; +static void tgen_umin(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_insn(s, rrr, UMIN, type, a0, a1, a2); +} + +static void tgen_umini(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, tcg_target_long a2) +{ + tcg_out_insn(s, minmax_imm, UMINI, type, a0, a1, a2); +} + static const TCGOutOpBinary outop_umin = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_uminmax, + .out_rrr = tgen_umin, + .out_rri = tgen_umini, }; static void tgen_xor(TCGContext *s, TCGType type, -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 27/38] target/riscv64: Implement min/max with Zbb 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (25 preceding siblings ...) 2026-08-18 17:01 ` [PULL 26/38] tcg/aarch64: Implement min/max with FEAT_CSSC Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 28/38] tcg/aarch64: Implement ctpop with FEAT_CSSC Richard Henderson ` (11 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv64/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 723c21b3da..2ce9d47a63 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -233,6 +233,10 @@ typedef enum { OPC_CPOPW = 0x6020101b, OPC_CTZ = 0x60101013, OPC_CTZW = 0x6010101b, + OPC_MAX = 0x0a006033, + OPC_MAXU = 0x0a007033, + OPC_MIN = 0x0a004033, + OPC_MINU = 0x0a005033, OPC_ORN = 0x40006033, OPC_REV8 = 0x6b805013, OPC_ROL = 0x60001033, @@ -2404,20 +2408,52 @@ static void tcg_out_set_borrow(TCGContext *s) g_assert_not_reached(); } +static void tgen_smax(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_opc_reg(s, OPC_MAX, a0, a1, a2); +} + static const TCGOutOpBinary outop_smax = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_zbb_rrr, + .out_rrr = tgen_smax, }; +static void tgen_smin(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_opc_reg(s, OPC_MIN, a0, a1, a2); +} + static const TCGOutOpBinary outop_smin = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_zbb_rrr, + .out_rrr = tgen_smin, }; +static void tgen_umax(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_opc_reg(s, OPC_MAXU, a0, a1, a2); +} + static const TCGOutOpBinary outop_umax = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_zbb_rrr, + .out_rrr = tgen_umax, }; +static void tgen_umin(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_opc_reg(s, OPC_MINU, a0, a1, a2); +} + static const TCGOutOpBinary outop_umin = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_zbb_rrr, + .out_rrr = tgen_umin, }; static void tgen_xor(TCGContext *s, TCGType type, -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 28/38] tcg/aarch64: Implement ctpop with FEAT_CSSC 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (26 preceding siblings ...) 2026-08-18 17:01 ` [PULL 27/38] target/riscv64: Implement min/max with Zbb Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 29/38] tcg/aarch64: Use CTZ from FEAT_CSSC Richard Henderson ` (10 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.c.inc | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 55b3be0b96..1f784e8d46 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -535,6 +535,7 @@ typedef enum { /* Data-processing (1 source) instructions. */ Irr_sf_CLZ = 0x5ac01000, + Irr_sf_CNT = 0x5ac01c00, Irr_sf_RBIT = 0x5ac00000, Irr_sf_REV = 0x5ac00000, /* + size << 10 */ @@ -2251,8 +2252,20 @@ static const TCGOutOpBinary outop_clz = { .out_rri = tgen_clzi, }; +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) +{ + return cpuinfo & CPUINFO_CSSC ? C_O1_I1(r, r) : C_NotImplemented; +} + +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_insn(s, rr_sf, CNT, type, a0, a1); +} + static const TCGOutOpUnary outop_ctpop = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_Dynamic, + .base.dynamic_constraint = cset_ctpop, + .out_rr = tgen_ctpop, }; static void tgen_ctz(TCGContext *s, TCGType type, -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 29/38] tcg/aarch64: Use CTZ from FEAT_CSSC 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (27 preceding siblings ...) 2026-08-18 17:01 ` [PULL 28/38] tcg/aarch64: Implement ctpop with FEAT_CSSC Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 30/38] target/riscv: Improve riscv_has_ext Richard Henderson ` (9 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé We already have an expansion of CTZ using RBIT+CLZ, but use the new insn with FEAT_CSSC is present. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.c.inc | 43 +++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1f784e8d46..ce5c039557 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -535,6 +535,7 @@ typedef enum { /* Data-processing (1 source) instructions. */ Irr_sf_CLZ = 0x5ac01000, + Irr_sf_CTZ = 0x5ac01800, Irr_sf_CNT = 0x5ac01c00, Irr_sf_RBIT = 0x5ac00000, Irr_sf_REV = 0x5ac00000, /* + size << 10 */ @@ -2213,24 +2214,30 @@ static const TCGOutOpBinary outop_andc = { .out_rrr = tgen_andc, }; -static void tgen_clz(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) +static void tgen_clzctz(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + TCGReg a2, AArch64Insn insn) { tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true); - tcg_out_insn(s, rr_sf, CLZ, type, TCG_REG_TMP0, a1); + tcg_out_insn_rr_sf(s, insn, type, TCG_REG_TMP0, a1); tcg_out_insn(s, csel, CSEL, type, a0, TCG_REG_TMP0, a2, TCG_COND_NE); } -static void tgen_clzi(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) +static void tgen_clz(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tgen_clzctz(s, type, a0, a1, a2, Irr_sf_CLZ); +} + +static void tgen_clzctzi(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, + tcg_target_long a2, AArch64Insn insn) { if (a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { - tcg_out_insn(s, rr_sf, CLZ, type, a0, a1); + tcg_out_insn_rr_sf(s, insn, type, a0, a1); return; } tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true); - tcg_out_insn(s, rr_sf, CLZ, type, a0, a1); + tcg_out_insn_rr_sf(s, insn, type, a0, a1); switch (a2) { case -1: @@ -2246,6 +2253,12 @@ static void tgen_clzi(TCGContext *s, TCGType type, } } +static void tgen_clzi(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, tcg_target_long a2) +{ + tgen_clzctzi(s, type, a0, a1, a2, Irr_sf_CLZ); +} + static const TCGOutOpBinary outop_clz = { .base.static_constraint = C_O1_I2(r, r, rAL), .out_rrr = tgen_clz, @@ -2271,15 +2284,23 @@ static const TCGOutOpUnary outop_ctpop = { static void tgen_ctz(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { - tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1); - tgen_clz(s, type, a0, TCG_REG_TMP0, a2); + if (cpuinfo & CPUINFO_CSSC) { + tgen_clzctz(s, type, a0, a1, a2, Irr_sf_CTZ); + } else { + tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1); + tgen_clzctz(s, type, a0, TCG_REG_TMP0, a2, Irr_sf_CLZ); + } } static void tgen_ctzi(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, tcg_target_long a2) { - tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1); - tgen_clzi(s, type, a0, TCG_REG_TMP0, a2); + if (cpuinfo & CPUINFO_CSSC) { + tgen_clzctzi(s, type, a0, a1, a2, Irr_sf_CTZ); + } else { + tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1); + tgen_clzctzi(s, type, a0, a1, a2, Irr_sf_CLZ); + } } static const TCGOutOpBinary outop_ctz = { -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 30/38] target/riscv: Improve riscv_has_ext 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (28 preceding siblings ...) 2026-08-18 17:01 ` [PULL 29/38] tcg/aarch64: Use CTZ from FEAT_CSSC Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 31/38] disas/capstone: Allow for cap_insn_unit > length Richard Henderson ` (8 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Constify the env pointer and return bool. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c9dfa7daff..376cff656f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -615,7 +615,7 @@ struct RISCVCPUClass { RISCVCPUDef *def; }; -static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext) +static inline bool riscv_has_ext(const CPURISCVState *env, uint32_t ext) { return (env->misa_ext & ext) != 0; } -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 31/38] disas/capstone: Allow for cap_insn_unit > length 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (29 preceding siblings ...) 2026-08-18 17:01 ` [PULL 30/38] target/riscv: Improve riscv_has_ext Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 32/38] target/riscv: Enable disassembly via capstone Richard Henderson ` (7 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé cap_insn_unit is designed for targets like arm thumb2 and s390x where 4 and 6-byte insns are displayed in 2-byte chunks. For riscv, we prefer 4-byte insns to display as one 4-byte unit, rather than 2x 2-byte units. So we will want to set cap_insn_unit to 4, but allow for insns that are smaller than 4. Emit padding to match. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- disas/capstone.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/disas/capstone.c b/disas/capstone.c index fe3efb0d3c..8fb8d0724c 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -107,8 +107,9 @@ static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn, { fprintf_function print = info->fprintf_func; FILE *stream = info->stream; + int unit = MIN(info->cap_insn_unit, n - i); - switch (info->cap_insn_unit) { + switch (unit) { case 4: if (info->endian == BFD_ENDIAN_BIG) { for (; i < n; i += 4) { @@ -140,6 +141,11 @@ static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn, } break; } + + if (unit < info->cap_insn_unit) { + int width = (info->cap_insn_unit - unit) * 2; + print(stream, "%*s", width, ""); + } } static void cap_dump_insn(disassemble_info *info, cs_insn *insn) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 32/38] target/riscv: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (30 preceding siblings ...) 2026-08-18 17:01 ` [PULL 31/38] disas/capstone: Allow for cap_insn_unit > length Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 33/38] target/sh4: " Richard Henderson ` (6 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé In capstone v5, riscv support is spare, but v6 is pretty good. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 34 +++++++++++++++++ disas/capstone.c | 19 ++++++++++ target/riscv/cpu.c | 81 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 133 insertions(+), 1 deletion(-) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index c43033f7f6..5c78824da2 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -11,6 +11,8 @@ /* Just enough to allow backends to init without ifdefs. */ +#define CS_API_MAJOR 0 + #define CS_ARCH_ARM -1 #define CS_ARCH_ARM64 -1 #define CS_ARCH_MIPS -1 @@ -37,4 +39,36 @@ #define CS_MODE_MIPS64 0 #endif /* CONFIG_CAPSTONE */ + +#if CS_API_MAJOR < 5 +#define CS_ARCH_RISCV -1 +#define CS_MODE_RISCV32 0 +#define CS_MODE_RISCV64 0 +#define CS_MODE_RISCV_C 0 +#elif CS_API_MAJOR == 5 +/* The C symbol name changed between v5 and v6 */ +#define CS_MODE_RISCV_C CS_MODE_RISCVC +#endif +#if CS_API_MAJOR < 6 +#define CS_MODE_RISCV_FD 0 +#define CS_MODE_RISCV_V 0 +#define CS_MODE_RISCV_ZFINX 0 +#define CS_MODE_RISCV_ZCMP_ZCMT_ZCE 0 +#define CS_MODE_RISCV_ZICFISS 0 +#define CS_MODE_RISCV_E 0 +#define CS_MODE_RISCV_A 0 +#define CS_MODE_RISCV_COREV 0 +#define CS_MODE_RISCV_THEAD 0 +#define CS_MODE_RISCV_SIFIVE 0 +#define CS_MODE_RISCV_BITMANIP 0 +#define CS_MODE_RISCV_ZBA 0 +#define CS_MODE_RISCV_ZBB 0 +#define CS_MODE_RISCV_ZBC 0 +#define CS_MODE_RISCV_ZBKB 0 +#define CS_MODE_RISCV_ZBKC 0 +#define CS_MODE_RISCV_ZBKX 0 +#define CS_MODE_RISCV_ZBS 0 +#define CS_MODE_RISCV_VENTANA 0 +#endif + #endif /* QEMU_CAPSTONE_H */ diff --git a/disas/capstone.c b/disas/capstone.c index 8fb8d0724c..78062339d0 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -49,6 +49,20 @@ static const cs_opt_skipdata cap_skipdata_s390x = { .callback = cap_skipdata_s390x_cb }; +/* Similarly for RISCV */ +static size_t CAPSTONE_API +cap_skipdata_riscv_cb(const uint8_t *code, size_t code_size, + size_t offset, void *user_data) +{ + /* See insn_len() from target/riscv/internals.h */ + return (code[offset] & 3) == 3 ? 4 : 2; +} + +static const cs_opt_skipdata cap_skipdata_riscv = { + .mnemonic = ".byte", + .callback = cap_skipdata_riscv_cb +}; + /* * Initialize the Capstone library. * @@ -76,6 +90,11 @@ static cs_err cap_disas_start(disassemble_info *info, csh *handle) cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON); switch (info->cap_arch) { + case CS_ARCH_RISCV: + cs_option(*handle, CS_OPT_SKIPDATA_SETUP, + (uintptr_t)&cap_skipdata_riscv); + break; + case CS_ARCH_SYSZ: cs_option(*handle, CS_OPT_SKIPDATA_SETUP, (uintptr_t)&cap_skipdata_s390x); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 23b5023dd3..e73ff53159 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -39,6 +39,7 @@ #include "system/tcg.h" #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" +#include "disas/capstone.h" #if !defined(CONFIG_USER_ONLY) #include "target/riscv/tcg/debug.h" #endif @@ -1099,6 +1100,7 @@ static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info) { const RISCVCPU *cpu = RISCV_CPU(s); const CPURISCVState *env = &cpu->env; + int cap_mode; info->target_info = &cpu->cfg; @@ -1111,16 +1113,93 @@ static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info) switch (env->xl) { case MXL_RV32: info->print_insn = print_insn_riscv32; + cap_mode = CS_MODE_RISCV32; break; case MXL_RV64: info->print_insn = print_insn_riscv64; + cap_mode = CS_MODE_RISCV64; break; case MXL_RV128: info->print_insn = print_insn_riscv128; - break; + /* capstone v6 doesn't support RV128 */ + return; default: g_assert_not_reached(); } + + info->cap_arch = CS_ARCH_RISCV; + info->cap_insn_unit = 4; + info->cap_insn_split = 4; + + /* + * Capstone compresses some features together. See RISCV_getFeatureBits, + * which maps LLVM feature bits to capstone bits. + */ + if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca) { + cap_mode |= CS_MODE_RISCV_C; + } + if (riscv_has_ext(env, RVF)) { + cap_mode |= CS_MODE_RISCV_FD; + } + if (riscv_has_ext(env, RVV)) { + cap_mode |= CS_MODE_RISCV_V; + } + if (cpu->cfg.ext_zfinx || cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx) { + cap_mode |= CS_MODE_RISCV_ZFINX; + } + if (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt || cpu->cfg.ext_zce) { + cap_mode |= CS_MODE_RISCV_ZCMP_ZCMT_ZCE; + } + if (cpu->cfg.ext_zicfiss) { + cap_mode |= CS_MODE_RISCV_ZICFISS; + } + if (riscv_has_ext(env, RVE)) { + cap_mode |= CS_MODE_RISCV_E; + } + if (riscv_has_ext(env, RVA)) { + cap_mode |= CS_MODE_RISCV_A; + } + if (cpu->cfg.ext_xlrbr) { + cap_mode |= CS_MODE_RISCV_BITMANIP; + } + if (cpu->cfg.ext_zba) { + cap_mode |= CS_MODE_RISCV_ZBA; + } + if (cpu->cfg.ext_zbb) { + cap_mode |= CS_MODE_RISCV_ZBB; + } + if (cpu->cfg.ext_zbc) { + cap_mode |= CS_MODE_RISCV_ZBC; + } + if (cpu->cfg.ext_zbkb) { + cap_mode |= CS_MODE_RISCV_ZBKB; + } + if (cpu->cfg.ext_zbkc) { + cap_mode |= CS_MODE_RISCV_ZBKC; + } + if (cpu->cfg.ext_zbkx) { + cap_mode |= CS_MODE_RISCV_ZBKX; + } + if (cpu->cfg.ext_zbs) { + cap_mode |= CS_MODE_RISCV_ZBS; + } + if (cpu->cfg.ext_xtheadba || + cpu->cfg.ext_xtheadbb || + cpu->cfg.ext_xtheadbs || + cpu->cfg.ext_xtheadcmo || + cpu->cfg.ext_xtheadcondmov || + cpu->cfg.ext_xtheadfmemidx || + cpu->cfg.ext_xtheadfmv || + cpu->cfg.ext_xtheadmac || + cpu->cfg.ext_xtheadmemidx || + cpu->cfg.ext_xtheadmempair || + cpu->cfg.ext_xtheadsync) { + cap_mode |= CS_MODE_RISCV_THEAD; + } + if (cpu->cfg.ext_XVentanaCondOps) { + cap_mode |= CS_MODE_RISCV_VENTANA; + } + info->cap_mode = cap_mode; } #ifndef CONFIG_USER_ONLY -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 33/38] target/sh4: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (31 preceding siblings ...) 2026-08-18 17:01 ` [PULL 32/38] target/riscv: Enable disassembly via capstone Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 34/38] target/tricore: " Richard Henderson ` (5 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 7 +++++++ target/sh4/cpu.c | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index 5c78824da2..788f90771a 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -71,4 +71,11 @@ #define CS_MODE_RISCV_VENTANA 0 #endif +#if CS_API_MAJOR < 5 +#define CS_ARCH_SH -1 +#define CS_MODE_SHFPU 0 +#define CS_MODE_SH4 0 +#define CS_MODE_SH4A 0 +#endif + #endif /* QEMU_CAPSTONE_H */ diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ad2ec28c1b..3bbdee301d 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -28,6 +28,7 @@ #include "fpu/softfloat-helpers.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" +#include "disas/capstone.h" static void superh_cpu_set_pc(CPUState *cs, vaddr value) { @@ -167,10 +168,23 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) static void superh_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) { + const CPUSH4State *env = cpu_env((CPUState *)cpu); + info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; info->mach = bfd_mach_sh4; info->print_insn = print_insn_sh; + + info->cap_arch = CS_ARCH_SH; + info->cap_insn_unit = 2; + info->cap_insn_split = 2; + /* + * Possible capstone bug: the isa levels are not additive: + * least significant bit wins, so SH4 overrides SH4A. + * Work around by setting one or the other but not both. + */ + info->cap_mode = CS_MODE_SHFPU + | (env->features & SH_FEATURE_SH4A ? CS_MODE_SH4A : CS_MODE_SH4); } static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 34/38] target/tricore: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (32 preceding siblings ...) 2026-08-18 17:01 ` [PULL 33/38] target/sh4: " Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 35/38] target/loongarch: " Richard Henderson ` (4 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 11 +++++++++++ target/tricore/cpu.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index 788f90771a..db1abe7f70 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -78,4 +78,15 @@ #define CS_MODE_SH4A 0 #endif +#if CS_API_MAJOR < 5 +#define CS_ARCH_TRICORE -1 +#define CS_MODE_TRICORE_110 0 +#define CS_MODE_TRICORE_120 0 +#define CS_MODE_TRICORE_130 0 +#define CS_MODE_TRICORE_131 0 +#define CS_MODE_TRICORE_160 0 +#define CS_MODE_TRICORE_161 0 +#define CS_MODE_TRICORE_162 0 +#endif + #endif /* QEMU_CAPSTONE_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 96e2817dee..dcd5c5065b 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -24,6 +24,7 @@ #include "qemu/error-report.h" #include "tcg/debug-assert.h" #include "accel/tcg/cpu-ops.h" +#include "disas/capstone.h" static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -35,6 +36,35 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) return "tricore"; } +static void tricore_disas_set_info(const CPUState *cpu, disassemble_info *info) +{ + CPUTriCoreState *env = cpu_env((CPUState *)cpu); + + info->endian = BFD_ENDIAN_LITTLE; + info->cap_arch = CS_ARCH_TRICORE; + info->cap_insn_unit = 4; + info->cap_insn_split = 4; + + /* + * Possible capstone bug: the isa levels are not additive. + * Work around by settiing only one. + * Note that TriCore 1.3.0 is the earliest we support. + */ + if (tricore_has_feature(env, TRICORE_FEATURE_162)) { + info->cap_mode = CS_MODE_TRICORE_162; + } else if (tricore_has_feature(env, TRICORE_FEATURE_161)) { + info->cap_mode = CS_MODE_TRICORE_161; + } else if (tricore_has_feature(env, TRICORE_FEATURE_16)) { + info->cap_mode = CS_MODE_TRICORE_160; + } else if (tricore_has_feature(env, TRICORE_FEATURE_131)) { + info->cap_mode = CS_MODE_TRICORE_131; + } else if (tricore_has_feature(env, TRICORE_FEATURE_13)) { + info->cap_mode = CS_MODE_TRICORE_130; + } else { + g_assert_not_reached(); + } +} + static void tricore_cpu_set_pc(CPUState *cs, vaddr value) { cpu_env(cs)->PC = value & ~1; @@ -214,6 +244,7 @@ static void tricore_cpu_class_init(ObjectClass *c, const void *data) cc->gdb_write_register = tricore_cpu_gdb_write_register; cc->gdb_num_core_regs = 44; cc->gdb_arch_name = tricore_gdb_arch_name; + cc->disas_set_info = tricore_disas_set_info; cc->dump_state = tricore_cpu_dump_state; cc->set_pc = tricore_cpu_set_pc; -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 35/38] target/loongarch: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (33 preceding siblings ...) 2026-08-18 17:01 ` [PULL 34/38] target/tricore: " Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 36/38] target/s390x: Update capstone disassembly to v6 Richard Henderson ` (3 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Song Gao, Philippe Mathieu-Daudé Reviewed-by: Song Gao <17746591750@163.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 6 ++++++ target/loongarch/cpu.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index db1abe7f70..a922f7627f 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -40,6 +40,12 @@ #endif /* CONFIG_CAPSTONE */ +#if CS_API_MAJOR < 6 +#define CS_ARCH_LOONGARCH -1 +#define CS_MODE_LOONGARCH32 0 +#define CS_MODE_LOONGARCH64 0 +#endif + #if CS_API_MAJOR < 5 #define CS_ARCH_RISCV -1 #define CS_MODE_RISCV32 0 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cb07f15110..8cd5bc18a3 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,6 +29,7 @@ #include <linux/kvm.h> #endif #include "tcg/tcg_loongarch.h" +#include "disas/capstone.h" const char * const regnames[32] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", @@ -694,8 +695,15 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) static void loongarch_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { + CPULoongArchState *env = cpu_env((CPUState *)cs); + info->endian = BFD_ENDIAN_LITTLE; info->print_insn = print_insn_loongarch; + + info->cap_arch = CS_ARCH_LOONGARCH; + info->cap_insn_unit = 4; + info->cap_insn_split = 4; + info->cap_mode = is_la64(env) ? CS_MODE_LOONGARCH64 : CS_MODE_LOONGARCH32; } static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 36/38] target/s390x: Update capstone disassembly to v6 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (34 preceding siblings ...) 2026-08-18 17:01 ` [PULL 35/38] target/loongarch: " Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 37/38] target/m68k: Enable disassembly via capstone Richard Henderson ` (2 subsequent siblings) 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé In particular, this enables many more vector insns. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 11 +++++++++-- disas/capstone.c | 2 +- target/s390x/cpu.c | 4 +++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index a922f7627f..87f8f6181f 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -4,7 +4,6 @@ #ifdef CONFIG_CAPSTONE #define CAPSTONE_AARCH64_COMPAT_HEADER -#define CAPSTONE_SYSTEMZ_COMPAT_HEADER #include <capstone.h> #else @@ -19,7 +18,6 @@ #define CS_ARCH_X86 -1 #define CS_ARCH_PPC -1 #define CS_ARCH_SPARC -1 -#define CS_ARCH_SYSZ -1 #define CS_MODE_LITTLE_ENDIAN 0 #define CS_MODE_BIG_ENDIAN 0 @@ -84,6 +82,15 @@ #define CS_MODE_SH4A 0 #endif +#if CS_API_MAJOR == 0 +#define CS_ARCH_SYSTEMZ -1 +#elif CS_API_MAJOR < 6 +#define CS_ARCH_SYSTEMZ CS_ARCH_SYSZ +#endif +#if CS_API_MAJOR < 6 +#define CS_MODE_SYSTEMZ_ARCH14 0 +#endif + #if CS_API_MAJOR < 5 #define CS_ARCH_TRICORE -1 #define CS_MODE_TRICORE_110 0 diff --git a/disas/capstone.c b/disas/capstone.c index 78062339d0..a5bd91890b 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -95,7 +95,7 @@ static cs_err cap_disas_start(disassemble_info *info, csh *handle) (uintptr_t)&cap_skipdata_riscv); break; - case CS_ARCH_SYSZ: + case CS_ARCH_SYSTEMZ: cs_option(*handle, CS_OPT_SKIPDATA_SETUP, (uintptr_t)&cap_skipdata_s390x); break; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 641ea96c8e..7c725b8a4a 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -225,10 +225,12 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) static void s390_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->mach = bfd_mach_s390_64; - info->cap_arch = CS_ARCH_SYSZ; + info->cap_arch = CS_ARCH_SYSTEMZ; info->endian = BFD_ENDIAN_BIG; info->cap_insn_unit = 2; info->cap_insn_split = 6; + /* Disassemble everything, even if the cpu would trap on the insn. */ + info->cap_mode = CS_MODE_SYSTEMZ_ARCH14; } static void s390_cpu_realizefn(DeviceState *dev, Error **errp) -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 37/38] target/m68k: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (35 preceding siblings ...) 2026-08-18 17:01 ` [PULL 36/38] target/s390x: Update capstone disassembly to v6 Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-18 17:01 ` [PULL 38/38] target/mips: " Richard Henderson 2026-08-19 15:21 ` [PULL 00/38] tcg patch queue Richard Henderson 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 20 +++++++++++++ target/m68k/cpu.c | 65 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 84 insertions(+), 1 deletion(-) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index 87f8f6181f..3d6f90d816 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -14,6 +14,7 @@ #define CS_ARCH_ARM -1 #define CS_ARCH_ARM64 -1 +#define CS_ARCH_M68K -1 #define CS_ARCH_MIPS -1 #define CS_ARCH_X86 -1 #define CS_ARCH_PPC -1 @@ -28,6 +29,12 @@ #define CS_MODE_THUMB 0 #define CS_MODE_MCLASS 0 #define CS_MODE_V8 0 +#define CS_MODE_M68K_000 0 +#define CS_MODE_M68K_010 0 +#define CS_MODE_M68K_020 0 +#define CS_MODE_M68K_030 0 +#define CS_MODE_M68K_040 0 +#define CS_MODE_M68K_060 0 #define CS_MODE_MICRO 0 #define CS_MODE_MIPS3 0 #define CS_MODE_MIPS32R6 0 @@ -44,6 +51,19 @@ #define CS_MODE_LOONGARCH64 0 #endif +#if CS_API_MAJOR < 6 +#define CS_MODE_M68K_CF_ISA_A 0 +#define CS_MODE_M68K_CF_ISA_A_PLUS 0 +#define CS_MODE_M68K_CF_ISA_B 0 +#define CS_MODE_M68K_CF_ISA_C 0 +#define CS_MODE_M68K_CF_USP 0 +#define CS_MODE_M68K_CF_DIV 0 +#define CS_MODE_M68K_CF_MAC 0 +#define CS_MODE_M68K_CF_EMAC 0 +#define CS_MODE_M68K_CF_EMAC_B 0 +#define CS_MODE_M68K_CF_FPU 0 +#endif + #if CS_API_MAJOR < 5 #define CS_ARCH_RISCV -1 #define CS_MODE_RISCV32 0 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index ce2707dee5..6012dc3186 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -22,7 +22,7 @@ #include "accel/tcg/cpu-ops.h" #include "fpu/softfloat.h" #include "qapi/error.h" - +#include "disas/capstone.h" #ifndef CONFIG_USER_ONLY #include "migration/vmstate.h" #include "monitor/hmp.h" @@ -182,9 +182,72 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { + CPUM68KState *env = cpu_env((CPUState *)cs); + int cap_mode = 0; + info->print_insn = print_insn_m68k; info->endian = BFD_ENDIAN_BIG; info->mach = 0; + + /* m68k support in capstone prior to v6 is unusably bad */ + if (CS_API_MAJOR < 6) { + return; + } + + info->cap_arch = CS_ARCH_M68K; + info->cap_insn_unit = 2; + + if (m68k_feature(env, M68K_FEATURE_M68K)) { + /* + * m68k insns may have up to 11 words, and 5 words are common. + * Choosing 12 bytes splits after 6 words and disassembly + * uses no more than 2 lines. + */ + info->cap_insn_split = 12; + if (m68k_feature(env, M68K_FEATURE_M68060)) { + cap_mode = CS_MODE_M68K_060; + } else if (m68k_feature(env, M68K_FEATURE_M68040)) { + cap_mode = CS_MODE_M68K_040; + } else if (m68k_feature(env, M68K_FEATURE_M68030)) { + cap_mode = CS_MODE_M68K_030; + } else if (m68k_feature(env, M68K_FEATURE_M68020)) { + cap_mode = CS_MODE_M68K_020; + } else if (m68k_feature(env, M68K_FEATURE_M68010)) { + cap_mode = CS_MODE_M68K_010; + } else { + cap_mode = CS_MODE_M68K_000; + } + } else { + /* ColdFire insns may have up to 3 words. */ + info->cap_insn_split = 6; + if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) { + cap_mode |= CS_MODE_M68K_CF_ISA_A; + cap_mode |= CS_MODE_M68K_CF_DIV; + } + if (m68k_feature(env, M68K_FEATURE_CF_ISA_B)) { + cap_mode |= CS_MODE_M68K_CF_ISA_B; + } + if (m68k_feature(env, M68K_FEATURE_CF_ISA_APLUSC)) { + cap_mode |= CS_MODE_M68K_CF_ISA_A_PLUS; + cap_mode |= CS_MODE_M68K_CF_ISA_C; + } + if (m68k_feature(env, M68K_FEATURE_USP)) { + cap_mode |= CS_MODE_M68K_CF_USP; + } + if (m68k_feature(env, M68K_FEATURE_CF_FPU)) { + cap_mode |= CS_MODE_M68K_CF_FPU; + } + if (m68k_feature(env, M68K_FEATURE_CF_MAC)) { + cap_mode |= CS_MODE_M68K_CF_MAC; + } + if (m68k_feature(env, M68K_FEATURE_CF_EMAC)) { + cap_mode |= CS_MODE_M68K_CF_EMAC; + } + if (m68k_feature(env, M68K_FEATURE_CF_EMAC_B)) { + cap_mode |= CS_MODE_M68K_CF_EMAC_B; + } + } + info->cap_mode = cap_mode; } /* CPU models */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PULL 38/38] target/mips: Enable disassembly via capstone 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (36 preceding siblings ...) 2026-08-18 17:01 ` [PULL 37/38] target/m68k: Enable disassembly via capstone Richard Henderson @ 2026-08-18 17:01 ` Richard Henderson 2026-08-19 15:21 ` [PULL 00/38] tcg patch queue Richard Henderson 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-18 17:01 UTC (permalink / raw) To: qemu-devel; +Cc: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/disas/capstone.h | 24 ++++++++++++++-- target/mips/cpu.c | 60 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 77 insertions(+), 7 deletions(-) diff --git a/include/disas/capstone.h b/include/disas/capstone.h index 3d6f90d816..e72faf8179 100644 --- a/include/disas/capstone.h +++ b/include/disas/capstone.h @@ -29,6 +29,7 @@ #define CS_MODE_THUMB 0 #define CS_MODE_MCLASS 0 #define CS_MODE_V8 0 +#define CS_MODE_V9 0 #define CS_MODE_M68K_000 0 #define CS_MODE_M68K_010 0 #define CS_MODE_M68K_020 0 @@ -36,11 +37,10 @@ #define CS_MODE_M68K_040 0 #define CS_MODE_M68K_060 0 #define CS_MODE_MICRO 0 +#define CS_MODE_MIPS2 0 #define CS_MODE_MIPS3 0 -#define CS_MODE_MIPS32R6 0 -#define CS_MODE_MIPSGP64 0 -#define CS_MODE_V9 0 #define CS_MODE_MIPS32 0 +#define CS_MODE_MIPS32R6 0 #define CS_MODE_MIPS64 0 #endif /* CONFIG_CAPSTONE */ @@ -64,6 +64,24 @@ #define CS_MODE_M68K_CF_FPU 0 #endif +#if CS_API_MAJOR < 6 +#define CS_MODE_MIPS16 0 +#define CS_MODE_MIPS1 0 +#define CS_MODE_MIPS32R2 0 +#define CS_MODE_MIPS32R3 0 +#define CS_MODE_MIPS32R5 0 +#define CS_MODE_MIPS4 0 +#define CS_MODE_MIPS5 0 +#define CS_MODE_MIPS64R2 0 +#define CS_MODE_MIPS64R3 0 +#define CS_MODE_MIPS64R5 0 +#define CS_MODE_MIPS64R6 0 +#define CS_MODE_OCTEON 0 +#define CS_MODE_OCTEONP 0 +#define CS_MODE_NANOMIPS 0 +#define CS_MODE_MIPS_PTR64 0 +#endif + #if CS_API_MAJOR < 5 #define CS_ARCH_RISCV -1 #define CS_MODE_RISCV32 0 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 669c7d99bb..0fead20d65 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -30,6 +30,7 @@ #include "system/qtest.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-clock.h" +#include "disas/capstone.h" #include "fpu_helper.h" #ifndef CONFIG_USER_ONLY #include "semihosting/semihost.h" @@ -488,15 +489,66 @@ static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { const MIPSCPU *cpu = MIPS_CPU(cs); const CPUMIPSState *env = &cpu->env; + bool is64 = env->hflags & MIPS_HFLAG_64; + int cap_mode = 0; - if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (env->insn_flags & ISA_NANOMIPS32) { + info->print_insn = print_insn_nanomips; + info->endian = BFD_ENDIAN_LITTLE; + /* nanomips has 16, 32 and 48-bit insns */ + info->cap_insn_unit = 2; + info->cap_insn_split = 6; + cap_mode = CS_MODE_NANOMIPS; + } else { info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips : print_insn_little_mips; - } else { - info->print_insn = print_insn_nanomips; - info->endian = BFD_ENDIAN_LITTLE; + + if (env->hflags & MIPS_HFLAG_M16) { + cap_mode = (env->insn_flags & ASE_MICROMIPS + ? CS_MODE_MICRO : CS_MODE_MIPS16); + /* Beware unsupported capstone mode */ + if (cap_mode == 0) { + return; + } + info->cap_insn_unit = 2; + } else { + info->cap_insn_unit = 4; + } + info->cap_insn_split = 4; + + cap_mode |= is64 ? CS_MODE_MIPS64 : CS_MODE_MIPS32; + if (env->insn_flags & ISA_MIPS_R6) { + cap_mode |= is64 ? CS_MODE_MIPS64R6 : CS_MODE_MIPS32R6; + } else if (env->insn_flags & ISA_MIPS_R5) { + cap_mode |= is64 ? CS_MODE_MIPS64R5 : CS_MODE_MIPS32R5; + } else if (env->insn_flags & ISA_MIPS_R3) { + cap_mode |= is64 ? CS_MODE_MIPS64R3 : CS_MODE_MIPS32R3; + } else if (env->insn_flags & ISA_MIPS_R2) { + cap_mode |= is64 ? CS_MODE_MIPS64R2 : CS_MODE_MIPS32R2; + } else if (env->insn_flags & ISA_MIPS5) { + cap_mode |= CS_MODE_MIPS5; + } else if (env->insn_flags & ISA_MIPS4) { + cap_mode |= CS_MODE_MIPS4; + } else if (env->insn_flags & ISA_MIPS3) { + cap_mode |= CS_MODE_MIPS3; + } else if (env->insn_flags & ISA_MIPS2) { + cap_mode |= CS_MODE_MIPS2; + } else if (env->insn_flags & ISA_MIPS1) { + cap_mode |= CS_MODE_MIPS1; + } + if (env->insn_flags & INSN_OCTEON) { + cap_mode |= CS_MODE_OCTEON | CS_MODE_OCTEONP; + } + if (is64 && !(env->hflags & MIPS_HFLAG_AWRAP)) { + cap_mode |= CS_MODE_MIPS_PTR64; + } + } + /* Beware unsupported capstone mode */ + if (cap_mode) { + info->cap_arch = CS_ARCH_MIPS; + info->cap_mode = cap_mode; } } -- 2.43.0 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PULL 00/38] tcg patch queue 2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson ` (37 preceding siblings ...) 2026-08-18 17:01 ` [PULL 38/38] target/mips: " Richard Henderson @ 2026-08-19 15:21 ` Richard Henderson 38 siblings, 0 replies; 44+ messages in thread From: Richard Henderson @ 2026-08-19 15:21 UTC (permalink / raw) To: qemu-devel On 8/18/26 10:01, Richard Henderson wrote: > ---------------------------------------------------------------- > accel/tcg: Allow overlapping reads in record_save > tcg/optimize: INDEX_op_mul is commutative > tcg/optimize: Fix s_mask computation for shifts > tcg: Defer tb_flush when initial thread region alloc fails > tcg: Add revbit{8,32,64} opcodes > tcg: Add integer min/max opcodes > disas: Updates for capstone v6 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/11.2 as appropriate. r~ ^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2026-08-24 9:31 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-18 17:01 [PULL 00/38] tcg patch queue Richard Henderson
2026-08-18 17:01 ` [PULL 01/38] tcg/optimize: INDEX_op_mul is commutative Richard Henderson
2026-08-18 17:01 ` [PULL 02/38] tcg/optimize: Fix s_mask computation for shifts Richard Henderson
2026-08-21 16:51 ` Michael Tokarev
2026-08-21 17:33 ` Richard Henderson
2026-08-18 17:01 ` [PULL 03/38] accel/tcg: Allow overlapping reads in record_save Richard Henderson
2026-08-18 17:01 ` [PULL 04/38] tcg: Return success from tcg_region_alloc__locked Richard Henderson
2026-08-18 17:01 ` [PULL 05/38] tcg: Return success from tcg_region_alloc Richard Henderson
2026-08-18 17:01 ` [PULL 06/38] tcg: Defer tb_flush when initial thread region alloc fails Richard Henderson
2026-08-18 17:01 ` [PULL 07/38] tcg: Fix opcode dump for bswap Richard Henderson
2026-08-18 17:01 ` [PULL 08/38] tcg: Add tcg_gen_revbit{8,32,64} Richard Henderson
2026-08-18 17:01 ` [PULL 09/38] tcg: Simplify bswap/hswap expansion using bitswap Richard Henderson
2026-08-24 9:05 ` Peter Maydell
2026-08-24 9:30 ` Philippe Mathieu-Daudé
2026-08-18 17:01 ` [PULL 10/38] target/arm: Use generic tcg_gen_revbit* Richard Henderson
2026-08-18 17:01 ` [PULL 11/38] target/loongarch: " Richard Henderson
2026-08-18 17:01 ` [PULL 12/38] target/mips: Expand octeon reflections inline Richard Henderson
2026-08-18 17:01 ` [PULL 13/38] target/riscv: Use generic tcg_gen_revbit8 Richard Henderson
2026-08-18 17:01 ` [PULL 14/38] tcg: Add revbit{8,32,64} opcodes Richard Henderson
2026-08-18 17:01 ` [PULL 15/38] tcg/optimize: Handle revbit{8,32,64} Richard Henderson
2026-08-18 17:01 ` [PULL 16/38] tcg/aarch64: Implement revbit{32,64} Richard Henderson
2026-08-18 17:01 ` [PULL 17/38] tcg/loongarch64: Import REVBIT insns Richard Henderson
2026-08-18 17:01 ` [PULL 18/38] tcg/loongarch64: Implement revbit{8,32,64} Richard Henderson
2026-08-18 17:01 ` [PULL 19/38] util/cpuinfo-riscv: Detect Zbkb Richard Henderson
2026-08-18 17:01 ` [PULL 20/38] tcg/riscv64: Implement revbit8 Richard Henderson
2026-08-18 17:01 ` [PULL 21/38] tests/tcg/loongarch64: Tidy test_bit.c Richard Henderson
2026-08-18 17:01 ` [PULL 22/38] tests/tcg/loongarch64: Add bitrev smoke tests Richard Henderson
2026-08-18 17:01 ` [PULL 23/38] tcg: Add integer min/max opcodes Richard Henderson
2026-08-18 17:01 ` [PULL 24/38] tcg/optimize: Handle " Richard Henderson
2026-08-18 17:01 ` [PULL 25/38] util/cpuinfo-aarch64: Detect FEAT_CSSC Richard Henderson
2026-08-18 17:01 ` [PULL 26/38] tcg/aarch64: Implement min/max with FEAT_CSSC Richard Henderson
2026-08-18 17:01 ` [PULL 27/38] target/riscv64: Implement min/max with Zbb Richard Henderson
2026-08-18 17:01 ` [PULL 28/38] tcg/aarch64: Implement ctpop with FEAT_CSSC Richard Henderson
2026-08-18 17:01 ` [PULL 29/38] tcg/aarch64: Use CTZ from FEAT_CSSC Richard Henderson
2026-08-18 17:01 ` [PULL 30/38] target/riscv: Improve riscv_has_ext Richard Henderson
2026-08-18 17:01 ` [PULL 31/38] disas/capstone: Allow for cap_insn_unit > length Richard Henderson
2026-08-18 17:01 ` [PULL 32/38] target/riscv: Enable disassembly via capstone Richard Henderson
2026-08-18 17:01 ` [PULL 33/38] target/sh4: " Richard Henderson
2026-08-18 17:01 ` [PULL 34/38] target/tricore: " Richard Henderson
2026-08-18 17:01 ` [PULL 35/38] target/loongarch: " Richard Henderson
2026-08-18 17:01 ` [PULL 36/38] target/s390x: Update capstone disassembly to v6 Richard Henderson
2026-08-18 17:01 ` [PULL 37/38] target/m68k: Enable disassembly via capstone Richard Henderson
2026-08-18 17:01 ` [PULL 38/38] target/mips: " Richard Henderson
2026-08-19 15:21 ` [PULL 00/38] tcg patch queue Richard Henderson
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.