From: Jan Beulich <jbeulich@suse.com>
To: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
"Baptiste Le Duc" <baptiste.le-duc@vates.tech>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
xen-devel@lists.xenproject.org, "Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger@xenproject.org>,
"Stefano Stabellini" <sstabellini@kernel.org>
Subject: Re: [PATCH v1 12/17] xen/riscv: extend exception tables with type and data fields
Date: Tue, 18 Aug 2026 09:56:02 +0200 [thread overview]
Message-ID: <b8b794ec-c86a-4a82-9d3a-b3ffcaa802f3@suse.com> (raw)
In-Reply-To: <3c9ef195-a8d4-489c-8daf-5635d3b53063@gmail.com>
On 17.08.2026 13:33, Oleksii Kurochko wrote:
> On 8/12/26 4:37 PM, Jan Beulich wrote:
>> On 20.07.2026 18:02, Oleksii Kurochko wrote:
>>> @@ -60,6 +68,40 @@ static void ex_handler_fixup(const struct exception_table_entry *ex,
>>> regs->sepc = ex_fixup(ex);
>>> }
>>>
>>> +static inline unsigned long regs_get_gpr(struct cpu_user_regs *regs,
>>> + unsigned int offset)
>>> +{
>>> + /*
>>> + * The GPR number -> offset arithmetic below relies on x0..x31 being
>>> + * laid out at the start of struct cpu_user_regs in architectural
>>> + * order.
>>> + */
>>> + BUILD_BUG_ON(offsetof(struct cpu_user_regs, ra) !=
>>> + sizeof(unsigned long));
>>> + BUILD_BUG_ON(offsetof(struct cpu_user_regs, t6) !=
>>> + 31 * sizeof(unsigned long));
>>> +
>>> + if ( unlikely(!offset || (offset > MAX_REG_OFFSET)) )
>>> + return 0;
>>
>> And an offset not divisible by sizeof(unsigned long) is okay?
>
> No, it isn't okay. I will apply your comment ...
>
>>
>> Returning 0 as error indicator also feels fragile.
>
> With what I suggested below returning could be just dropped.
>
>>
>>> + return *(unsigned long *)((unsigned long)regs + offset);
>>> +}
>>> +
>>> +static void ex_handler_trap_info(const struct exception_table_entry *ex,
>>> + struct cpu_user_regs *regs)
>>> +{
>>> + struct trap_info *trap_info =
>>> + (struct trap_info *)regs_get_gpr(regs, ex->data * sizeof(unsigned long));
>>
>> Related to the earlier comment: Simply pass just ex->data here, leaving the
>> multiplication to regs_get_gpr()?
>
> ... It would be better to move the multiplication inside regs_get_gpr().
>
> Your comment made me think about whether the multiplication is needed at
> all (regardless of where it is done). In other words, ex->data contains
> the register number, so we could just write:
>
> static unsigned long regs_get_gpr(const struct cpu_user_regs *regs,
> unsigned int num)
> {
> /*
> * The GPR number -> offset arithmetic below relies on x0..x31 being
> * laid out at the start of struct cpu_user_regs in architectural
> order.
> */
> BUILD_BUG_ON(offsetof(struct cpu_user_regs, ra) != sizeof(unsigned
> long));
> BUILD_BUG_ON(offsetof(struct cpu_user_regs, t6) != 31 *
> sizeof(unsigned long));
>
> ASSERT(num && (num < 32));
>
> return ((const unsigned long *)regs)[num];
> }
>
> Probably, we want to consider this function out of context (for now
> context is that we use it to recieve a pointer to trap_info which can't
> be obviously stored in x0 as it should be always hardwired zero). In
> that case, there is no need to check that num is 0.
>
> So, it probably makes sense to just have:
> ASSERT(num < 32);
>
> ASSERT() is fine here as I don't think that compiler will use incorrect
> number during register allocation.
I agree.
However, the x0 aspect is still odd. Why again is it that struct cpu_user_regs
has a field for it, when the register value is always 0? (And tangentially,
what's the pregs field there, and what is stack_cpu_regs?)
>>> --- /dev/null
>>> +++ b/xen/arch/riscv/include/asm/gpr-num.h
>>> @@ -0,0 +1,33 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> +#ifndef RISCV_GPR_NUM_H
>>> +#define RISCV_GPR_NUM_H
>>> +
>>> +/* GPR ABI names, in register-number order (x0 .. x31). */
>>> +#define GPR_ABI_NAMES \
>>> + zero, ra, sp, gp, tp, t0, t1, t2, \
>>> + s0, s1, a0, a1, a2, a3, a4, a5, \
>>> + a6, a7, s2, s3, s4, s5, s6, s7, \
>>> + s8, s9, s10, s11, t3, t4, t5, t6
Having looked at struct cpu_user_regs for the response above: How is this
macro intended to be kept in sync with struct cpu_user_regs? Yes, the ABI
isn't going to change, but (a) still and (b) if later another ABI was
introduced, names here and fields there could still easily diverge.
>>> +#ifdef __ASSEMBLER__
>>> +
>>> + .equ .L_gpr_num, 0
>>> + .irp name, GPR_ABI_NAMES
>>> + .equ .L_gpr_num_\name, .L_gpr_num
>>> + .equ .L_gpr_num, .L_gpr_num + 1
>>> + .endr
>>
>> So this is emitted no matter whether a .S file actually uses any of the constants.
>> Perhaps okayish, but somewhat wasteful.
>
> I can move #include <asm/gpr-num.h> inside "#else /* __ASSEMBLER__ */"
> in asm/extable.h and it will be enough for now. Or just drop declaration
> of .L_gpr_num for assembler code until it will be needed by it.
How would either of these address the remark I made? Not every .S file
including asm/extable.h will need these constants. Imo this new file wants
strictly only including by files which actually need .L_gpr_num_*.
Jan
next prev parent reply other threads:[~2026-08-18 7:56 UTC|newest]
Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 16:01 [PATCH v1 00/17] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support Oleksii Kurochko
2026-07-20 16:01 ` [PATCH v1 01/17] xen/riscv: manage IRQ_DISABLED flag in APLIC irq enable/disable callbacks Oleksii Kurochko
2026-07-27 15:19 ` Jan Beulich
2026-08-10 13:32 ` Baptiste Le Duc
2026-07-20 16:02 ` [PATCH v1 02/17] xen/riscv: add basic VGEIN management for AIA guests Oleksii Kurochko
2026-07-27 15:41 ` Jan Beulich
2026-07-29 14:55 ` Oleksii Kurochko
2026-07-30 7:42 ` Jan Beulich
2026-07-30 15:46 ` Oleksii Kurochko
2026-07-30 16:03 ` Jan Beulich
2026-07-31 14:59 ` Oleksii Kurochko
2026-08-03 10:37 ` Jan Beulich
2026-08-10 13:32 ` Baptiste Le Duc
2026-08-10 15:04 ` Oleksii Kurochko
2026-08-11 8:13 ` Baptiste Le Duc
2026-07-20 16:02 ` [PATCH v1 03/17] xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h Oleksii Kurochko
2026-07-28 12:02 ` Jan Beulich
2026-07-29 15:26 ` Oleksii Kurochko
2026-07-30 7:53 ` Jan Beulich
2026-08-10 13:45 ` Baptiste Le Duc
2026-08-10 14:45 ` Oleksii Kurochko
2026-08-10 14:51 ` Baptiste Le Duc
2026-07-20 16:02 ` [PATCH v1 04/17] xen/riscv: introduce device-agnostic MMIO emulation dispatch Oleksii Kurochko
2026-07-28 12:23 ` Jan Beulich
2026-07-30 16:03 ` Oleksii Kurochko
2026-07-30 16:09 ` Jan Beulich
2026-07-31 15:24 ` Oleksii Kurochko
2026-08-03 10:41 ` Jan Beulich
2026-08-04 10:26 ` Oleksii Kurochko
2026-08-10 14:49 ` Baptiste Le Duc
2026-08-10 15:36 ` Oleksii Kurochko
2026-08-11 8:17 ` Baptiste Le Duc
2026-08-11 11:49 ` Oleksii Kurochko
2026-08-12 7:21 ` Jan Beulich
2026-08-12 7:47 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 05/17] xen/riscv: implement virtual APLIC MMIO emulation Oleksii Kurochko
2026-08-06 14:28 ` Jan Beulich
2026-08-07 16:08 ` Oleksii Kurochko
2026-08-11 9:21 ` Baptiste Le Duc
2026-08-11 14:36 ` Oleksii Kurochko
2026-08-11 15:29 ` Baptiste Le Duc
2026-08-11 16:24 ` Oleksii Kurochko
2026-08-12 9:47 ` Baptiste Le Duc
2026-08-12 10:05 ` Oleksii Kurochko
2026-08-12 9:10 ` Jan Beulich
2026-08-12 11:51 ` Oleksii Kurochko
2026-08-12 11:56 ` Jan Beulich
2026-08-12 14:03 ` Baptiste Le Duc
2026-08-12 15:59 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 06/17] xen/riscv: map IMSIC interrupt file for vCPUs Oleksii Kurochko
2026-08-06 14:48 ` Jan Beulich
2026-08-10 8:50 ` Oleksii Kurochko
2026-08-12 9:16 ` Jan Beulich
2026-08-13 9:06 ` Baptiste Le Duc
2026-08-13 9:42 ` Oleksii Kurochko
2026-08-13 9:49 ` Baptiste Le Duc
2026-08-13 9:56 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 07/17] xen/riscv: introduce vCPU AIA initialization Oleksii Kurochko
2026-08-06 14:56 ` Jan Beulich
2026-08-10 10:01 ` Oleksii Kurochko
2026-08-13 9:24 ` Baptiste Le Duc
2026-08-13 9:31 ` Oleksii Kurochko
2026-08-13 9:47 ` Jan Beulich
2026-08-13 11:35 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 08/17] xen/riscv: add IMSIC state save/restore Oleksii Kurochko
2026-08-12 13:57 ` Jan Beulich
2026-08-17 9:23 ` Oleksii Kurochko
2026-08-13 9:30 ` Baptiste Le Duc
2026-08-13 9:34 ` Oleksii Kurochko
2026-08-13 9:51 ` Jan Beulich
2026-08-13 10:22 ` Oleksii Kurochko
2026-08-13 10:44 ` Jan Beulich
2026-08-13 10:56 ` Oleksii Kurochko
2026-08-13 11:04 ` Jan Beulich
2026-07-20 16:02 ` [PATCH v1 09/17] xen/riscv: add helper to check APLIC MSI mode Oleksii Kurochko
2026-08-12 14:08 ` Jan Beulich
2026-08-13 9:34 ` Baptiste Le Duc
2026-07-20 16:02 ` [PATCH v1 10/17] xen/riscv: introduce vintc_state_{save,restore}() Oleksii Kurochko
2026-08-12 14:13 ` Jan Beulich
2026-08-13 9:42 ` Baptiste Le Duc
2026-08-17 8:31 ` Oleksii Kurochko
2026-08-18 8:28 ` Baptiste Le Duc
2026-08-18 8:31 ` Jan Beulich
2026-08-18 8:40 ` Baptiste Le Duc
2026-07-20 16:02 ` [PATCH v1 11/17] xen/riscv: add vAPLIC state save/restore hooks Oleksii Kurochko
2026-08-12 14:19 ` Jan Beulich
2026-08-17 8:43 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 12/17] xen/riscv: extend exception tables with type and data fields Oleksii Kurochko
2026-08-12 14:37 ` Jan Beulich
2026-08-17 11:33 ` Oleksii Kurochko
2026-08-17 11:39 ` Oleksii Kurochko
2026-08-18 7:58 ` Jan Beulich
2026-08-18 8:17 ` Oleksii Kurochko
2026-08-18 7:56 ` Jan Beulich [this message]
2026-08-18 9:14 ` Oleksii Kurochko
2026-08-18 9:26 ` Jan Beulich
2026-08-18 9:40 ` Oleksii Kurochko
2026-08-18 10:30 ` Jan Beulich
2026-07-20 16:02 ` [PATCH v1 13/17] xen/riscv: add unprivileged guest memory read helper Oleksii Kurochko
2026-08-12 15:30 ` Jan Beulich
2026-08-17 15:36 ` Oleksii Kurochko
2026-08-18 8:17 ` Jan Beulich
2026-08-18 10:27 ` Oleksii Kurochko
2026-08-18 10:43 ` Jan Beulich
2026-08-18 13:38 ` Oleksii Kurochko
2026-08-18 14:16 ` Jan Beulich
2026-07-20 16:02 ` [PATCH v1 14/17] xen/riscv: add guest page fault handling stub Oleksii Kurochko
2026-08-12 15:48 ` Jan Beulich
2026-08-17 16:10 ` Oleksii Kurochko
2026-08-18 8:29 ` Jan Beulich
2026-08-18 16:04 ` Oleksii Kurochko
2026-08-19 8:59 ` Oleksii Kurochko
2026-08-19 9:52 ` Jan Beulich
2026-08-19 9:58 ` Oleksii Kurochko
2026-07-20 16:02 ` [PATCH v1 15/17] xen/riscv: implement trap redirection to a guest Oleksii Kurochko
2026-08-12 16:03 ` Jan Beulich
2026-08-18 7:47 ` Oleksii Kurochko
2026-08-18 8:35 ` Jan Beulich
2026-07-27 15:21 ` [PATCH v1 00/17] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support Jan Beulich
2026-07-29 13:41 ` Oleksii Kurochko
2026-07-29 13:40 ` [PATCH v1 16/17] xen/riscv: add guest load emulation for trapped MMIO accesses Oleksii Kurochko
2026-08-13 7:15 ` Jan Beulich
2026-08-13 7:28 ` Jan Beulich
2026-08-19 11:00 ` Oleksii Kurochko
2026-07-29 13:40 ` [PATCH v1 17/17] xen/riscv: add guest store " Oleksii Kurochko
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