Re: [RFC v5 28/28] [NOT-MERGE] hw/arm/smmuv3: temporarily enable SEL2 bit and some other features

[Tao Tang <tangtao1634@phytium.com.cn>]

Hi Eric,

On 2026/8/31 16:54, Eric Auger wrote:
> Hi Tao,
>
> On 8/13/26 6:26 PM, Tao Tang wrote:
>> Temporarily:
>> - enable S_IDR1.SEL2,
>> - change AIDR to 0x2 to indicate SMMUv3.2,
>> - use smaller SID size and Cmd/Evt queue size.
> Each of those changes shall be carefully justified.
>
> Weren't there any assumpion in previous patches that we supported 3.2.
> tbh I did not notice you changed it in the last patch. wrt that change
> we would need to be careful the 3.2 does not require us to implement new
> features besides secure stuff.


You are right.  The cover letter explains that this is a Hafnium 
bring-up patch, but the patch itself does not explain why each override 
is needed.

These overrides are only intended to let Hafnium reach the Secure-bank 
MMIO access test.  They do not mean that QEMU implements Secure stage 2 
or the complete SMMUv3.2 architecture. We should even drop this patch 
when we test DMA translation with iommu-testdev [1]

[1]: 
https://gitlab.com/TaoTang/qemu/-/commits/integration/secure-smmu-v5-qtest

I will document these individual constraints in the commit message and 
keep this patch outside the final mergeable series.

Best regards,
Tao


>
> Thanks
>
> Eric
>> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
>> ---
>>   hw/arm/smmuv3.c                | 3 ++-
>>   include/hw/arm/smmuv3-common.h | 6 +++---
>>   2 files changed, 5 insertions(+), 4 deletions(-)
>>
>>