Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers

[Dmitry Baryshkov <dmitry.baryshkov@linaro.org>]

On 26/10/2022 17:31, Manivannan Sadhasivam wrote:
> On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote:
>> On 10/09/2022 09:38, Manivannan Sadhasivam wrote:
>>> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
>>> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
>>> and QPHY_V5_PCS_EQ_CONFIG3.
>>>
>>> This causes high latency when ASPM is enabled, so fix it!
>>
>> I have checked against vendor's tree [1]. The registers in question have
>> offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS
>> region base for the PCIe PHY1. Thus the correct offsets for the table are
>> 0x1e0/0x1e4.
>>
>> There might be a mistake in the name of the register, but the address
>> corresponds to the address in the vendor's tree.
>>
> 
> Right. Only the register name is wrong and I've got the offset wrong here.
> But the actual latency issue is fixed by clearing the
> QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space.

Please, don't use v4 register names in v5.2 tables. If the register 
matches, could you please add corresponding define?

> 
> I will check with Qcom on this behaviour and post v2 with register name fix.
> 
> Thanks,
> Mani
> 
>> [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520
>>
>>>
>>> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> ---
>>>    drivers/phy/qualcomm/phy-qcom-qmp-pcie.c   | 4 ++--
>>>    drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
>>>    2 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> index 4648467d5cac..b508903d77d0 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
>>>    };
>>>    static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
>>> -	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
>>> -	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
>>> +	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
>>> +	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
>>>    	QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
>>>    	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
>>>    };
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> index 61a44519f969..cca6455ec98c 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> @@ -11,7 +11,7 @@
>>>    #define QPHY_V5_PCS_G3S2_PRE_GAIN			0x170
>>>    #define QPHY_V5_PCS_RX_SIGDET_LVL			0x188
>>>    #define QPHY_V5_PCS_RATE_SLEW_CNTRL1			0x198
>>> -#define QPHY_V5_PCS_EQ_CONFIG2				0x1e0
>>> -#define QPHY_V5_PCS_EQ_CONFIG3				0x1e4
>>> +#define QPHY_V5_PCS_EQ_CONFIG4				0x2e0
>>> +#define QPHY_V5_PCS_EQ_CONFIG5				0x2e4
>>>    #endif
-- 
With best wishes
Dmitry