[PATCH 0/2] drm/amd/display: stabilize DCN35 ODM and DSC sequencing

[PATCH 0/2] drm/amd/display: stabilize DCN35 ODM and DSC sequencing

[Mauricio Bellon]

From: Mauricio Bellon <mbellon@lenovo.com>

Two related direct DisplayPort failures occur on DCN35 with a
high-refresh DSC stream using two-way ODM. A normal transition from
4K120 to 4K144 can commit successfully but produce no visible output.
After 4K144 is working, a long-pulse hotplug can reconstruct the same
stream but leave the monitor black.

The first patch stabilizes the DCN35 ODM update. It exposes the missing
ODM double-buffer pending-clear callback, keeps the horizontal timing
divider under manual control while programming the ODM topology, waits
for the update to complete, and restores the timing-derived target
manual mode.

The second patch enables sink DSC before source DSC in the DPMS-on
pre-enable path and removes the later redundant sink DSC enablement.

The complete series was built and booted as
7.1.0-bellon18-amd-final+ on a Lenovo ThinkPad X13 Gen 6 AMD with a
Krackan Point Radeon 840M and Corsair Xeneon 32UHD144 connected directly
through USB-C DP Alt Mode SST.

The following scenarios all produced stable visible output:

- 4K144 initial modeset
- 4K120 to 4K144
- 4K144 to 4K120 to 4K144
- 4K144 long-pulse unplug/replug
- repeated 4K144 unplug/replug cycles

This series covers the direct-SST modeset and hotplug reconstruction
failures. It does not claim to address the separate DPIA/MST warning
observed through the USB4 dock.

The commits retain my Lenovo author and Signed-off-by address. This
submission is sent through my personal Gmail account because Lenovo
email is not compatible with git send-email.

Bug report:
https://gitlab.freedesktop.org/drm/amd/-/issues/5033

Mauricio Bellon (2):
  drm/amd/display: stabilize DCN35 ODM update sequencing
  drm/amd/display: enable sink DSC before source DSC

 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 20 +++++++++++++++++--
 .../gpu/drm/amd/display/dc/link/link_dpms.c   |  5 +++--
 .../amd/display/dc/optc/dcn35/dcn35_optc.c    |  2 ++
 3 files changed, 23 insertions(+), 4 deletions(-)


base-commit: 232bf7d5453df6cc0d877a1003f9aa172e9750de
-- 
2.53.0

[PATCH 1/2] drm/amd/display: stabilize DCN35 ODM update sequencing

[Mauricio Bellon]

From: Mauricio Bellon <mbellon@lenovo.com>

Two related direct DisplayPort failures occur with a high-refresh DSC
stream using two-way ODM on DCN35. A normal transition from 4K120 to
4K144 can commit successfully but produce no visible output. After 4K144
is working, a long-pulse hotplug can reconstruct the same DSC/ODM stream
but leave the monitor black.

The horizontal timing divider changes together with the ODM topology.
DCN35 does not expose wait_odm_doublebuffer_pending_clear(), so the
common completion path can continue before the divider update has
latched. Hook up the compatible DCN32 wait implementation and wait
immediately after dcn35_update_odm() programs combine or bypass.

Keep the divider under manual control while changing the ODM topology.
After the pending update completes, restore manual mode explicitly from
the target stream using the same FRL, horizontal-timing divisibility, and
virtual-signal policy as stream timing setup. Keep that restoration
separate from hwss_wait_for_odm_update_pending_complete() so the wait
helper remains limited to waiting for hardware updates.

The affected 4K144 timing has odd horizontal blank boundaries and
requires manual divider mode, while the 4K120 timing is divisible by two
and uses automatic mode. The ODM combine and bypass functions explicitly
program OTG_H_TIMING_DIV_MODE before completion.

Cc: stable@vger.kernel.org
Signed-off-by: Mauricio Bellon <mbellon@lenovo.com>
---
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 20 +++++++++++++++++--
 .../amd/display/dc/optc/dcn35/dcn35_optc.c    |  2 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 6e1079377..a5b914b81 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -433,18 +433,30 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 {
 	(void)context;
 	struct pipe_ctx *odm_pipe;
+	struct pipe_ctx *current_pipe_ctx =
+		&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 	int opp_cnt = 0;
 	int opp_inst[MAX_PIPES] = {0};
 	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
 	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
 	struct mpc *mpc = dc->res_pool->mpc;
+	bool target_manual_mode;
+	bool update_odm;
 	int i;
 
 	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
+	update_odm = opp_cnt > 1 || current_pipe_ctx->next_odm_pipe;
+	target_manual_mode = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||
+		!is_h_timing_divisible_by_2(pipe_ctx->stream) ||
+		dc_is_virtual_signal(pipe_ctx->stream->signal);
 
 	if (!(pipe_ctx->stream_res.hpo_frl_stream_enc &&
 			pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_fifo_odm_enabled &&
 			pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_fifo_odm_enabled(pipe_ctx->stream_res.hpo_frl_stream_enc))) {
+		if (update_odm && tg->funcs->set_h_timing_div_manual_mode)
+			tg->funcs->set_h_timing_div_manual_mode(tg, true);
+
 	if (opp_cnt > 1)
 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 				pipe_ctx->stream_res.tg,
@@ -454,6 +466,12 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 
+		if (update_odm && tg->funcs->wait_odm_doublebuffer_pending_clear)
+			tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
+
+		if (update_odm && tg->funcs->set_h_timing_div_manual_mode)
+			tg->funcs->set_h_timing_div_manual_mode(tg, target_manual_mode);
+
 	if (mpc->funcs->set_out_rate_control) {
 		for (i = 0; i < opp_cnt; ++i) {
 			mpc->funcs->set_out_rate_control(
@@ -472,8 +490,6 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 	}
 
 	if (pipe_ctx->stream_res.dsc) {
-		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
 		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
 
 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index 897f857db..c26a2fd70 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -603,6 +603,8 @@ static const struct timing_generator_funcs dcn35_tg_funcs = {
 		.set_odm_combine = optc35_set_odm_combine,
 		.get_optc_source = optc2_get_optc_source,
 		.wait_otg_disable = optc35_wait_otg_disable,
+		.wait_odm_doublebuffer_pending_clear =
+			optc32_wait_odm_doublebuffer_pending_clear,
 		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
 		.set_out_mux = optc3_set_out_mux,
 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
-- 
2.53.0

[PATCH 2/2] drm/amd/display: enable sink DSC before source DSC

[Mauricio Bellon]

From: Mauricio Bellon <mbellon@lenovo.com>

Direct DisplayPort high-refresh modes using DSC and two-way ODM can
commit without visible output during a 4K120-to-4K144 transition. A
working 4K144 stream can also return black after long-pulse hotplug
reconstruction.

The DPMS-on path currently enables source DSC before link enablement but
does not enable sink DSC until after the source stream is enabled. This
leaves the sink and source compression state ordered differently while
the stream is brought up.

Enable sink DSC immediately before source DSC in the pre-enable phase,
and remove the later redundant sink-enable operation near PPS packet
programming. This establishes the order as sink DSC, source DSC, stream
enablement, and PPS before the compressed stream becomes visible.

Cc: stable@vger.kernel.org
Signed-off-by: Mauricio Bellon <mbellon@lenovo.com>
---
 drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 48b086d15..412ce52b3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2635,8 +2635,10 @@ static enum dc_status link_set_dpms_on_pre_enable_link(
 	 */
 	if (stream->timing.flags.DSC) {
 		if (dc_is_dp_signal(stream->signal) ||
-			dc_is_virtual_signal(stream->signal))
+			dc_is_virtual_signal(stream->signal)) {
+			dp_set_dsc_on_rx(pipe_ctx, true);
 			link_set_dsc_enable(pipe_ctx, true);
+		}
 	}
 
 	if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal))
@@ -2729,7 +2731,6 @@ static enum dc_status link_set_dpms_on_post_enable_link(
 	if (stream->timing.flags.DSC) {
 		if (dc_is_dp_signal(stream->signal) ||
 				dc_is_virtual_signal(stream->signal)) {
-			dp_set_dsc_on_rx(pipe_ctx, true);
 			link_set_dsc_pps_packet(pipe_ctx, true, true);
 		}
 	}
-- 
2.53.0

Re: [PATCH 0/2] drm/amd/display: stabilize DCN35 ODM and DSC sequencing

[Mario Limonciello]

On 8/25/26 4:18 PM, Mauricio Bellon wrote:
> From: Mauricio Bellon <mbellon@lenovo.com>
> 
> Two related direct DisplayPort failures occur on DCN35 with a
> high-refresh DSC stream using two-way ODM. A normal transition from
> 4K120 to 4K144 can commit successfully but produce no visible output.
> After 4K144 is working, a long-pulse hotplug can reconstruct the same
> stream but leave the monitor black.
> 
> The first patch stabilizes the DCN35 ODM update. It exposes the missing
> ODM double-buffer pending-clear callback, keeps the horizontal timing
> divider under manual control while programming the ODM topology, waits
> for the update to complete, and restores the timing-derived target
> manual mode.
> 
> The second patch enables sink DSC before source DSC in the DPMS-on
> pre-enable path and removes the later redundant sink DSC enablement.
> 
> The complete series was built and booted as
> 7.1.0-bellon18-amd-final+ on a Lenovo ThinkPad X13 Gen 6 AMD with a
> Krackan Point Radeon 840M and Corsair Xeneon 32UHD144 connected directly
> through USB-C DP Alt Mode SST.
> 
> The following scenarios all produced stable visible output:
> 
> - 4K144 initial modeset
> - 4K120 to 4K144
> - 4K144 to 4K120 to 4K144
> - 4K144 long-pulse unplug/replug
> - repeated 4K144 unplug/replug cycles
> 
> This series covers the direct-SST modeset and hotplug reconstruction
> failures. It does not claim to address the separate DPIA/MST warning
> observed through the USB4 dock.
> 
> The commits retain my Lenovo author and Signed-off-by address. This
> submission is sent through my personal Gmail account because Lenovo
> email is not compatible with git send-email.
> 
> Bug report:
> https://gitlab.freedesktop.org/drm/amd/-/issues/5033

Thanks for the submission.  If there ends up being any changes to it, I 
would suggest adding to both the code commits:

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5033

No need to spin for now, whoever reviews and accepts this can add that 
when committing.

> 
> Mauricio Bellon (2):
>    drm/amd/display: stabilize DCN35 ODM update sequencing
>    drm/amd/display: enable sink DSC before source DSC
> 
>   .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 20 +++++++++++++++++--
>   .../gpu/drm/amd/display/dc/link/link_dpms.c   |  5 +++--
>   .../amd/display/dc/optc/dcn35/dcn35_optc.c    |  2 ++
>   3 files changed, 23 insertions(+), 4 deletions(-)
> 
> 
> base-commit: 232bf7d5453df6cc0d877a1003f9aa172e9750de

RE: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC

[Zuo, Jerry]

AMD General

Hi Mauricio:

     This change breaks dsc, causing black screen.

     Sink RX dsc enable should land after link training. Writing dsc enable to the RX on an untrained link is too early, that should be done after training. That is likely to be the main sequence regression.

Regards,
Jerry

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Mauricio Bellon
> Sent: Tuesday, August 25, 2026 17:18
> To: amd-gfx@lists.freedesktop.org
> Cc: Lin, Wayne <Wayne.Lin@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Mauricio Bellon <mbellon@lenovo.com>;
> Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo)
> <Sunpeng.Li@amd.com>; Rodrigo Siqueira <siqueira@igalia.com>; Deucher,
> Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; stable@vger.kernel.org
> Subject: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC
>
> [Some people who received this message don't often get email from
> mauriciobellon@gmail.com. Learn why this is important at
> https://aka.ms/LearnAboutSenderIdentification ]
>
> From: Mauricio Bellon <mbellon@lenovo.com>
>
> Direct DisplayPort high-refresh modes using DSC and two-way ODM can
> commit without visible output during a 4K120-to-4K144 transition. A working
> 4K144 stream can also return black after long-pulse hotplug reconstruction.
>
> The DPMS-on path currently enables source DSC before link enablement but
> does not enable sink DSC until after the source stream is enabled. This leaves
> the sink and source compression state ordered differently while the stream is
> brought up.
>
> Enable sink DSC immediately before source DSC in the pre-enable phase, and
> remove the later redundant sink-enable operation near PPS packet
> programming. This establishes the order as sink DSC, source DSC, stream
> enablement, and PPS before the compressed stream becomes visible.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Mauricio Bellon <mbellon@lenovo.com>
> ---
>  drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> index 48b086d15..412ce52b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> @@ -2635,8 +2635,10 @@ static enum dc_status
> link_set_dpms_on_pre_enable_link(
>          */
>         if (stream->timing.flags.DSC) {
>                 if (dc_is_dp_signal(stream->signal) ||
> -                       dc_is_virtual_signal(stream->signal))
> +                       dc_is_virtual_signal(stream->signal)) {
> +                       dp_set_dsc_on_rx(pipe_ctx, true);
>                         link_set_dsc_enable(pipe_ctx, true);
> +               }
>         }
>
>         if (link->replay_settings.config.replay_supported
> && !dc_is_embedded_signal(link->connector_signal))
> @@ -2729,7 +2731,6 @@ static enum dc_status
> link_set_dpms_on_post_enable_link(
>         if (stream->timing.flags.DSC) {
>                 if (dc_is_dp_signal(stream->signal) ||
>                                 dc_is_virtual_signal(stream->signal)) {
> -                       dp_set_dsc_on_rx(pipe_ctx, true);
>                         link_set_dsc_pps_packet(pipe_ctx, true, true);
>                 }
>         }
> --
> 2.53.0

Re: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC

[Mauricio Bellon]

Hi Jerry,

Thanks for catching that, you're right.

I went back through the sequence and confirmed that my new
dp_set_dsc_on_rx() call runs in the pre-enable phase, before
enable_link() performs DP link training. I had mixed up the requirement
to configure source-side DSC before link setup with the separate
requirement to enable DSC on the sink only after training.

It happened to work with the X13 and monitor I tested, including the
hotplug cases, but that clearly doesn't make the ordering safe for other
sinks. I won't keep patch 2 in its current form.

Would the right place for dp_set_dsc_on_rx() be at the start of the
post-enable phase, after link training but before
hwss->enable_stream()? Or should it stay in its current location after
hwss->enable_stream()?

I'll wait for your guidance on the intended placement before sending a
revision. Patch 1 should be independent of this sink DSC ordering change.

Thanks,
Mauricio


Em ter., 8 de set. de 2026 às 15:14, Zuo, Jerry <Jerry.Zuo@amd.com> escreveu:
>
> AMD General
>
> Hi Mauricio:
>
>      This change breaks dsc, causing black screen.
>
>      Sink RX dsc enable should land after link training. Writing dsc enable to the RX on an untrained link is too early, that should be done after training. That is likely to be the main sequence regression.
>
> Regards,
> Jerry
>
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Mauricio Bellon
> > Sent: Tuesday, August 25, 2026 17:18
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Lin, Wayne <Wayne.Lin@amd.com>; Limonciello, Mario
> > <Mario.Limonciello@amd.com>; Mauricio Bellon <mbellon@lenovo.com>;
> > Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo)
> > <Sunpeng.Li@amd.com>; Rodrigo Siqueira <siqueira@igalia.com>; Deucher,
> > Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> > <Christian.Koenig@amd.com>; stable@vger.kernel.org
> > Subject: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC
> >
> > [Some people who received this message don't often get email from
> > mauriciobellon@gmail.com. Learn why this is important at
> > https://aka.ms/LearnAboutSenderIdentification ]
> >
> > From: Mauricio Bellon <mbellon@lenovo.com>
> >
> > Direct DisplayPort high-refresh modes using DSC and two-way ODM can
> > commit without visible output during a 4K120-to-4K144 transition. A working
> > 4K144 stream can also return black after long-pulse hotplug reconstruction.
> >
> > The DPMS-on path currently enables source DSC before link enablement but
> > does not enable sink DSC until after the source stream is enabled. This leaves
> > the sink and source compression state ordered differently while the stream is
> > brought up.
> >
> > Enable sink DSC immediately before source DSC in the pre-enable phase, and
> > remove the later redundant sink-enable operation near PPS packet
> > programming. This establishes the order as sink DSC, source DSC, stream
> > enablement, and PPS before the compressed stream becomes visible.
> >
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Mauricio Bellon <mbellon@lenovo.com>
> > ---
> >  drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > index 48b086d15..412ce52b3 100644
> > --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > @@ -2635,8 +2635,10 @@ static enum dc_status
> > link_set_dpms_on_pre_enable_link(
> >          */
> >         if (stream->timing.flags.DSC) {
> >                 if (dc_is_dp_signal(stream->signal) ||
> > -                       dc_is_virtual_signal(stream->signal))
> > +                       dc_is_virtual_signal(stream->signal)) {
> > +                       dp_set_dsc_on_rx(pipe_ctx, true);
> >                         link_set_dsc_enable(pipe_ctx, true);
> > +               }
> >         }
> >
> >         if (link->replay_settings.config.replay_supported
> > && !dc_is_embedded_signal(link->connector_signal))
> > @@ -2729,7 +2731,6 @@ static enum dc_status
> > link_set_dpms_on_post_enable_link(
> >         if (stream->timing.flags.DSC) {
> >                 if (dc_is_dp_signal(stream->signal) ||
> >                                 dc_is_virtual_signal(stream->signal)) {
> > -                       dp_set_dsc_on_rx(pipe_ctx, true);
> >                         link_set_dsc_pps_packet(pipe_ctx, true, true);
> >                 }
> >         }
> > --
> > 2.53.0
>

Re: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC

[Mauricio Bellon]

Hi Jerry,

Just a friendly ping on the DSC ordering question below. I'm currently
blocked on this before preparing the next revision.

Thanks,
Mauricio

Em ter., 8 de set. de 2026 às 17:00, Mauricio Bellon
<mauriciobellon@gmail.com> escreveu:

>
> Hi Jerry,
>
> Thanks for catching that, you're right.
>
> I went back through the sequence and confirmed that my new
> dp_set_dsc_on_rx() call runs in the pre-enable phase, before
> enable_link() performs DP link training. I had mixed up the requirement
> to configure source-side DSC before link setup with the separate
> requirement to enable DSC on the sink only after training.
>
> It happened to work with the X13 and monitor I tested, including the
> hotplug cases, but that clearly doesn't make the ordering safe for other
> sinks. I won't keep patch 2 in its current form.
>
> Would the right place for dp_set_dsc_on_rx() be at the start of the
> post-enable phase, after link training but before
> hwss->enable_stream()? Or should it stay in its current location after
> hwss->enable_stream()?
>
> I'll wait for your guidance on the intended placement before sending a
> revision. Patch 1 should be independent of this sink DSC ordering change.
>
> Thanks,
> Mauricio
>
>
> Em ter., 8 de set. de 2026 às 15:14, Zuo, Jerry <Jerry.Zuo@amd.com> escreveu:
> >
> > AMD General
> >
> > Hi Mauricio:
> >
> >      This change breaks dsc, causing black screen.
> >
> >      Sink RX dsc enable should land after link training. Writing dsc enable to the RX on an untrained link is too early, that should be done after training. That is likely to be the main sequence regression.
> >
> > Regards,
> > Jerry
> >
> > > -----Original Message-----
> > > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > > Mauricio Bellon
> > > Sent: Tuesday, August 25, 2026 17:18
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Lin, Wayne <Wayne.Lin@amd.com>; Limonciello, Mario
> > > <Mario.Limonciello@amd.com>; Mauricio Bellon <mbellon@lenovo.com>;
> > > Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo)
> > > <Sunpeng.Li@amd.com>; Rodrigo Siqueira <siqueira@igalia.com>; Deucher,
> > > Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> > > <Christian.Koenig@amd.com>; stable@vger.kernel.org
> > > Subject: [PATCH 2/2] drm/amd/display: enable sink DSC before source DSC
> > >
> > > [Some people who received this message don't often get email from
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> > >
> > > From: Mauricio Bellon <mbellon@lenovo.com>
> > >
> > > Direct DisplayPort high-refresh modes using DSC and two-way ODM can
> > > commit without visible output during a 4K120-to-4K144 transition. A working
> > > 4K144 stream can also return black after long-pulse hotplug reconstruction.
> > >
> > > The DPMS-on path currently enables source DSC before link enablement but
> > > does not enable sink DSC until after the source stream is enabled. This leaves
> > > the sink and source compression state ordered differently while the stream is
> > > brought up.
> > >
> > > Enable sink DSC immediately before source DSC in the pre-enable phase, and
> > > remove the later redundant sink-enable operation near PPS packet
> > > programming. This establishes the order as sink DSC, source DSC, stream
> > > enablement, and PPS before the compressed stream becomes visible.
> > >
> > > Cc: stable@vger.kernel.org
> > > Signed-off-by: Mauricio Bellon <mbellon@lenovo.com>
> > > ---
> > >  drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > > b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > > index 48b086d15..412ce52b3 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> > > @@ -2635,8 +2635,10 @@ static enum dc_status
> > > link_set_dpms_on_pre_enable_link(
> > >          */
> > >         if (stream->timing.flags.DSC) {
> > >                 if (dc_is_dp_signal(stream->signal) ||
> > > -                       dc_is_virtual_signal(stream->signal))
> > > +                       dc_is_virtual_signal(stream->signal)) {
> > > +                       dp_set_dsc_on_rx(pipe_ctx, true);
> > >                         link_set_dsc_enable(pipe_ctx, true);
> > > +               }
> > >         }
> > >
> > >         if (link->replay_settings.config.replay_supported
> > > && !dc_is_embedded_signal(link->connector_signal))
> > > @@ -2729,7 +2731,6 @@ static enum dc_status
> > > link_set_dpms_on_post_enable_link(
> > >         if (stream->timing.flags.DSC) {
> > >                 if (dc_is_dp_signal(stream->signal) ||
> > >                                 dc_is_virtual_signal(stream->signal)) {
> > > -                       dp_set_dsc_on_rx(pipe_ctx, true);
> > >                         link_set_dsc_pps_packet(pipe_ctx, true, true);
> > >                 }
> > >         }
> > > --
> > > 2.53.0
> >