From: Michael Morrell <mmorrell@tachyum.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: RE: Denormal input handling
Date: Mon, 21 Jun 2021 23:13:11 +0000 [thread overview]
Message-ID: <c021f386dcfb49aca2ab0c01f66bccc2@tachyum.com> (raw)
In-Reply-To: <30eafc8be31446f9aecbc40f487467e1@tachyum.com>
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I have another couple of thoughts around input denormal handling.
The first is straightforward. I noticed that the Aarch64 port doesn't report input denormals (I could not find any code which sets the IDC bit in the FPSR). I found code in the arm (not aarch64) port that sets other bits like IXC, but nothing for IDC. Is that simply because no one has bothered to add this support?
The second concerns support for cases where multiple exception conditions occur. I had originally thought that denormal input handling would be orthogonal to everything else and so a case like "sNaN + denorm" would set both the invalid and input denormal flags or "denorm / 0" would set both idivde by zero and input denormal, but I don't think that is true for at least some architectures. Perhaps some specialization is needed here?
Michael
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next prev parent reply other threads:[~2021-06-21 23:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-26 17:37 Denormal input handling Michael Morrell
2021-05-26 20:18 ` Peter Maydell
2021-05-26 21:59 ` Michael Morrell
2021-05-27 1:14 ` Richard Henderson
2021-06-21 23:13 ` Michael Morrell [this message]
2021-06-21 23:30 ` Richard Henderson
2021-06-21 23:39 ` Michael Morrell
2021-06-22 0:57 ` Michael Morrell
2021-06-22 18:50 ` Michael Morrell
[not found] <746277332.296230.1622055775751.ref@mail.yahoo.com>
2021-05-26 19:02 ` Michael Morrell via
2021-05-26 19:23 ` Richard Henderson
2021-05-26 19:28 ` Richard Henderson
2021-05-26 19:52 ` Michael Morrell via
2021-05-26 20:15 ` Richard Henderson
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