* [PATCH 01/15] drm/i915/pfit: s/pch_pfit/pfit/
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
@ 2026-10-19 13:52 ` Ville Syrjala
2026-10-19 15:48 ` Jani Nikula
2026-10-19 13:52 ` [PATCH 02/15] drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/ Ville Syrjala
` (18 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename crtc_state->pch_fit to just crtc_state->pfit in
anticipation of using it also on GMCH platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_casf.c | 28 ++++++-------
.../drm/i915/display/intel_crtc_state_dump.c | 14 +++----
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +--
drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++---------
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_pfit.c | 18 ++++-----
drivers/gpu/drm/i915/display/skl_scaler.c | 40 +++++++++----------
7 files changed, 73 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index cafd21a03632..64d99d6480ac 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -81,11 +81,11 @@ static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
u32 total_pixels = mode->hdisplay * mode->vdisplay;
if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
- crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3;
+ crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3;
else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
- crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5;
+ crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5;
else
- crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7;
+ crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7;
}
static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state);
@@ -103,7 +103,7 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
return -EINVAL;
}
- crtc_state->pch_pfit.casf.enable = true;
+ crtc_state->pfit.casf.enable = true;
/*
* HW takes a value in form (1.0 + strength) in 4.4 fixed format.
@@ -113,7 +113,7 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
* 6.3125 in 4.4 format is b01100101 which is equal to 101.
* Also 85 + 16 = 101.
*/
- crtc_state->pch_pfit.casf.strength =
+ crtc_state->pfit.casf.strength =
min(crtc_state->hw.sharpness_strength, 0xEF) + 0x10;
intel_casf_compute_win_size(crtc_state);
@@ -133,12 +133,12 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
if (sharp & FILTER_EN) {
if (drm_WARN_ON(display->drm,
REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
- crtc_state->pch_pfit.casf.strength = 0;
+ crtc_state->pfit.casf.strength = 0;
else
- crtc_state->pch_pfit.casf.strength =
+ crtc_state->pfit.casf.strength =
REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
- crtc_state->pch_pfit.casf.enable = true;
- crtc_state->pch_pfit.casf.win_size =
+ crtc_state->pfit.casf.enable = true;
+ crtc_state->pfit.casf.win_size =
REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
}
}
@@ -153,7 +153,7 @@ static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int tap)
struct scaler_filter_coeff value;
u32 coeff;
- value = crtc_state->pch_pfit.casf.coeff[tap];
+ value = crtc_state->pfit.casf.coeff[tap];
value.sign = 0;
coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3;
@@ -163,7 +163,7 @@ static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int tap)
/*
* 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
* To enable casf: program scaler coefficients with the coefficients
- * that are calculated and stored in pch_pfit.casf.coeff as per
+ * that are calculated and stored in pfit.casf.coeff as per
* SCALER_COEFFICIENT_FORMAT
*/
static void intel_casf_write_coeff(const struct intel_crtc_state *crtc_state)
@@ -221,9 +221,9 @@ static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state)
u16 sum_coeff = 0;
int i;
- if (crtc_state->pch_pfit.casf.win_size == 0)
+ if (crtc_state->pfit.casf.win_size == 0)
filtercoeff = filtercoeff_1;
- else if (crtc_state->pch_pfit.casf.win_size == 1)
+ else if (crtc_state->pfit.casf.win_size == 1)
filtercoeff = filtercoeff_2;
else
filtercoeff = filtercoeff_3;
@@ -233,7 +233,7 @@ static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state)
for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) {
filter_coeff[i] = (*(filtercoeff + i) * 100 / sum_coeff);
- convert_sharpness_coeff_binary(&crtc_state->pch_pfit.casf.coeff[i],
+ convert_sharpness_coeff_binary(&crtc_state->pfit.casf.coeff[i],
filter_coeff[i]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 92675a88b969..f30d07bc6b07 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -356,15 +356,15 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
pipe_config->gmch_pfit.pgm_ratios,
pipe_config->gmch_pfit.lvds_border_bits);
else
- drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
- DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
- str_enabled_disabled(pipe_config->pch_pfit.enabled),
- str_yes_no(pipe_config->pch_pfit.force_thru));
+ drm_printf(&p, "pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+ DRM_RECT_ARG(&pipe_config->pfit.dst),
+ str_enabled_disabled(pipe_config->pfit.enabled),
+ str_yes_no(pipe_config->pfit.force_thru));
drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
- pipe_config->pch_pfit.casf.strength,
- pipe_config->pch_pfit.casf.win_size,
- pipe_config->pch_pfit.casf.enable);
+ pipe_config->pfit.casf.strength,
+ pipe_config->pfit.casf.win_size,
+ pipe_config->pfit.casf.enable);
drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n",
pipe_config->ips_enabled, pipe_config->double_wide,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70f..2c09fccecbbf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -562,7 +562,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
* eDP when not using the panel fitter, and when not
* using motion blur mitigation (which we don't
* support). */
- if (crtc_state->pch_pfit.force_thru)
+ if (crtc_state->pfit.force_thru)
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
else
temp |= TRANS_DDI_EDP_INPUT_A_ON;
@@ -4560,8 +4560,8 @@ static int intel_ddi_compute_config(struct intel_atomic_state *state,
if (display->platform.haswell && crtc->pipe == PIPE_A &&
pipe_config->cpu_transcoder == TRANSCODER_EDP)
- pipe_config->pch_pfit.force_thru =
- pipe_config->pch_pfit.enabled ||
+ pipe_config->pfit.force_thru =
+ pipe_config->pfit.enabled ||
pipe_config->crc_enabled;
if (display->platform.geminilake || display->platform.broxton)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5d4453f283b..723dec35402a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1130,7 +1130,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
intel_encoders_audio_enable(state, crtc);
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117)) {
- if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
+ if (old_crtc_state->pfit.enabled != new_crtc_state->pfit.enabled)
adl_scaler_ecc_unmask(new_crtc_state);
}
@@ -1652,7 +1652,7 @@ static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_
{
struct intel_display *display = to_intel_display(crtc_state);
- return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
+ return DISPLAY_VER(display) == 10 && crtc_state->pfit.enabled;
}
static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
@@ -2052,8 +2052,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
- if (crtc_state->pch_pfit.enabled ||
- crtc_state->pch_pfit.force_thru)
+ if (crtc_state->pfit.enabled ||
+ crtc_state->pfit.force_thru)
set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
drm_for_each_encoder_mask(encoder, display->drm,
@@ -2288,14 +2288,14 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
* PF-ID we'll need to adjust the pixel_rate here.
*/
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pfit.enabled)
return pixel_rate;
drm_rect_init(&src, 0, 0,
drm_rect_width(&crtc_state->pipe_src) << 16,
drm_rect_height(&crtc_state->pipe_src) << 16);
- return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
+ return intel_adjusted_rate(&src, &crtc_state->pfit.dst,
pixel_rate);
}
@@ -2311,14 +2311,14 @@ static u32 ilk_pipe_pixel_rate_cdclk(const struct intel_crtc_state *crtc_state)
* PF-ID we'll need to adjust the pixel_rate here.
*/
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pfit.enabled)
return pixel_rate;
drm_rect_init(&src, 0, 0,
drm_rect_width(&crtc_state->pipe_src) << 16,
drm_rect_height(&crtc_state->pipe_src) << 16);
- return intel_adjusted_rate_cdclk(&src, &crtc_state->pch_pfit.dst,
+ return intel_adjusted_rate_cdclk(&src, &crtc_state->pfit.dst,
pixel_rate, ppc);
}
@@ -4012,7 +4012,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
- pipe_config->pch_pfit.force_thru = true;
+ pipe_config->pfit.force_thru = true;
}
tmp = intel_de_read(display,
@@ -5475,16 +5475,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
* Changing the EDP transcoder input mux
* (A_ONOFF vs. A_ON) requires a full modeset.
*/
- PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
+ PIPE_CONF_CHECK_BOOL(pfit.force_thru);
if (!fastset) {
PIPE_CONF_CHECK_RECT(pipe_src);
- PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
- PIPE_CONF_CHECK_RECT(pch_pfit.dst);
- PIPE_CONF_CHECK_BOOL(pch_pfit.casf.enable);
- PIPE_CONF_CHECK_I(pch_pfit.casf.win_size);
- PIPE_CONF_CHECK_I(pch_pfit.casf.strength);
+ PIPE_CONF_CHECK_BOOL(pfit.enabled);
+ PIPE_CONF_CHECK_RECT(pfit.dst);
+ PIPE_CONF_CHECK_BOOL(pfit.casf.enable);
+ PIPE_CONF_CHECK_I(pfit.casf.win_size);
+ PIPE_CONF_CHECK_I(pfit.casf.strength);
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
PIPE_CONF_CHECK_I(pixel_rate_cdclk);
@@ -6775,12 +6775,12 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
/* on skylake this is done by detaching scalers */
if (DISPLAY_VER(display) >= 9) {
- if (new_crtc_state->pch_pfit.enabled)
+ if (new_crtc_state->pfit.enabled)
skl_pfit_enable(new_crtc_state);
} else if (HAS_PCH_SPLIT(display)) {
- if (new_crtc_state->pch_pfit.enabled)
+ if (new_crtc_state->pfit.enabled)
ilk_pfit_enable(new_crtc_state);
- else if (old_crtc_state->pch_pfit.enabled)
+ else if (old_crtc_state->pfit.enabled)
ilk_pfit_disable(old_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0e3083e852d5..b3d55993e41a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1251,13 +1251,13 @@ struct intel_crtc_state {
u32 lvds_border_bits;
} gmch_pfit;
- /* Panel fitter placement and size for Ironlake+ */
+ /* Panel fitter placement and size */
struct {
struct intel_casf casf;
struct drm_rect dst;
bool enabled;
bool force_thru;
- } pch_pfit;
+ } pfit;
/* FDI configuration, only valid if has_pch_encoder is set. */
int fdi_lanes;
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 5b170c74a510..3e3c69233e58 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -22,7 +22,7 @@ static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_s
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ const struct drm_rect *dst = &crtc_state->pfit.dst;
int width = drm_rect_width(dst);
int height = drm_rect_height(dst);
int x = dst->x1;
@@ -109,7 +109,7 @@ static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_stat
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ const struct drm_rect *dst = &crtc_state->pfit.dst;
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
int hscale, vscale, max_scale = 0x12000; /* 1.125 */
@@ -271,9 +271,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- drm_rect_init(&crtc_state->pch_pfit.dst,
+ drm_rect_init(&crtc_state->pfit.dst,
x, y, width, height);
- crtc_state->pch_pfit.enabled = true;
+ crtc_state->pfit.enabled = true;
/*
* SKL+ have unified scalers for pipes/planes so the
@@ -594,14 +594,14 @@ void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ const struct drm_rect *dst = &crtc_state->pfit.dst;
enum pipe pipe = crtc->pipe;
int width = drm_rect_width(dst);
int height = drm_rect_height(dst);
int x = dst->x1;
int y = dst->y1;
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pfit.enabled)
return;
/*
@@ -630,7 +630,7 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
* To avoid upsetting the power well on haswell only disable the pfit if
* it's in use. The hw state code will make sure we get this right.
*/
- if (!old_crtc_state->pch_pfit.enabled)
+ if (!old_crtc_state->pfit.enabled)
return;
intel_de_write_fw(display, PF_CTL(pipe), 0);
@@ -654,12 +654,12 @@ void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
else
pipe = crtc->pipe;
- crtc_state->pch_pfit.enabled = true;
+ crtc_state->pfit.enabled = true;
pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));
size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));
- drm_rect_init(&crtc_state->pch_pfit.dst,
+ drm_rect_init(&crtc_state->pfit.dst,
REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 7994b983d509..0be6808bc2e4 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -276,9 +276,9 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- if (crtc_state->pch_pfit.enabled) {
- width = drm_rect_width(&crtc_state->pch_pfit.dst);
- height = drm_rect_height(&crtc_state->pch_pfit.dst);
+ if (crtc_state->pfit.enabled) {
+ width = drm_rect_width(&crtc_state->pfit.dst);
+ height = drm_rect_height(&crtc_state->pfit.dst);
} else {
width = pipe_mode->crtc_hdisplay;
height = pipe_mode->crtc_vdisplay;
@@ -289,7 +289,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
drm_rect_width(&crtc_state->pipe_src),
drm_rect_height(&crtc_state->pipe_src),
width, height, NULL, 0,
- crtc_state->pch_pfit.enabled);
+ crtc_state->pfit.enabled);
}
/**
@@ -482,7 +482,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
}
}
- if (crtc_state->pch_pfit.enabled) {
+ if (crtc_state->pfit.enabled) {
struct drm_rect src;
int max_hscale, max_vscale;
@@ -503,9 +503,9 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
max_vscale = 0x10000;
}
- hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,
+ hscale = drm_rect_calc_hscale(&src, &crtc_state->pfit.dst,
0, max_hscale);
- vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,
+ vscale = drm_rect_calc_vscale(&src, &crtc_state->pfit.dst,
0, max_vscale);
if (hscale < 0 || vscale < 0) {
@@ -513,7 +513,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
"Scaler %d doesn't support required pipe scaling\n",
*scaler_id);
drm_rect_debug_print("src: ", &src, true);
- drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);
+ drm_rect_debug_print("dst: ", &crtc_state->pfit.dst, false);
return -EINVAL;
}
@@ -542,7 +542,7 @@ static int setup_crtc_scaler(struct intel_atomic_state *state,
hweight32(scaler_state->scaler_users),
crtc, "CRTC", crtc->base.base.id,
NULL, &scaler_state->scaler_id,
- crtc_state->pch_pfit.casf.enable);
+ crtc_state->pfit.casf.enable);
}
static int setup_plane_scaler(struct intel_atomic_state *state,
@@ -760,12 +760,12 @@ static void skl_scaler_setup_filter(struct intel_display *display,
static u32 casf_sharpness_ctl(const struct intel_crtc_state *crtc_state)
{
- if (!crtc_state->pch_pfit.casf.enable)
+ if (!crtc_state->pfit.casf.enable)
return 0;
return FILTER_EN |
- FILTER_STRENGTH(crtc_state->pch_pfit.casf.strength) |
- crtc_state->pch_pfit.casf.win_size;
+ FILTER_STRENGTH(crtc_state->pfit.casf.strength) |
+ crtc_state->pfit.casf.win_size;
}
void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -774,7 +774,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
- const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ const struct drm_rect *dst = &crtc_state->pfit.dst;
u16 uv_rgb_hphase, uv_rgb_vphase;
enum pipe pipe = crtc->pipe;
int width = drm_rect_width(dst);
@@ -786,7 +786,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
int id;
u32 ps_ctrl;
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pfit.enabled)
return;
if (drm_WARN_ON(display->drm,
@@ -810,11 +810,11 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
skl_scaler_get_filter_select(crtc_state->hw.scaling_filter,
- crtc_state->pch_pfit.casf.enable);
+ crtc_state->pfit.casf.enable);
trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height);
- if (crtc_state->pch_pfit.casf.enable)
+ if (crtc_state->pfit.casf.enable)
intel_casf_setup(crtc_state);
else
skl_scaler_setup_filter(display, NULL, pipe, id, 0,
@@ -977,12 +977,12 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
if (scaler_has_casf(display, scaler_id))
intel_casf_sharpness_get_config(crtc_state);
- crtc_state->pch_pfit.enabled = true;
+ crtc_state->pfit.enabled = true;
pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, scaler_id));
size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, scaler_id));
- drm_rect_init(&crtc_state->pch_pfit.dst,
+ drm_rect_init(&crtc_state->pfit.dst,
REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
@@ -998,7 +998,7 @@ void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pfit.enabled)
return;
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
@@ -1056,7 +1056,7 @@ unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_st
&crtc_state->scaler_state;
int num_scalers = hweight32(scaler_state->scaler_users);
- if (num_scalers > 1 && crtc_state->pch_pfit.enabled)
+ if (num_scalers > 1 && crtc_state->pfit.enabled)
return 4 << 16;
return 0;
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 01/15] drm/i915/pfit: s/pch_pfit/pfit/
2026-10-19 13:52 ` [PATCH 01/15] drm/i915/pfit: s/pch_pfit/pfit/ Ville Syrjala
@ 2026-10-19 15:48 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 15:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename crtc_state->pch_fit to just crtc_state->pfit in
> anticipation of using it also on GMCH platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_casf.c | 28 ++++++-------
> .../drm/i915/display/intel_crtc_state_dump.c | 14 +++----
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +--
> drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++---------
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_pfit.c | 18 ++++-----
> drivers/gpu/drm/i915/display/skl_scaler.c | 40 +++++++++----------
> 7 files changed, 73 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index cafd21a03632..64d99d6480ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -81,11 +81,11 @@ static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
> u32 total_pixels = mode->hdisplay * mode->vdisplay;
>
> if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
> - crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3;
> + crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3;
> else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
> - crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5;
> + crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5;
> else
> - crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7;
> + crtc_state->pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7;
> }
>
> static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state);
> @@ -103,7 +103,7 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
> return -EINVAL;
> }
>
> - crtc_state->pch_pfit.casf.enable = true;
> + crtc_state->pfit.casf.enable = true;
>
> /*
> * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> @@ -113,7 +113,7 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
> * 6.3125 in 4.4 format is b01100101 which is equal to 101.
> * Also 85 + 16 = 101.
> */
> - crtc_state->pch_pfit.casf.strength =
> + crtc_state->pfit.casf.strength =
> min(crtc_state->hw.sharpness_strength, 0xEF) + 0x10;
>
> intel_casf_compute_win_size(crtc_state);
> @@ -133,12 +133,12 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
> if (sharp & FILTER_EN) {
> if (drm_WARN_ON(display->drm,
> REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
> - crtc_state->pch_pfit.casf.strength = 0;
> + crtc_state->pfit.casf.strength = 0;
> else
> - crtc_state->pch_pfit.casf.strength =
> + crtc_state->pfit.casf.strength =
> REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
> - crtc_state->pch_pfit.casf.enable = true;
> - crtc_state->pch_pfit.casf.win_size =
> + crtc_state->pfit.casf.enable = true;
> + crtc_state->pfit.casf.win_size =
> REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
> }
> }
> @@ -153,7 +153,7 @@ static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int tap)
> struct scaler_filter_coeff value;
> u32 coeff;
>
> - value = crtc_state->pch_pfit.casf.coeff[tap];
> + value = crtc_state->pfit.casf.coeff[tap];
> value.sign = 0;
>
> coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3;
> @@ -163,7 +163,7 @@ static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int tap)
> /*
> * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
> * To enable casf: program scaler coefficients with the coefficients
> - * that are calculated and stored in pch_pfit.casf.coeff as per
> + * that are calculated and stored in pfit.casf.coeff as per
> * SCALER_COEFFICIENT_FORMAT
> */
> static void intel_casf_write_coeff(const struct intel_crtc_state *crtc_state)
> @@ -221,9 +221,9 @@ static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state)
> u16 sum_coeff = 0;
> int i;
>
> - if (crtc_state->pch_pfit.casf.win_size == 0)
> + if (crtc_state->pfit.casf.win_size == 0)
> filtercoeff = filtercoeff_1;
> - else if (crtc_state->pch_pfit.casf.win_size == 1)
> + else if (crtc_state->pfit.casf.win_size == 1)
> filtercoeff = filtercoeff_2;
> else
> filtercoeff = filtercoeff_3;
> @@ -233,7 +233,7 @@ static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state)
>
> for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) {
> filter_coeff[i] = (*(filtercoeff + i) * 100 / sum_coeff);
> - convert_sharpness_coeff_binary(&crtc_state->pch_pfit.casf.coeff[i],
> + convert_sharpness_coeff_binary(&crtc_state->pfit.casf.coeff[i],
> filter_coeff[i]);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 92675a88b969..f30d07bc6b07 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -356,15 +356,15 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
> pipe_config->gmch_pfit.pgm_ratios,
> pipe_config->gmch_pfit.lvds_border_bits);
> else
> - drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
> - DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
> - str_enabled_disabled(pipe_config->pch_pfit.enabled),
> - str_yes_no(pipe_config->pch_pfit.force_thru));
> + drm_printf(&p, "pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
> + DRM_RECT_ARG(&pipe_config->pfit.dst),
> + str_enabled_disabled(pipe_config->pfit.enabled),
> + str_yes_no(pipe_config->pfit.force_thru));
>
> drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
> - pipe_config->pch_pfit.casf.strength,
> - pipe_config->pch_pfit.casf.win_size,
> - pipe_config->pch_pfit.casf.enable);
> + pipe_config->pfit.casf.strength,
> + pipe_config->pfit.casf.win_size,
> + pipe_config->pfit.casf.enable);
>
> drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n",
> pipe_config->ips_enabled, pipe_config->double_wide,
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a46ab5d3d70f..2c09fccecbbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -562,7 +562,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
> * eDP when not using the panel fitter, and when not
> * using motion blur mitigation (which we don't
> * support). */
> - if (crtc_state->pch_pfit.force_thru)
> + if (crtc_state->pfit.force_thru)
> temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> else
> temp |= TRANS_DDI_EDP_INPUT_A_ON;
> @@ -4560,8 +4560,8 @@ static int intel_ddi_compute_config(struct intel_atomic_state *state,
>
> if (display->platform.haswell && crtc->pipe == PIPE_A &&
> pipe_config->cpu_transcoder == TRANSCODER_EDP)
> - pipe_config->pch_pfit.force_thru =
> - pipe_config->pch_pfit.enabled ||
> + pipe_config->pfit.force_thru =
> + pipe_config->pfit.enabled ||
> pipe_config->crc_enabled;
>
> if (display->platform.geminilake || display->platform.broxton)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5d4453f283b..723dec35402a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1130,7 +1130,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
> intel_encoders_audio_enable(state, crtc);
>
> if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117)) {
> - if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
> + if (old_crtc_state->pfit.enabled != new_crtc_state->pfit.enabled)
> adl_scaler_ecc_unmask(new_crtc_state);
> }
>
> @@ -1652,7 +1652,7 @@ static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_
> {
> struct intel_display *display = to_intel_display(crtc_state);
>
> - return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
> + return DISPLAY_VER(display) == 10 && crtc_state->pfit.enabled;
> }
>
> static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
> @@ -2052,8 +2052,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
>
> set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
> set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
> - if (crtc_state->pch_pfit.enabled ||
> - crtc_state->pch_pfit.force_thru)
> + if (crtc_state->pfit.enabled ||
> + crtc_state->pfit.force_thru)
> set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
>
> drm_for_each_encoder_mask(encoder, display->drm,
> @@ -2288,14 +2288,14 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> * PF-ID we'll need to adjust the pixel_rate here.
> */
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pfit.enabled)
> return pixel_rate;
>
> drm_rect_init(&src, 0, 0,
> drm_rect_width(&crtc_state->pipe_src) << 16,
> drm_rect_height(&crtc_state->pipe_src) << 16);
>
> - return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
> + return intel_adjusted_rate(&src, &crtc_state->pfit.dst,
> pixel_rate);
> }
>
> @@ -2311,14 +2311,14 @@ static u32 ilk_pipe_pixel_rate_cdclk(const struct intel_crtc_state *crtc_state)
> * PF-ID we'll need to adjust the pixel_rate here.
> */
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pfit.enabled)
> return pixel_rate;
>
> drm_rect_init(&src, 0, 0,
> drm_rect_width(&crtc_state->pipe_src) << 16,
> drm_rect_height(&crtc_state->pipe_src) << 16);
>
> - return intel_adjusted_rate_cdclk(&src, &crtc_state->pch_pfit.dst,
> + return intel_adjusted_rate_cdclk(&src, &crtc_state->pfit.dst,
> pixel_rate, ppc);
> }
>
> @@ -4012,7 +4012,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
>
> if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
> - pipe_config->pch_pfit.force_thru = true;
> + pipe_config->pfit.force_thru = true;
> }
>
> tmp = intel_de_read(display,
> @@ -5475,16 +5475,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> * Changing the EDP transcoder input mux
> * (A_ONOFF vs. A_ON) requires a full modeset.
> */
> - PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
> + PIPE_CONF_CHECK_BOOL(pfit.force_thru);
>
> if (!fastset) {
> PIPE_CONF_CHECK_RECT(pipe_src);
>
> - PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
> - PIPE_CONF_CHECK_RECT(pch_pfit.dst);
> - PIPE_CONF_CHECK_BOOL(pch_pfit.casf.enable);
> - PIPE_CONF_CHECK_I(pch_pfit.casf.win_size);
> - PIPE_CONF_CHECK_I(pch_pfit.casf.strength);
> + PIPE_CONF_CHECK_BOOL(pfit.enabled);
> + PIPE_CONF_CHECK_RECT(pfit.dst);
> + PIPE_CONF_CHECK_BOOL(pfit.casf.enable);
> + PIPE_CONF_CHECK_I(pfit.casf.win_size);
> + PIPE_CONF_CHECK_I(pfit.casf.strength);
>
> PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> PIPE_CONF_CHECK_I(pixel_rate_cdclk);
> @@ -6775,12 +6775,12 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
>
> /* on skylake this is done by detaching scalers */
> if (DISPLAY_VER(display) >= 9) {
> - if (new_crtc_state->pch_pfit.enabled)
> + if (new_crtc_state->pfit.enabled)
> skl_pfit_enable(new_crtc_state);
> } else if (HAS_PCH_SPLIT(display)) {
> - if (new_crtc_state->pch_pfit.enabled)
> + if (new_crtc_state->pfit.enabled)
> ilk_pfit_enable(new_crtc_state);
> - else if (old_crtc_state->pch_pfit.enabled)
> + else if (old_crtc_state->pfit.enabled)
> ilk_pfit_disable(old_crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0e3083e852d5..b3d55993e41a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1251,13 +1251,13 @@ struct intel_crtc_state {
> u32 lvds_border_bits;
> } gmch_pfit;
>
> - /* Panel fitter placement and size for Ironlake+ */
> + /* Panel fitter placement and size */
> struct {
> struct intel_casf casf;
> struct drm_rect dst;
> bool enabled;
> bool force_thru;
> - } pch_pfit;
> + } pfit;
>
> /* FDI configuration, only valid if has_pch_encoder is set. */
> int fdi_lanes;
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 5b170c74a510..3e3c69233e58 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -22,7 +22,7 @@ static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_s
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> - const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
> + const struct drm_rect *dst = &crtc_state->pfit.dst;
> int width = drm_rect_width(dst);
> int height = drm_rect_height(dst);
> int x = dst->x1;
> @@ -109,7 +109,7 @@ static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_stat
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
> + const struct drm_rect *dst = &crtc_state->pfit.dst;
> int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
> int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
> int hscale, vscale, max_scale = 0x12000; /* 1.125 */
> @@ -271,9 +271,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - drm_rect_init(&crtc_state->pch_pfit.dst,
> + drm_rect_init(&crtc_state->pfit.dst,
> x, y, width, height);
> - crtc_state->pch_pfit.enabled = true;
> + crtc_state->pfit.enabled = true;
>
> /*
> * SKL+ have unified scalers for pipes/planes so the
> @@ -594,14 +594,14 @@ void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
> + const struct drm_rect *dst = &crtc_state->pfit.dst;
> enum pipe pipe = crtc->pipe;
> int width = drm_rect_width(dst);
> int height = drm_rect_height(dst);
> int x = dst->x1;
> int y = dst->y1;
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pfit.enabled)
> return;
>
> /*
> @@ -630,7 +630,7 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> * To avoid upsetting the power well on haswell only disable the pfit if
> * it's in use. The hw state code will make sure we get this right.
> */
> - if (!old_crtc_state->pch_pfit.enabled)
> + if (!old_crtc_state->pfit.enabled)
> return;
>
> intel_de_write_fw(display, PF_CTL(pipe), 0);
> @@ -654,12 +654,12 @@ void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
> else
> pipe = crtc->pipe;
>
> - crtc_state->pch_pfit.enabled = true;
> + crtc_state->pfit.enabled = true;
>
> pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));
> size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));
>
> - drm_rect_init(&crtc_state->pch_pfit.dst,
> + drm_rect_init(&crtc_state->pfit.dst,
> REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 7994b983d509..0be6808bc2e4 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -276,9 +276,9 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
> if (ret)
> return ret;
>
> - if (crtc_state->pch_pfit.enabled) {
> - width = drm_rect_width(&crtc_state->pch_pfit.dst);
> - height = drm_rect_height(&crtc_state->pch_pfit.dst);
> + if (crtc_state->pfit.enabled) {
> + width = drm_rect_width(&crtc_state->pfit.dst);
> + height = drm_rect_height(&crtc_state->pfit.dst);
> } else {
> width = pipe_mode->crtc_hdisplay;
> height = pipe_mode->crtc_vdisplay;
> @@ -289,7 +289,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
> drm_rect_width(&crtc_state->pipe_src),
> drm_rect_height(&crtc_state->pipe_src),
> width, height, NULL, 0,
> - crtc_state->pch_pfit.enabled);
> + crtc_state->pfit.enabled);
> }
>
> /**
> @@ -482,7 +482,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
> }
> }
>
> - if (crtc_state->pch_pfit.enabled) {
> + if (crtc_state->pfit.enabled) {
> struct drm_rect src;
> int max_hscale, max_vscale;
>
> @@ -503,9 +503,9 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
> max_vscale = 0x10000;
> }
>
> - hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,
> + hscale = drm_rect_calc_hscale(&src, &crtc_state->pfit.dst,
> 0, max_hscale);
> - vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,
> + vscale = drm_rect_calc_vscale(&src, &crtc_state->pfit.dst,
> 0, max_vscale);
>
> if (hscale < 0 || vscale < 0) {
> @@ -513,7 +513,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
> "Scaler %d doesn't support required pipe scaling\n",
> *scaler_id);
> drm_rect_debug_print("src: ", &src, true);
> - drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);
> + drm_rect_debug_print("dst: ", &crtc_state->pfit.dst, false);
>
> return -EINVAL;
> }
> @@ -542,7 +542,7 @@ static int setup_crtc_scaler(struct intel_atomic_state *state,
> hweight32(scaler_state->scaler_users),
> crtc, "CRTC", crtc->base.base.id,
> NULL, &scaler_state->scaler_id,
> - crtc_state->pch_pfit.casf.enable);
> + crtc_state->pfit.casf.enable);
> }
>
> static int setup_plane_scaler(struct intel_atomic_state *state,
> @@ -760,12 +760,12 @@ static void skl_scaler_setup_filter(struct intel_display *display,
>
> static u32 casf_sharpness_ctl(const struct intel_crtc_state *crtc_state)
> {
> - if (!crtc_state->pch_pfit.casf.enable)
> + if (!crtc_state->pfit.casf.enable)
> return 0;
>
> return FILTER_EN |
> - FILTER_STRENGTH(crtc_state->pch_pfit.casf.strength) |
> - crtc_state->pch_pfit.casf.win_size;
> + FILTER_STRENGTH(crtc_state->pfit.casf.strength) |
> + crtc_state->pfit.casf.win_size;
> }
>
> void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -774,7 +774,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> - const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
> + const struct drm_rect *dst = &crtc_state->pfit.dst;
> u16 uv_rgb_hphase, uv_rgb_vphase;
> enum pipe pipe = crtc->pipe;
> int width = drm_rect_width(dst);
> @@ -786,7 +786,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> int id;
> u32 ps_ctrl;
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pfit.enabled)
> return;
>
> if (drm_WARN_ON(display->drm,
> @@ -810,11 +810,11 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
> skl_scaler_get_filter_select(crtc_state->hw.scaling_filter,
> - crtc_state->pch_pfit.casf.enable);
> + crtc_state->pfit.casf.enable);
>
> trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height);
>
> - if (crtc_state->pch_pfit.casf.enable)
> + if (crtc_state->pfit.casf.enable)
> intel_casf_setup(crtc_state);
> else
> skl_scaler_setup_filter(display, NULL, pipe, id, 0,
> @@ -977,12 +977,12 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> if (scaler_has_casf(display, scaler_id))
> intel_casf_sharpness_get_config(crtc_state);
>
> - crtc_state->pch_pfit.enabled = true;
> + crtc_state->pfit.enabled = true;
>
> pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, scaler_id));
> size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, scaler_id));
>
> - drm_rect_init(&crtc_state->pch_pfit.dst,
> + drm_rect_init(&crtc_state->pfit.dst,
> REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
> REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
> REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
> @@ -998,7 +998,7 @@ void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pfit.enabled)
> return;
>
> intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
> @@ -1056,7 +1056,7 @@ unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_st
> &crtc_state->scaler_state;
> int num_scalers = hweight32(scaler_state->scaler_users);
>
> - if (num_scalers > 1 && crtc_state->pch_pfit.enabled)
> + if (num_scalers > 1 && crtc_state->pfit.enabled)
> return 4 << 16;
>
> return 0;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 02/15] drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
2026-10-19 13:52 ` [PATCH 01/15] drm/i915/pfit: s/pch_pfit/pfit/ Ville Syrjala
@ 2026-10-19 13:52 ` Ville Syrjala
2026-10-19 15:49 ` Jani Nikula
2026-10-19 13:52 ` [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places Ville Syrjala
` (17 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The intel_pch_pfit_*() have nothing to do with PCH. Rename
them to just ilk_pfit_*() to better reflect their meaning.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 24 +++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 3e3c69233e58..aa4a4d10d124 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -16,7 +16,7 @@
#include "intel_pfit_regs.h"
#include "skl_scaler.h"
-static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
+static int ilk_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -67,7 +67,7 @@ static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_s
return 0;
}
-static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
+static int ilk_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -105,7 +105,7 @@ static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_sta
return 0;
}
-static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
+static int ilk_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -140,7 +140,7 @@ static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_stat
return 0;
}
-static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+static int ilk_pfit_check_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -158,7 +158,7 @@ static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_stat
return 0;
}
-static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
+static int ilk_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -182,7 +182,7 @@ static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_stat
}
/* adjusted_mode has been preset to be the panel's fixed mode */
-static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
+static int ilk_panel_fitting(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -282,23 +282,23 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(display) >= 9)
return 0;
- ret = intel_pch_pfit_check_dst_window(crtc_state);
+ ret = ilk_pfit_check_dst_window(crtc_state);
if (ret)
return ret;
- ret = intel_pch_pfit_check_src_size(crtc_state);
+ ret = ilk_pfit_check_src_size(crtc_state);
if (ret)
return ret;
- ret = intel_pch_pfit_check_scaling(crtc_state);
+ ret = ilk_pfit_check_scaling(crtc_state);
if (ret)
return ret;
- ret = intel_pch_pfit_check_timings(crtc_state);
+ ret = ilk_pfit_check_timings(crtc_state);
if (ret)
return ret;
- ret = intel_pch_pfit_check_cloning(crtc_state);
+ ret = ilk_pfit_check_cloning(crtc_state);
if (ret)
return ret;
@@ -587,7 +587,7 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
if (HAS_GMCH(display))
return gmch_panel_fitting(crtc_state, conn_state);
else
- return pch_panel_fitting(crtc_state, conn_state);
+ return ilk_panel_fitting(crtc_state, conn_state);
}
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 02/15] drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/
2026-10-19 13:52 ` [PATCH 02/15] drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/ Ville Syrjala
@ 2026-10-19 15:49 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 15:49 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The intel_pch_pfit_*() have nothing to do with PCH. Rename
> them to just ilk_pfit_*() to better reflect their meaning.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_pfit.c | 24 +++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 3e3c69233e58..aa4a4d10d124 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -16,7 +16,7 @@
> #include "intel_pfit_regs.h"
> #include "skl_scaler.h"
>
> -static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
> +static int ilk_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -67,7 +67,7 @@ static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_s
> return 0;
> }
>
> -static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
> +static int ilk_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -105,7 +105,7 @@ static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_sta
> return 0;
> }
>
> -static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
> +static int ilk_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -140,7 +140,7 @@ static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_stat
> return 0;
> }
>
> -static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
> +static int ilk_pfit_check_timings(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -158,7 +158,7 @@ static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_stat
> return 0;
> }
>
> -static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
> +static int ilk_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -182,7 +182,7 @@ static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_stat
> }
>
> /* adjusted_mode has been preset to be the panel's fixed mode */
> -static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
> +static int ilk_panel_fitting(struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> @@ -282,23 +282,23 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
> if (DISPLAY_VER(display) >= 9)
> return 0;
>
> - ret = intel_pch_pfit_check_dst_window(crtc_state);
> + ret = ilk_pfit_check_dst_window(crtc_state);
> if (ret)
> return ret;
>
> - ret = intel_pch_pfit_check_src_size(crtc_state);
> + ret = ilk_pfit_check_src_size(crtc_state);
> if (ret)
> return ret;
>
> - ret = intel_pch_pfit_check_scaling(crtc_state);
> + ret = ilk_pfit_check_scaling(crtc_state);
> if (ret)
> return ret;
>
> - ret = intel_pch_pfit_check_timings(crtc_state);
> + ret = ilk_pfit_check_timings(crtc_state);
> if (ret)
> return ret;
>
> - ret = intel_pch_pfit_check_cloning(crtc_state);
> + ret = ilk_pfit_check_cloning(crtc_state);
> if (ret)
> return ret;
>
> @@ -587,7 +587,7 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
> if (HAS_GMCH(display))
> return gmch_panel_fitting(crtc_state, conn_state);
> else
> - return pch_panel_fitting(crtc_state, conn_state);
> + return ilk_panel_fitting(crtc_state, conn_state);
> }
>
> void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
2026-10-19 13:52 ` [PATCH 01/15] drm/i915/pfit: s/pch_pfit/pfit/ Ville Syrjala
2026-10-19 13:52 ` [PATCH 02/15] drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/ Ville Syrjala
@ 2026-10-19 13:52 ` Ville Syrjala
2026-10-19 15:49 ` Jani Nikula
2026-10-19 13:52 ` [PATCH 04/15] drm/i915/pfit: Introduce intel_pfit_get_config() Ville Syrjala
` (16 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop using HAS_PCH_SPLIT() in places that have nothing to
do with PCH. !HAS_GMCH is a more sensible thing top check for.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 86d1c9f7f0ff..0233f5053d95 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -4150,7 +4150,7 @@ static const struct intel_wm_funcs nop_funcs = {
void i9xx_wm_init(struct intel_display *display)
{
/* For FIFO watermark updates */
- if (HAS_PCH_SPLIT(display)) {
+ if (!HAS_GMCH(display)) {
ilk_setup_wm_latency(display);
display->wm.funcs = &ilk_wm_funcs;
} else if (display->platform.valleyview || display->platform.cherryview) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 723dec35402a..d1440cc6dba4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6777,7 +6777,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
if (DISPLAY_VER(display) >= 9) {
if (new_crtc_state->pfit.enabled)
skl_pfit_enable(new_crtc_state);
- } else if (HAS_PCH_SPLIT(display)) {
+ } else if (!HAS_GMCH(display)) {
if (new_crtc_state->pfit.enabled)
ilk_pfit_enable(new_crtc_state);
else if (old_crtc_state->pfit.enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3e302f23f247..dba34f034785 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -96,7 +96,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
if (DISPLAY_VER(display) >= 9)
/* no global SR status; inspect per-plane WM */;
- else if (HAS_PCH_SPLIT(display))
+ else if (!HAS_GMCH(display))
sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
else if (display->platform.i965gm || display->platform.g4x ||
display->platform.i945g || display->platform.i945gm)
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places
2026-10-19 13:52 ` [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places Ville Syrjala
@ 2026-10-19 15:49 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 15:49 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop using HAS_PCH_SPLIT() in places that have nothing to
> do with PCH. !HAS_GMCH is a more sensible thing top check for.
*to
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 86d1c9f7f0ff..0233f5053d95 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -4150,7 +4150,7 @@ static const struct intel_wm_funcs nop_funcs = {
> void i9xx_wm_init(struct intel_display *display)
> {
> /* For FIFO watermark updates */
> - if (HAS_PCH_SPLIT(display)) {
> + if (!HAS_GMCH(display)) {
> ilk_setup_wm_latency(display);
> display->wm.funcs = &ilk_wm_funcs;
> } else if (display->platform.valleyview || display->platform.cherryview) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 723dec35402a..d1440cc6dba4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6777,7 +6777,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> if (DISPLAY_VER(display) >= 9) {
> if (new_crtc_state->pfit.enabled)
> skl_pfit_enable(new_crtc_state);
> - } else if (HAS_PCH_SPLIT(display)) {
> + } else if (!HAS_GMCH(display)) {
> if (new_crtc_state->pfit.enabled)
> ilk_pfit_enable(new_crtc_state);
> else if (old_crtc_state->pfit.enabled)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3e302f23f247..dba34f034785 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -96,7 +96,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>
> if (DISPLAY_VER(display) >= 9)
> /* no global SR status; inspect per-plane WM */;
> - else if (HAS_PCH_SPLIT(display))
> + else if (!HAS_GMCH(display))
> sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
> else if (display->platform.i965gm || display->platform.g4x ||
> display->platform.i945g || display->platform.i945gm)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 04/15] drm/i915/pfit: Introduce intel_pfit_get_config()
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (2 preceding siblings ...)
2026-10-19 13:52 ` [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places Ville Syrjala
@ 2026-10-19 13:52 ` Ville Syrjala
2026-10-19 15:53 ` Jani Nikula
2026-10-19 13:52 ` [PATCH 05/15] drm/i915/pfit: Rename some pfit functions Ville Syrjala
` (15 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Introduce a new intel_pfit_get_config() wrapper to better
contain the pfit details inside intel_pfit.c.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++--------
drivers/gpu/drm/i915/display/intel_pfit.c | 16 ++++++++++++++--
drivers/gpu/drm/i915/display/intel_pfit.h | 3 +--
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d1440cc6dba4..79c4aff1c633 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3236,7 +3236,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- i9xx_pfit_get_config(pipe_config);
+ intel_pfit_get_config(pipe_config);
i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
@@ -3586,7 +3586,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- ilk_pfit_get_config(pipe_config);
+ intel_pfit_get_config(pipe_config);
ret = true;
@@ -4153,12 +4153,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
- POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
- if (DISPLAY_VER(display) >= 9)
- skl_scaler_get_config(pipe_config);
- else
- ilk_pfit_get_config(pipe_config);
- }
+ POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe)))
+ intel_pfit_get_config(pipe_config);
hsw_ips_get_config(pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index aa4a4d10d124..b4a201dc8f7b 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -638,7 +638,7 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);
}
-void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
+static void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -724,7 +724,7 @@ static bool i9xx_has_pfit(struct intel_display *display)
display->platform.pineview || display->platform.mobile;
}
-void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
+static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -751,3 +751,15 @@ void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
crtc_state->gmch_pfit.pgm_ratios =
intel_de_read(display, PFIT_PGM_RATIOS(display));
}
+
+void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (HAS_GMCH(display))
+ i9xx_pfit_get_config(crtc_state);
+ else if (DISPLAY_VER(display) >= 9)
+ skl_scaler_get_config(crtc_state);
+ else
+ ilk_pfit_get_config(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h b/drivers/gpu/drm/i915/display/intel_pfit.h
index c1bb0d1f344e..184e1932eae5 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.h
+++ b/drivers/gpu/drm/i915/display/intel_pfit.h
@@ -17,10 +17,9 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
-void ilk_pfit_get_config(struct intel_crtc_state *crtc_state);
void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state);
void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state);
-void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state);
+void intel_pfit_get_config(struct intel_crtc_state *crtc_state);
enum drm_mode_status
intel_pfit_mode_valid(struct intel_display *display,
const struct drm_display_mode *mode,
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 04/15] drm/i915/pfit: Introduce intel_pfit_get_config()
2026-10-19 13:52 ` [PATCH 04/15] drm/i915/pfit: Introduce intel_pfit_get_config() Ville Syrjala
@ 2026-10-19 15:53 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 15:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Introduce a new intel_pfit_get_config() wrapper to better
> contain the pfit details inside intel_pfit.c.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++++--------
> drivers/gpu/drm/i915/display/intel_pfit.c | 16 ++++++++++++++--
> drivers/gpu/drm/i915/display/intel_pfit.h | 3 +--
> 3 files changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d1440cc6dba4..79c4aff1c633 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3236,7 +3236,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
>
> - i9xx_pfit_get_config(pipe_config);
> + intel_pfit_get_config(pipe_config);
>
> i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
>
> @@ -3586,7 +3586,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
>
> - ilk_pfit_get_config(pipe_config);
> + intel_pfit_get_config(pipe_config);
>
> ret = true;
>
> @@ -4153,12 +4153,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
>
> if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
> - POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
> - if (DISPLAY_VER(display) >= 9)
> - skl_scaler_get_config(pipe_config);
> - else
> - ilk_pfit_get_config(pipe_config);
> - }
> + POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe)))
> + intel_pfit_get_config(pipe_config);
>
> hsw_ips_get_config(pipe_config);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index aa4a4d10d124..b4a201dc8f7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -638,7 +638,7 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);
> }
>
> -void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
> +static void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -724,7 +724,7 @@ static bool i9xx_has_pfit(struct intel_display *display)
> display->platform.pineview || display->platform.mobile;
> }
>
> -void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> +static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -751,3 +751,15 @@ void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->gmch_pfit.pgm_ratios =
> intel_de_read(display, PFIT_PGM_RATIOS(display));
> }
> +
> +void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (HAS_GMCH(display))
> + i9xx_pfit_get_config(crtc_state);
> + else if (DISPLAY_VER(display) >= 9)
> + skl_scaler_get_config(crtc_state);
> + else
> + ilk_pfit_get_config(crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h b/drivers/gpu/drm/i915/display/intel_pfit.h
> index c1bb0d1f344e..184e1932eae5 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.h
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.h
> @@ -17,10 +17,9 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> -void ilk_pfit_get_config(struct intel_crtc_state *crtc_state);
> void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state);
> void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> -void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state);
> +void intel_pfit_get_config(struct intel_crtc_state *crtc_state);
> enum drm_mode_status
> intel_pfit_mode_valid(struct intel_display *display,
> const struct drm_display_mode *mode,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 05/15] drm/i915/pfit: Rename some pfit functions
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (3 preceding siblings ...)
2026-10-19 13:52 ` [PATCH 04/15] drm/i915/pfit: Introduce intel_pfit_get_config() Ville Syrjala
@ 2026-10-19 13:52 ` Ville Syrjala
2026-10-19 15:54 ` Jani Nikula
2026-10-19 13:53 ` [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config() Ville Syrjala
` (14 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Most pfit functions are called {ilk,i9xx}_pfit_*(). Rename
{gmch,ilk}_panel_fitting() and intel_gmch_pfit_check_timings()
to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index b4a201dc8f7b..972218346362 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -182,8 +182,8 @@ static int ilk_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
}
/* adjusted_mode has been preset to be the panel's fixed mode */
-static int ilk_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+static int ilk_pfit_compute_config(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -438,7 +438,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
}
}
-static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+static int i9xx_pfit_check_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -470,8 +470,8 @@ static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_sta
return 0;
}
-static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -479,6 +479,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
+ int ret;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
@@ -566,7 +567,11 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
if ((pfit_control & PFIT_ENABLE) == 0)
return 0;
- return intel_gmch_pfit_check_timings(crtc_state);
+ ret = i9xx_pfit_check_timings(crtc_state);
+ if (ret)
+ return ret;
+
+ return 0;
}
enum drm_mode_status
@@ -585,9 +590,9 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
struct intel_display *display = to_intel_display(crtc_state);
if (HAS_GMCH(display))
- return gmch_panel_fitting(crtc_state, conn_state);
+ return i9xx_pfit_compute_config(crtc_state, conn_state);
else
- return ilk_panel_fitting(crtc_state, conn_state);
+ return ilk_pfit_compute_config(crtc_state, conn_state);
}
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 05/15] drm/i915/pfit: Rename some pfit functions
2026-10-19 13:52 ` [PATCH 05/15] drm/i915/pfit: Rename some pfit functions Ville Syrjala
@ 2026-10-19 15:54 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 15:54 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Most pfit functions are called {ilk,i9xx}_pfit_*(). Rename
> {gmch,ilk}_panel_fitting() and intel_gmch_pfit_check_timings()
> to match.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_pfit.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index b4a201dc8f7b..972218346362 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -182,8 +182,8 @@ static int ilk_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
> }
>
> /* adjusted_mode has been preset to be the panel's fixed mode */
> -static int ilk_panel_fitting(struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static int ilk_pfit_compute_config(struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -438,7 +438,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> }
> }
>
> -static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
> +static int i9xx_pfit_check_timings(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -470,8 +470,8 @@ static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_sta
> return 0;
> }
>
> -static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -479,6 +479,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
> int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
> + int ret;
>
> /* Native modes don't need fitting */
> if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
> @@ -566,7 +567,11 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> if ((pfit_control & PFIT_ENABLE) == 0)
> return 0;
>
> - return intel_gmch_pfit_check_timings(crtc_state);
> + ret = i9xx_pfit_check_timings(crtc_state);
> + if (ret)
> + return ret;
> +
> + return 0;
> }
>
> enum drm_mode_status
> @@ -585,9 +590,9 @@ int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
> struct intel_display *display = to_intel_display(crtc_state);
>
> if (HAS_GMCH(display))
> - return gmch_panel_fitting(crtc_state, conn_state);
> + return i9xx_pfit_compute_config(crtc_state, conn_state);
> else
> - return ilk_panel_fitting(crtc_state, conn_state);
> + return ilk_pfit_compute_config(crtc_state, conn_state);
> }
>
> void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config()
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (4 preceding siblings ...)
2026-10-19 13:52 ` [PATCH 05/15] drm/i915/pfit: Rename some pfit functions Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 16:02 ` Jani Nikula
2026-10-19 13:53 ` [PATCH 07/15] drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios Ville Syrjala
` (13 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split i965_pfit_get_config() out from i9xx_pfit_get_config() to
unconfuse things a bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 66 ++++++++++++++---------
1 file changed, 42 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 972218346362..82804159d0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -720,39 +720,52 @@ void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
intel_de_write(display, PFIT_CONTROL(display), 0);
}
-static bool i9xx_has_pfit(struct intel_display *display)
-{
- if (display->platform.i830)
- return false;
-
- return DISPLAY_VER(display) >= 4 ||
- display->platform.pineview || display->platform.mobile;
-}
-
-static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
+static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe;
u32 tmp;
- if (!i9xx_has_pfit(display))
- return;
-
tmp = intel_de_read(display, PFIT_CONTROL(display));
if (!(tmp & PFIT_ENABLE))
return;
/* Check whether the pfit is attached to our pipe. */
- if (DISPLAY_VER(display) >= 4)
- pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
- else
- pipe = PIPE_B;
-
+ pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
if (pipe != crtc->pipe)
return;
crtc_state->gmch_pfit.control = tmp;
+}
+
+static bool i9xx_has_pfit(struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+
+ if (crtc->pipe != PIPE_B)
+ return false;
+
+ if (display->platform.i830)
+ return false;
+
+ return display->platform.pineview || display->platform.mobile;
+}
+
+static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ u32 tmp;
+
+ if (!i9xx_has_pfit(crtc))
+ return;
+
+ tmp = intel_de_read(display, PFIT_CONTROL(display));
+ if (!(tmp & PFIT_ENABLE))
+ return;
+
+ crtc_state->gmch_pfit.control = tmp;
crtc_state->gmch_pfit.pgm_ratios =
intel_de_read(display, PFIT_PGM_RATIOS(display));
}
@@ -761,10 +774,15 @@ void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- if (HAS_GMCH(display))
- i9xx_pfit_get_config(crtc_state);
- else if (DISPLAY_VER(display) >= 9)
- skl_scaler_get_config(crtc_state);
- else
- ilk_pfit_get_config(crtc_state);
+ if (HAS_GMCH(display)) {
+ if (DISPLAY_VER(display) >= 4)
+ i965_pfit_get_config(crtc_state);
+ else
+ i9xx_pfit_get_config(crtc_state);
+ } else {
+ if (DISPLAY_VER(display) >= 9)
+ skl_scaler_get_config(crtc_state);
+ else
+ ilk_pfit_get_config(crtc_state);
+ }
}
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config()
2026-10-19 13:53 ` [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config() Ville Syrjala
@ 2026-10-19 16:02 ` Jani Nikula
2026-10-19 16:05 ` Jani Nikula
0 siblings, 1 reply; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 16:02 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split i965_pfit_get_config() out from i9xx_pfit_get_config() to
> unconfuse things a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_pfit.c | 66 ++++++++++++++---------
> 1 file changed, 42 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 972218346362..82804159d0a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -720,39 +720,52 @@ void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> intel_de_write(display, PFIT_CONTROL(display), 0);
> }
>
> -static bool i9xx_has_pfit(struct intel_display *display)
> -{
> - if (display->platform.i830)
> - return false;
> -
> - return DISPLAY_VER(display) >= 4 ||
> - display->platform.pineview || display->platform.mobile;
> -}
> -
> -static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> +static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe;
> u32 tmp;
>
> - if (!i9xx_has_pfit(display))
> - return;
> -
> tmp = intel_de_read(display, PFIT_CONTROL(display));
> if (!(tmp & PFIT_ENABLE))
> return;
>
> /* Check whether the pfit is attached to our pipe. */
> - if (DISPLAY_VER(display) >= 4)
> - pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> - else
> - pipe = PIPE_B;
> -
> + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> if (pipe != crtc->pipe)
> return;
>
> crtc_state->gmch_pfit.control = tmp;
This drops PFIT_PGM_RATIOS read.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +}
> +
> +static bool i9xx_has_pfit(struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc);
> +
> + if (crtc->pipe != PIPE_B)
> + return false;
> +
> + if (display->platform.i830)
> + return false;
> +
> + return display->platform.pineview || display->platform.mobile;
> +}
> +
> +static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + u32 tmp;
> +
> + if (!i9xx_has_pfit(crtc))
> + return;
> +
> + tmp = intel_de_read(display, PFIT_CONTROL(display));
> + if (!(tmp & PFIT_ENABLE))
> + return;
> +
> + crtc_state->gmch_pfit.control = tmp;
> crtc_state->gmch_pfit.pgm_ratios =
> intel_de_read(display, PFIT_PGM_RATIOS(display));
> }
> @@ -761,10 +774,15 @@ void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
>
> - if (HAS_GMCH(display))
> - i9xx_pfit_get_config(crtc_state);
> - else if (DISPLAY_VER(display) >= 9)
> - skl_scaler_get_config(crtc_state);
> - else
> - ilk_pfit_get_config(crtc_state);
> + if (HAS_GMCH(display)) {
> + if (DISPLAY_VER(display) >= 4)
> + i965_pfit_get_config(crtc_state);
> + else
> + i9xx_pfit_get_config(crtc_state);
> + } else {
> + if (DISPLAY_VER(display) >= 9)
> + skl_scaler_get_config(crtc_state);
> + else
> + ilk_pfit_get_config(crtc_state);
> + }
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config()
2026-10-19 16:02 ` Jani Nikula
@ 2026-10-19 16:05 ` Jani Nikula
2026-10-19 17:04 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 16:05 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Split i965_pfit_get_config() out from i9xx_pfit_get_config() to
>> unconfuse things a bit.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_pfit.c | 66 ++++++++++++++---------
>> 1 file changed, 42 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
>> index 972218346362..82804159d0a1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
>> @@ -720,39 +720,52 @@ void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>> intel_de_write(display, PFIT_CONTROL(display), 0);
>> }
>>
>> -static bool i9xx_has_pfit(struct intel_display *display)
>> -{
>> - if (display->platform.i830)
>> - return false;
>> -
>> - return DISPLAY_VER(display) >= 4 ||
>> - display->platform.pineview || display->platform.mobile;
>> -}
>> -
>> -static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
>> +static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> enum pipe pipe;
>> u32 tmp;
>>
>> - if (!i9xx_has_pfit(display))
>> - return;
>> -
>> tmp = intel_de_read(display, PFIT_CONTROL(display));
>> if (!(tmp & PFIT_ENABLE))
>> return;
>>
>> /* Check whether the pfit is attached to our pipe. */
>> - if (DISPLAY_VER(display) >= 4)
>> - pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
>> - else
>> - pipe = PIPE_B;
>> -
>> + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
>> if (pipe != crtc->pipe)
>> return;
>>
>> crtc_state->gmch_pfit.control = tmp;
>
> This drops PFIT_PGM_RATIOS read.
Judging by the next patch, this is intentional. Should be mentioned in
the commit message, and why it's okay we're still writing the register
also for i965.
BR,
Jani.
>
> With that fixed,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +}
>> +
>> +static bool i9xx_has_pfit(struct intel_crtc *crtc)
>> +{
>> + struct intel_display *display = to_intel_display(crtc);
>> +
>> + if (crtc->pipe != PIPE_B)
>> + return false;
>> +
>> + if (display->platform.i830)
>> + return false;
>> +
>> + return display->platform.pineview || display->platform.mobile;
>> +}
>> +
>> +static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_display *display = to_intel_display(crtc_state);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + u32 tmp;
>> +
>> + if (!i9xx_has_pfit(crtc))
>> + return;
>> +
>> + tmp = intel_de_read(display, PFIT_CONTROL(display));
>> + if (!(tmp & PFIT_ENABLE))
>> + return;
>> +
>> + crtc_state->gmch_pfit.control = tmp;
>> crtc_state->gmch_pfit.pgm_ratios =
>> intel_de_read(display, PFIT_PGM_RATIOS(display));
>> }
>> @@ -761,10 +774,15 @@ void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>>
>> - if (HAS_GMCH(display))
>> - i9xx_pfit_get_config(crtc_state);
>> - else if (DISPLAY_VER(display) >= 9)
>> - skl_scaler_get_config(crtc_state);
>> - else
>> - ilk_pfit_get_config(crtc_state);
>> + if (HAS_GMCH(display)) {
>> + if (DISPLAY_VER(display) >= 4)
>> + i965_pfit_get_config(crtc_state);
>> + else
>> + i9xx_pfit_get_config(crtc_state);
>> + } else {
>> + if (DISPLAY_VER(display) >= 9)
>> + skl_scaler_get_config(crtc_state);
>> + else
>> + ilk_pfit_get_config(crtc_state);
>> + }
>> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config()
2026-10-19 16:05 ` Jani Nikula
@ 2026-10-19 17:04 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2026-10-19 17:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Mon, Oct 19, 2026 at 07:05:05PM +0300, Jani Nikula wrote:
> On Mon, 19 Oct 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Split i965_pfit_get_config() out from i9xx_pfit_get_config() to
> >> unconfuse things a bit.
> >>
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_pfit.c | 66 ++++++++++++++---------
> >> 1 file changed, 42 insertions(+), 24 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> >> index 972218346362..82804159d0a1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> >> @@ -720,39 +720,52 @@ void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> >> intel_de_write(display, PFIT_CONTROL(display), 0);
> >> }
> >>
> >> -static bool i9xx_has_pfit(struct intel_display *display)
> >> -{
> >> - if (display->platform.i830)
> >> - return false;
> >> -
> >> - return DISPLAY_VER(display) >= 4 ||
> >> - display->platform.pineview || display->platform.mobile;
> >> -}
> >> -
> >> -static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
> >> +static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
> >> {
> >> struct intel_display *display = to_intel_display(crtc_state);
> >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> enum pipe pipe;
> >> u32 tmp;
> >>
> >> - if (!i9xx_has_pfit(display))
> >> - return;
> >> -
> >> tmp = intel_de_read(display, PFIT_CONTROL(display));
> >> if (!(tmp & PFIT_ENABLE))
> >> return;
> >>
> >> /* Check whether the pfit is attached to our pipe. */
> >> - if (DISPLAY_VER(display) >= 4)
> >> - pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> >> - else
> >> - pipe = PIPE_B;
> >> -
> >> + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> >> if (pipe != crtc->pipe)
> >> return;
> >>
> >> crtc_state->gmch_pfit.control = tmp;
> >
> > This drops PFIT_PGM_RATIOS read.
>
> Judging by the next patch, this is intentional. Should be mentioned in
> the commit message, and why it's okay we're still writing the register
> also for i965.
Yeah, we don't use programmed scale factors on i965+ and reading
the register just gives back the automagic ratios that the hardware
calculated (and some of which is garbage in the letterbox/pillabox
modes).
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 07/15] drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (5 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 06/15] drm/i915/pfit: Extract i965_pfit_get_config() Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 16:05 ` Jani Nikula
2026-10-19 13:53 ` [PATCH 08/15] drm/i915/pfit: Unconfuse panel_fitter_scaling() Ville Syrjala
` (12 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The platform check in the state checker for gmch_pfit.pgm_ratios
is now pointless. gmch_pfit.pgm_ratios will always be 0 on i965+.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 79c4aff1c633..200426bf0c59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5462,9 +5462,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_X(gmch_pfit.control);
- /* pfit ratios are autocomputed by the hw on gen4+ */
- if (DISPLAY_VER(display) < 4)
- PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
+ PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
/*
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 07/15] drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios
2026-10-19 13:53 ` [PATCH 07/15] drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios Ville Syrjala
@ 2026-10-19 16:05 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 16:05 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The platform check in the state checker for gmch_pfit.pgm_ratios
> is now pointless. gmch_pfit.pgm_ratios will always be 0 on i965+.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 79c4aff1c633..200426bf0c59 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5462,9 +5462,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> }
>
> PIPE_CONF_CHECK_X(gmch_pfit.control);
> - /* pfit ratios are autocomputed by the hw on gen4+ */
> - if (DISPLAY_VER(display) < 4)
> - PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
> + PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
> PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>
> /*
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 08/15] drm/i915/pfit: Unconfuse panel_fitter_scaling()
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (6 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 07/15] drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 16:15 ` Jani Nikula
2026-10-19 13:53 ` [PATCH 09/15] drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms Ville Syrjala
` (11 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
panel_fitter_scaling() apparently tries to implemnt
DIV_ROUND_CLOSEST() by hand, but in a somewhat weird way
where the division and rounding are done as separate steps.
Just use the real DIV_ROUND_CLOSEST() instead.
This does in fact match how the i965+ hardware calculates
the automagic scaling factors, which will be important
for upcoming readout support.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 82804159d0a1..5d519f45adbe 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -350,15 +350,7 @@ centre_vertically(struct drm_display_mode *adjusted_mode,
static u32 panel_fitter_scaling(u32 source, u32 target)
{
- /*
- * Floating point operation is not supported. So the FACTOR
- * is defined, which can avoid the floating point computation
- * when calculating the panel ratio.
- */
-#define ACCURACY 12
-#define FACTOR (1 << ACCURACY)
- u32 ratio = source * FACTOR / target;
- return (FACTOR * ratio + FACTOR/2) / FACTOR;
+ return DIV_ROUND_CLOSEST(source << 12, target);
}
static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 08/15] drm/i915/pfit: Unconfuse panel_fitter_scaling()
2026-10-19 13:53 ` [PATCH 08/15] drm/i915/pfit: Unconfuse panel_fitter_scaling() Ville Syrjala
@ 2026-10-19 16:15 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2026-10-19 16:15 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Mon, 19 Oct 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> panel_fitter_scaling() apparently tries to implemnt
*implement
> DIV_ROUND_CLOSEST() by hand, but in a somewhat weird way
> where the division and rounding are done as separate steps.
> Just use the real DIV_ROUND_CLOSEST() instead.
>
> This does in fact match how the i965+ hardware calculates
> the automagic scaling factors, which will be important
> for upcoming readout support.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_pfit.c | 10 +---------
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 82804159d0a1..5d519f45adbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -350,15 +350,7 @@ centre_vertically(struct drm_display_mode *adjusted_mode,
>
> static u32 panel_fitter_scaling(u32 source, u32 target)
> {
> - /*
> - * Floating point operation is not supported. So the FACTOR
> - * is defined, which can avoid the floating point computation
> - * when calculating the panel ratio.
> - */
> -#define ACCURACY 12
> -#define FACTOR (1 << ACCURACY)
> - u32 ratio = source * FACTOR / target;
> - return (FACTOR * ratio + FACTOR/2) / FACTOR;
> + return DIV_ROUND_CLOSEST(source << 12, target);
> }
>
> static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 09/15] drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (7 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 08/15] drm/i915/pfit: Unconfuse panel_fitter_scaling() Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 14:23 ` sashiko-bot
2026-10-19 13:53 ` [PATCH 10/15] drm/i915/pfit: Check scaling factor on GMCH Ville Syrjala
` (10 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Populate crtc_state->pfit.dst on GMCH platforms. Since
(unlike ILK+) we don't actually program the pfit window
coordinates to the hardware we need to compute the coordinates
based on the scaling factor the hardware will use (whether
that'll be the manually programmed thing on pre-i965 or
the automagic thing on i965+). As long as we do the computation
the same way .compute_config() and readout we'll get matching
results, which is important to the state checker.
Note that the automagic scaling factors on i965+ are slightly
weird in that only one of the scaling factors in the register
will read out correctly in the letterbox/pillabox modes. So
the readout will have to know which direction has the correct
information.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_crtc_state_dump.c | 10 +-
drivers/gpu/drm/i915/display/intel_pfit.c | 231 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_pfit.h | 2 +
.../gpu/drm/i915/display/intel_pfit_regs.h | 4 +-
4 files changed, 184 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index f30d07bc6b07..9220c73d2f5e 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -355,11 +355,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
pipe_config->gmch_pfit.control,
pipe_config->gmch_pfit.pgm_ratios,
pipe_config->gmch_pfit.lvds_border_bits);
- else
- drm_printf(&p, "pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
- DRM_RECT_ARG(&pipe_config->pfit.dst),
- str_enabled_disabled(pipe_config->pfit.enabled),
- str_yes_no(pipe_config->pfit.force_thru));
+
+ drm_printf(&p, "pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+ DRM_RECT_ARG(&pipe_config->pfit.dst),
+ str_enabled_disabled(pipe_config->pfit.enabled),
+ str_yes_no(pipe_config->pfit.force_thru));
drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
pipe_config->pfit.casf.strength,
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 5d519f45adbe..63e5a656a33b 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -353,6 +353,35 @@ static u32 panel_fitter_scaling(u32 source, u32 target)
return DIV_ROUND_CLOSEST(source << 12, target);
}
+static void i9xx_compute_pfit_dst(struct intel_crtc_state *crtc_state,
+ u32 hscale, u32 vscale)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
+ int x, y, width, height;
+
+ /* don't explode if the hw state was gibberish */
+ if (hscale == 0)
+ hscale = 1 << 12;
+ if (vscale == 0)
+ vscale = 1 << 12;
+
+ width = DIV_ROUND_CLOSEST(pipe_src_w << 12, hscale);
+ height = DIV_ROUND_CLOSEST(pipe_src_h << 12, vscale);
+
+ width = min(width, adjusted_mode->crtc_hdisplay);
+ height = min(height, adjusted_mode->crtc_vdisplay);
+
+ x = DIV_ROUND_CLOSEST(adjusted_mode->crtc_hdisplay - width, 2);
+ y = DIV_ROUND_CLOSEST(adjusted_mode->crtc_vdisplay - height, 2);
+
+ crtc_state->pfit.enabled = true;
+
+ drm_rect_init(&crtc_state->pfit.dst, x, y, width, height);
+}
+
static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
u32 *pfit_control)
{
@@ -362,16 +391,54 @@ static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
+ u32 hscale, vscale;
/* 965+ is easy, it does everything in hw */
- if (scaled_width > scaled_height)
+ if (scaled_width > scaled_height) {
*pfit_control |= PFIT_ENABLE |
PFIT_SCALING_PILLAR;
- else if (scaled_width < scaled_height)
+
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+ hscale = vscale;
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
+ } else if (scaled_width < scaled_height) {
*pfit_control |= PFIT_ENABLE |
PFIT_SCALING_LETTER;
- else if (adjusted_mode->crtc_hdisplay != pipe_src_w)
+
+ hscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ vscale = hscale;
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
+ } else if (adjusted_mode->crtc_hdisplay != pipe_src_w) {
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
+
+ hscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
+ }
+}
+
+static void i965_scale_fullscreen(struct intel_crtc_state *crtc_state,
+ u32 *pfit_control)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
+ u32 hscale, vscale;
+
+ if (pipe_src_h == adjusted_mode->crtc_vdisplay &&
+ pipe_src_w == adjusted_mode->crtc_hdisplay)
+ return;
+
+ *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
+
+ hscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
@@ -383,7 +450,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
- u32 bits;
+ u32 hscale, vscale;
/*
* For earlier chips we have to calculate the scaling
@@ -396,14 +463,16 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
*border = LVDS_BORDER_ENABLE;
if (pipe_src_h != adjusted_mode->crtc_vdisplay) {
- bits = panel_fitter_scaling(pipe_src_h,
- adjusted_mode->crtc_vdisplay);
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+ hscale = vscale;
- *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
- PFIT_VERT_SCALE(bits));
+ *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(hscale) |
+ PFIT_VERT_SCALE(vscale));
*pfit_control |= (PFIT_ENABLE |
PFIT_VERT_INTERP_BILINEAR |
PFIT_HORIZ_INTERP_BILINEAR);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
} else if (scaled_width < scaled_height) { /* letter */
centre_vertically(adjusted_mode,
@@ -411,14 +480,16 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
*border = LVDS_BORDER_ENABLE;
if (pipe_src_w != adjusted_mode->crtc_hdisplay) {
- bits = panel_fitter_scaling(pipe_src_w,
- adjusted_mode->crtc_hdisplay);
+ vscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ hscale = vscale;
- *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
- PFIT_VERT_SCALE(bits));
+ *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(hscale) |
+ PFIT_VERT_SCALE(vscale));
*pfit_control |= (PFIT_ENABLE |
PFIT_VERT_INTERP_BILINEAR |
PFIT_HORIZ_INTERP_BILINEAR);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
} else {
/* Aspects match, Let hw scale both directions */
@@ -427,9 +498,40 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
PFIT_HORIZ_AUTO_SCALE |
PFIT_VERT_INTERP_BILINEAR |
PFIT_HORIZ_INTERP_BILINEAR);
+
+ hscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
}
+static void i9xx_scale_fullscreen(struct intel_crtc_state *crtc_state,
+ u32 *pfit_control, u32 *pfit_pgm_ratios,
+ u32 *border)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
+ u32 hscale, vscale;
+
+ if (pipe_src_h == adjusted_mode->crtc_vdisplay &&
+ pipe_src_w == adjusted_mode->crtc_hdisplay)
+ return;
+
+ *pfit_control |= (PFIT_ENABLE |
+ PFIT_VERT_AUTO_SCALE |
+ PFIT_HORIZ_AUTO_SCALE |
+ PFIT_VERT_INTERP_BILINEAR |
+ PFIT_HORIZ_INTERP_BILINEAR);
+
+ hscale = panel_fitter_scaling(pipe_src_w, adjusted_mode->crtc_hdisplay);
+ vscale = panel_fitter_scaling(pipe_src_h, adjusted_mode->crtc_vdisplay);
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
+}
+
static int i9xx_pfit_check_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -478,27 +580,18 @@ static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
adjusted_mode->crtc_vdisplay == pipe_src_h)
goto out;
- /*
- * TODO: implement downscaling for i965+. Need to account
- * for downscaling in intel_crtc_compute_pixel_rate().
- */
- if (adjusted_mode->crtc_hdisplay < pipe_src_w) {
- drm_dbg_kms(display->drm,
- "[CRTC:%d:%s] pfit horizontal downscaling (%d->%d) not supported\n",
- crtc->base.base.id, crtc->base.name,
- pipe_src_w, adjusted_mode->crtc_hdisplay);
- return -EINVAL;
- }
- if (adjusted_mode->crtc_vdisplay < pipe_src_h) {
- drm_dbg_kms(display->drm,
- "[CRTC:%d:%s] pfit vertical downscaling (%d->%d) not supported\n",
- crtc->base.base.id, crtc->base.name,
- pipe_src_h, adjusted_mode->crtc_vdisplay);
- return -EINVAL;
- }
-
switch (conn_state->scaling_mode) {
case DRM_MODE_SCALE_CENTER:
+ if (adjusted_mode->crtc_hdisplay < pipe_src_w ||
+ adjusted_mode->crtc_vdisplay < pipe_src_h) {
+ drm_dbg_kms(display->drm,
+ "[CRTC:%d:%s] pfit center mode source (%dx%d) exceeds display (%dx%d)\n",
+ crtc->base.base.id, crtc->base.name,
+ pipe_src_w, pipe_src_h,
+ adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_vdisplay);
+ return -EINVAL;
+ }
/*
* For centered modes, we have to calculate border widths &
* heights and modify the values programmed into the CRTC.
@@ -516,21 +609,11 @@ static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
&pfit_pgm_ratios, &border);
break;
case DRM_MODE_SCALE_FULLSCREEN:
- /*
- * Full scaling, even if it changes the aspect ratio.
- * Fortunately this is all done for us in hw.
- */
- if (pipe_src_h != adjusted_mode->crtc_vdisplay ||
- pipe_src_w != adjusted_mode->crtc_hdisplay) {
- pfit_control |= PFIT_ENABLE;
- if (DISPLAY_VER(display) >= 4)
- pfit_control |= PFIT_SCALING_AUTO;
- else
- pfit_control |= (PFIT_VERT_AUTO_SCALE |
- PFIT_VERT_INTERP_BILINEAR |
- PFIT_HORIZ_AUTO_SCALE |
- PFIT_HORIZ_INTERP_BILINEAR);
- }
+ if (DISPLAY_VER(display) >= 4)
+ i965_scale_fullscreen(crtc_state, &pfit_control);
+ else
+ i9xx_scale_fullscreen(crtc_state, &pfit_control,
+ &pfit_pgm_ratios, &border);
break;
default:
MISSING_CASE(conn_state->scaling_mode);
@@ -716,19 +799,39 @@ static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ u32 hscale, vscale, control, ratios;
enum pipe pipe;
- u32 tmp;
- tmp = intel_de_read(display, PFIT_CONTROL(display));
- if (!(tmp & PFIT_ENABLE))
+ control = intel_de_read(display, PFIT_CONTROL(display));
+ if (!(control & PFIT_ENABLE))
return;
/* Check whether the pfit is attached to our pipe. */
- pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
+ pipe = REG_FIELD_GET(PFIT_PIPE_MASK, control);
if (pipe != crtc->pipe)
return;
- crtc_state->gmch_pfit.control = tmp;
+ crtc_state->gmch_pfit.control = control;
+
+ ratios = intel_de_read(display, PFIT_PGM_RATIOS(display));
+
+ switch (control & PFIT_SCALING_MASK) {
+ case PFIT_SCALING_LETTER:
+ hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK_965, ratios);
+ vscale = hscale; /* PFIT_VERT_SCALE_MASK_965 contains garbage */
+ break;
+ case PFIT_SCALING_PILLAR:
+ vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, ratios);
+ hscale = vscale; /* PFIT_HORIZ_SCALE_MASK_965 contains garbage */
+ break;
+ case PFIT_SCALING_AUTO:
+ case PFIT_SCALING_PROGRAMMED:
+ hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK_965, ratios);
+ vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, ratios);
+ break;
+ }
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
static bool i9xx_has_pfit(struct intel_crtc *crtc)
@@ -748,18 +851,32 @@ static void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- u32 tmp;
+ u32 hscale, vscale, control, ratios;
if (!i9xx_has_pfit(crtc))
return;
- tmp = intel_de_read(display, PFIT_CONTROL(display));
- if (!(tmp & PFIT_ENABLE))
+ control = intel_de_read(display, PFIT_CONTROL(display));
+ if (!(control & PFIT_ENABLE))
return;
- crtc_state->gmch_pfit.control = tmp;
- crtc_state->gmch_pfit.pgm_ratios =
- intel_de_read(display, PFIT_PGM_RATIOS(display));
+ crtc_state->gmch_pfit.control = control;
+
+ ratios = intel_de_read(display, PFIT_AUTO_RATIOS(display));
+ if (control & PFIT_HORIZ_AUTO_SCALE)
+ hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK, ratios);
+ if (control & PFIT_VERT_AUTO_SCALE)
+ vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, ratios);
+
+ ratios = intel_de_read(display, PFIT_PGM_RATIOS(display));
+ if ((control & PFIT_HORIZ_AUTO_SCALE) == 0)
+ hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK, ratios);
+ if ((control & PFIT_VERT_AUTO_SCALE) == 0)
+ vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, ratios);
+
+ crtc_state->gmch_pfit.pgm_ratios = ratios;
+
+ i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h b/drivers/gpu/drm/i915/display/intel_pfit.h
index 184e1932eae5..f1162b37d407 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.h
+++ b/drivers/gpu/drm/i915/display/intel_pfit.h
@@ -6,6 +6,8 @@
#ifndef __INTEL_PFIT_H__
#define __INTEL_PFIT_H__
+#include <linux/types.h>
+
enum drm_mode_status;
struct drm_display_mode;
struct drm_connector_state;
diff --git a/drivers/gpu/drm/i915/display/intel_pfit_regs.h b/drivers/gpu/drm/i915/display/intel_pfit_regs.h
index add8ce28004e..a83ac3b20ca3 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_pfit_regs.h
@@ -34,9 +34,11 @@
#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
+#define PFIT_VERT_SCALE_965(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK_965, (x))
#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
+#define PFIT_HORIZ_SCALE_965(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK_965, (x))
-#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
+#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) /* pre-965 */
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 09/15] drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms
2026-10-19 13:53 ` [PATCH 09/15] drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms Ville Syrjala
@ 2026-10-19 14:23 ` sashiko-bot
0 siblings, 0 replies; 33+ messages in thread
From: sashiko-bot @ 2026-10-19 14:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/pfit: uninitialized hscale and vscale in i965_pfit_get_config()
--
commit 1baf5f8a446b17a6276479fa9824e29481b05caf
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms
This commit populates crtc_state->pfit.dst on GMCH platforms by computing
the destination window coordinates from the horizontal and vertical panel
fitter scaling factors during both config computation and hardware readout.
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 5d519f45adbec..63e5a656a33b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
[ ... ]
> @@ -716,19 +799,39 @@ static void i965_pfit_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + u32 hscale, vscale, control, ratios;
> enum pipe pipe;
> - u32 tmp;
>
> - tmp = intel_de_read(display, PFIT_CONTROL(display));
> - if (!(tmp & PFIT_ENABLE))
> + control = intel_de_read(display, PFIT_CONTROL(display));
> + if (!(control & PFIT_ENABLE))
> return;
>
> /* Check whether the pfit is attached to our pipe. */
> - pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, control);
> if (pipe != crtc->pipe)
> return;
>
> - crtc_state->gmch_pfit.control = tmp;
> + crtc_state->gmch_pfit.control = control;
> +
> + ratios = intel_de_read(display, PFIT_PGM_RATIOS(display));
> +
> + switch (control & PFIT_SCALING_MASK) {
> + case PFIT_SCALING_LETTER:
> + hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK_965, ratios);
> + vscale = hscale; /* PFIT_VERT_SCALE_MASK_965 contains garbage */
> + break;
> + case PFIT_SCALING_PILLAR:
> + vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, ratios);
> + hscale = vscale; /* PFIT_HORIZ_SCALE_MASK_965 contains garbage */
> + break;
> + case PFIT_SCALING_AUTO:
> + case PFIT_SCALING_PROGRAMMED:
> + hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK_965, ratios);
> + vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, ratios);
> + break;
> + }
> +
> + i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
> }
[Severity: Medium]
Can hscale and vscale be used uninitialized in i965_pfit_get_config()?
In drivers/gpu/drm/i915/display/intel_pfit_regs.h, PFIT_SCALING_MASK is a
3-bit mask with 8 possible values, while only 4 constants (0..3) are
defined:
#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
Since the switch in intel_pfit_get_config() -> i965_pfit_get_config() has no
default case and hscale and vscale are not initialized at declaration, could
a reserved value in PFIT_CONTROL pass uninitialized stack values into
i9xx_compute_pfit_dst() (and trigger compiler uninitialized-variable
warnings)?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261019135309.23578-1-ville.syrjala@linux.intel.com?part=9
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 10/15] drm/i915/pfit: Check scaling factor on GMCH
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (8 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 09/15] drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 13:53 ` [PATCH 11/15] drm/i915/pfit: Check panel fitter source size " Ville Syrjala
` (9 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure the pfit scaling factor is legal on GMCH platforms.
For now we'll limit all platforms to upscaling only, even
though i965+ can actually downscale.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 40 +++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 63e5a656a33b..5c2e7fdb93cc 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -532,6 +532,42 @@ static void i9xx_scale_fullscreen(struct intel_crtc_state *crtc_state,
i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
+static int i9xx_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_rect *dst = &crtc_state->pfit.dst;
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
+ int hscale, vscale, max_scale;
+ struct drm_rect src;
+
+ max_scale = 0x10000;
+
+ drm_rect_init(&src, 0, 0, pipe_src_w << 16, pipe_src_h << 16);
+
+ hscale = drm_rect_calc_hscale(&src, dst, 0, max_scale);
+ if (hscale < 0) {
+ drm_dbg_kms(display->drm,
+ "[CRTC:%d:%s] pfit horizontal downscaling (%d->%d) exceeds max (0x%x)\n",
+ crtc->base.base.id, crtc->base.name,
+ pipe_src_w, drm_rect_width(dst),
+ max_scale);
+ return hscale;
+ }
+
+ vscale = drm_rect_calc_vscale(&src, dst, 0, max_scale);
+ if (vscale < 0) {
+ drm_dbg_kms(display->drm,
+ "[CRTC:%d:%s] pfit vertical downscaling (%d->%d) exceeds max (0x%x)\n",
+ crtc->base.base.id, crtc->base.name,
+ pipe_src_h, drm_rect_height(dst),
+ max_scale);
+ return vscale;
+ }
+
+ return 0;
+}
static int i9xx_pfit_check_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -642,6 +678,10 @@ static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
if ((pfit_control & PFIT_ENABLE) == 0)
return 0;
+ ret = i9xx_pfit_check_scaling(crtc_state);
+ if (ret)
+ return ret;
+
ret = i9xx_pfit_check_timings(crtc_state);
if (ret)
return ret;
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 11/15] drm/i915/pfit: Check panel fitter source size on GMCH
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (9 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 10/15] drm/i915/pfit: Check scaling factor on GMCH Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 13:53 ` [PATCH 12/15] drm/i915/pfit: Extract i9xx_pfit_vscale_ratio() and i9xx_pfit_is_one_line_mode() Ville Syrjala
` (8 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The GMCH panel fitter is limited to <=2048 pixel wide
sources. Check for that.
There doesn't really seem to be any vertical limit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 5c2e7fdb93cc..d94301c80d57 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -532,6 +532,27 @@ static void i9xx_scale_fullscreen(struct intel_crtc_state *crtc_state,
i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
}
+static int i9xx_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int max_src_w;
+
+ /* Not sure there is any vertical limit */
+ max_src_w = 2048;
+
+ if (pipe_src_w > max_src_w) {
+ drm_dbg_kms(display->drm,
+ "[CRTC:%d:%s] source width %d exceeds pfit max %d\n",
+ crtc->base.base.id, crtc->base.name,
+ pipe_src_w, max_src_w);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -678,6 +699,10 @@ static int i9xx_pfit_compute_config(struct intel_crtc_state *crtc_state,
if ((pfit_control & PFIT_ENABLE) == 0)
return 0;
+ ret = i9xx_pfit_check_src_size(crtc_state);
+ if (ret)
+ return ret;
+
ret = i9xx_pfit_check_scaling(crtc_state);
if (ret)
return ret;
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 12/15] drm/i915/pfit: Extract i9xx_pfit_vscale_ratio() and i9xx_pfit_is_one_line_mode()
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (10 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 11/15] drm/i915/pfit: Check panel fitter source size " Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 13:53 ` [PATCH 13/15] drm/i915/pfit: No pfit one line mode on i965+ Ville Syrjala
` (7 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the raw pfit stuff from the overlay code into intel_pfit.c.
For now we'll stick to the "read registers" approach in
i9xx_pfit_vscale_ratio(), but really we should just use precomputed
values there...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_overlay.c | 31 ++++----------------
drivers/gpu/drm/i915/display/intel_pfit.c | 30 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_pfit.h | 3 ++
3 files changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index a809aa2950ac..822eef96ea37 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -37,7 +37,7 @@
#include "intel_frontbuffer.h"
#include "intel_overlay.h"
#include "intel_parent.h"
-#include "intel_pfit_regs.h"
+#include "intel_pfit.h"
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
@@ -614,28 +614,8 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
{
struct intel_display *display = overlay->display;
- u32 ratio;
- /* XXX: This is not the same logic as in the xorg driver, but more in
- * line with the intel documentation for the i965
- */
- if (DISPLAY_VER(display) >= 4) {
- u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
-
- /* on i965 use the PGM reg to read out the autoscaler values */
- ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
- } else {
- u32 tmp;
-
- if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)
- tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
- else
- tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
-
- ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
- }
-
- overlay->pfit_vscale_ratio = ratio;
+ overlay->pfit_vscale_ratio = i9xx_pfit_vscale_ratio(display);
}
static int check_overlay_dst(struct intel_overlay *overlay,
@@ -838,13 +818,12 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
overlay->crtc = crtc;
crtc->overlay = overlay;
- /* line too wide, i.e. one-line-mode */
- if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&
- crtc->config->gmch_pfit.control & PFIT_ENABLE) {
+ if (i9xx_pfit_is_one_line_mode(crtc->config)) {
overlay->pfit_active = true;
update_pfit_vscale_ratio(overlay);
- } else
+ } else {
overlay->pfit_active = false;
+ }
}
ret = check_overlay_dst(overlay, params);
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index d94301c80d57..d8daa463452e 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -960,3 +960,33 @@ void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
ilk_pfit_get_config(crtc_state);
}
}
+
+bool i9xx_pfit_is_one_line_mode(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->gmch_pfit.control & PFIT_ENABLE &&
+ drm_rect_width(&crtc_state->pipe_src) > 1024;
+}
+
+u32 i9xx_pfit_vscale_ratio(struct intel_display *display)
+{
+ /* XXX: This is not the same logic as in the xorg driver, but more in
+ * line with the intel documentation for the i965
+ *
+ * FIXME don't read this from the hardware but use a computed value
+ */
+ if (DISPLAY_VER(display) >= 4) {
+ u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
+
+ /* on i965 use the PGM reg to read out the autoscaler values */
+ return REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
+ } else {
+ u32 tmp;
+
+ if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)
+ tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
+ else
+ tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
+
+ return REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h b/drivers/gpu/drm/i915/display/intel_pfit.h
index f1162b37d407..e6cd3af2e2a4 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.h
+++ b/drivers/gpu/drm/i915/display/intel_pfit.h
@@ -27,4 +27,7 @@ intel_pfit_mode_valid(struct intel_display *display,
const struct drm_display_mode *mode,
enum intel_output_format output_format,
int num_joined_pipes);
+bool i9xx_pfit_is_one_line_mode(const struct intel_crtc_state *crtc_state);
+u32 i9xx_pfit_vscale_ratio(struct intel_display *display);
+
#endif /* __INTEL_PFIT_H__ */
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 13/15] drm/i915/pfit: No pfit one line mode on i965+
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (11 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 12/15] drm/i915/pfit: Extract i9xx_pfit_vscale_ratio() and i9xx_pfit_is_one_line_mode() Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 13:53 ` [PATCH 14/15] drm/i915/pfit: Account for pfit downscaling in pixel rate on GMCH platforms Ville Syrjala
` (6 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
i965+ panel fitter no longer appaers to have the "one line mode"
fallback for wide sources. Presumably the line buffers are now
big enough that the one line mode is not needed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index d8daa463452e..6eb457047bf4 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -963,7 +963,10 @@ void intel_pfit_get_config(struct intel_crtc_state *crtc_state)
bool i9xx_pfit_is_one_line_mode(const struct intel_crtc_state *crtc_state)
{
- return crtc_state->gmch_pfit.control & PFIT_ENABLE &&
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return DISPLAY_VER(display) < 4 &&
+ crtc_state->gmch_pfit.control & PFIT_ENABLE &&
drm_rect_width(&crtc_state->pipe_src) > 1024;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 14/15] drm/i915/pfit: Account for pfit downscaling in pixel rate on GMCH platforms
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (12 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 13/15] drm/i915/pfit: No pfit one line mode on i965+ Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 13:53 ` [PATCH 15/15] drm/i915/pfit: Allow downscaling on i966+ Ville Syrjala
` (5 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that we have crtc_state->pch.dst populated on GMCH platforms
we can use the existing ILK+ code to calculate the downscale
adjusted pixel rate correctly on GMCH platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++-------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 200426bf0c59..6b813efff955 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2278,7 +2278,8 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
(crtc->pipe == PIPE_A || display->platform.i915g);
}
-static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
+static unsigned int
+intel_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
struct drm_rect src;
@@ -2299,7 +2300,8 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
pixel_rate);
}
-static u32 ilk_pipe_pixel_rate_cdclk(const struct intel_crtc_state *crtc_state)
+static unsigned int
+intel_pipe_pixel_rate_cdclk(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
@@ -2345,19 +2347,10 @@ static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- if (HAS_GMCH(display)) {
- /* FIXME calculate proper pipe pixel rate for GMCH pfit */
- crtc_state->pixel_rate =
- crtc_state->hw.pipe_mode.crtc_clock;
- crtc_state->pixel_rate_cdclk = crtc_state->pixel_rate;
- } else {
- crtc_state->pixel_rate =
- ilk_pipe_pixel_rate(crtc_state);
- crtc_state->pixel_rate_cdclk =
- ilk_pipe_pixel_rate_cdclk(crtc_state);
- }
+ crtc_state->pixel_rate =
+ intel_pipe_pixel_rate(crtc_state);
+ crtc_state->pixel_rate_cdclk =
+ intel_pipe_pixel_rate_cdclk(crtc_state);
}
static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 15/15] drm/i915/pfit: Allow downscaling on i966+
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (13 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 14/15] drm/i915/pfit: Account for pfit downscaling in pixel rate on GMCH platforms Ville Syrjala
@ 2026-10-19 13:53 ` Ville Syrjala
2026-10-19 14:47 ` sashiko-bot
2026-10-19 14:01 ` ✗ CI.checkpatch: warning for drm/i915/pfit: Make GMCH panel fitter nicer Patchwork
` (4 subsequent siblings)
19 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjala @ 2026-10-19 13:53 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The i965+ panel fitter supports downscaling. Allow it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 6eb457047bf4..2b6706c7af53 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -563,7 +563,10 @@ static int i9xx_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
int hscale, vscale, max_scale;
struct drm_rect src;
- max_scale = 0x10000;
+ if (DISPLAY_VER(display) >= 4)
+ max_scale = 0x20000;
+ else
+ max_scale = 0x10000;
drm_rect_init(&src, 0, 0, pipe_src_w << 16, pipe_src_h << 16);
--
2.55.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 15/15] drm/i915/pfit: Allow downscaling on i966+
2026-10-19 13:53 ` [PATCH 15/15] drm/i915/pfit: Allow downscaling on i966+ Ville Syrjala
@ 2026-10-19 14:47 ` sashiko-bot
0 siblings, 0 replies; 33+ messages in thread
From: sashiko-bot @ 2026-10-19 14:47 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/pfit: off-by-one max_scale in i9xx_pfit_check_scaling()
--
commit c5496f644982a254aa09057b7c02f1bea3cb5b18
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/i915/pfit: Allow downscaling on i966+
This commit updates i9xx_pfit_check_scaling() to raise max_scale to 0x20000 on
DISPLAY_VER(display) >= 4 platforms to permit panel fitter downscaling.
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 6eb457047bf4c..2b6706c7af534 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -563,7 +563,10 @@ static int i9xx_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
> int hscale, vscale, max_scale;
> struct drm_rect src;
>
> - max_scale = 0x10000;
> + if (DISPLAY_VER(display) >= 4)
> + max_scale = 0x20000;
> + else
> + max_scale = 0x10000;
>
> drm_rect_init(&src, 0, 0, pipe_src_w << 16, pipe_src_h << 16);
>
[Severity: Medium]
Should max_scale be 0x20000 - 1 (or 0x1fff0) rather than 0x20000 here?
In i9xx_pfit_check_scaling(), max_scale is passed to drm_rect_calc_hscale()
and drm_rect_calc_vscale(), which treat max_hscale and max_vscale as inclusive
upper bounds and only reject with -ERANGE when scale > max_scale. Setting
max_scale = 0x20000 allows an exact 2.0x downscale factor (for example, when
scaling a 1600x1200 pipe_src to an 800x600 dst).
However, in drivers/gpu/drm/i915/display/intel_pfit_regs.h, the i965+ scaling
ratio fields in PFIT_PGM_RATIOS are 13-bit 1.12 fixed-point values:
#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
#define PFIT_VERT_SCALE_965(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK_965, (x))
#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
#define PFIT_HORIZ_SCALE_965(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK_965, (x))
These 13-bit fields have a maximum representable value of 0x1fff (< 2.0). For
an exact 2.0x downscale, panel_fitter_scaling() computes 0x2000 (BIT(13)),
which overflows the 13-bit register field and causes a hardware state readout
mismatch in i965_pfit_get_config() -> i9xx_compute_pfit_dst() on
crtc_state->pfit.dst and pixel_rate:
drivers/gpu/drm/i915/display/intel_pfit.c:i965_pfit_get_config() {
...
case PFIT_SCALING_AUTO:
case PFIT_SCALING_PROGRAMMED:
hscale = REG_FIELD_GET(PFIT_HORIZ_SCALE_MASK_965, ratios);
vscale = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, ratios);
break;
}
i9xx_compute_pfit_dst(crtc_state, hscale, vscale);
...
}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261019135309.23578-1-ville.syrjala@linux.intel.com?part=15
^ permalink raw reply [flat|nested] 33+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/pfit: Make GMCH panel fitter nicer
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (14 preceding siblings ...)
2026-10-19 13:53 ` [PATCH 15/15] drm/i915/pfit: Allow downscaling on i966+ Ville Syrjala
@ 2026-10-19 14:01 ` Patchwork
2026-10-19 14:04 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2026-10-19 14:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/pfit: Make GMCH panel fitter nicer
URL : https://patchwork.freedesktop.org/series/176401/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6bef5ce5c74dc76b4ee69ab2832c0d1fd63c91c7
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit dfacdea70d3fa1c83815eefbf837b1cd86e6335c
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Oct 19 16:53:09 2026 +0300
drm/i915/pfit: Allow downscaling on i966+
The i965+ panel fitter supports downscaling. Allow it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch a16b0e27155a8187d222dc914932a2d244d254b2 drm-intel
52589fd94ad9 drm/i915/pfit: s/pch_pfit/pfit/
-:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#104: FILE: drivers/gpu/drm/i915/display/intel_casf.c:237:
+ convert_sharpness_coeff_binary(&crtc_state->pfit.casf.coeff[i],
filter_coeff[i]);
total: 0 errors, 0 warnings, 1 checks, 433 lines checked
7f63c170b3ab drm/i915/pfit: s/intel_pch_pfit/ilk_pfit/
160a095ba66e drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places
bbecbc9bc4a3 drm/i915/pfit: Introduce intel_pfit_get_config()
3e16ce61ff58 drm/i915/pfit: Rename some pfit functions
84538a9688bd drm/i915/pfit: Extract i965_pfit_get_config()
adf000edc24e drm/i915/pfit: Drop platform check for gmch_pfit.pgm_ratios
a40b5002e278 drm/i915/pfit: Unconfuse panel_fitter_scaling()
d43794005bec drm/i915/pfit: Populate crtc_state->pfit.dst on GMCH platforms
590e407b52a3 drm/i915/pfit: Check scaling factor on GMCH
4559f8434e8f drm/i915/pfit: Check panel fitter source size on GMCH
42d854a9bcb7 drm/i915/pfit: Extract i9xx_pfit_vscale_ratio() and i9xx_pfit_is_one_line_mode()
-:104: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#104: FILE: drivers/gpu/drm/i915/display/intel_pfit.c:982:
+ return REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
+ } else {
total: 0 errors, 1 warnings, 0 checks, 93 lines checked
38082aacfe92 drm/i915/pfit: No pfit one line mode on i965+
cba24780688a drm/i915/pfit: Account for pfit downscaling in pixel rate on GMCH platforms
dfacdea70d3f drm/i915/pfit: Allow downscaling on i966+
^ permalink raw reply [flat|nested] 33+ messages in thread* ✓ CI.KUnit: success for drm/i915/pfit: Make GMCH panel fitter nicer
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (15 preceding siblings ...)
2026-10-19 14:01 ` ✗ CI.checkpatch: warning for drm/i915/pfit: Make GMCH panel fitter nicer Patchwork
@ 2026-10-19 14:04 ` Patchwork
2026-10-19 14:45 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2026-10-19 14:04 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/pfit: Make GMCH panel fitter nicer
URL : https://patchwork.freedesktop.org/series/176401/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[14:01:58] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:02:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:02:23] Starting KUnit Kernel (1/1)...
[14:02:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:02:23] ================= gpu_buddy (14 subtests) ==================
[14:02:23] [PASSED] gpu_test_buddy_alloc_limit
[14:02:23] [PASSED] gpu_test_buddy_alloc_optimistic
[14:02:23] [PASSED] gpu_test_buddy_alloc_pessimistic
[14:02:23] [PASSED] gpu_test_buddy_alloc_pathological
[14:02:23] [PASSED] gpu_test_buddy_alloc_contiguous
[14:02:23] [PASSED] gpu_test_buddy_alloc_clear
[14:02:23] [PASSED] gpu_test_buddy_alloc_range
[14:02:23] [PASSED] gpu_test_buddy_alloc_range_bias
[14:02:24] [PASSED] gpu_test_buddy_fragmentation_performance
[14:02:25] [PASSED] gpu_test_buddy_dirty_tracker_performance
[14:02:25] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[14:02:25] [PASSED] gpu_test_buddy_offset_aligned_allocation
[14:02:25] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[14:02:25] [PASSED] gpu_test_buddy_addr_to_block
[14:02:25] ==================== [PASSED] gpu_buddy ====================
[14:02:25] ============================================================
[14:02:25] Testing complete. Ran 14 tests: passed: 14
[14:02:25] Elapsed time: 27.208s total, 4.439s configuring, 20.650s building, 2.050s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:02:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:02:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:03:07] Starting KUnit Kernel (1/1)...
[14:03:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:03:07] ================== guc_buf (11 subtests) ===================
[14:03:07] [PASSED] test_smallest
[14:03:07] [PASSED] test_largest
[14:03:07] [PASSED] test_granular
[14:03:07] [PASSED] test_unique
[14:03:07] [PASSED] test_overlap
[14:03:07] [PASSED] test_reusable
[14:03:07] [PASSED] test_too_big
[14:03:07] [PASSED] test_flush
[14:03:07] [PASSED] test_lookup
[14:03:07] [PASSED] test_data
[14:03:07] [PASSED] test_class
[14:03:07] ===================== [PASSED] guc_buf =====================
[14:03:07] =================== guc_dbm (7 subtests) ===================
[14:03:07] [PASSED] test_empty
[14:03:07] [PASSED] test_default
[14:03:07] ======================== test_size ========================
[14:03:07] [PASSED] 4
[14:03:07] [PASSED] 8
[14:03:07] [PASSED] 32
[14:03:07] [PASSED] 256
[14:03:07] ==================== [PASSED] test_size ====================
[14:03:07] ======================= test_reuse ========================
[14:03:07] [PASSED] 4
[14:03:07] [PASSED] 8
[14:03:07] [PASSED] 32
[14:03:07] [PASSED] 256
[14:03:07] =================== [PASSED] test_reuse ====================
[14:03:07] =================== test_range_overlap ====================
[14:03:07] [PASSED] 4
[14:03:07] [PASSED] 8
[14:03:07] [PASSED] 32
[14:03:07] [PASSED] 256
[14:03:07] =============== [PASSED] test_range_overlap ================
[14:03:07] =================== test_range_compact ====================
[14:03:07] [PASSED] 4
[14:03:07] [PASSED] 8
[14:03:07] [PASSED] 32
[14:03:07] [PASSED] 256
[14:03:07] =============== [PASSED] test_range_compact ================
[14:03:07] ==================== test_range_spare =====================
[14:03:07] [PASSED] 4
[14:03:07] [PASSED] 8
[14:03:07] [PASSED] 32
[14:03:07] [PASSED] 256
[14:03:07] ================ [PASSED] test_range_spare =================
[14:03:07] ===================== [PASSED] guc_dbm =====================
[14:03:07] ================== guc_idm (22 subtests) ===================
[14:03:07] [PASSED] bad_init
[14:03:07] [PASSED] no_init
[14:03:07] [PASSED] init_fini
[14:03:07] [PASSED] check_init_small
[14:03:07] [PASSED] check_init_shared
[14:03:07] [PASSED] check_used
[14:03:07] [PASSED] check_quota
[14:03:07] [PASSED] check_all
[14:03:07] [PASSED] check_limits
[14:03:07] [PASSED] check_overlap
[14:03:07] [PASSED] check_overlap_alloc
[14:03:07] [PASSED] check_overlap_release
[14:03:07] [PASSED] check_overlap_partial_init
[14:03:07] [PASSED] check_overlap_partial_shared_range_blocking
[14:03:07] [PASSED] check_used_usable
[14:03:07] [PASSED] check_used_shareable
[14:03:07] [PASSED] check_used_mixed
[14:03:07] [PASSED] check_release_usable_range
[14:03:07] [PASSED] check_release_shareable_range
[14:03:07] [PASSED] check_split_boundaries
[14:03:07] [PASSED] check_shareable_spare
[14:03:07] [PASSED] check_shareable_spare_fragmented_tail
[14:03:07] ===================== [PASSED] guc_idm =====================
[14:03:07] ============== guc_klv_helpers (13 subtests) ===============
[14:03:07] [PASSED] test_count
[14:03:07] [PASSED] test_encode_u32
[14:03:07] [PASSED] test_encode_u64
[14:03:07] [PASSED] test_encode_string
[14:03:07] [PASSED] test_encode_object_raw
[14:03:07] [PASSED] test_encode_object_klv
[14:03:07] [PASSED] test_encode_object_nested
[14:03:07] [PASSED] test_encode_object_basic
[14:03:07] ===================== test_decode_u16 =====================
[14:03:07] [PASSED] empty
[14:03:07] [PASSED] valid
[14:03:07] [PASSED] max
[14:03:07] [PASSED] big
[14:03:07] [PASSED] long
[14:03:07] ================= [PASSED] test_decode_u16 =================
[14:03:07] ===================== test_decode_u32 =====================
[14:03:07] [PASSED] empty
[14:03:07] [PASSED] valid
[14:03:07] [PASSED] max
[14:03:07] [PASSED] long
[14:03:07] ================= [PASSED] test_decode_u32 =================
[14:03:07] ===================== test_decode_u64 =====================
[14:03:07] [PASSED] empty
[14:03:07] [PASSED] short
[14:03:07] [PASSED] valid
[14:03:07] [PASSED] max
[14:03:07] [PASSED] long
[14:03:07] ================= [PASSED] test_decode_u64 =================
[14:03:07] ===================== test_decode_str =====================
[14:03:07] [PASSED] empty
[14:03:07] [PASSED] one
[14:03:07] [PASSED] one_trash
[14:03:07] [PASSED] two
[14:03:07] [PASSED] two_trash
[14:03:07] [PASSED] three
[14:03:07] [PASSED] dword
[14:03:07] [PASSED] four
[14:03:07] [PASSED] five
[14:03:07] [PASSED] six
[14:03:07] [PASSED] seven
[14:03:07] [PASSED] qword
[14:03:07] ================= [PASSED] test_decode_str =================
[14:03:07] [PASSED] test_print
[14:03:07] ================= [PASSED] guc_klv_helpers =================
[14:03:07] =================== xe_log (4 subtests) ====================
[14:03:07] [PASSED] demo_cper
[14:03:07] [PASSED] demo_dmesg
[14:03:07] ======================= test_dmesg ========================
[14:03:07] [PASSED] test_fatal
[14:03:07] [PASSED] test_fatal_tile
[14:03:07] [PASSED] test_fatal_gt
[14:03:07] [PASSED] test_fatal_comp
[14:03:07] [PASSED] test_fatal_comp_tile
[14:03:07] [PASSED] test_fatal_comp_gt
[14:03:07] [PASSED] test_fatal_all
[14:03:07] [PASSED] test_recoverable
[14:03:07] [PASSED] test_recoverable_tile
[14:03:07] [PASSED] test_recoverable_gt
[14:03:07] [PASSED] test_recoverable_comp
[14:03:07] [PASSED] test_recoverable_comp_tile
[14:03:07] [PASSED] test_recoverable_comp_gt
[14:03:07] [PASSED] test_recoverable_all
[14:03:07] [PASSED] test_info
[14:03:07] [PASSED] test_info_tile
[14:03:07] [PASSED] test_info_gt
[14:03:07] [PASSED] test_info_err
[14:03:07] [PASSED] test_info_comp
[14:03:07] [PASSED] test_info_comp_tile
[14:03:07] [PASSED] test_info_comp_gt
[14:03:07] [PASSED] test_info_all
[14:03:07] [PASSED] test_hw_fatal
[14:03:07] [PASSED] test_hw_recoverable
[14:03:07] [PASSED] test_hw_corrected
[14:03:07] [PASSED] test_hw_informational
[14:03:07] =================== [PASSED] test_dmesg ====================
[14:03:07] ====================== test_invalid =======================
[14:03:07] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[14:03:07] ================== [SKIPPED] test_invalid ==================
[14:03:07] ===================== [PASSED] xe_log ======================
[14:03:07] ================== no_relay (3 subtests) ===================
[14:03:07] [PASSED] xe_drops_guc2pf_if_not_ready
[14:03:07] [PASSED] xe_drops_guc2vf_if_not_ready
[14:03:07] [PASSED] xe_rejects_send_if_not_ready
[14:03:07] ==================== [PASSED] no_relay =====================
[14:03:07] ================== pf_relay (14 subtests) ==================
[14:03:07] [PASSED] pf_rejects_guc2pf_too_short
[14:03:07] [PASSED] pf_rejects_guc2pf_too_long
[14:03:07] [PASSED] pf_rejects_guc2pf_no_payload
[14:03:07] [PASSED] pf_fails_no_payload
[14:03:07] [PASSED] pf_fails_bad_origin
[14:03:07] [PASSED] pf_fails_bad_type
[14:03:07] [PASSED] pf_txn_reports_error
[14:03:07] [PASSED] pf_txn_sends_pf2guc
[14:03:07] [PASSED] pf_sends_pf2guc
[14:03:07] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[14:03:07] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[14:03:07] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[14:03:07] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[14:03:07] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[14:03:07] ==================== [PASSED] pf_relay =====================
[14:03:07] ================== vf_relay (3 subtests) ===================
[14:03:07] [PASSED] vf_rejects_guc2vf_too_short
[14:03:07] [PASSED] vf_rejects_guc2vf_too_long
[14:03:07] [PASSED] vf_rejects_guc2vf_no_payload
[14:03:07] ==================== [PASSED] vf_relay =====================
[14:03:07] ================ pf_gt_config (9 subtests) =================
[14:03:07] [PASSED] fair_contexts_1vf
[14:03:07] [PASSED] fair_doorbells_1vf
[14:03:07] [PASSED] fair_ggtt_1vf
[14:03:07] ====================== fair_vram_1vf ======================
[14:03:07] [PASSED] 3.50 GiB
[14:03:07] [PASSED] 11.5 GiB
[14:03:07] [PASSED] 15.5 GiB
[14:03:07] [PASSED] 31.5 GiB
[14:03:07] [PASSED] 63.5 GiB
[14:03:07] [PASSED] 1.91 GiB
[14:03:07] ================== [PASSED] fair_vram_1vf ==================
[14:03:07] ================ fair_vram_1vf_admin_only =================
[14:03:07] [PASSED] 3.50 GiB
[14:03:07] [PASSED] 11.5 GiB
[14:03:07] [PASSED] 15.5 GiB
[14:03:07] [PASSED] 31.5 GiB
[14:03:07] [PASSED] 63.5 GiB
[14:03:07] [PASSED] 1.91 GiB
[14:03:07] ============ [PASSED] fair_vram_1vf_admin_only =============
[14:03:07] ====================== fair_contexts ======================
[14:03:07] [PASSED] 1 VF
[14:03:07] [PASSED] 2 VFs
[14:03:07] [PASSED] 3 VFs
[14:03:07] [PASSED] 4 VFs
[14:03:07] [PASSED] 5 VFs
[14:03:07] [PASSED] 6 VFs
[14:03:07] [PASSED] 7 VFs
[14:03:07] [PASSED] 8 VFs
[14:03:07] [PASSED] 9 VFs
[14:03:07] [PASSED] 10 VFs
[14:03:07] [PASSED] 11 VFs
[14:03:07] [PASSED] 12 VFs
[14:03:07] [PASSED] 13 VFs
[14:03:07] [PASSED] 14 VFs
[14:03:07] [PASSED] 15 VFs
[14:03:07] [PASSED] 16 VFs
[14:03:07] [PASSED] 17 VFs
[14:03:07] [PASSED] 18 VFs
[14:03:07] [PASSED] 19 VFs
[14:03:07] [PASSED] 20 VFs
[14:03:07] [PASSED] 21 VFs
[14:03:07] [PASSED] 22 VFs
[14:03:07] [PASSED] 23 VFs
[14:03:07] [PASSED] 24 VFs
[14:03:07] [PASSED] 25 VFs
[14:03:07] [PASSED] 26 VFs
[14:03:07] [PASSED] 27 VFs
[14:03:07] [PASSED] 28 VFs
[14:03:07] [PASSED] 29 VFs
[14:03:07] [PASSED] 30 VFs
[14:03:07] [PASSED] 31 VFs
[14:03:07] [PASSED] 32 VFs
[14:03:07] [PASSED] 33 VFs
[14:03:07] [PASSED] 34 VFs
[14:03:07] [PASSED] 35 VFs
[14:03:07] [PASSED] 36 VFs
[14:03:07] [PASSED] 37 VFs
[14:03:07] [PASSED] 38 VFs
[14:03:07] [PASSED] 39 VFs
[14:03:07] [PASSED] 40 VFs
[14:03:07] [PASSED] 41 VFs
[14:03:07] [PASSED] 42 VFs
[14:03:07] [PASSED] 43 VFs
[14:03:07] [PASSED] 44 VFs
[14:03:07] [PASSED] 45 VFs
[14:03:07] [PASSED] 46 VFs
[14:03:07] [PASSED] 47 VFs
[14:03:07] [PASSED] 48 VFs
[14:03:07] [PASSED] 49 VFs
[14:03:07] [PASSED] 50 VFs
[14:03:07] [PASSED] 51 VFs
[14:03:07] [PASSED] 52 VFs
[14:03:07] [PASSED] 53 VFs
[14:03:07] [PASSED] 54 VFs
[14:03:07] [PASSED] 55 VFs
[14:03:07] [PASSED] 56 VFs
[14:03:07] [PASSED] 57 VFs
[14:03:07] [PASSED] 58 VFs
[14:03:07] [PASSED] 59 VFs
[14:03:07] [PASSED] 60 VFs
[14:03:07] [PASSED] 61 VFs
[14:03:07] [PASSED] 62 VFs
[14:03:07] [PASSED] 63 VFs
[14:03:07] ================== [PASSED] fair_contexts ==================
[14:03:07] ===================== fair_doorbells ======================
[14:03:07] [PASSED] 1 VF
[14:03:07] [PASSED] 2 VFs
[14:03:07] [PASSED] 3 VFs
[14:03:07] [PASSED] 4 VFs
[14:03:07] [PASSED] 5 VFs
[14:03:07] [PASSED] 6 VFs
[14:03:07] [PASSED] 7 VFs
[14:03:07] [PASSED] 8 VFs
[14:03:07] [PASSED] 9 VFs
[14:03:07] [PASSED] 10 VFs
[14:03:07] [PASSED] 11 VFs
[14:03:07] [PASSED] 12 VFs
[14:03:07] [PASSED] 13 VFs
[14:03:07] [PASSED] 14 VFs
[14:03:07] [PASSED] 15 VFs
[14:03:07] [PASSED] 16 VFs
[14:03:07] [PASSED] 17 VFs
[14:03:07] [PASSED] 18 VFs
[14:03:07] [PASSED] 19 VFs
[14:03:07] [PASSED] 20 VFs
[14:03:07] [PASSED] 21 VFs
[14:03:07] [PASSED] 22 VFs
[14:03:07] [PASSED] 23 VFs
[14:03:07] [PASSED] 24 VFs
[14:03:07] [PASSED] 25 VFs
[14:03:07] [PASSED] 26 VFs
[14:03:07] [PASSED] 27 VFs
[14:03:07] [PASSED] 28 VFs
[14:03:07] [PASSED] 29 VFs
[14:03:07] [PASSED] 30 VFs
[14:03:07] [PASSED] 31 VFs
[14:03:07] [PASSED] 32 VFs
[14:03:07] [PASSED] 33 VFs
[14:03:07] [PASSED] 34 VFs
[14:03:07] [PASSED] 35 VFs
[14:03:07] [PASSED] 36 VFs
[14:03:07] [PASSED] 37 VFs
[14:03:07] [PASSED] 38 VFs
[14:03:07] [PASSED] 39 VFs
[14:03:07] [PASSED] 40 VFs
[14:03:07] [PASSED] 41 VFs
[14:03:07] [PASSED] 42 VFs
[14:03:07] [PASSED] 43 VFs
[14:03:07] [PASSED] 44 VFs
[14:03:07] [PASSED] 45 VFs
[14:03:07] [PASSED] 46 VFs
[14:03:07] [PASSED] 47 VFs
[14:03:07] [PASSED] 48 VFs
[14:03:07] [PASSED] 49 VFs
[14:03:07] [PASSED] 50 VFs
[14:03:07] [PASSED] 51 VFs
[14:03:07] [PASSED] 52 VFs
[14:03:07] [PASSED] 53 VFs
[14:03:07] [PASSED] 54 VFs
[14:03:07] [PASSED] 55 VFs
[14:03:07] [PASSED] 56 VFs
[14:03:07] [PASSED] 57 VFs
[14:03:07] [PASSED] 58 VFs
[14:03:07] [PASSED] 59 VFs
[14:03:07] [PASSED] 60 VFs
[14:03:07] [PASSED] 61 VFs
[14:03:07] [PASSED] 62 VFs
[14:03:07] [PASSED] 63 VFs
[14:03:07] ================= [PASSED] fair_doorbells ==================
[14:03:07] ======================== fair_ggtt ========================
[14:03:07] [PASSED] 1 VF
[14:03:07] [PASSED] 2 VFs
[14:03:07] [PASSED] 3 VFs
[14:03:07] [PASSED] 4 VFs
[14:03:07] [PASSED] 5 VFs
[14:03:07] [PASSED] 6 VFs
[14:03:07] [PASSED] 7 VFs
[14:03:07] [PASSED] 8 VFs
[14:03:07] [PASSED] 9 VFs
[14:03:07] [PASSED] 10 VFs
[14:03:07] [PASSED] 11 VFs
[14:03:07] [PASSED] 12 VFs
[14:03:07] [PASSED] 13 VFs
[14:03:07] [PASSED] 14 VFs
[14:03:07] [PASSED] 15 VFs
[14:03:07] [PASSED] 16 VFs
[14:03:07] [PASSED] 17 VFs
[14:03:07] [PASSED] 18 VFs
[14:03:07] [PASSED] 19 VFs
[14:03:07] [PASSED] 20 VFs
[14:03:07] [PASSED] 21 VFs
[14:03:07] [PASSED] 22 VFs
[14:03:07] [PASSED] 23 VFs
[14:03:07] [PASSED] 24 VFs
[14:03:07] [PASSED] 25 VFs
[14:03:07] [PASSED] 26 VFs
[14:03:07] [PASSED] 27 VFs
[14:03:07] [PASSED] 28 VFs
[14:03:07] [PASSED] 29 VFs
[14:03:07] [PASSED] 30 VFs
[14:03:07] [PASSED] 31 VFs
[14:03:07] [PASSED] 32 VFs
[14:03:07] [PASSED] 33 VFs
[14:03:07] [PASSED] 34 VFs
[14:03:07] [PASSED] 35 VFs
[14:03:07] [PASSED] 36 VFs
[14:03:07] [PASSED] 37 VFs
[14:03:07] [PASSED] 38 VFs
[14:03:07] [PASSED] 39 VFs
[14:03:07] [PASSED] 40 VFs
[14:03:07] [PASSED] 41 VFs
[14:03:07] [PASSED] 42 VFs
[14:03:07] [PASSED] 43 VFs
[14:03:07] [PASSED] 44 VFs
[14:03:07] [PASSED] 45 VFs
[14:03:07] [PASSED] 46 VFs
[14:03:07] [PASSED] 47 VFs
[14:03:07] [PASSED] 48 VFs
[14:03:07] [PASSED] 49 VFs
[14:03:07] [PASSED] 50 VFs
[14:03:07] [PASSED] 51 VFs
[14:03:07] [PASSED] 52 VFs
[14:03:07] [PASSED] 53 VFs
[14:03:07] [PASSED] 54 VFs
[14:03:07] [PASSED] 55 VFs
[14:03:07] [PASSED] 56 VFs
[14:03:07] [PASSED] 57 VFs
[14:03:07] [PASSED] 58 VFs
[14:03:07] [PASSED] 59 VFs
[14:03:07] [PASSED] 60 VFs
[14:03:07] [PASSED] 61 VFs
[14:03:07] [PASSED] 62 VFs
[14:03:07] [PASSED] 63 VFs
[14:03:07] ==================== [PASSED] fair_ggtt ====================
[14:03:07] ======================== fair_vram ========================
[14:03:07] [PASSED] 1 VF
[14:03:07] [PASSED] 2 VFs
[14:03:07] [PASSED] 3 VFs
[14:03:07] [PASSED] 4 VFs
[14:03:07] [PASSED] 5 VFs
[14:03:07] [PASSED] 6 VFs
[14:03:07] [PASSED] 7 VFs
[14:03:07] [PASSED] 8 VFs
[14:03:07] [PASSED] 9 VFs
[14:03:07] [PASSED] 10 VFs
[14:03:07] [PASSED] 11 VFs
[14:03:07] [PASSED] 12 VFs
[14:03:07] [PASSED] 13 VFs
[14:03:07] [PASSED] 14 VFs
[14:03:07] [PASSED] 15 VFs
[14:03:07] [PASSED] 16 VFs
[14:03:07] [PASSED] 17 VFs
[14:03:07] [PASSED] 18 VFs
[14:03:07] [PASSED] 19 VFs
[14:03:07] [PASSED] 20 VFs
[14:03:07] [PASSED] 21 VFs
[14:03:07] [PASSED] 22 VFs
[14:03:07] [PASSED] 23 VFs
[14:03:07] [PASSED] 24 VFs
[14:03:07] [PASSED] 25 VFs
[14:03:07] [PASSED] 26 VFs
[14:03:07] [PASSED] 27 VFs
[14:03:07] [PASSED] 28 VFs
[14:03:07] [PASSED] 29 VFs
[14:03:07] [PASSED] 30 VFs
[14:03:07] [PASSED] 31 VFs
[14:03:07] [PASSED] 32 VFs
[14:03:07] [PASSED] 33 VFs
[14:03:07] [PASSED] 34 VFs
[14:03:07] [PASSED] 35 VFs
[14:03:07] [PASSED] 36 VFs
[14:03:07] [PASSED] 37 VFs
[14:03:07] [PASSED] 38 VFs
[14:03:07] [PASSED] 39 VFs
[14:03:07] [PASSED] 40 VFs
[14:03:07] [PASSED] 41 VFs
[14:03:07] [PASSED] 42 VFs
[14:03:07] [PASSED] 43 VFs
[14:03:07] [PASSED] 44 VFs
[14:03:07] [PASSED] 45 VFs
[14:03:07] [PASSED] 46 VFs
[14:03:07] [PASSED] 47 VFs
[14:03:07] [PASSED] 48 VFs
[14:03:07] [PASSED] 49 VFs
[14:03:07] [PASSED] 50 VFs
[14:03:07] [PASSED] 51 VFs
[14:03:07] [PASSED] 52 VFs
[14:03:07] [PASSED] 53 VFs
[14:03:07] [PASSED] 54 VFs
[14:03:07] [PASSED] 55 VFs
[14:03:07] [PASSED] 56 VFs
[14:03:07] [PASSED] 57 VFs
[14:03:07] [PASSED] 58 VFs
[14:03:07] [PASSED] 59 VFs
[14:03:07] [PASSED] 60 VFs
[14:03:07] [PASSED] 61 VFs
[14:03:07] [PASSED] 62 VFs
[14:03:07] [PASSED] 63 VFs
[14:03:07] ==================== [PASSED] fair_vram ====================
[14:03:07] ================== [PASSED] pf_gt_config ===================
[14:03:07] ===================== lmtt (1 subtest) =====================
[14:03:07] ======================== test_ops =========================
[14:03:07] [PASSED] 2-level
[14:03:07] [PASSED] multi-level
[14:03:07] ==================== [PASSED] test_ops =====================
[14:03:07] ====================== [PASSED] lmtt =======================
[14:03:07] ================= sriov_packet (1 subtest) =================
[14:03:07] [PASSED] test_descriptor_init
[14:03:07] ================== [PASSED] sriov_packet ===================
[14:03:07] ================= pf_service (11 subtests) =================
[14:03:07] [PASSED] pf_negotiate_any
[14:03:07] [PASSED] pf_negotiate_base_match
[14:03:07] [PASSED] pf_negotiate_base_newer
[14:03:07] [PASSED] pf_negotiate_base_next
[14:03:07] [SKIPPED] pf_negotiate_base_older (no older minor)
[14:03:07] [PASSED] pf_negotiate_base_prev
[14:03:07] [PASSED] pf_negotiate_latest_match
[14:03:07] [PASSED] pf_negotiate_latest_newer
[14:03:07] [PASSED] pf_negotiate_latest_next
[14:03:07] [SKIPPED] pf_negotiate_latest_older (no older minor)
[14:03:07] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[14:03:07] =================== [PASSED] pf_service ====================
[14:03:07] ================= xe_guc_g2g (2 subtests) ==================
[14:03:07] ============== xe_live_guc_g2g_kunit_default ==============
[14:03:07] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:03:07] ============== xe_live_guc_g2g_kunit_allmem ===============
[14:03:07] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:03:07] =================== [SKIPPED] xe_guc_g2g ===================
[14:03:07] =================== xe_mocs (2 subtests) ===================
[14:03:07] ================ xe_live_mocs_kernel_kunit ================
[14:03:07] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:03:07] ================ xe_live_mocs_reset_kunit =================
[14:03:07] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:03:07] ==================== [SKIPPED] xe_mocs =====================
[14:03:07] ================= xe_migrate (2 subtests) ==================
[14:03:07] ================= xe_migrate_sanity_kunit =================
[14:03:07] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:03:07] ================== xe_validate_ccs_kunit ==================
[14:03:07] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:03:07] =================== [SKIPPED] xe_migrate ===================
[14:03:07] ================== xe_dma_buf (1 subtest) ==================
[14:03:07] ==================== xe_dma_buf_kunit =====================
[14:03:07] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:03:07] =================== [SKIPPED] xe_dma_buf ===================
[14:03:07] ================= xe_bo_shrink (1 subtest) =================
[14:03:07] =================== xe_bo_shrink_kunit ====================
[14:03:07] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:03:07] ================== [SKIPPED] xe_bo_shrink ==================
[14:03:07] ==================== xe_bo (2 subtests) ====================
[14:03:07] ================== xe_ccs_migrate_kunit ===================
[14:03:07] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:03:07] ==================== xe_bo_evict_kunit ====================
[14:03:07] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:03:07] ===================== [SKIPPED] xe_bo ======================
[14:03:07] =================== xe_any (9 subtests) ====================
[14:03:07] [PASSED] test_to_xe
[14:03:07] [PASSED] test_to_dev
[14:03:07] [PASSED] test_to_pdev
[14:03:07] [PASSED] test_to_drm
[14:03:07] [PASSED] test_if_pdev
[14:03:07] [PASSED] test_if_xe
[14:03:07] [PASSED] test_if_tile
[14:03:07] [PASSED] test_if_gt
[14:03:07] [PASSED] test_to_id
[14:03:07] ===================== [PASSED] xe_any ======================
[14:03:07] ==================== args (13 subtests) ====================
[14:03:07] [PASSED] count_args_test
[14:03:07] [PASSED] call_args_example
[14:03:07] [PASSED] call_args_test
[14:03:07] [PASSED] drop_first_arg_example
[14:03:07] [PASSED] drop_first_arg_test
[14:03:07] [PASSED] first_arg_example
[14:03:07] [PASSED] first_arg_test
[14:03:07] [PASSED] last_arg_example
[14:03:07] [PASSED] last_arg_test
[14:03:07] [PASSED] pick_arg_example
[14:03:07] [PASSED] if_args_example
[14:03:07] [PASSED] if_args_test
[14:03:07] [PASSED] sep_comma_example
[14:03:07] ====================== [PASSED] args =======================
[14:03:07] =================== xe_pci (3 subtests) ====================
[14:03:07] ==================== check_graphics_ip ====================
[14:03:07] [PASSED] 12.00 Xe_LP
[14:03:07] [PASSED] 12.10 Xe_LP+
[14:03:07] [PASSED] 12.55 Xe_HPG
[14:03:07] [PASSED] 12.60 Xe_HPC
[14:03:07] [PASSED] 12.70 Xe_LPG
[14:03:07] [PASSED] 12.71 Xe_LPG
[14:03:07] [PASSED] 12.74 Xe_LPG+
[14:03:07] [PASSED] 20.01 Xe2_HPG
[14:03:07] [PASSED] 20.02 Xe2_HPG
[14:03:07] [PASSED] 20.04 Xe2_LPG
[14:03:07] [PASSED] 30.00 Xe3_LPG
[14:03:07] [PASSED] 30.01 Xe3_LPG
[14:03:07] [PASSED] 30.03 Xe3_LPG
[14:03:07] [PASSED] 30.04 Xe3_LPG
[14:03:07] [PASSED] 30.05 Xe3_LPG
[14:03:07] [PASSED] 35.10 Xe3p_LPG
[14:03:07] [PASSED] 35.11 Xe3p_XPC
[14:03:07] ================ [PASSED] check_graphics_ip ================
[14:03:07] ===================== check_media_ip ======================
[14:03:07] [PASSED] 12.00 Xe_M
[14:03:07] [PASSED] 12.55 Xe_HPM
[14:03:07] [PASSED] 13.00 Xe_LPM+
[14:03:07] [PASSED] 13.01 Xe2_HPM
[14:03:07] [PASSED] 20.00 Xe2_LPM
[14:03:07] [PASSED] 30.00 Xe3_LPM
[14:03:07] [PASSED] 30.02 Xe3_LPM
[14:03:07] [PASSED] 35.00 Xe3p_LPM
[14:03:07] [PASSED] 35.03 Xe3p_HPM
[14:03:07] ================= [PASSED] check_media_ip ==================
[14:03:07] =================== check_platform_desc ===================
[14:03:07] [PASSED] 0x9A60 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A68 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A70 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A40 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A49 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A59 (TIGERLAKE)
[14:03:07] [PASSED] 0x9A78 (TIGERLAKE)
[14:03:07] [PASSED] 0x9AC0 (TIGERLAKE)
[14:03:07] [PASSED] 0x9AC9 (TIGERLAKE)
[14:03:07] [PASSED] 0x9AD9 (TIGERLAKE)
[14:03:07] [PASSED] 0x9AF8 (TIGERLAKE)
[14:03:07] [PASSED] 0x4C80 (ROCKETLAKE)
[14:03:07] [PASSED] 0x4C8A (ROCKETLAKE)
[14:03:07] [PASSED] 0x4C8B (ROCKETLAKE)
[14:03:07] [PASSED] 0x4C8C (ROCKETLAKE)
[14:03:07] [PASSED] 0x4C90 (ROCKETLAKE)
[14:03:07] [PASSED] 0x4C9A (ROCKETLAKE)
[14:03:07] [PASSED] 0x4680 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4682 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4688 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x468A (ALDERLAKE_S)
[14:03:07] [PASSED] 0x468B (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4690 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4692 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4693 (ALDERLAKE_S)
[14:03:07] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46AA (ALDERLAKE_P)
[14:03:07] [PASSED] 0x462A (ALDERLAKE_P)
[14:03:07] [PASSED] 0x4626 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x4628 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:03:07] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:03:07] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:03:07] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:03:07] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:03:07] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:03:07] [PASSED] 0xA721 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA720 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:03:07] [PASSED] 0xA780 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA781 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA782 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA783 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA788 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA789 (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA78A (ALDERLAKE_S)
[14:03:07] [PASSED] 0xA78B (ALDERLAKE_S)
[14:03:07] [PASSED] 0x4905 (DG1)
[14:03:07] [PASSED] 0x4906 (DG1)
[14:03:07] [PASSED] 0x4907 (DG1)
[14:03:07] [PASSED] 0x4908 (DG1)
[14:03:07] [PASSED] 0x4909 (DG1)
[14:03:07] [PASSED] 0x56C0 (DG2)
[14:03:07] [PASSED] 0x56C2 (DG2)
[14:03:07] [PASSED] 0x56C1 (DG2)
[14:03:07] [PASSED] 0x7D51 (METEORLAKE)
[14:03:07] [PASSED] 0x7DD1 (METEORLAKE)
[14:03:07] [PASSED] 0x7D41 (METEORLAKE)
[14:03:07] [PASSED] 0x7D67 (METEORLAKE)
[14:03:07] [PASSED] 0xB640 (METEORLAKE)
[14:03:07] [PASSED] 0x56A0 (DG2)
[14:03:07] [PASSED] 0x56A1 (DG2)
[14:03:07] [PASSED] 0x56A2 (DG2)
[14:03:07] [PASSED] 0x56BE (DG2)
[14:03:07] [PASSED] 0x56BF (DG2)
[14:03:07] [PASSED] 0x5690 (DG2)
[14:03:07] [PASSED] 0x5691 (DG2)
[14:03:07] [PASSED] 0x5692 (DG2)
[14:03:07] [PASSED] 0x56A5 (DG2)
[14:03:07] [PASSED] 0x56A6 (DG2)
[14:03:07] [PASSED] 0x56B0 (DG2)
[14:03:07] [PASSED] 0x56B1 (DG2)
[14:03:07] [PASSED] 0x56BA (DG2)
[14:03:07] [PASSED] 0x56BB (DG2)
[14:03:07] [PASSED] 0x56BC (DG2)
[14:03:07] [PASSED] 0x56BD (DG2)
[14:03:07] [PASSED] 0x5693 (DG2)
[14:03:07] [PASSED] 0x5694 (DG2)
[14:03:07] [PASSED] 0x5695 (DG2)
[14:03:07] [PASSED] 0x56A3 (DG2)
[14:03:07] [PASSED] 0x56A4 (DG2)
[14:03:07] [PASSED] 0x56B2 (DG2)
[14:03:07] [PASSED] 0x56B3 (DG2)
[14:03:07] [PASSED] 0x5696 (DG2)
[14:03:07] [PASSED] 0x5697 (DG2)
[14:03:07] [PASSED] 0xB69 (PVC)
[14:03:07] [PASSED] 0xB6E (PVC)
[14:03:07] [PASSED] 0xBD4 (PVC)
[14:03:07] [PASSED] 0xBD5 (PVC)
[14:03:07] [PASSED] 0xBD6 (PVC)
[14:03:07] [PASSED] 0xBD7 (PVC)
[14:03:07] [PASSED] 0xBD8 (PVC)
[14:03:07] [PASSED] 0xBD9 (PVC)
[14:03:07] [PASSED] 0xBDA (PVC)
[14:03:07] [PASSED] 0xBDB (PVC)
[14:03:07] [PASSED] 0xBE0 (PVC)
[14:03:07] [PASSED] 0xBE1 (PVC)
[14:03:07] [PASSED] 0xBE5 (PVC)
[14:03:07] [PASSED] 0x7D40 (METEORLAKE)
[14:03:07] [PASSED] 0x7D45 (METEORLAKE)
[14:03:07] [PASSED] 0x7D55 (METEORLAKE)
[14:03:07] [PASSED] 0x7D60 (METEORLAKE)
[14:03:07] [PASSED] 0x7DD5 (METEORLAKE)
[14:03:07] [PASSED] 0x6420 (LUNARLAKE)
[14:03:07] [PASSED] 0x64A0 (LUNARLAKE)
[14:03:07] [PASSED] 0x64B0 (LUNARLAKE)
[14:03:07] [PASSED] 0xE202 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE209 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE20B (BATTLEMAGE)
[14:03:07] [PASSED] 0xE20C (BATTLEMAGE)
[14:03:07] [PASSED] 0xE20D (BATTLEMAGE)
[14:03:07] [PASSED] 0xE210 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE211 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE212 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE216 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE220 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE221 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE222 (BATTLEMAGE)
[14:03:07] [PASSED] 0xE223 (BATTLEMAGE)
[14:03:07] [PASSED] 0xB080 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB081 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB082 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB083 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB084 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB085 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB086 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB087 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB08F (PANTHERLAKE)
[14:03:07] [PASSED] 0xB090 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB0A1 (PANTHERLAKE)
[14:03:07] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:03:07] [PASSED] 0xFD80 (PANTHERLAKE)
[14:03:07] [PASSED] 0xFD81 (PANTHERLAKE)
[14:03:07] [PASSED] 0xD740 (NOVALAKE_S)
[14:03:07] [PASSED] 0xD741 (NOVALAKE_S)
[14:03:07] [PASSED] 0xD742 (NOVALAKE_S)
[14:03:07] [PASSED] 0xD743 (NOVALAKE_S)
[14:03:07] [PASSED] 0xD745 (NOVALAKE_S)
[14:03:07] [PASSED] 0xD74A (NOVALAKE_S)
[14:03:07] [PASSED] 0xD74B (NOVALAKE_S)
[14:03:07] [PASSED] 0x674C (CRESCENTISLAND)
[14:03:07] [PASSED] 0x674D (CRESCENTISLAND)
[14:03:07] [PASSED] 0x674E (CRESCENTISLAND)
[14:03:07] [PASSED] 0x674F (CRESCENTISLAND)
[14:03:07] [PASSED] 0x6750 (CRESCENTISLAND)
[14:03:07] [PASSED] 0x6751 (CRESCENTISLAND)
[14:03:07] [PASSED] 0xD750 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD751 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD752 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD753 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD754 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD755 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD756 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD757 (NOVALAKE_P)
[14:03:07] [PASSED] 0xD75F (NOVALAKE_P)
[14:03:07] =============== [PASSED] check_platform_desc ===============
[14:03:07] ===================== [PASSED] xe_pci ======================
[14:03:07] ============= xe_rtp_tables_test (5 subtests) ==============
[14:03:07] ================== xe_rtp_table_gt_test ===================
[14:03:07] [PASSED] gt_was/14011060649
[14:03:07] [PASSED] gt_was/14011059788
[14:03:07] [PASSED] gt_was/14015795083
[14:03:07] [PASSED] gt_was/16021867713
[14:03:07] [PASSED] gt_was/14019449301
[14:03:07] [PASSED] gt_was/16028005424
[14:03:07] [PASSED] gt_was/14026578760
[14:03:07] [PASSED] gt_was/1409420604
[14:03:07] [PASSED] gt_was/1408615072
[14:03:07] [PASSED] gt_was/22010523718
[14:03:07] [PASSED] gt_was/14011006942
[14:03:07] [PASSED] gt_was/14014830051
[14:03:07] [PASSED] gt_was/18018781329
[14:03:07] [PASSED] gt_was/1509235366
[14:03:07] [PASSED] gt_was/18018781329
[14:03:07] [PASSED] gt_was/16016694945
[14:03:07] [PASSED] gt_was/14018575942
[14:03:07] [PASSED] gt_was/22016670082
[14:03:07] [PASSED] gt_was/22016670082
[14:03:07] [PASSED] gt_was/14017421178
[14:03:07] [PASSED] gt_was/16025250150
[14:03:07] [PASSED] gt_was/14021871409
[14:03:07] [PASSED] gt_was/16021865536
[14:03:07] [PASSED] gt_was/14021486841
[14:03:07] [PASSED] gt_was/14025160223
[14:03:07] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[14:03:07] [PASSED] gt_was/14025635424
[14:03:07] [PASSED] gt_was/16028005424
[14:03:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[14:03:07] ================== xe_rtp_table_gt_test ===================
[14:03:07] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[14:03:07] [PASSED] gt_tunings/Tuning: 32B Access Enable
[14:03:07] [PASSED] gt_tunings/Tuning: L3 cache
[14:03:07] [PASSED] gt_tunings/Tuning: L3 cache - media
[14:03:07] [PASSED] gt_tunings/Tuning: Compression Overfetch
[14:03:07] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[14:03:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[14:03:07] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[14:03:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[14:03:07] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[14:03:07] [PASSED] gt_tunings/Tuning: Stateless compression control
[14:03:07] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[14:03:07] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[14:03:07] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[14:03:07] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[14:03:07] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[14:03:07] ============== [PASSED] xe_rtp_table_gt_test ===============
[14:03:07] ================== xe_rtp_table_oob_test ==================
[14:03:07] [PASSED] oob_was/1607983814
[14:03:07] [PASSED] oob_was/16010904313
[14:03:07] [PASSED] oob_was/18022495364
[14:03:07] [PASSED] oob_was/22012773006
[14:03:07] [PASSED] oob_was/14014475959
[14:03:07] [PASSED] oob_was/22011391025
[14:03:07] [PASSED] oob_was/22012727170
[14:03:07] [PASSED] oob_was/22012727685
[14:03:07] [PASSED] oob_was/22016596838
[14:03:07] [PASSED] oob_was/18020744125
[14:03:07] [PASSED] oob_was/1409600907
[14:03:07] [PASSED] oob_was/22014953428
[14:03:07] [PASSED] oob_was/16017236439
[14:03:07] [PASSED] oob_was/14019821291
[14:03:07] [PASSED] oob_was/14015076503
[14:03:07] [PASSED] oob_was/22016122933
[14:03:07] [PASSED] oob_was/14018913170
[14:03:07] [PASSED] oob_was/14018094691
[14:03:07] [PASSED] oob_was/18024947630
[14:03:07] [PASSED] oob_was/16022287689
[14:03:07] [PASSED] oob_was/13011645652
[14:03:07] [PASSED] oob_was/14022293748
[14:03:07] [PASSED] oob_was/22019794406
[14:03:07] [PASSED] oob_was/22019338487
[14:03:07] [PASSED] oob_was/16023588340
[14:03:07] [PASSED] oob_was/14019789679
[14:03:07] [PASSED] oob_was/14022866841
[14:03:07] [PASSED] oob_was/16021333562
[14:03:07] [PASSED] oob_was/14016712196
[14:03:07] [PASSED] oob_was/14015568240
[14:03:07] [PASSED] oob_was/18013179988
[14:03:07] [PASSED] oob_was/1508761755
[14:03:07] [PASSED] oob_was/16023105232
[14:03:07] [PASSED] oob_was/16026508708
[14:03:07] [PASSED] oob_was/14020001231
[14:03:07] [PASSED] oob_was/16023683509
[14:03:07] [PASSED] oob_was/14025515070
[14:03:07] [PASSED] oob_was/15015404425_disable
[14:03:07] [PASSED] oob_was/16026007364
[14:03:07] [PASSED] oob_was/14020316580
[14:03:07] [PASSED] oob_was/14025883347
[14:03:07] [PASSED] oob_was/16029380221
[14:03:07] [PASSED] oob_was/22022079272
[14:03:07] [PASSED] oob_was/16029897822
[14:03:07] [PASSED] oob_was/14027054324
[14:03:07] [PASSED] oob_was/14025941587
[14:03:07] [PASSED] oob_was/16030224309
[14:03:07] ============== [PASSED] xe_rtp_table_oob_test ==============
[14:03:07] ================ xe_rtp_table_dev_oob_test ================
[14:03:07] [PASSED] device_oob_was/22010954014
[14:03:07] [PASSED] device_oob_was/15015404425
[14:03:07] [PASSED] device_oob_was/22019338487_display
[14:03:07] [PASSED] device_oob_was/14022085890
[14:03:07] [PASSED] device_oob_was/14026539277
[14:03:07] [PASSED] device_oob_was/14026633728
[14:03:07] [PASSED] device_oob_was/14026746987
[14:03:07] [PASSED] device_oob_was/14026779378
[14:03:07] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[14:03:07] ========== xe_rtp_table_missing_upper_bound_test ==========
[14:03:07] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[14:03:07] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[14:03:07] [PASSED] register_whitelist/1806527549
[14:03:07] [PASSED] register_whitelist/allow_read_ctx_timestamp
[14:03:07] [PASSED] register_whitelist/allow_read_queue_timestamp
[14:03:07] [PASSED] register_whitelist/16014440446
[14:03:07] [PASSED] register_whitelist/16017236439
[14:03:07] [PASSED] register_whitelist/16020183090
[14:03:07] [PASSED] register_whitelist/14024997852
[14:03:07] [PASSED] register_whitelist/14024997852
[14:03:07] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[14:03:07] =============== [PASSED] xe_rtp_tables_test ================
[14:03:07] =================== xe_rtp (3 subtests) ====================
[14:03:07] =================== xe_rtp_rules_tests ====================
[14:03:07] [PASSED] no
[14:03:07] [PASSED] yes
[14:03:07] [PASSED] no-and-no
[14:03:07] [PASSED] no-and-yes
[14:03:07] [PASSED] yes-and-no
[14:03:07] [PASSED] yes-and-yes
[14:03:07] [PASSED] no-or-no
[14:03:07] [PASSED] no-or-yes
[14:03:07] [PASSED] yes-or-no
[14:03:07] [PASSED] yes-or-yes
[14:03:07] [PASSED] no-yes-or-yes-no
[14:03:07] [PASSED] no-yes-or-yes-yes
[14:03:07] [PASSED] yes-yes-or-no-yes
[14:03:07] [PASSED] yes-yes-or-yes-yes
[14:03:07] [PASSED] no-no-or-yes-or-no
[14:03:07] [PASSED] or
[14:03:07] [PASSED] or-yes
[14:03:07] [PASSED] or-no
[14:03:07] [PASSED] yes-or
[14:03:07] [PASSED] no-or
[14:03:07] [PASSED] no-or-or-yes
[14:03:07] [PASSED] yes-or-or-no
[14:03:07] [PASSED] no-or-or-no
[14:03:07] [PASSED] missing-context-engine-class
[14:03:07] [PASSED] missing-context-engine-class-or-yes
[14:03:07] [PASSED] missing-context-engine-class-or-or-yes
[14:03:07] =============== [PASSED] xe_rtp_rules_tests ================
[14:03:07] =============== xe_rtp_process_to_sr_tests ================
[14:03:07] [PASSED] coalesce-same-reg
[14:03:07] [PASSED] coalesce-same-reg-literal-and-func
[14:03:07] [PASSED] no-match-no-add
[14:03:07] [PASSED] two-regs-two-entries
[14:03:07] [PASSED] clr-one-set-other
[14:03:07] [PASSED] set-field
[14:03:07] [PASSED] conflict-duplicate
[14:03:07] [PASSED] conflict-not-disjoint
[14:03:07] [PASSED] conflict-not-disjoint-literal-and-func
[14:03:07] [PASSED] conflict-reg-type
[14:03:07] [PASSED] bad-mcr-reg-forced-to-regular
[14:03:07] [PASSED] bad-regular-reg-forced-to-mcr
[14:03:07] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:03:07] ================== xe_rtp_process_tests ===================
[14:03:07] [PASSED] active1
[14:03:07] [PASSED] active2
[14:03:07] [PASSED] active-inactive
[14:03:07] [PASSED] inactive-active
[14:03:07] [PASSED] inactive-active-inactive
[14:03:07] [PASSED] inactive-inactive-inactive
[14:03:07] ============== [PASSED] xe_rtp_process_tests ===============
[14:03:07] ===================== [PASSED] xe_rtp ======================
[14:03:07] ==================== xe_wa (1 subtest) =====================
[14:03:07] ======================== xe_wa_gt =========================
[14:03:07] [PASSED] TIGERLAKE B0
[14:03:07] [PASSED] DG1 A0
[14:03:07] [PASSED] DG1 B0
[14:03:07] [PASSED] ALDERLAKE_S A0
[14:03:07] [PASSED] ALDERLAKE_S B0
[14:03:07] [PASSED] ALDERLAKE_S C0
[14:03:07] [PASSED] ALDERLAKE_S D0
[14:03:07] [PASSED] ALDERLAKE_P A0
[14:03:07] [PASSED] ALDERLAKE_P B0
[14:03:07] [PASSED] ALDERLAKE_P C0
[14:03:07] [PASSED] ALDERLAKE_S RPLS D0
[14:03:07] [PASSED] ALDERLAKE_P RPLU E0
[14:03:07] [PASSED] DG2 G10 C0
[14:03:07] [PASSED] DG2 G11 B1
[14:03:07] [PASSED] DG2 G12 A1
[14:03:07] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:03:07] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:03:07] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:03:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:03:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:03:07] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:03:07] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:03:07] ==================== [PASSED] xe_wa_gt =====================
[14:03:07] ====================== [PASSED] xe_wa ======================
[14:03:07] ============================================================
[14:03:07] Testing complete. Ran 837 tests: passed: 809, skipped: 28
[14:03:07] Elapsed time: 42.076s total, 1.855s configuring, 39.454s building, 0.736s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:03:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:03:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:03:35] Starting KUnit Kernel (1/1)...
[14:03:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:03:35] ============ drm_test_pick_cmdline (2 subtests) ============
[14:03:35] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:03:35] =============== drm_test_pick_cmdline_named ===============
[14:03:35] [PASSED] NTSC
[14:03:35] [PASSED] NTSC-J
[14:03:35] [PASSED] PAL
[14:03:35] [PASSED] PAL-M
[14:03:35] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:03:35] ============== [PASSED] drm_test_pick_cmdline ==============
[14:03:35] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:03:35] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:03:35] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:03:35] =========== drm_validate_clone_mode (2 subtests) ===========
[14:03:35] ============== drm_test_check_in_clone_mode ===============
[14:03:35] [PASSED] in_clone_mode
[14:03:35] [PASSED] not_in_clone_mode
[14:03:35] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:03:35] =============== drm_test_check_valid_clones ===============
[14:03:35] [PASSED] not_in_clone_mode
[14:03:35] [PASSED] valid_clone
[14:03:35] [PASSED] invalid_clone
[14:03:35] =========== [PASSED] drm_test_check_valid_clones ===========
[14:03:35] ============= [PASSED] drm_validate_clone_mode =============
[14:03:35] ============= drm_validate_modeset (1 subtest) =============
[14:03:35] [PASSED] drm_test_check_connector_changed_modeset
[14:03:35] ============== [PASSED] drm_validate_modeset ===============
[14:03:35] ====== drm_test_bridge_get_current_state (1 subtest) =======
[14:03:35] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:03:35] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:03:35] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:03:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:03:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:03:35] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[14:03:35] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:03:35] ============== drm_bridge_alloc (2 subtests) ===============
[14:03:35] [PASSED] drm_test_drm_bridge_alloc_basic
[14:03:35] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:03:35] ================ [PASSED] drm_bridge_alloc =================
[14:03:35] ============= drm_bridge_bus_fmt (5 subtests) ==============
[14:03:35] [PASSED] drm_test_bridge_rgb_yuv_rgb
[14:03:35] [PASSED] drm_test_bridge_must_convert_to_yuv444
[14:03:35] [PASSED] drm_test_bridge_hdmi_auto_rgb
[14:03:35] [PASSED] drm_test_bridge_auto_first
[14:03:35] [PASSED] drm_test_bridge_rgb_yuv_no_path
[14:03:35] =============== [PASSED] drm_bridge_bus_fmt ================
[14:03:35] ============= drm_cmdline_parser (40 subtests) =============
[14:03:35] [PASSED] drm_test_cmdline_force_d_only
[14:03:35] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:03:35] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:03:35] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:03:35] [PASSED] drm_test_cmdline_force_e_only
[14:03:35] [PASSED] drm_test_cmdline_res
[14:03:35] [PASSED] drm_test_cmdline_res_vesa
[14:03:35] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:03:35] [PASSED] drm_test_cmdline_res_rblank
[14:03:35] [PASSED] drm_test_cmdline_res_bpp
[14:03:35] [PASSED] drm_test_cmdline_res_refresh
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:03:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:03:35] [PASSED] drm_test_cmdline_res_margins_force_on
[14:03:35] [PASSED] drm_test_cmdline_res_vesa_margins
[14:03:35] [PASSED] drm_test_cmdline_name
[14:03:35] [PASSED] drm_test_cmdline_name_bpp
[14:03:35] [PASSED] drm_test_cmdline_name_option
[14:03:35] [PASSED] drm_test_cmdline_name_bpp_option
[14:03:35] [PASSED] drm_test_cmdline_rotate_0
[14:03:35] [PASSED] drm_test_cmdline_rotate_90
[14:03:35] [PASSED] drm_test_cmdline_rotate_180
[14:03:35] [PASSED] drm_test_cmdline_rotate_270
[14:03:35] [PASSED] drm_test_cmdline_hmirror
[14:03:35] [PASSED] drm_test_cmdline_vmirror
[14:03:35] [PASSED] drm_test_cmdline_margin_options
[14:03:35] [PASSED] drm_test_cmdline_multiple_options
[14:03:35] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:03:35] [PASSED] drm_test_cmdline_extra_and_option
[14:03:35] [PASSED] drm_test_cmdline_freestanding_options
[14:03:35] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:03:35] [PASSED] drm_test_cmdline_panel_orientation
[14:03:35] ================ drm_test_cmdline_invalid =================
[14:03:35] [PASSED] margin_only
[14:03:35] [PASSED] interlace_only
[14:03:35] [PASSED] res_missing_x
[14:03:35] [PASSED] res_missing_y
[14:03:35] [PASSED] res_bad_y
[14:03:35] [PASSED] res_missing_y_bpp
[14:03:35] [PASSED] res_bad_bpp
[14:03:35] [PASSED] res_bad_refresh
[14:03:35] [PASSED] res_bpp_refresh_force_on_off
[14:03:35] [PASSED] res_invalid_mode
[14:03:35] [PASSED] res_bpp_wrong_place_mode
[14:03:35] [PASSED] name_bpp_refresh
[14:03:35] [PASSED] name_refresh
[14:03:35] [PASSED] name_refresh_wrong_mode
[14:03:35] [PASSED] name_refresh_invalid_mode
[14:03:35] [PASSED] rotate_multiple
[14:03:35] [PASSED] rotate_invalid_val
[14:03:35] [PASSED] rotate_truncated
[14:03:35] [PASSED] invalid_option
[14:03:35] [PASSED] invalid_tv_option
[14:03:35] [PASSED] truncated_tv_option
[14:03:35] ============ [PASSED] drm_test_cmdline_invalid =============
[14:03:35] =============== drm_test_cmdline_tv_options ===============
[14:03:35] [PASSED] NTSC
[14:03:35] [PASSED] NTSC_443
[14:03:35] [PASSED] NTSC_J
[14:03:35] [PASSED] PAL
[14:03:35] [PASSED] PAL_M
[14:03:35] [PASSED] PAL_N
[14:03:35] [PASSED] SECAM
[14:03:35] [PASSED] MONO_525
[14:03:35] [PASSED] MONO_625
[14:03:35] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:03:35] =============== [PASSED] drm_cmdline_parser ================
[14:03:35] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:03:35] [PASSED] drm_test_connector_hdmi_init_valid
[14:03:35] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:03:35] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:03:35] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:03:35] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:03:35] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:03:35] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:03:35] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:03:35] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:03:35] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:03:35] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:03:35] [PASSED] supported_formats=0x5 yuv420_allowed=1
[14:03:35] [PASSED] supported_formats=0x5 yuv420_allowed=0
[14:03:35] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:03:35] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:03:35] [PASSED] drm_test_connector_hdmi_init_null_product
[14:03:35] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:03:35] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:03:35] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:03:35] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:03:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:03:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:03:35] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:03:35] ========= drm_test_connector_hdmi_init_type_valid =========
[14:03:35] [PASSED] HDMI-A
[14:03:35] [PASSED] HDMI-B
[14:03:35] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:03:35] ======== drm_test_connector_hdmi_init_type_invalid ========
[14:03:35] [PASSED] Unknown
[14:03:35] [PASSED] VGA
[14:03:35] [PASSED] DVI-I
[14:03:35] [PASSED] DVI-D
[14:03:35] [PASSED] DVI-A
[14:03:35] [PASSED] Composite
[14:03:35] [PASSED] SVIDEO
[14:03:35] [PASSED] LVDS
[14:03:35] [PASSED] Component
[14:03:35] [PASSED] DIN
[14:03:35] [PASSED] DP
[14:03:35] [PASSED] TV
[14:03:35] [PASSED] eDP
[14:03:35] [PASSED] Virtual
[14:03:35] [PASSED] DSI
[14:03:35] [PASSED] DPI
[14:03:35] [PASSED] Writeback
[14:03:35] [PASSED] SPI
[14:03:35] [PASSED] USB
[14:03:35] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:03:35] ============ [PASSED] drmm_connector_hdmi_init =============
[14:03:35] ============= drmm_connector_init (3 subtests) =============
[14:03:35] [PASSED] drm_test_drmm_connector_init
[14:03:35] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:03:35] ========= drm_test_drmm_connector_init_type_valid =========
[14:03:35] [PASSED] Unknown
[14:03:35] [PASSED] VGA
[14:03:35] [PASSED] DVI-I
[14:03:35] [PASSED] DVI-D
[14:03:35] [PASSED] DVI-A
[14:03:35] [PASSED] Composite
[14:03:35] [PASSED] SVIDEO
[14:03:35] [PASSED] LVDS
[14:03:35] [PASSED] Component
[14:03:35] [PASSED] DIN
[14:03:35] [PASSED] DP
[14:03:35] [PASSED] HDMI-A
[14:03:35] [PASSED] HDMI-B
[14:03:35] [PASSED] TV
[14:03:35] [PASSED] eDP
[14:03:35] [PASSED] Virtual
[14:03:35] [PASSED] DSI
[14:03:35] [PASSED] DPI
[14:03:35] [PASSED] Writeback
[14:03:35] [PASSED] SPI
[14:03:35] [PASSED] USB
[14:03:35] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:03:35] =============== [PASSED] drmm_connector_init ===============
[14:03:35] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_init
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:03:35] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[14:03:35] [PASSED] Unknown
[14:03:35] [PASSED] VGA
[14:03:35] [PASSED] DVI-I
[14:03:35] [PASSED] DVI-D
[14:03:35] [PASSED] DVI-A
[14:03:35] [PASSED] Composite
[14:03:35] [PASSED] SVIDEO
[14:03:35] [PASSED] LVDS
[14:03:35] [PASSED] Component
[14:03:35] [PASSED] DIN
[14:03:35] [PASSED] DP
[14:03:35] [PASSED] HDMI-A
[14:03:35] [PASSED] HDMI-B
[14:03:35] [PASSED] TV
[14:03:35] [PASSED] eDP
[14:03:35] [PASSED] Virtual
[14:03:35] [PASSED] DSI
[14:03:35] [PASSED] DPI
[14:03:35] [PASSED] Writeback
[14:03:35] [PASSED] SPI
[14:03:35] [PASSED] USB
[14:03:35] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:03:35] ======== drm_test_drm_connector_dynamic_init_name =========
[14:03:35] [PASSED] Unknown
[14:03:35] [PASSED] VGA
[14:03:35] [PASSED] DVI-I
[14:03:35] [PASSED] DVI-D
[14:03:35] [PASSED] DVI-A
[14:03:35] [PASSED] Composite
[14:03:35] [PASSED] SVIDEO
[14:03:35] [PASSED] LVDS
[14:03:35] [PASSED] Component
[14:03:35] [PASSED] DIN
[14:03:35] [PASSED] DP
[14:03:35] [PASSED] HDMI-A
[14:03:35] [PASSED] HDMI-B
[14:03:35] [PASSED] TV
[14:03:35] [PASSED] eDP
[14:03:35] [PASSED] Virtual
[14:03:35] [PASSED] DSI
[14:03:35] [PASSED] DPI
[14:03:35] [PASSED] Writeback
[14:03:35] [PASSED] SPI
[14:03:35] [PASSED] USB
[14:03:35] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:03:35] =========== [PASSED] drm_connector_dynamic_init ============
[14:03:35] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:03:35] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:03:35] ======= drm_connector_dynamic_register (7 subtests) ========
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:03:35] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:03:35] ========= [PASSED] drm_connector_dynamic_register ==========
[14:03:35] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:03:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:03:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:03:35] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:03:35] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:03:35] ========== drm_test_get_tv_mode_from_name_valid ===========
[14:03:35] [PASSED] NTSC
[14:03:35] [PASSED] NTSC-443
[14:03:35] [PASSED] NTSC-J
[14:03:35] [PASSED] PAL
[14:03:35] [PASSED] PAL-M
[14:03:35] [PASSED] PAL-N
[14:03:35] [PASSED] SECAM
[14:03:35] [PASSED] Mono
[14:03:35] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:03:35] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:03:35] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:03:35] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:03:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:03:35] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[14:03:35] [PASSED] VIC 96
[14:03:35] [PASSED] VIC 97
[14:03:35] [PASSED] VIC 101
[14:03:35] [PASSED] VIC 102
[14:03:35] [PASSED] VIC 106
[14:03:35] [PASSED] VIC 107
[14:03:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:03:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:03:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:03:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:03:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:03:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:03:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:03:35] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:03:35] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[14:03:35] [PASSED] Automatic
[14:03:35] [PASSED] Full
[14:03:35] [PASSED] Limited 16:235
[14:03:35] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:03:35] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:03:35] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:03:35] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:03:35] === drm_test_drm_hdmi_connector_get_output_format_name ====
[14:03:35] [PASSED] RGB
[14:03:35] [PASSED] YUV 4:2:0
[14:03:35] [PASSED] YUV 4:2:2
[14:03:35] [PASSED] YUV 4:4:4
[14:03:35] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:03:35] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:03:35] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:03:35] ============= drm_damage_helper (21 subtests) ==============
[14:03:35] [PASSED] drm_test_damage_iter_no_damage
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:03:35] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:03:35] [PASSED] drm_test_damage_iter_simple_damage
[14:03:35] [PASSED] drm_test_damage_iter_single_damage
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:03:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:03:35] [PASSED] drm_test_damage_iter_damage
[14:03:35] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:03:35] [PASSED] drm_test_damage_iter_damage_one_outside
[14:03:35] [PASSED] drm_test_damage_iter_damage_src_moved
[14:03:35] [PASSED] drm_test_damage_iter_damage_not_visible
[14:03:35] ================ [PASSED] drm_damage_helper ================
[14:03:35] ============== drm_dp_mst_helper (3 subtests) ==============
[14:03:35] ============== drm_test_dp_mst_calc_pbn_mode ==============
[14:03:35] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:03:35] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:03:35] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:03:35] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:03:35] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:03:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:03:35] ============== drm_test_dp_mst_calc_pbn_div ===============
[14:03:35] [PASSED] Link rate 2000000 lane count 4
[14:03:35] [PASSED] Link rate 2000000 lane count 2
[14:03:35] [PASSED] Link rate 2000000 lane count 1
[14:03:35] [PASSED] Link rate 1350000 lane count 4
[14:03:35] [PASSED] Link rate 1350000 lane count 2
[14:03:35] [PASSED] Link rate 1350000 lane count 1
[14:03:35] [PASSED] Link rate 1000000 lane count 4
[14:03:35] [PASSED] Link rate 1000000 lane count 2
[14:03:35] [PASSED] Link rate 1000000 lane count 1
[14:03:35] [PASSED] Link rate 810000 lane count 4
[14:03:35] [PASSED] Link rate 810000 lane count 2
[14:03:35] [PASSED] Link rate 810000 lane count 1
[14:03:35] [PASSED] Link rate 540000 lane count 4
[14:03:35] [PASSED] Link rate 540000 lane count 2
[14:03:35] [PASSED] Link rate 540000 lane count 1
[14:03:35] [PASSED] Link rate 270000 lane count 4
[14:03:35] [PASSED] Link rate 270000 lane count 2
[14:03:35] [PASSED] Link rate 270000 lane count 1
[14:03:35] [PASSED] Link rate 162000 lane count 4
[14:03:35] [PASSED] Link rate 162000 lane count 2
[14:03:35] [PASSED] Link rate 162000 lane count 1
[14:03:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:03:35] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[14:03:35] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:03:35] [PASSED] DP_POWER_UP_PHY with port number
[14:03:35] [PASSED] DP_POWER_DOWN_PHY with port number
[14:03:35] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:03:35] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:03:35] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:03:35] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:03:35] [PASSED] DP_QUERY_PAYLOAD with port number
[14:03:35] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:03:35] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:03:35] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:03:35] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:03:35] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:03:35] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:03:35] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:03:35] [PASSED] DP_REMOTE_I2C_READ with port number
[14:03:35] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:03:35] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:03:35] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:03:35] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:03:35] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:03:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:03:35] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:03:35] ================ [PASSED] drm_dp_mst_helper ================
[14:03:35] ================== drm_exec (7 subtests) ===================
[14:03:35] [PASSED] sanitycheck
[14:03:35] [PASSED] test_lock
[14:03:35] [PASSED] test_lock_unlock
[14:03:35] [PASSED] test_duplicates
[14:03:35] [PASSED] test_prepare
[14:03:35] [PASSED] test_prepare_array
[14:03:35] [PASSED] test_multiple_loops
[14:03:35] ==================== [PASSED] drm_exec =====================
[14:03:35] =========== drm_format_helper_test (17 subtests) ===========
[14:03:35] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:03:35] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:03:35] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:03:35] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:03:35] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:03:35] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:03:35] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:03:35] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:03:35] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:03:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:03:35] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:03:35] ============== drm_test_fb_xrgb8888_to_mono ===============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:03:35] ==================== drm_test_fb_swab =====================
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ================ [PASSED] drm_test_fb_swab =================
[14:03:35] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:03:35] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[14:03:35] [PASSED] single_pixel_source_buffer
[14:03:35] [PASSED] single_pixel_clip_rectangle
[14:03:35] [PASSED] well_known_colors
[14:03:35] [PASSED] destination_pitch
[14:03:35] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:03:35] ================= drm_test_fb_clip_offset =================
[14:03:35] [PASSED] pass through
[14:03:35] [PASSED] horizontal offset
[14:03:35] [PASSED] vertical offset
[14:03:35] [PASSED] horizontal and vertical offset
[14:03:35] [PASSED] horizontal offset (custom pitch)
[14:03:35] [PASSED] vertical offset (custom pitch)
[14:03:35] [PASSED] horizontal and vertical offset (custom pitch)
[14:03:35] ============= [PASSED] drm_test_fb_clip_offset =============
[14:03:35] =================== drm_test_fb_memcpy ====================
[14:03:35] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:03:35] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:03:35] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:03:35] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:03:35] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:03:35] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:03:35] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:03:35] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:03:35] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:03:35] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:03:35] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:03:35] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:03:35] =============== [PASSED] drm_test_fb_memcpy ================
[14:03:35] ============= [PASSED] drm_format_helper_test ==============
[14:03:35] ================= drm_format (18 subtests) =================
[14:03:35] [PASSED] drm_test_format_block_width_invalid
[14:03:35] [PASSED] drm_test_format_block_width_one_plane
[14:03:35] [PASSED] drm_test_format_block_width_two_plane
[14:03:35] [PASSED] drm_test_format_block_width_three_plane
[14:03:35] [PASSED] drm_test_format_block_width_tiled
[14:03:35] [PASSED] drm_test_format_block_height_invalid
[14:03:35] [PASSED] drm_test_format_block_height_one_plane
[14:03:35] [PASSED] drm_test_format_block_height_two_plane
[14:03:35] [PASSED] drm_test_format_block_height_three_plane
[14:03:35] [PASSED] drm_test_format_block_height_tiled
[14:03:35] [PASSED] drm_test_format_min_pitch_invalid
[14:03:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:03:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:03:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:03:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:03:35] [PASSED] drm_test_format_min_pitch_two_plane
[14:03:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:03:35] [PASSED] drm_test_format_min_pitch_tiled
[14:03:35] =================== [PASSED] drm_format ====================
[14:03:35] ============== drm_framebuffer (10 subtests) ===============
[14:03:35] ========== drm_test_framebuffer_check_src_coords ==========
[14:03:35] [PASSED] Success: source fits into fb
[14:03:35] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:03:35] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:03:35] [PASSED] Fail: overflowing fb with source width
[14:03:35] [PASSED] Fail: overflowing fb with source height
[14:03:35] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:03:35] [PASSED] drm_test_framebuffer_cleanup
[14:03:35] =============== drm_test_framebuffer_create ===============
[14:03:35] [PASSED] ABGR8888 normal sizes
[14:03:35] [PASSED] ABGR8888 max sizes
[14:03:35] [PASSED] ABGR8888 pitch greater than min required
[14:03:35] [PASSED] ABGR8888 pitch less than min required
[14:03:35] [PASSED] ABGR8888 Invalid width
[14:03:35] [PASSED] ABGR8888 Invalid buffer handle
[14:03:35] [PASSED] No pixel format
[14:03:35] [PASSED] ABGR8888 Width 0
[14:03:35] [PASSED] ABGR8888 Height 0
[14:03:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:03:35] [PASSED] ABGR8888 Large buffer offset
[14:03:35] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:03:35] [PASSED] ABGR8888 Invalid flag
[14:03:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:03:35] [PASSED] ABGR8888 Valid buffer modifier
[14:03:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:03:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] NV12 Normal sizes
[14:03:35] [PASSED] NV12 Max sizes
[14:03:35] [PASSED] NV12 Invalid pitch
[14:03:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:03:35] [PASSED] NV12 different modifier per-plane
[14:03:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:03:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] NV12 Modifier for inexistent plane
[14:03:35] [PASSED] NV12 Handle for inexistent plane
[14:03:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:03:35] [PASSED] YVU420 Normal sizes
[14:03:35] [PASSED] YVU420 Max sizes
[14:03:35] [PASSED] YVU420 Invalid pitch
[14:03:35] [PASSED] YVU420 Different pitches
[14:03:35] [PASSED] YVU420 Different buffer offsets/pitches
[14:03:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:03:35] [PASSED] YVU420 Valid modifier
[14:03:35] [PASSED] YVU420 Different modifiers per plane
[14:03:35] [PASSED] YVU420 Modifier for inexistent plane
[14:03:35] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:03:35] [PASSED] X0L2 Normal sizes
[14:03:35] [PASSED] X0L2 Max sizes
[14:03:35] [PASSED] X0L2 Invalid pitch
[14:03:35] [PASSED] X0L2 Pitch greater than minimum required
[14:03:35] [PASSED] X0L2 Handle for inexistent plane
[14:03:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:03:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:03:35] [PASSED] X0L2 Valid modifier
[14:03:35] [PASSED] X0L2 Modifier for inexistent plane
[14:03:35] =========== [PASSED] drm_test_framebuffer_create ===========
[14:03:35] [PASSED] drm_test_framebuffer_free
[14:03:35] [PASSED] drm_test_framebuffer_init
[14:03:35] [PASSED] drm_test_framebuffer_init_bad_format
[14:03:35] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:03:35] [PASSED] drm_test_framebuffer_lookup
[14:03:35] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:03:35] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:03:35] ================= [PASSED] drm_framebuffer =================
[14:03:35] ================ drm_gem_shmem (8 subtests) ================
[14:03:35] [PASSED] drm_gem_shmem_test_obj_create
[14:03:35] [PASSED] drm_gem_shmem_test_obj_create_private
[14:03:35] [PASSED] drm_gem_shmem_test_pin_pages
[14:03:35] [PASSED] drm_gem_shmem_test_vmap
[14:03:35] [PASSED] drm_gem_shmem_test_get_sg_table
[14:03:35] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:03:35] [PASSED] drm_gem_shmem_test_madvise
[14:03:35] [PASSED] drm_gem_shmem_test_purge
[14:03:35] ================== [PASSED] drm_gem_shmem ==================
[14:03:35] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:03:35] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[14:03:35] [PASSED] Automatic
[14:03:35] [PASSED] Full
[14:03:35] [PASSED] Limited 16:235
[14:03:35] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:03:35] [PASSED] drm_test_check_disable_connector
[14:03:35] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:03:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:03:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:03:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:03:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:03:35] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:03:35] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:03:35] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:03:35] [PASSED] drm_test_check_output_bpc_dvi
[14:03:35] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:03:35] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:03:35] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:03:35] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:03:35] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:03:35] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:03:35] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:03:35] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:03:35] ============ drm_test_check_hdmi_color_format =============
[14:03:35] [PASSED] AUTO -> RGB
[14:03:35] [PASSED] YCBCR422 -> YUV422
[14:03:35] [PASSED] YCBCR420 -> YUV420
[14:03:35] [PASSED] YCBCR444 -> YUV444
[14:03:35] [PASSED] RGB -> RGB
[14:03:35] ======== [PASSED] drm_test_check_hdmi_color_format =========
[14:03:35] ======== drm_test_check_hdmi_color_format_420_only ========
[14:03:35] [PASSED] RGB should fail
[14:03:35] [PASSED] YUV444 should fail
[14:03:35] [PASSED] YUV422 should fail
[14:03:35] [PASSED] YUV420 should work
[14:03:35] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[14:03:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:03:35] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:03:35] [PASSED] drm_test_check_broadcast_rgb_value
[14:03:35] [PASSED] drm_test_check_bpc_8_value
[14:03:35] [PASSED] drm_test_check_bpc_10_value
[14:03:35] [PASSED] drm_test_check_bpc_12_value
[14:03:35] [PASSED] drm_test_check_format_value
[14:03:35] [PASSED] drm_test_check_tmds_char_value
[14:03:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:03:35] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[14:03:35] [PASSED] drm_test_check_mode_valid
[14:03:35] [PASSED] drm_test_check_mode_valid_reject
[14:03:35] [PASSED] drm_test_check_mode_valid_reject_rate
[14:03:35] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:03:35] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[14:03:35] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[14:03:35] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[14:03:35] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:03:35] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[14:03:35] [PASSED] drm_test_check_infoframes
[14:03:35] [PASSED] drm_test_check_reject_avi_infoframe
[14:03:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[14:03:35] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[14:03:35] [PASSED] drm_test_check_reject_audio_infoframe
[14:03:35] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[14:03:35] ================= drm_managed (2 subtests) =================
[14:03:35] [PASSED] drm_test_managed_release_action
[14:03:35] [PASSED] drm_test_managed_run_action
[14:03:35] =================== [PASSED] drm_managed ===================
[14:03:35] =================== drm_mm (6 subtests) ====================
[14:03:35] [PASSED] drm_test_mm_init
[14:03:35] [PASSED] drm_test_mm_debug
[14:03:35] [PASSED] drm_test_mm_align32
[14:03:35] [PASSED] drm_test_mm_align64
[14:03:35] [PASSED] drm_test_mm_lowest
[14:03:35] [PASSED] drm_test_mm_highest
[14:03:35] ===================== [PASSED] drm_mm ======================
[14:03:35] ============= drm_modes_analog_tv (5 subtests) =============
[14:03:35] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:03:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:03:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:03:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:03:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:03:35] =============== [PASSED] drm_modes_analog_tv ===============
[14:03:35] ============== drm_panic_helper (3 subtests) ===============
[14:03:35] ============= drm_test_panic_screen_user_map ==============
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] ========= [PASSED] drm_test_panic_screen_user_map ==========
[14:03:35] ============= drm_test_panic_screen_user_page =============
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] ========= [PASSED] drm_test_panic_screen_user_page =========
[14:03:35] ========== drm_test_panic_screen_user_set_pixel ===========
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[14:03:35] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[14:03:35] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[14:03:35] ================ [PASSED] drm_panic_helper =================
[14:03:35] ============== drm_plane_helper (2 subtests) ===============
[14:03:35] =============== drm_test_check_plane_state ================
[14:03:35] [PASSED] clipping_simple
[14:03:35] [PASSED] clipping_rotate_reflect
[14:03:35] [PASSED] positioning_simple
[14:03:35] [PASSED] upscaling
[14:03:35] [PASSED] downscaling
[14:03:35] [PASSED] rounding1
[14:03:35] [PASSED] rounding2
[14:03:35] [PASSED] rounding3
[14:03:35] [PASSED] rounding4
[14:03:35] =========== [PASSED] drm_test_check_plane_state ============
[14:03:35] =========== drm_test_check_invalid_plane_state ============
[14:03:35] [PASSED] positioning_invalid
[14:03:35] [PASSED] upscaling_invalid
[14:03:35] [PASSED] downscaling_invalid
[14:03:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:03:35] ================ [PASSED] drm_plane_helper =================
[14:03:35] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:03:35] ====== drm_test_connector_helper_tv_get_modes_check =======
[14:03:35] [PASSED] None
[14:03:35] [PASSED] PAL
[14:03:35] [PASSED] NTSC
[14:03:35] [PASSED] Both, NTSC Default
[14:03:35] [PASSED] Both, PAL Default
[14:03:35] [PASSED] Both, NTSC Default, with PAL on command-line
[14:03:35] [PASSED] Both, PAL Default, with NTSC on command-line
[14:03:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:03:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:03:35] ================== drm_rect (9 subtests) ===================
[14:03:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:03:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:03:35] [PASSED] drm_test_rect_clip_scaled_clipped
[14:03:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:03:35] ================= drm_test_rect_intersect =================
[14:03:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:03:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:03:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:03:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:03:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:03:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:03:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:03:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:03:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:03:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:03:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:03:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:03:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:03:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:03:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:03:35] ============= [PASSED] drm_test_rect_intersect =============
[14:03:35] ================ drm_test_rect_calc_hscale ================
[14:03:35] [PASSED] normal use
[14:03:35] [PASSED] out of max range
[14:03:35] [PASSED] out of min range
[14:03:35] [PASSED] zero dst
[14:03:35] [PASSED] negative src
[14:03:35] [PASSED] negative dst
[14:03:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:03:35] ================ drm_test_rect_calc_vscale ================
[14:03:35] [PASSED] normal use
[14:03:35] [PASSED] out of max range
[14:03:35] [PASSED] out of min range
[14:03:35] [PASSED] zero dst
[14:03:35] [PASSED] negative src
[14:03:35] [PASSED] negative dst
[14:03:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:03:35] ================== drm_test_rect_rotate ===================
[14:03:35] [PASSED] reflect-x
[14:03:35] [PASSED] reflect-y
[14:03:35] [PASSED] rotate-0
[14:03:35] [PASSED] rotate-90
[14:03:35] [PASSED] rotate-180
[14:03:35] [PASSED] rotate-270
[14:03:35] ============== [PASSED] drm_test_rect_rotate ===============
[14:03:35] ================ drm_test_rect_rotate_inv =================
[14:03:35] [PASSED] reflect-x
[14:03:35] [PASSED] reflect-y
[14:03:35] [PASSED] rotate-0
[14:03:35] [PASSED] rotate-90
[14:03:35] [PASSED] rotate-180
[14:03:35] [PASSED] rotate-270
[14:03:35] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:03:35] ==================== [PASSED] drm_rect =====================
[14:03:35] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:03:35] ============ drm_test_sysfb_build_fourcc_list =============
[14:03:35] [PASSED] no native formats
[14:03:35] [PASSED] XRGB8888 as native format
[14:03:35] [PASSED] remove duplicates
[14:03:35] [PASSED] convert alpha formats
[14:03:35] [PASSED] random formats
[14:03:35] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:03:35] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:03:35] ================== drm_fixp (2 subtests) ===================
[14:03:35] [PASSED] drm_test_int2fixp
[14:03:35] [PASSED] drm_test_sm2fixp
[14:03:35] ==================== [PASSED] drm_fixp =====================
[14:03:35] ============================================================
[14:03:35] Testing complete. Ran 667 tests: passed: 667
[14:03:35] Elapsed time: 27.735s total, 1.881s configuring, 25.438s building, 0.409s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:03:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:03:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:03:47] Starting KUnit Kernel (1/1)...
[14:03:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:03:48] ================= ttm_device (5 subtests) ==================
[14:03:48] [PASSED] ttm_device_init_basic
[14:03:48] [PASSED] ttm_device_init_multiple
[14:03:48] [PASSED] ttm_device_fini_basic
[14:03:48] [PASSED] ttm_device_init_no_vma_man
[14:03:48] ================== ttm_device_init_pools ==================
[14:03:48] [PASSED] No DMA allocations, no DMA32 required
[14:03:48] [PASSED] DMA allocations, DMA32 required
[14:03:48] [PASSED] No DMA allocations, DMA32 required
[14:03:48] [PASSED] DMA allocations, no DMA32 required
[14:03:48] ============== [PASSED] ttm_device_init_pools ==============
[14:03:48] =================== [PASSED] ttm_device ====================
[14:03:48] ================== ttm_pool (8 subtests) ===================
[14:03:48] ================== ttm_pool_alloc_basic ===================
[14:03:48] [PASSED] One page
[14:03:48] [PASSED] More than one page
[14:03:48] [PASSED] Above the allocation limit
[14:03:48] [PASSED] One page, with coherent DMA mappings enabled
[14:03:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:03:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:03:48] ============== ttm_pool_alloc_basic_dma_addr ==============
[14:03:48] [PASSED] One page
[14:03:48] [PASSED] More than one page
[14:03:48] [PASSED] Above the allocation limit
[14:03:48] [PASSED] One page, with coherent DMA mappings enabled
[14:03:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:03:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:03:48] [PASSED] ttm_pool_alloc_order_caching_match
[14:03:48] [PASSED] ttm_pool_alloc_caching_mismatch
[14:03:48] [PASSED] ttm_pool_alloc_order_mismatch
[14:03:48] [PASSED] ttm_pool_free_dma_alloc
[14:03:48] [PASSED] ttm_pool_free_no_dma_alloc
[14:03:48] [PASSED] ttm_pool_fini_basic
[14:03:48] ==================== [PASSED] ttm_pool =====================
[14:03:48] ================ ttm_resource (8 subtests) =================
[14:03:48] ================= ttm_resource_init_basic =================
[14:03:48] [PASSED] Init resource in TTM_PL_SYSTEM
[14:03:48] [PASSED] Init resource in TTM_PL_VRAM
[14:03:48] [PASSED] Init resource in a private placement
[14:03:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:03:48] ============= [PASSED] ttm_resource_init_basic =============
[14:03:48] [PASSED] ttm_resource_init_pinned
[14:03:48] [PASSED] ttm_resource_fini_basic
[14:03:48] [PASSED] ttm_resource_manager_init_basic
[14:03:48] [PASSED] ttm_resource_manager_usage_basic
[14:03:48] [PASSED] ttm_resource_manager_set_used_basic
[14:03:48] [PASSED] ttm_sys_man_alloc_basic
[14:03:48] [PASSED] ttm_sys_man_free_basic
[14:03:48] ================== [PASSED] ttm_resource ===================
[14:03:48] =================== ttm_tt (15 subtests) ===================
[14:03:48] ==================== ttm_tt_init_basic ====================
[14:03:48] [PASSED] Page-aligned size
[14:03:48] [PASSED] Extra pages requested
[14:03:48] ================ [PASSED] ttm_tt_init_basic ================
[14:03:48] [PASSED] ttm_tt_init_misaligned
[14:03:48] [PASSED] ttm_tt_fini_basic
[14:03:48] [PASSED] ttm_tt_fini_sg
[14:03:48] [PASSED] ttm_tt_fini_shmem
[14:03:48] [PASSED] ttm_tt_create_basic
[14:03:48] [PASSED] ttm_tt_create_invalid_bo_type
[14:03:48] [PASSED] ttm_tt_create_ttm_exists
[14:03:48] [PASSED] ttm_tt_create_failed
[14:03:48] [PASSED] ttm_tt_destroy_basic
[14:03:48] [PASSED] ttm_tt_populate_null_ttm
[14:03:48] [PASSED] ttm_tt_populate_populated_ttm
[14:03:48] [PASSED] ttm_tt_unpopulate_basic
[14:03:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:03:48] [PASSED] ttm_tt_swapin_basic
[14:03:48] ===================== [PASSED] ttm_tt ======================
[14:03:48] =================== ttm_bo (14 subtests) ===================
[14:03:48] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[14:03:48] [PASSED] Cannot be interrupted and sleeps
[14:03:48] [PASSED] Cannot be interrupted, locks straight away
[14:03:48] [PASSED] Can be interrupted, sleeps
[14:03:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:03:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:03:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:03:48] [PASSED] ttm_bo_reserve_double_resv
[14:03:48] [PASSED] ttm_bo_reserve_interrupted
[14:03:48] [PASSED] ttm_bo_reserve_deadlock
[14:03:48] [PASSED] ttm_bo_unreserve_basic
[14:03:48] [PASSED] ttm_bo_unreserve_pinned
[14:03:48] [PASSED] ttm_bo_unreserve_bulk
[14:03:48] [PASSED] ttm_bo_fini_basic
[14:03:48] [PASSED] ttm_bo_fini_shared_resv
[14:03:48] [PASSED] ttm_bo_pin_basic
[14:03:48] [PASSED] ttm_bo_pin_unpin_resource
[14:03:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:03:48] ===================== [PASSED] ttm_bo ======================
[14:03:48] ============== ttm_bo_validate (22 subtests) ===============
[14:03:48] ============== ttm_bo_init_reserved_sys_man ===============
[14:03:48] [PASSED] Buffer object for userspace
[14:03:48] [PASSED] Kernel buffer object
[14:03:48] [PASSED] Shared buffer object
[14:03:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:03:48] ============== ttm_bo_init_reserved_mock_man ==============
[14:03:48] [PASSED] Buffer object for userspace
[14:03:48] [PASSED] Kernel buffer object
[14:03:48] [PASSED] Shared buffer object
[14:03:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:03:48] [PASSED] ttm_bo_init_reserved_resv
[14:03:48] ================== ttm_bo_validate_basic ==================
[14:03:48] [PASSED] Buffer object for userspace
[14:03:48] [PASSED] Kernel buffer object
[14:03:48] [PASSED] Shared buffer object
[14:03:48] ============== [PASSED] ttm_bo_validate_basic ==============
[14:03:48] [PASSED] ttm_bo_validate_invalid_placement
[14:03:48] ============= ttm_bo_validate_same_placement ==============
[14:03:48] [PASSED] System manager
[14:03:48] [PASSED] VRAM manager
[14:03:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:03:48] [PASSED] ttm_bo_validate_failed_alloc
[14:03:48] [PASSED] ttm_bo_validate_pinned
[14:03:48] [PASSED] ttm_bo_validate_busy_placement
[14:03:48] ================ ttm_bo_validate_multihop =================
[14:03:48] [PASSED] Buffer object for userspace
[14:03:48] [PASSED] Kernel buffer object
[14:03:48] [PASSED] Shared buffer object
[14:03:48] ============ [PASSED] ttm_bo_validate_multihop =============
[14:03:48] ========== ttm_bo_validate_no_placement_signaled ==========
[14:03:48] [PASSED] Buffer object in system domain, no page vector
[14:03:48] [PASSED] Buffer object in system domain with an existing page vector
[14:03:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:03:48] ======== ttm_bo_validate_no_placement_not_signaled ========
[14:03:48] [PASSED] Buffer object for userspace
[14:03:48] [PASSED] Kernel buffer object
[14:03:48] [PASSED] Shared buffer object
[14:03:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:03:48] [PASSED] ttm_bo_validate_move_fence_signaled
[14:03:48] ========= ttm_bo_validate_move_fence_not_signaled =========
[14:03:48] [PASSED] Waits for GPU
[14:03:48] [PASSED] Tries to lock straight away
[14:03:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:03:48] [PASSED] ttm_bo_validate_swapout
[14:03:48] [PASSED] ttm_bo_validate_happy_evict
[14:03:48] [PASSED] ttm_bo_validate_all_pinned_evict
[14:03:48] [PASSED] ttm_bo_validate_allowed_only_evict
[14:03:48] [PASSED] ttm_bo_validate_deleted_evict
[14:03:48] [PASSED] ttm_bo_validate_busy_domain_evict
[14:03:48] [PASSED] ttm_bo_validate_evict_gutting
[14:03:48] [PASSED] ttm_bo_validate_recrusive_evict
[14:03:48] ================= [PASSED] ttm_bo_validate =================
[14:03:48] ============================================================
[14:03:48] Testing complete. Ran 102 tests: passed: 102
[14:03:48] Elapsed time: 12.306s total, 1.784s configuring, 10.306s building, 0.184s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[14:03:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:03:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:03:59] Starting KUnit Kernel (1/1)...
[14:03:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:03:59] =============== dma-buf-fence (12 subtests) ================
[14:03:59] [PASSED] test_sanitycheck
[14:03:59] [PASSED] test_signaling
[14:03:59] [PASSED] test_add_callback
[14:03:59] [PASSED] test_late_add_callback
[14:03:59] [PASSED] test_rm_callback
[14:03:59] [PASSED] test_late_rm_callback
[14:03:59] [PASSED] test_status
[14:03:59] [PASSED] test_error
[14:03:59] [PASSED] test_wait
[14:03:59] [PASSED] test_wait_timeout
[14:03:59] [PASSED] test_stub
[14:03:59] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[14:03:59] ================== [PASSED] dma-buf-fence ==================
[14:03:59] ============ dma-buf-fence-chain (11 subtests) =============
[14:03:59] [PASSED] test_sanitycheck
[14:03:59] [PASSED] test_find_seqno
[14:03:59] [PASSED] test_find_signaled
[14:03:59] [PASSED] test_find_out_of_order
[14:04:04] [PASSED] test_find_gap
[14:04:04] [PASSED] test_find_race
[14:04:04] [PASSED] test_signal_forward
[14:04:04] [PASSED] test_signal_backward
[14:04:04] [PASSED] test_wait_forward
[14:04:04] [PASSED] test_wait_backward
[14:04:04] [PASSED] test_wait_random
[14:04:04] =============== [PASSED] dma-buf-fence-chain ===============
[14:04:04] ============ dma-buf-fence-unwrap (11 subtests) ============
[14:04:04] [PASSED] test_sanitycheck
[14:04:04] [PASSED] test_unwrap_array
[14:04:04] [PASSED] test_unwrap_chain
[14:04:04] [PASSED] test_unwrap_chain_array
[14:04:04] [PASSED] test_unwrap_merge
[14:04:04] [PASSED] test_unwrap_merge_duplicate
[14:04:04] [PASSED] test_unwrap_merge_seqno
[14:04:04] [PASSED] test_unwrap_merge_order
[14:04:04] [PASSED] test_unwrap_merge_complex
[14:04:04] [PASSED] test_unwrap_merge_complex_seqno
[14:04:04] [PASSED] test_dedup_empty
[14:04:04] ============== [PASSED] dma-buf-fence-unwrap ===============
[14:04:04] ================ dma-buf-resv (5 subtests) =================
[14:04:04] [PASSED] test_sanitycheck
[14:04:04] ===================== test_signaling ======================
[14:04:04] [PASSED] kernel
[14:04:04] [PASSED] write
[14:04:04] [PASSED] read
[14:04:04] [PASSED] bookkeep
[14:04:04] ================= [PASSED] test_signaling ==================
[14:04:04] ====================== test_for_each ======================
[14:04:04] [PASSED] kernel
[14:04:04] [PASSED] write
[14:04:04] [PASSED] read
[14:04:04] [PASSED] bookkeep
[14:04:04] ================== [PASSED] test_for_each ==================
[14:04:04] ================= test_for_each_unlocked ==================
[14:04:04] [PASSED] kernel
[14:04:04] [PASSED] write
[14:04:04] [PASSED] read
[14:04:04] [PASSED] bookkeep
[14:04:04] ============= [PASSED] test_for_each_unlocked ==============
[14:04:04] ===================== test_get_fences =====================
[14:04:04] [PASSED] kernel
[14:04:04] [PASSED] write
[14:04:04] [PASSED] read
[14:04:04] [PASSED] bookkeep
[14:04:04] ================= [PASSED] test_get_fences =================
[14:04:04] ================== [PASSED] dma-buf-resv ===================
[14:04:04] ============================================================
[14:04:04] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[14:04:04] Elapsed time: 16.038s total, 1.891s configuring, 8.876s building, 5.264s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 33+ messages in thread* ✓ Xe.CI.BAT: success for drm/i915/pfit: Make GMCH panel fitter nicer
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (16 preceding siblings ...)
2026-10-19 14:04 ` ✓ CI.KUnit: success " Patchwork
@ 2026-10-19 14:45 ` Patchwork
2026-10-19 17:03 ` ✓ Xe.CI.FULL: " Patchwork
2026-10-19 17:23 ` ✓ i915.CI.BAT: " Patchwork
19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2026-10-19 14:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 957 bytes --]
== Series Details ==
Series: drm/i915/pfit: Make GMCH panel fitter nicer
URL : https://patchwork.freedesktop.org/series/176401/
State : success
== Summary ==
CI Bug Log - changes from xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767_BAT -> xe-pw-176401v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767 -> xe-pw-176401v1
IGT_9150: 18811c476bfde62ffbb4c0af55cd6f57e36e0dca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767: b0311e0de50840c3f35aafa2e95c14bf38f4a767
xe-pw-176401v1: 176401v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/index.html
[-- Attachment #2: Type: text/html, Size: 1505 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread* ✓ Xe.CI.FULL: success for drm/i915/pfit: Make GMCH panel fitter nicer
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (17 preceding siblings ...)
2026-10-19 14:45 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-10-19 17:03 ` Patchwork
2026-10-19 17:23 ` ✓ i915.CI.BAT: " Patchwork
19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2026-10-19 17:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 65332 bytes --]
== Series Details ==
Series: drm/i915/pfit: Make GMCH panel fitter nicer
URL : https://patchwork.freedesktop.org/series/176401/
State : success
== Summary ==
CI Bug Log - changes from xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767_FULL -> xe-pw-176401v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767_FULL and xe-pw-176401v1_FULL:
### New IGT tests (1) ###
* igt@xe_oa@buffer-size@oag-0-64m:
- Statuses : 1 pass(s)
- Exec time: [4.71] s
Known issues
------------
Here are the changes found in xe-pw-176401v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-ptl: NOTRUN -> [SKIP][1] ([Intel XE#5947])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#2327]) +1 other test skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-ptl: NOTRUN -> [SKIP][3] ([Intel XE#5901])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][4] ([Intel XE#1407]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-ptl: NOTRUN -> [SKIP][5] ([Intel XE#5808]) +12 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][6] ([Intel XE#1124])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#1124])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-ptl: NOTRUN -> [SKIP][8] ([Intel XE#5851])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p:
- shard-ptl: NOTRUN -> [SKIP][9] ([Intel XE#7679]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p:
- shard-lnl: NOTRUN -> [SKIP][10] ([Intel XE#7679])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html
* igt@kms_bw@linear-tiling-4-displays-target-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#367])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_bw@linear-tiling-4-displays-target-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-target-2560x1440p:
- shard-ptl: NOTRUN -> [SKIP][12] ([Intel XE#367]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_bw@linear-tiling-4-displays-target-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][13] ([Intel XE#2887]) +4 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2887]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][15] ([Intel XE#5823] / [Intel XE#6918]) +9 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3:
- shard-bmg: [PASS][16] -> [INCOMPLETE][17] ([Intel XE#7084] / [Intel XE#8150])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#3432])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
- shard-ptl: NOTRUN -> [SKIP][19] ([Intel XE#5822]) +7 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-ptl: NOTRUN -> [SKIP][20] ([Intel XE#9205]) +4 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#373]) +3 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-ptl: NOTRUN -> [SKIP][22] ([Intel XE#5824])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020:
- shard-ptl: NOTRUN -> [SKIP][23] ([Intel XE#8391]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020.html
* igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#7358])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html
* igt@kms_chamelium_edid@hdmi-mode-timings:
- shard-ptl: NOTRUN -> [SKIP][25] ([Intel XE#2252]) +9 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_chamelium_edid@hdmi-mode-timings.html
* igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2252])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
* igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-d-plane-4:
- shard-ptl: NOTRUN -> [SKIP][27] ([Intel XE#6969]) +7 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_color_pipeline@plane-lut1d-post-ctm3x4@pipe-d-plane-4.html
* igt@kms_content_protection@atomic-hdcp14:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#7642])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_content_protection@atomic-hdcp14.html
* igt@kms_content_protection@dp-mst-type-0-hdcp14:
- shard-ptl: NOTRUN -> [SKIP][29] ([Intel XE#6974])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
* igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][30] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-4/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html
* igt@kms_content_protection@srm:
- shard-ptl: NOTRUN -> [SKIP][31] ([Intel XE#7642]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-ptl: NOTRUN -> [SKIP][32] ([Intel XE#5846]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-ptl: NOTRUN -> [SKIP][33] ([Intel XE#5900]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#2320])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-ptl: NOTRUN -> [SKIP][35] ([Intel XE#5962]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#309] / [Intel XE#7343])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-ptl: NOTRUN -> [SKIP][37] ([Intel XE#5958])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#8265])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-formats-bigjoiner:
- shard-ptl: NOTRUN -> [SKIP][39] ([Intel XE#5907]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_dsc@dsc-with-formats-bigjoiner.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#4422] / [Intel XE#7442])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-ptl: NOTRUN -> [SKIP][41] ([Intel XE#2316]) +7 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#1421])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][43] -> [FAIL][44] ([Intel XE#301])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][45] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-ptl: NOTRUN -> [SKIP][46] ([Intel XE#5828]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-ptl: NOTRUN -> [SKIP][48] ([Intel XE#7178]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt:
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][50] ([Intel XE#6312]) +13 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#4141]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render:
- shard-ptl: NOTRUN -> [SKIP][52] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary:
- shard-ptl: NOTRUN -> [SKIP][53] ([Intel XE#5800] / [Intel XE#6312]) +6 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#2311]) +10 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-draw-render:
- shard-ptl: NOTRUN -> [SKIP][55] ([Intel XE#5812]) +60 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#6312]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][57] ([Intel XE#7865]) +16 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][58] ([Intel XE#7905]) +9 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#656] / [Intel XE#7905]) +9 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2313]) +12 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
- shard-ptl: NOTRUN -> [SKIP][61] ([Intel XE#7399])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html
* igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][62] ([Intel XE#7061]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-render:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#7865]) +6 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdmi_audio_bw@audio-bw-hblank80:
- shard-ptl: NOTRUN -> [SKIP][65] ([Intel XE#9312])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
* igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery:
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#9312])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_hdmi_audio_bw@suspend-disk-audio-recovery.html
* igt@kms_hdmi_inject@inject-audio:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#1470] / [Intel XE#2853])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-ptl: NOTRUN -> [SKIP][68] ([Intel XE#5917] / [Intel XE#6174])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-ptl: NOTRUN -> [SKIP][69] ([Intel XE#6900])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-xtiled:
- shard-ptl: NOTRUN -> [SKIP][70] ([Intel XE#6912]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#4329] / [Intel XE#6912] / [Intel XE#7375])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
- shard-ptl: NOTRUN -> [FAIL][72] ([Intel XE#9340]) +1 other test fail
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#7283])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html
* igt@kms_plane@pixel-format-x-tiled-modifier-source-clamping:
- shard-ptl: NOTRUN -> [SKIP][74] ([Intel XE#7283]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_plane@pixel-format-x-tiled-modifier-source-clamping.html
* igt@kms_plane@pixel-format-y-tiled-modifier:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#7283]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-modifier.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
- shard-lnl: NOTRUN -> [SKIP][76] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d:
- shard-ptl: NOTRUN -> [SKIP][77] ([Intel XE#6886]) +4 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d.html
* igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888:
- shard-ptl: NOTRUN -> [SKIP][78] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888.html
* igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
- shard-ptl: NOTRUN -> [SKIP][79] ([Intel XE#8396]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html
* igt@kms_pm_dc@dc3co-vpb-framegap@pr-xrgb8888:
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-framegap@pr-xrgb8888.html
* igt@kms_pm_dc@dc3co-vpb-framegap@psr2-xrgb8888:
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#8396]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-framegap@psr2-xrgb8888.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-lnl: NOTRUN -> [SKIP][82] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][83] ([Intel XE#5858])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
- shard-ptl: NOTRUN -> [SKIP][84] ([Intel XE#5858] / [Intel XE#7304]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#4608]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][87] ([Intel XE#4608] / [Intel XE#7304]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
- shard-ptl: NOTRUN -> [SKIP][88] ([Intel XE#7304]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#1489])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#2387] / [Intel XE#7429])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_psr2_su@page_flip-p010.html
- shard-ptl: NOTRUN -> [SKIP][91] ([Intel XE#7413])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#1406]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@fbc-pr-dpms:
- shard-ptl: NOTRUN -> [SKIP][93] ([Intel XE#1406]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@fbc-psr-suspend@edp-1:
- shard-ptl: NOTRUN -> [ABORT][95] ([Intel XE#9362]) +2 other tests abort
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@kms_psr@fbc-psr-suspend@edp-1.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-ptl: NOTRUN -> [SKIP][96] ([Intel XE#1406] / [Intel XE#5835]) +3 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-ptl: NOTRUN -> [SKIP][97] ([Intel XE#5813])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-lnl: NOTRUN -> [SKIP][98] ([Intel XE#1127] / [Intel XE#5813])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-ptl: NOTRUN -> [SKIP][99] ([Intel XE#5848])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-bmg: [PASS][100] -> [DMESG-WARN][101] ([Intel XE#9365]) +4 other tests dmesg-warn
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-7/igt@kms_vblank@ts-continuation-suspend.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-10/igt@kms_vblank@ts-continuation-suspend.html
- shard-ptl: [PASS][102] -> [ABORT][103] ([Intel XE#9362]) +6 other tests abort
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@kms_vblank@ts-continuation-suspend.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-3/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
- shard-ptl: [PASS][104] -> [FAIL][105] ([Intel XE#6293] / [Intel XE#7397])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-6/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-5/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
* igt@kms_vrr@flip-dpms@pipe-a-edp-1:
- shard-ptl: [PASS][106] -> [FAIL][107] ([Intel XE#4227] / [Intel XE#7397]) +4 other tests fail
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
* igt@kms_vrr@flipline:
- shard-lnl: [PASS][108] -> [FAIL][109] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-5/igt@kms_vrr@flipline.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-5/igt@kms_vrr@flipline.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-lnl: NOTRUN -> [SKIP][110] ([Intel XE#1091] / [Intel XE#2849])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@sriov_basic@pf-unbind-with-vf-probed:
- shard-ptl: NOTRUN -> [ABORT][111] ([Intel XE#8868])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@sriov_basic@pf-unbind-with-vf-probed.html
* igt@xe_ccs@vm-bind-fault-mode-decompress:
- shard-ptl: NOTRUN -> [SKIP][112] ([Intel XE#7644])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@xe_ccs@vm-bind-fault-mode-decompress.html
* igt@xe_evict@evict-beng-cm-threads-large:
- shard-lnl: NOTRUN -> [SKIP][113] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_evict@evict-beng-cm-threads-large.html
* igt@xe_evict@evict-beng-cm-threads-large-multi-vm:
- shard-ptl: NOTRUN -> [SKIP][114] ([Intel XE#5764]) +5 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_evict@evict-beng-cm-threads-large-multi-vm.html
* igt@xe_evict@evict-small-multi-queue-cm:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#8370])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@xe_evict@evict-small-multi-queue-cm.html
* igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen:
- shard-ptl: NOTRUN -> [SKIP][116] ([Intel XE#6144]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen.html
* igt@xe_exec_balancer@once-parallel-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][117] ([Intel XE#7482]) +11 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_exec_balancer@once-parallel-userptr-rebind.html
* igt@xe_exec_balancer@twice-cm-parallel-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#7482]) +4 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_exec_balancer@twice-cm-parallel-userptr-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
- shard-ptl: NOTRUN -> [SKIP][120] ([Intel XE#5575] / [Intel XE#7484]) +7 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-userptr:
- shard-lnl: NOTRUN -> [SKIP][121] ([Intel XE#1392]) +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_exec_basic@multigpu-once-userptr.html
* igt@xe_exec_fault_mode@once-multi-queue-invalid-fault:
- shard-ptl: NOTRUN -> [SKIP][122] ([Intel XE#8374]) +8 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_exec_fault_mode@once-multi-queue-invalid-fault.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch:
- shard-bmg: NOTRUN -> [SKIP][123] ([Intel XE#8374])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-prefetch.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-prefetch:
- shard-lnl: NOTRUN -> [SKIP][124] ([Intel XE#8374])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-prefetch.html
* igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority-smem:
- shard-lnl: NOTRUN -> [SKIP][125] ([Intel XE#8364]) +6 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority-smem.html
* igt@xe_exec_multi_queue@many-queues-priority-smem:
- shard-bmg: NOTRUN -> [SKIP][126] ([Intel XE#8364]) +4 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@xe_exec_multi_queue@many-queues-priority-smem.html
* igt@xe_exec_multi_queue@max-queues-preempt-mode-priority:
- shard-ptl: NOTRUN -> [SKIP][127] ([Intel XE#8364]) +22 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_exec_multi_queue@max-queues-preempt-mode-priority.html
* igt@xe_exec_reset@multi-queue-close-execqueues:
- shard-ptl: NOTRUN -> [SKIP][128] ([Intel XE#8369]) +2 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@xe_exec_reset@multi-queue-close-execqueues.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma:
- shard-ptl: NOTRUN -> [SKIP][129] ([Intel XE#6196]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma.html
* igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
- shard-bmg: [PASS][130] -> [FAIL][131] ([Intel XE#9096])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-4/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-5/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
* igt@xe_exec_threads@threads-multi-queue-mixed-basic:
- shard-lnl: NOTRUN -> [SKIP][132] ([Intel XE#8378]) +1 other test skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-mixed-basic.html
* igt@xe_exec_threads@threads-multi-queue-shared-vm-basic:
- shard-ptl: NOTRUN -> [SKIP][133] ([Intel XE#8378]) +5 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_exec_threads@threads-multi-queue-shared-vm-basic.html
- shard-bmg: NOTRUN -> [SKIP][134] ([Intel XE#8378])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-shared-vm-basic.html
* igt@xe_madvise@atomic-cpu:
- shard-ptl: NOTRUN -> [SKIP][135] ([Intel XE#7980])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_madvise@atomic-cpu.html
* igt@xe_media_fill@media-fill:
- shard-ptl: NOTRUN -> [SKIP][136] ([Intel XE#5830] / [Intel XE#7453])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_media_fill@media-fill.html
* igt@xe_mempage_offline@inject-duplicate-page:
- shard-ptl: NOTRUN -> [SKIP][137] ([Intel XE#9203])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_mempage_offline@inject-duplicate-page.html
* igt@xe_mmap@pci-membarrier:
- shard-lnl: NOTRUN -> [SKIP][138] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_mmap@pci-membarrier.html
* igt@xe_module_load@load:
- shard-ptl: ([PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163]) -> ([PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [SKIP][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189]) ([Intel XE#9286])
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-2/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-2/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-8/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-7/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-6/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-4/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-4/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-8/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-4/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-6/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-3/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-8/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-3/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-3/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-5/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-7/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-7/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-1/igt@xe_module_load@load.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-1/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-8/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-1/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-2/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-3/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-8/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-8/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-5/igt@xe_module_load@load.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_module_load@load.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_module_load@load.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_module_load@load.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-5/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-3/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@xe_module_load@load.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_module_load@load.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_module_load@load.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-7/igt@xe_module_load@load.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-3/igt@xe_module_load@load.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@xe_module_load@load.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@xe_module_load@load.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-4/igt@xe_module_load@load.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-8/igt@xe_module_load@load.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_module_load@load.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_module_load@load.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-5/igt@xe_module_load@load.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_module_load@load.html
* igt@xe_multigpu_svm@mgpu-latency-prefetch:
- shard-ptl: NOTRUN -> [SKIP][190] ([Intel XE#6964])
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_multigpu_svm@mgpu-latency-prefetch.html
* igt@xe_multigpu_svm@mgpu-pagefault-basic:
- shard-lnl: NOTRUN -> [SKIP][191] ([Intel XE#6964])
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_multigpu_svm@mgpu-pagefault-basic.html
* igt@xe_page_reclaim@binds-full-pd:
- shard-lnl: NOTRUN -> [SKIP][192] ([Intel XE#7793])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_page_reclaim@binds-full-pd.html
* igt@xe_page_reclaim@binds-large-split:
- shard-ptl: NOTRUN -> [SKIP][193] ([Intel XE#7793]) +1 other test skip
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_page_reclaim@binds-large-split.html
* igt@xe_pm@d3cold-mocs:
- shard-ptl: NOTRUN -> [SKIP][194] ([Intel XE#5741])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_pm@d3cold-mocs.html
* igt@xe_pm@d3hot-i2c:
- shard-lnl: NOTRUN -> [SKIP][195] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400])
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-ptl: NOTRUN -> [SKIP][196] ([Intel XE#6867])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pm@s4-exec-after:
- shard-lnl: [PASS][197] -> [ABORT][198] ([Intel XE#9426])
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-1/igt@xe_pm@s4-exec-after.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-2/igt@xe_pm@s4-exec-after.html
* igt@xe_query@multigpu-query-oa-units:
- shard-ptl: NOTRUN -> [SKIP][199] ([Intel XE#6019])
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_query@multigpu-query-oa-units.html
* igt@xe_sriov_scheduling@equal-throughput-low-priority:
- shard-lnl: NOTRUN -> [SKIP][200] ([Intel XE#8339])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_sriov_scheduling@equal-throughput-low-priority.html
* igt@xe_sriov_vram@vf-access-after-resize-up:
- shard-lnl: NOTRUN -> [SKIP][201] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_sriov_vram@vf-access-after-resize-up.html
* igt@xe_sriov_vram@vf-access-beyond:
- shard-ptl: NOTRUN -> [SKIP][202] ([Intel XE#6376] / [Intel XE#7422])
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-6/igt@xe_sriov_vram@vf-access-beyond.html
* igt@xe_survivability@runtime-survivability:
- shard-ptl: NOTRUN -> [SKIP][203] ([Intel XE#8415] / [Intel XE#8432])
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@xe_survivability@runtime-survivability.html
* igt@xe_vm@out-of-memory:
- shard-ptl: NOTRUN -> [SKIP][204] ([Intel XE#5745] / [Intel XE#7892])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_vm@out-of-memory.html
* igt@xe_vm@overcommit-fault-vram-lr-no-overcommit:
- shard-ptl: NOTRUN -> [SKIP][205] ([Intel XE#9597])
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-1/igt@xe_vm@overcommit-fault-vram-lr-no-overcommit.html
#### Possible fixes ####
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-lnl: [FAIL][206] ([Intel XE#1231]) -> [PASS][207]
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][208] ([Intel XE#301]) -> [PASS][209]
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-ptl: [FAIL][210] ([Intel XE#3321]) -> [PASS][211] +1 other test pass
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend:
- shard-bmg: [ABORT][212] ([Intel XE#9362]) -> [PASS][213] +1 other test pass
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-6/igt@kms_flip@flip-vs-suspend.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][214] ([Intel XE#1503]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-10/igt@kms_hdr@invalid-hdr.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-ptl: [ABORT][216] ([Intel XE#9362]) -> [PASS][217] +8 other tests pass
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-2/igt@kms_pm_backlight@fade-with-suspend.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-2/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_vrr@flip-basic:
- shard-ptl: [FAIL][218] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][219] +1 other test pass
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-ptl-2/igt@kms_vrr@flip-basic.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-ptl-8/igt@kms_vrr@flip-basic.html
* igt@xe_ccs@suspend-resume:
- shard-bmg: [ABORT][220] ([Intel XE#9362] / [Intel XE#9425] / [Intel XE#9581]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-4/igt@xe_ccs@suspend-resume.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-8/igt@xe_ccs@suspend-resume.html
* igt@xe_ccs@suspend-resume@tile4-compressed-compfmt0-system-vram01:
- shard-bmg: [ABORT][222] ([Intel XE#9362] / [Intel XE#9425]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-4/igt@xe_ccs@suspend-resume@tile4-compressed-compfmt0-system-vram01.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-8/igt@xe_ccs@suspend-resume@tile4-compressed-compfmt0-system-vram01.html
* igt@xe_pm@s4-basic-exec:
- shard-lnl: [ABORT][224] ([Intel XE#9362]) -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-lnl-8/igt@xe_pm@s4-basic-exec.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-lnl-3/igt@xe_pm@s4-basic-exec.html
#### Warnings ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [ABORT][226] ([Intel XE#9393] / [Intel XE#9406]) -> [INCOMPLETE][227] ([Intel XE#7084] / [Intel XE#8150])
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
[Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
[Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
[Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
[Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
[Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
[Intel XE#5830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5830
[Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
[Intel XE#5846]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5846
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
[Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
[Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
[Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
[Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
[Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
[Intel XE#5947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5947
[Intel XE#5958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5958
[Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
[Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
[Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
[Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
[Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
[Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
[Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
[Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
[Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
[Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
[Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
[Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
[Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
[Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
[Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
[Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
[Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
[Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
[Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
[Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
[Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
[Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
[Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
[Intel XE#8432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8432
[Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
[Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
[Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
[Intel XE#9203]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9203
[Intel XE#9205]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9205
[Intel XE#9286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9286
[Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
[Intel XE#9340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9340
[Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
[Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
[Intel XE#9393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9393
[Intel XE#9406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9406
[Intel XE#9425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9425
[Intel XE#9426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9426
[Intel XE#9581]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9581
[Intel XE#9597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9597
Build changes
-------------
* Linux: xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767 -> xe-pw-176401v1
IGT_9150: 18811c476bfde62ffbb4c0af55cd6f57e36e0dca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5975-b0311e0de50840c3f35aafa2e95c14bf38f4a767: b0311e0de50840c3f35aafa2e95c14bf38f4a767
xe-pw-176401v1: 176401v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-176401v1/index.html
[-- Attachment #2: Type: text/html, Size: 74188 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread* ✓ i915.CI.BAT: success for drm/i915/pfit: Make GMCH panel fitter nicer
2026-10-19 13:52 [PATCH 00/15] drm/i915/pfit: Make GMCH panel fitter nicer Ville Syrjala
` (18 preceding siblings ...)
2026-10-19 17:03 ` ✓ Xe.CI.FULL: " Patchwork
@ 2026-10-19 17:23 ` Patchwork
19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2026-10-19 17:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1080 bytes --]
== Series Details ==
Series: drm/i915/pfit: Make GMCH panel fitter nicer
URL : https://patchwork.freedesktop.org/series/176400/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_19362 -> Patchwork_176400v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_176400v1/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): bat-dg2-13
Changes
-------
No changes found
Build changes
-------------
* Linux: CI_DRM_19362 -> Patchwork_176400v1
CI-20190529: 20190529
CI_DRM_19362: a16b0e27155a8187d222dc914932a2d244d254b2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_9150: 18811c476bfde62ffbb4c0af55cd6f57e36e0dca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_176400v1: a16b0e27155a8187d222dc914932a2d244d254b2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_176400v1/index.html
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