All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Matt Ranostay <mranostay@ti.com>, <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <tjoseph@cadence.com>, <vigneshr@ti.com>
Subject: Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
Date: Fri, 23 Sep 2022 14:50:19 +0530	[thread overview]
Message-ID: <ce9bf8e3-bfb7-5f38-39ac-3a80da2c3839@ti.com> (raw)
In-Reply-To: <20220909201607.3835-2-mranostay@ti.com>

Hi Matt,

On 10/09/22 1:46 am, Matt Ranostay wrote:
> Increase LANE_COUNT_MASK to two-bit field that allows selection of
> 4x lane PCIe which was previously limited to 2x lane support.
> 
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>   drivers/pci/controller/cadence/pci-j721e.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..62c2c70256b8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,7 @@ enum link_status {
>   };
>   
>   #define J721E_MODE_RC			BIT(7)
> -#define LANE_COUNT_MASK			BIT(8)
> +#define LANE_COUNT_MASK			GENMASK(9, 8)

The MASK value as well has to be specific to platforms. For J721E, it is 
1 bit only.

Thanks,
Kishon

>   #define LANE_COUNT(n)			((n) << 8)
>   
>   #define GENERATION_SEL_MASK		GENMASK(1, 0)
> 

WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Matt Ranostay <mranostay@ti.com>, <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <tjoseph@cadence.com>, <vigneshr@ti.com>
Subject: Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
Date: Fri, 23 Sep 2022 14:50:19 +0530	[thread overview]
Message-ID: <ce9bf8e3-bfb7-5f38-39ac-3a80da2c3839@ti.com> (raw)
In-Reply-To: <20220909201607.3835-2-mranostay@ti.com>

Hi Matt,

On 10/09/22 1:46 am, Matt Ranostay wrote:
> Increase LANE_COUNT_MASK to two-bit field that allows selection of
> 4x lane PCIe which was previously limited to 2x lane support.
> 
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>   drivers/pci/controller/cadence/pci-j721e.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..62c2c70256b8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,7 @@ enum link_status {
>   };
>   
>   #define J721E_MODE_RC			BIT(7)
> -#define LANE_COUNT_MASK			BIT(8)
> +#define LANE_COUNT_MASK			GENMASK(9, 8)

The MASK value as well has to be specific to platforms. For J721E, it is 
1 bit only.

Thanks,
Kishon

>   #define LANE_COUNT(n)			((n) << 8)
>   
>   #define GENERATION_SEL_MASK		GENMASK(1, 0)
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-09-23  9:20 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-09 20:16 [PATCH 0/3] PCI: add 4x lane support for pci-j721e controllers Matt Ranostay
2022-09-09 20:16 ` Matt Ranostay
2022-09-09 20:16 ` [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-09-09 20:16   ` Matt Ranostay
2022-09-23  9:20   ` Kishon Vijay Abraham I [this message]
2022-09-23  9:20     ` Kishon Vijay Abraham I
2022-09-24 23:21     ` Matt Ranostay
2022-09-24 23:21       ` Matt Ranostay
2022-09-09 20:16 ` [PATCH 2/3] PCI: j721e: Add per platform maximum lane settings Matt Ranostay
2022-09-09 20:16   ` Matt Ranostay
2022-09-09 20:16 ` [PATCH 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration Matt Ranostay
2022-09-09 20:16   ` Matt Ranostay

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ce9bf8e3-bfb7-5f38-39ac-3a80da2c3839@ti.com \
    --to=kishon@ti.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mranostay@ti.com \
    --cc=tjoseph@cadence.com \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.