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From: Matt Ranostay <mranostay@ti.com>
To: <linux-pci@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <tjoseph@cadence.com>, <vigneshr@ti.com>, <kishon@ti.com>,
	Matt Ranostay <mranostay@ti.com>
Subject: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
Date: Fri, 9 Sep 2022 13:16:05 -0700	[thread overview]
Message-ID: <20220909201607.3835-2-mranostay@ti.com> (raw)
In-Reply-To: <20220909201607.3835-1-mranostay@ti.com>

Increase LANE_COUNT_MASK to two-bit field that allows selection of
4x lane PCIe which was previously limited to 2x lane support.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..62c2c70256b8 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,7 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
+#define LANE_COUNT_MASK			GENMASK(9, 8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
-- 
2.37.2


WARNING: multiple messages have this Message-ID (diff)
From: Matt Ranostay <mranostay@ti.com>
To: <linux-pci@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <tjoseph@cadence.com>, <vigneshr@ti.com>, <kishon@ti.com>,
	Matt Ranostay <mranostay@ti.com>
Subject: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
Date: Fri, 9 Sep 2022 13:16:05 -0700	[thread overview]
Message-ID: <20220909201607.3835-2-mranostay@ti.com> (raw)
In-Reply-To: <20220909201607.3835-1-mranostay@ti.com>

Increase LANE_COUNT_MASK to two-bit field that allows selection of
4x lane PCIe which was previously limited to 2x lane support.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..62c2c70256b8 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,7 @@ enum link_status {
 };
 
 #define J721E_MODE_RC			BIT(7)
-#define LANE_COUNT_MASK			BIT(8)
+#define LANE_COUNT_MASK			GENMASK(9, 8)
 #define LANE_COUNT(n)			((n) << 8)
 
 #define GENERATION_SEL_MASK		GENMASK(1, 0)
-- 
2.37.2


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  reply	other threads:[~2022-09-09 20:16 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-09 20:16 [PATCH 0/3] PCI: add 4x lane support for pci-j721e controllers Matt Ranostay
2022-09-09 20:16 ` Matt Ranostay
2022-09-09 20:16 ` Matt Ranostay [this message]
2022-09-09 20:16   ` [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-09-23  9:20   ` Kishon Vijay Abraham I
2022-09-23  9:20     ` Kishon Vijay Abraham I
2022-09-24 23:21     ` Matt Ranostay
2022-09-24 23:21       ` Matt Ranostay
2022-09-09 20:16 ` [PATCH 2/3] PCI: j721e: Add per platform maximum lane settings Matt Ranostay
2022-09-09 20:16   ` Matt Ranostay
2022-09-09 20:16 ` [PATCH 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration Matt Ranostay
2022-09-09 20:16   ` Matt Ranostay

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