* [PATCH 0/3] PCI: add 4x lane support for pci-j721e controllers
@ 2022-09-09 20:16 ` Matt Ranostay
0 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Matt Ranostay (3):
PCI: j721e: Add PCIe 4x lane selection support
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add warnings on num-lanes misconfiguration
drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
--
2.37.2
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
2022-09-09 20:16 ` Matt Ranostay
@ 2022-09-09 20:16 ` Matt Ranostay
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Increase LANE_COUNT_MASK to two-bit field that allows selection of
4x lane PCIe which was previously limited to 2x lane support.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..62c2c70256b8 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,7 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
-#define LANE_COUNT_MASK BIT(8)
+#define LANE_COUNT_MASK GENMASK(9, 8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
@ 2022-09-09 20:16 ` Matt Ranostay
0 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Increase LANE_COUNT_MASK to two-bit field that allows selection of
4x lane PCIe which was previously limited to 2x lane support.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..62c2c70256b8 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -43,7 +43,7 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
-#define LANE_COUNT_MASK BIT(8)
+#define LANE_COUNT_MASK GENMASK(9, 8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
--
2.37.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
2022-09-09 20:16 ` Matt Ranostay
@ 2022-09-23 9:20 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 12+ messages in thread
From: Kishon Vijay Abraham I @ 2022-09-23 9:20 UTC (permalink / raw)
To: Matt Ranostay, linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr
Hi Matt,
On 10/09/22 1:46 am, Matt Ranostay wrote:
> Increase LANE_COUNT_MASK to two-bit field that allows selection of
> 4x lane PCIe which was previously limited to 2x lane support.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..62c2c70256b8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,7 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> +#define LANE_COUNT_MASK GENMASK(9, 8)
The MASK value as well has to be specific to platforms. For J721E, it is
1 bit only.
Thanks,
Kishon
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
@ 2022-09-23 9:20 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 12+ messages in thread
From: Kishon Vijay Abraham I @ 2022-09-23 9:20 UTC (permalink / raw)
To: Matt Ranostay, linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr
Hi Matt,
On 10/09/22 1:46 am, Matt Ranostay wrote:
> Increase LANE_COUNT_MASK to two-bit field that allows selection of
> 4x lane PCIe which was previously limited to 2x lane support.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index a82f845cc4b5..62c2c70256b8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -43,7 +43,7 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> +#define LANE_COUNT_MASK GENMASK(9, 8)
The MASK value as well has to be specific to platforms. For J721E, it is
1 bit only.
Thanks,
Kishon
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
2022-09-23 9:20 ` Kishon Vijay Abraham I
@ 2022-09-24 23:21 ` Matt Ranostay
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-24 23:21 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: linux-pci, linux-arm-kernel, tjoseph, vigneshr
On Fri, Sep 23, 2022 at 02:50:19PM +0530, Kishon Vijay Abraham I wrote:
> Hi Matt,
>
> On 10/09/22 1:46 am, Matt Ranostay wrote:
> > Increase LANE_COUNT_MASK to two-bit field that allows selection of
> > 4x lane PCIe which was previously limited to 2x lane support.
> >
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > ---
> > drivers/pci/controller/cadence/pci-j721e.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index a82f845cc4b5..62c2c70256b8 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -43,7 +43,7 @@ enum link_status {
> > };
> > #define J721E_MODE_RC BIT(7)
> > -#define LANE_COUNT_MASK BIT(8)
> > +#define LANE_COUNT_MASK GENMASK(9, 8)
>
> The MASK value as well has to be specific to platforms. For J721E, it is 1
> bit only.
>
Noted. Will revise in next version of the patchset.
- Matt
> Thanks,
> Kishon
>
> > #define LANE_COUNT(n) ((n) << 8)
> > #define GENERATION_SEL_MASK GENMASK(1, 0)
> >
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support
@ 2022-09-24 23:21 ` Matt Ranostay
0 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-24 23:21 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: linux-pci, linux-arm-kernel, tjoseph, vigneshr
On Fri, Sep 23, 2022 at 02:50:19PM +0530, Kishon Vijay Abraham I wrote:
> Hi Matt,
>
> On 10/09/22 1:46 am, Matt Ranostay wrote:
> > Increase LANE_COUNT_MASK to two-bit field that allows selection of
> > 4x lane PCIe which was previously limited to 2x lane support.
> >
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > ---
> > drivers/pci/controller/cadence/pci-j721e.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index a82f845cc4b5..62c2c70256b8 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -43,7 +43,7 @@ enum link_status {
> > };
> > #define J721E_MODE_RC BIT(7)
> > -#define LANE_COUNT_MASK BIT(8)
> > +#define LANE_COUNT_MASK GENMASK(9, 8)
>
> The MASK value as well has to be specific to platforms. For J721E, it is 1
> bit only.
>
Noted. Will revise in next version of the patchset.
- Matt
> Thanks,
> Kishon
>
> > #define LANE_COUNT(n) ((n) << 8)
> > #define GENERATION_SEL_MASK GENMASK(1, 0)
> >
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] PCI: j721e: Add per platform maximum lane settings
2022-09-09 20:16 ` Matt Ranostay
@ 2022-09-09 20:16 ` Matt Ranostay
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Various platforms have different maximum amount of lanes that
can be selected. Add max_lanes to struct j721e_pcie to allow
for error checking on num-lanes selection from device tree.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 62c2c70256b8..4c6c677fab54 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -48,8 +48,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -72,6 +70,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes)
num_lanes = 1;
pcie->num_lanes = num_lanes;
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/3] PCI: j721e: Add per platform maximum lane settings
@ 2022-09-09 20:16 ` Matt Ranostay
0 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Various platforms have different maximum amount of lanes that
can be selected. Add max_lanes to struct j721e_pcie to allow
for error checking on num-lanes selection from device tree.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 62c2c70256b8..4c6c677fab54 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -48,8 +48,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -72,6 +70,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 4,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes)
num_lanes = 1;
pcie->num_lanes = num_lanes;
--
2.37.2
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration
2022-09-09 20:16 ` Matt Ranostay
@ 2022-09-09 20:16 ` Matt Ranostay
-1 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Added dev_warn messages to alert of devicetree misconfigurations
for incorrect num-lanes setting, or the lack of one being defined.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 4c6c677fab54..4f0464371e80 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -438,8 +438,17 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > data->max_lanes)
+ if (ret) {
+ dev_warn(dev, "no num-lanes defined, defaulting to 1\n");
num_lanes = 1;
+ }
+
+ if (num_lanes > data->max_lanes) {
+ dev_warn(dev, "defined num-lanes %d is greater than the "
+ "allowed maximum of %d, defaulting to 1\n",
+ num_lanes, data->max_lanes);
+ num_lanes = 1;
+ }
pcie->num_lanes = num_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
--
2.37.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration
@ 2022-09-09 20:16 ` Matt Ranostay
0 siblings, 0 replies; 12+ messages in thread
From: Matt Ranostay @ 2022-09-09 20:16 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel; +Cc: tjoseph, vigneshr, kishon, Matt Ranostay
Added dev_warn messages to alert of devicetree misconfigurations
for incorrect num-lanes setting, or the lack of one being defined.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 4c6c677fab54..4f0464371e80 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -438,8 +438,17 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > data->max_lanes)
+ if (ret) {
+ dev_warn(dev, "no num-lanes defined, defaulting to 1\n");
num_lanes = 1;
+ }
+
+ if (num_lanes > data->max_lanes) {
+ dev_warn(dev, "defined num-lanes %d is greater than the "
+ "allowed maximum of %d, defaulting to 1\n",
+ num_lanes, data->max_lanes);
+ num_lanes = 1;
+ }
pcie->num_lanes = num_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
--
2.37.2
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^ permalink raw reply related [flat|nested] 12+ messages in thread