* [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
@ 2010-03-19 17:40 ` Richard Henderson
2010-03-26 21:30 ` Aurelien Jarno
2010-03-19 18:12 ` [Qemu-devel] [PATCH 2/9] tcg: Name the opcode enumeration Richard Henderson
` (8 subsequent siblings)
9 siblings, 1 reply; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 17:40 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
This opcode is unused. It was incorrectly implemented
on at least one host. Just remove it.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/README | 7 +------
tcg/arm/tcg-target.c | 7 -------
tcg/hppa/tcg-target.c | 5 -----
tcg/i386/tcg-target.c | 9 ---------
tcg/mips/tcg-target.c | 5 -----
tcg/ppc/tcg-target.c | 10 ----------
tcg/ppc64/tcg-target.c | 10 ----------
tcg/sparc/tcg-target.c | 2 --
tcg/tcg-opc.h | 1 -
tcg/x86_64/tcg-target.c | 8 --------
10 files changed, 1 insertions(+), 63 deletions(-)
diff --git a/tcg/README b/tcg/README
index 281c114..53737fb 100644
--- a/tcg/README
+++ b/tcg/README
@@ -88,8 +88,7 @@ supported.
* Branches:
-Use the instruction 'br' to jump to a label. Use 'jmp' to jump to an
-explicit address. Conditional branches can only jump to labels.
+Use the instruction 'br' to jump to a label.
3.3) Code Optimizations
@@ -129,10 +128,6 @@ call function 'ptr' (pointer type)
********* Jumps/Labels
-* jmp t0
-
-Absolute jump to address t0 (pointer type).
-
* set_label $label
Define label 'label' at the current program point.
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 35e14c1..167728a 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1312,12 +1312,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
else
tcg_out_callr(s, COND_AL, args[0]);
break;
- case INDEX_op_jmp:
- if (const_args[0])
- tcg_out_goto(s, COND_AL, args[0]);
- else
- tcg_out_bx(s, COND_AL, args[0]);
- break;
case INDEX_op_br:
tcg_out_goto_label(s, COND_AL, args[0]);
break;
@@ -1540,7 +1534,6 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
- { INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 4677971..98f04fe 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -753,10 +753,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out32(s, BLE_SR4 | INSN_R2(args[0]));
tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
break;
- case INDEX_op_jmp:
- fprintf(stderr, "unimplemented jmp\n");
- tcg_abort();
- break;
case INDEX_op_br:
fprintf(stderr, "unimplemented br\n");
tcg_abort();
@@ -892,7 +888,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "r" } },
- { INDEX_op_jmp, { "r" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 09c73b4..c7af11c 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1001,14 +1001,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
tcg_out_modrm(s, 0xff, 2, args[0]);
}
break;
- case INDEX_op_jmp:
- if (const_args[0]) {
- tcg_out8(s, 0xe9);
- tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
- } else {
- tcg_out_modrm(s, 0xff, 4, args[0]);
- }
- break;
case INDEX_op_br:
tcg_out_jxx(s, JCC_JMP, args[0], 0);
break;
@@ -1226,7 +1218,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
- { INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
{ INDEX_op_movi_i32, { "r" } },
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index ec687ad..cb3adf3 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1115,10 +1115,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, args[0], 0);
tcg_out_nop(s);
break;
- case INDEX_op_jmp:
- tcg_out_opc_reg(s, OPC_JR, 0, args[0], 0);
- tcg_out_nop(s);
- break;
case INDEX_op_br:
tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, args[0]);
break;
@@ -1326,7 +1322,6 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "C" } },
- { INDEX_op_jmp, { "r" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 81633ed..4098a4f 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1331,15 +1331,6 @@ static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
case INDEX_op_call:
tcg_out_call (s, args[0], const_args[0]);
break;
- case INDEX_op_jmp:
- if (const_args[0]) {
- tcg_out_b (s, 0, args[0]);
- }
- else {
- tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
- tcg_out32 (s, BCCTR | BO_ALWAYS);
- }
- break;
case INDEX_op_movi_i32:
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
break;
@@ -1721,7 +1712,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
- { INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index cf36c55..4087d17 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1242,15 +1242,6 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
case INDEX_op_call:
tcg_out_call (s, args[0], const_args[0]);
break;
- case INDEX_op_jmp:
- if (const_args[0]) {
- tcg_out_b (s, 0, args[0]);
- }
- else {
- tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
- tcg_out32 (s, BCCTR | BO_ALWAYS);
- }
- break;
case INDEX_op_movi_i32:
tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
break;
@@ -1575,7 +1566,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
- { INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 620c666..e119166 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1169,7 +1169,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
sizeof(long), HOST_LD_OP);
break;
- case INDEX_op_jmp:
case INDEX_op_br:
tcg_out_branch_i32(s, COND_A, args[0]);
tcg_out_nop(s);
@@ -1431,7 +1430,6 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
- { INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 01fea1e..2682bd7 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -37,7 +37,6 @@ DEF2(discard, 1, 0, 0, 0)
DEF2(set_label, 0, 0, 1, 0)
DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
-DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(mov_i32, 1, 1, 0, 0)
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index ea313fa..b1f2c12 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -935,13 +935,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_modrm(s, 0xff, 2, args[0]);
}
break;
- case INDEX_op_jmp:
- if (const_args[0]) {
- tcg_out_goto(s, 0, (void *) args[0]);
- } else {
- tcg_out_modrm(s, 0xff, 4, args[0]);
- }
- break;
case INDEX_op_br:
tcg_out_jxx(s, JCC_JMP, args[0]);
break;
@@ -1320,7 +1313,6 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
- { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
{ INDEX_op_br, { } },
{ INDEX_op_mov_i32, { "r", "r" } },
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 2/9] tcg: Name the opcode enumeration.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
2010-03-19 17:40 ` [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode Richard Henderson
@ 2010-03-19 18:12 ` Richard Henderson
2010-03-19 18:26 ` [Qemu-devel] [PATCH 3/9] tcg: Use TCGCond where appropriate Richard Henderson
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 18:12 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.c | 2 +-
tcg/hppa/tcg-target.c | 2 +-
tcg/i386/tcg-target.c | 2 +-
tcg/mips/tcg-target.c | 2 +-
tcg/ppc/tcg-target.c | 2 +-
tcg/ppc64/tcg-target.c | 2 +-
tcg/s390/tcg-target.c | 2 +-
tcg/sparc/tcg-target.c | 2 +-
tcg/tcg-op.h | 84 +++++++++++++++++++++++-----------------------
tcg/tcg.c | 33 +++++++++++++-----
tcg/tcg.h | 6 ++--
tcg/x86_64/tcg-target.c | 2 +-
12 files changed, 78 insertions(+), 63 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 167728a..6927278 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1247,7 +1247,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
static uint8_t *tb_ret_addr;
-static inline void tcg_out_op(TCGContext *s, int opc,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
int c;
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 98f04fe..2f075f2 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -723,7 +723,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
#endif
}
-static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
int c;
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index c7af11c..af6a9d0 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -968,7 +968,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
#endif
}
-static inline void tcg_out_op(TCGContext *s, int opc,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
int c;
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index cb3adf3..e700552 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1088,7 +1088,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
#endif
}
-static inline void tcg_out_op(TCGContext *s, int opc,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
switch(opc) {
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 4098a4f..f911b54 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1292,7 +1292,7 @@ void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
flush_icache_range(jmp_addr, jmp_addr + patch_size);
}
-static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
switch (opc) {
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 4087d17..ffe1ca0 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1201,7 +1201,7 @@ void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
flush_icache_range (jmp_addr, jmp_addr + patch_size);
}
-static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
+static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
int c;
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 356b1a4..265194a 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -78,7 +78,7 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
tcg_abort();
}
-static inline void tcg_out_op(TCGContext *s, int opc,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
tcg_abort();
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index e119166..c1976ad 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1119,7 +1119,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
#endif
}
-static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
int c;
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index a58b17a..a44f050 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -25,60 +25,60 @@
int gen_new_label(void);
-static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
+static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
}
-static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
+static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
}
-static inline void tcg_gen_op1i(int opc, TCGArg arg1)
+static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg1;
}
-static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
}
-static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
+static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
}
-static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
+static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
*gen_opparam_ptr++ = arg2;
}
-static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
+static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
*gen_opparam_ptr++ = arg2;
}
-static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
+static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg1;
*gen_opparam_ptr++ = arg2;
}
-static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3)
{
*gen_opc_ptr++ = opc;
@@ -87,7 +87,7 @@ static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
}
-static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3)
{
*gen_opc_ptr++ = opc;
@@ -96,8 +96,8 @@ static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
}
-static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
- TCGArg arg3)
+static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
+ TCGv_i32 arg2, TCGArg arg3)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
@@ -105,8 +105,8 @@ static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg3;
}
-static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
- TCGArg arg3)
+static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
+ TCGv_i64 arg2, TCGArg arg3)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
@@ -114,8 +114,8 @@ static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg3;
}
-static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
- TCGArg offset)
+static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
+ TCGv_ptr base, TCGArg offset)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(val);
@@ -123,8 +123,8 @@ static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
*gen_opparam_ptr++ = offset;
}
-static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
- TCGArg offset)
+static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
+ TCGv_ptr base, TCGArg offset)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(val);
@@ -132,8 +132,8 @@ static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
*gen_opparam_ptr++ = offset;
}
-static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
- TCGArg mem_index)
+static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
+ TCGv_i32 addr, TCGArg mem_index)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(val);
@@ -141,8 +141,8 @@ static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32
*gen_opparam_ptr++ = mem_index;
}
-static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
- TCGArg mem_index)
+static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
+ TCGv_i64 addr, TCGArg mem_index)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(val);
@@ -150,7 +150,7 @@ static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64
*gen_opparam_ptr++ = mem_index;
}
-static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4)
{
*gen_opc_ptr++ = opc;
@@ -160,7 +160,7 @@ static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
}
-static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGv_i64 arg4)
{
*gen_opc_ptr++ = opc;
@@ -170,7 +170,7 @@ static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
}
-static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGArg arg4)
{
*gen_opc_ptr++ = opc;
@@ -180,7 +180,7 @@ static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg4;
}
-static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGArg arg4)
{
*gen_opc_ptr++ = opc;
@@ -190,7 +190,7 @@ static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg4;
}
-static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGArg arg3, TCGArg arg4)
{
*gen_opc_ptr++ = opc;
@@ -200,7 +200,7 @@ static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg4;
}
-static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGArg arg3, TCGArg arg4)
{
*gen_opc_ptr++ = opc;
@@ -210,7 +210,7 @@ static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg4;
}
-static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
{
*gen_opc_ptr++ = opc;
@@ -221,7 +221,7 @@ static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = GET_TCGV_I32(arg5);
}
-static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
{
*gen_opc_ptr++ = opc;
@@ -232,7 +232,7 @@ static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = GET_TCGV_I64(arg5);
}
-static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
{
*gen_opc_ptr++ = opc;
@@ -243,7 +243,7 @@ static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg5;
}
-static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
{
*gen_opc_ptr++ = opc;
@@ -254,7 +254,7 @@ static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg5;
}
-static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
TCGv_i32 arg6)
{
@@ -267,7 +267,7 @@ static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = GET_TCGV_I32(arg6);
}
-static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
TCGv_i64 arg6)
{
@@ -280,7 +280,7 @@ static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = GET_TCGV_I64(arg6);
}
-static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
+static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4,
TCGv_i32 arg5, TCGArg arg6)
{
@@ -293,7 +293,7 @@ static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg6;
}
-static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
+static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
TCGv_i64 arg3, TCGv_i64 arg4,
TCGv_i64 arg5, TCGArg arg6)
{
@@ -306,9 +306,9 @@ static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg6;
}
-static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
- TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
- TCGArg arg6)
+static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
+ TCGv_i32 arg2, TCGv_i32 arg3,
+ TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
@@ -319,9 +319,9 @@ static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
*gen_opparam_ptr++ = arg6;
}
-static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
- TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
- TCGArg arg6)
+static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
+ TCGv_i64 arg2, TCGv_i64 arg3,
+ TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1818868..95e14cc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -783,7 +783,8 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
const uint16_t *opc_ptr;
const TCGArg *args;
TCGArg arg;
- int c, i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
+ TCGOpcode c;
+ int i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
const TCGOpDef *def;
char buf[128];
@@ -970,13 +971,13 @@ static void sort_constraints(TCGOpDef *def, int start, int n)
void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
{
- int op;
+ TCGOpcode op;
TCGOpDef *def;
const char *ct_str;
int i, nb_args;
for(;;) {
- if (tdefs->op < 0)
+ if (tdefs->op == (TCGOpcode)-1)
break;
op = tdefs->op;
assert(op >= 0 && op < NB_OPS);
@@ -1046,15 +1047,27 @@ void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
}
#if defined(CONFIG_DEBUG_TCG)
+ i = 0;
for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
if (op < INDEX_op_call || op == INDEX_op_debug_insn_start) {
/* Wrong entry in op definitions? */
- assert(!tcg_op_defs[op].used);
+ if (tcg_op_defs[op].used) {
+ fprintf(stderr, "Invalid op definition for %s\n",
+ tcg_op_defs[op].name);
+ i = 1;
+ }
} else {
/* Missing entry in op definitions? */
- assert(tcg_op_defs[op].used);
+ if (!tcg_op_defs[op].used) {
+ fprintf(stderr, "Missing op definition for %s\n",
+ tcg_op_defs[op].name);
+ i = 1;
+ }
}
}
+ if (i == 1) {
+ tcg_abort();
+ }
#endif
}
@@ -1106,7 +1119,8 @@ static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps)
temporaries are removed. */
static void tcg_liveness_analysis(TCGContext *s)
{
- int i, op_index, op, nb_args, nb_iargs, nb_oargs, arg, nb_ops;
+ int i, op_index, nb_args, nb_iargs, nb_oargs, arg, nb_ops;
+ TCGOpcode op;
TCGArg *args;
const TCGOpDef *def;
uint8_t *dead_temps;
@@ -1547,7 +1561,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
}
static void tcg_reg_alloc_op(TCGContext *s,
- const TCGOpDef *def, int opc,
+ const TCGOpDef *def, TCGOpcode opc,
const TCGArg *args,
unsigned int dead_iargs)
{
@@ -1714,7 +1728,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
#endif
static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
- int opc, const TCGArg *args,
+ TCGOpcode opc, const TCGArg *args,
unsigned int dead_iargs)
{
int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params;
@@ -1911,7 +1925,8 @@ static void dump_op_count(void)
static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
long search_pc)
{
- int opc, op_index;
+ TCGOpcode opc;
+ int op_index;
const TCGOpDef *def;
unsigned int dead_iargs;
const TCGArg *args;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cf3a508..dd02a47 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -47,12 +47,12 @@ typedef uint64_t TCGRegSet;
#error unsupported
#endif
-enum {
+typedef enum TCGOpcode {
#define DEF(s, n, copy_size) INDEX_op_ ## s,
#include "tcg-opc.h"
#undef DEF
NB_OPS,
-};
+} TCGOpcode;
#define tcg_regset_clear(d) (d) = 0
#define tcg_regset_set(d, s) (d) = (s)
@@ -418,7 +418,7 @@ typedef struct TCGOpDef {
} TCGOpDef;
typedef struct TCGTargetOpDef {
- int op;
+ TCGOpcode op;
const char *args_ct_str[TCG_MAX_OP_ARGS];
} TCGTargetOpDef;
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index b1f2c12..cb7d651 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -903,7 +903,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
#endif
}
-static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args)
{
int c;
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 3/9] tcg: Use TCGCond where appropriate.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
2010-03-19 17:40 ` [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode Richard Henderson
2010-03-19 18:12 ` [Qemu-devel] [PATCH 2/9] tcg: Name the opcode enumeration Richard Henderson
@ 2010-03-19 18:26 ` Richard Henderson
2010-03-19 18:36 ` [Qemu-devel] [PATCH 4/9] tcg: Change TCGType to an enumeration Richard Henderson
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/i386/tcg-target.c | 4 ++--
tcg/mips/tcg-target.c | 8 ++++----
tcg/ppc/tcg-target.c | 7 ++++---
tcg/ppc64/tcg-target.c | 7 ++++---
tcg/sparc/tcg-target.c | 12 ++++++------
tcg/tcg-op.h | 34 +++++++++++++++++-----------------
tcg/x86_64/tcg-target.c | 4 ++--
7 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index af6a9d0..036f6ed 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -376,7 +376,7 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
}
}
-static void tcg_out_brcond(TCGContext *s, int cond,
+static void tcg_out_brcond(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index, int small)
{
@@ -466,7 +466,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
}
-static void tcg_out_setcond(TCGContext *s, int cond, TCGArg dest,
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
TCGArg arg1, TCGArg arg2, int const_arg2)
{
tcg_out_cmp(s, arg1, arg2, const_arg2);
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index e700552..f71a648 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -464,7 +464,7 @@ static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
}
}
-static void tcg_out_brcond(TCGContext *s, int cond, int arg1,
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, int arg1,
int arg2, int label_index)
{
TCGLabel *l = &s->labels[label_index];
@@ -522,7 +522,7 @@ static void tcg_out_brcond(TCGContext *s, int cond, int arg1,
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
-static void tcg_out_brcond2(TCGContext *s, int cond, int arg1,
+static void tcg_out_brcond2(TCGContext *s, TCGCond cond, int arg1,
int arg2, int arg3, int arg4, int label_index)
{
void *label_ptr;
@@ -585,7 +585,7 @@ static void tcg_out_brcond2(TCGContext *s, int cond, int arg1,
reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
}
-static void tcg_out_setcond(TCGContext *s, int cond, int ret,
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, int ret,
int arg1, int arg2)
{
switch (cond) {
@@ -645,7 +645,7 @@ static void tcg_out_setcond(TCGContext *s, int cond, int ret,
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
-static void tcg_out_setcond2(TCGContext *s, int cond, int ret,
+static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
int arg1, int arg2, int arg3, int arg4)
{
switch (cond) {
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index f911b54..8b9e7f3 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1080,7 +1080,8 @@ static void tcg_out_bc (TCGContext *s, int bc, int label_index)
static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
const int *const_args)
{
- int cond = args[4], op;
+ TCGCond cond = args[4];
+ int op;
struct { int bit1; int bit2; int cond2; } bits[] = {
[TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
[TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
@@ -1120,7 +1121,7 @@ static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
}
}
-static void tcg_out_setcond (TCGContext *s, int cond, TCGArg arg0,
+static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
TCGArg arg1, TCGArg arg2, int const_arg2)
{
int crop, sh, arg;
@@ -1244,7 +1245,7 @@ static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
);
}
-static void tcg_out_brcond (TCGContext *s, int cond,
+static void tcg_out_brcond (TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index)
{
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index ffe1ca0..cfcf869 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1051,8 +1051,9 @@ static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
}
-static void tcg_out_setcond (TCGContext *s, TCGType type, int cond, TCGArg arg0,
- TCGArg arg1, TCGArg arg2, int const_arg2)
+static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
+ TCGArg arg0, TCGArg arg1, TCGArg arg2,
+ int const_arg2)
{
int crop, sh, arg;
@@ -1182,7 +1183,7 @@ static void tcg_out_bc (TCGContext *s, int bc, int label_index)
}
}
-static void tcg_out_brcond (TCGContext *s, int cond,
+static void tcg_out_brcond (TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index, int arch64)
{
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index c1976ad..344e948 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -520,7 +520,7 @@ static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
}
-static void tcg_out_brcond_i32(TCGContext *s, int cond,
+static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index)
{
@@ -530,7 +530,7 @@ static void tcg_out_brcond_i32(TCGContext *s, int cond,
}
#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_brcond_i64(TCGContext *s, int cond,
+static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index)
{
@@ -539,7 +539,7 @@ static void tcg_out_brcond_i64(TCGContext *s, int cond,
tcg_out_nop(s);
}
#else
-static void tcg_out_brcond2_i32(TCGContext *s, int cond,
+static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
TCGArg al, TCGArg ah,
TCGArg bl, int blconst,
TCGArg bh, int bhconst, int label_dest)
@@ -587,7 +587,7 @@ static void tcg_out_brcond2_i32(TCGContext *s, int cond,
}
#endif
-static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
+static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const)
{
TCGArg t;
@@ -643,7 +643,7 @@ static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
}
#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
+static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const)
{
tcg_out_cmp(s, c1, c2, c2const);
@@ -653,7 +653,7 @@ static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
| MOVCC_XCC | INSN_IMM11(1));
}
#else
-static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
+static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg al, TCGArg ah,
TCGArg bl, int blconst,
TCGArg bh, int bhconst)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index a44f050..350a096 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -593,28 +593,28 @@ static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
}
}
-static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
- int label_index)
+static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
+ TCGv_i32 arg2, int label_index)
{
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
}
-static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
- int label_index)
+static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
+ int32_t arg2, int label_index)
{
TCGv_i32 t0 = tcg_const_i32(arg2);
tcg_gen_brcond_i32(cond, arg1, t0, label_index);
tcg_temp_free_i32(t0);
}
-static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret,
+static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
}
-static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1,
- int32_t arg2)
+static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
+ TCGv_i32 arg1, int32_t arg2)
{
TCGv_i32 t0 = tcg_const_i32(arg2);
tcg_gen_setcond_i32(cond, ret, arg1, t0);
@@ -895,15 +895,15 @@ static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
}
-static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
- int label_index)
+static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
+ TCGv_i64 arg2, int label_index)
{
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
TCGV_HIGH(arg2), cond, label_index);
}
-static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
+static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2)
{
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
@@ -1136,13 +1136,13 @@ static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
}
}
-static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
- int label_index)
+static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
+ TCGv_i64 arg2, int label_index)
{
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
}
-static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
+static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2)
{
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
@@ -1263,16 +1263,16 @@ static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
tcg_temp_free_i64(t0);
}
}
-static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
- int label_index)
+static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
+ int64_t arg2, int label_index)
{
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_brcond_i64(cond, arg1, t0, label_index);
tcg_temp_free_i64(t0);
}
-static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1,
- int64_t arg2)
+static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
+ TCGv_i64 arg1, int64_t arg2)
{
TCGv_i64 t0 = tcg_const_i64(arg2);
tcg_gen_setcond_i64(cond, ret, arg1, t0);
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index cb7d651..a664168 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -518,7 +518,7 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
}
}
-static void tcg_out_brcond(TCGContext *s, int cond,
+static void tcg_out_brcond(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index, int rexw)
{
@@ -526,7 +526,7 @@ static void tcg_out_brcond(TCGContext *s, int cond,
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
}
-static void tcg_out_setcond(TCGContext *s, int cond, TCGArg dest,
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
TCGArg arg1, TCGArg arg2, int const_arg2, int rexw)
{
tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 4/9] tcg: Change TCGType to an enumeration.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (2 preceding siblings ...)
2010-03-19 18:26 ` [Qemu-devel] [PATCH 3/9] tcg: Use TCGCond where appropriate Richard Henderson
@ 2010-03-19 18:36 ` Richard Henderson
2010-03-19 19:00 ` [Qemu-devel] [PATCH 5/9] tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs Richard Henderson
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 18:36 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
The TCGType name was already used consistently. Changing it
to an enumeration instead of a set of defines aids debugging.
---
tcg/tcg-op.h | 2 --
tcg/tcg.h | 19 ++++++++++++-------
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 350a096..e2873ff 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2175,7 +2175,6 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#endif /* TCG_TARGET_REG_BITS != 32 */
#if TARGET_LONG_BITS == 64
-#define TCG_TYPE_TL TCG_TYPE_I64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
@@ -2247,7 +2246,6 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#else
-#define TCG_TYPE_TL TCG_TYPE_I32
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
diff --git a/tcg/tcg.h b/tcg/tcg.h
index dd02a47..166c889 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -96,17 +96,22 @@ typedef struct TCGPool {
this value, they are statically allocated in the TB stack frame */
#define TCG_STATIC_CALL_ARGS_SIZE 128
-typedef int TCGType;
-
-#define TCG_TYPE_I32 0
-#define TCG_TYPE_I64 1
-#define TCG_TYPE_COUNT 2 /* number of different types */
+typedef enum TCGType {
+ TCG_TYPE_I32,
+ TCG_TYPE_I64,
+ TCG_TYPE_COUNT, /* number of different types */
#if TCG_TARGET_REG_BITS == 32
-#define TCG_TYPE_PTR TCG_TYPE_I32
+ TCG_TYPE_PTR = TCG_TYPE_I32,
+#else
+ TCG_TYPE_PTR = TCG_TYPE_I64,
+#endif
+#if TARGET_LONG_BITS == 64
+ TCG_TYPE_TL = TCG_TYPE_I64,
#else
-#define TCG_TYPE_PTR TCG_TYPE_I64
+ TCG_TYPE_TL = TCG_TYPE_I32,
#endif
+} TCGType;
typedef tcg_target_ulong TCGArg;
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 5/9] tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (3 preceding siblings ...)
2010-03-19 18:36 ` [Qemu-devel] [PATCH 4/9] tcg: Change TCGType to an enumeration Richard Henderson
@ 2010-03-19 19:00 ` Richard Henderson
2010-03-19 19:44 ` [Qemu-devel] [PATCH 6/9] tcg: Use not_i32 to implement not_i64 Richard Henderson
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with
a given extension to a 64-bit result. This distinction already
exists for the ld* loads, but not the qemu_ld* loads.
Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for
32-bit outputs. Adjust all code generators to match.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/README | 10 +++++++---
tcg/arm/tcg-target.c | 4 ++--
tcg/hppa/tcg-target.c | 6 +++---
tcg/i386/tcg-target.c | 6 +++---
tcg/mips/tcg-target.c | 6 +++---
tcg/ppc/tcg-target.c | 6 +++---
tcg/ppc64/tcg-target.c | 2 ++
tcg/sparc/tcg-target.c | 6 +++++-
tcg/tcg-op.h | 8 ++++----
tcg/tcg-opc.h | 5 +++--
tcg/x86_64/tcg-target.c | 2 ++
11 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/tcg/README b/tcg/README
index 53737fb..43f769a 100644
--- a/tcg/README
+++ b/tcg/README
@@ -373,13 +373,17 @@ instructions.
qemu_ld8s t0, t1, flags
qemu_ld16u t0, t1, flags
qemu_ld16s t0, t1, flags
+qemu_ld32 t0, t1, flags
qemu_ld32u t0, t1, flags
qemu_ld32s t0, t1, flags
qemu_ld64 t0, t1, flags
-Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU
-address type. 'flags' contains the QEMU memory index (selects user or
-kernel access) for example.
+Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU address
+type. 'flags' contains the QEMU memory index (selects user or kernel access)
+for example.
+
+Note that "qemu_ld32" implies a 32-bit result, while "qemu_ld32u" and
+"qemu_ld32s" imply a 64-bit result appropriately extended from 32 bits.
* qemu_st8 t0, t1, flags
qemu_st16 t0, t1, flags
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 6927278..f862b03 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1482,7 +1482,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
break;
- case INDEX_op_qemu_ld32u:
+ case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, COND_AL, args, 2);
break;
case INDEX_op_qemu_ld64:
@@ -1577,7 +1577,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "x", "X" } },
{ INDEX_op_qemu_ld16u, { "r", "x", "X" } },
{ INDEX_op_qemu_ld16s, { "r", "x", "X" } },
- { INDEX_op_qemu_ld32u, { "r", "x", "X" } },
+ { INDEX_op_qemu_ld32, { "r", "x", "X" } },
{ INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
{ INDEX_op_qemu_st8, { "x", "x", "X" } },
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 2f075f2..f024623 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -859,7 +859,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
- case INDEX_op_qemu_ld32u:
+ case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, args, 2);
break;
@@ -918,7 +918,7 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
{ INDEX_op_qemu_st8, { "L", "L" } },
@@ -930,7 +930,7 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
{ INDEX_op_qemu_st8, { "L", "L", "L" } },
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 036f6ed..9f917ca 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1189,7 +1189,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
- case INDEX_op_qemu_ld32u:
+ case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, args, 2);
break;
case INDEX_op_qemu_ld64:
@@ -1272,7 +1272,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
{ INDEX_op_qemu_st8, { "cb", "L" } },
@@ -1284,7 +1284,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index f71a648..5585909 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1294,7 +1294,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
- case INDEX_op_qemu_ld32u:
+ case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, args, 2);
break;
case INDEX_op_qemu_ld64:
@@ -1366,7 +1366,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "L", "lZ" } },
{ INDEX_op_qemu_ld16u, { "L", "lZ" } },
{ INDEX_op_qemu_ld16s, { "L", "lZ" } },
- { INDEX_op_qemu_ld32u, { "L", "lZ" } },
+ { INDEX_op_qemu_ld32, { "L", "lZ" } },
{ INDEX_op_qemu_ld64, { "L", "L", "lZ" } },
{ INDEX_op_qemu_st8, { "SZ", "SZ" } },
@@ -1378,7 +1378,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "L", "lZ", "lZ" } },
{ INDEX_op_qemu_ld16u, { "L", "lZ", "lZ" } },
{ INDEX_op_qemu_ld16s, { "L", "lZ", "lZ" } },
- { INDEX_op_qemu_ld32u, { "L", "lZ", "lZ" } },
+ { INDEX_op_qemu_ld32, { "L", "lZ", "lZ" } },
{ INDEX_op_qemu_ld64, { "L", "L", "lZ", "lZ" } },
{ INDEX_op_qemu_st8, { "SZ", "SZ", "SZ" } },
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 8b9e7f3..c77d96c 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1652,7 +1652,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
- case INDEX_op_qemu_ld32u:
+ case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, args, 2);
break;
case INDEX_op_qemu_ld64:
@@ -1765,7 +1765,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
{ INDEX_op_qemu_st8, { "K", "K" } },
@@ -1777,7 +1777,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
{ INDEX_op_qemu_st8, { "K", "K", "K" } },
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index cfcf869..2f11cce 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1511,6 +1511,7 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld (s, args, 1 | 4);
break;
+ case INDEX_op_qemu_ld32:
case INDEX_op_qemu_ld32u:
tcg_out_qemu_ld (s, args, 2);
break;
@@ -1638,6 +1639,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
{ INDEX_op_qemu_ld32s, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "L" } },
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 344e948..6da35c5 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1323,7 +1323,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
+ case INDEX_op_qemu_ld32:
+#if TCG_TARGET_REG_BITS == 64
case INDEX_op_qemu_ld32u:
+#endif
tcg_out_qemu_ld(s, args, 2);
break;
#if TCG_TARGET_REG_BITS == 64
@@ -1478,8 +1481,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
#if TCG_TARGET_REG_BITS == 64
+ { INDEX_op_qemu_ld32u, { "r", "L" } },
{ INDEX_op_qemu_ld32s, { "r", "L" } },
#endif
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index e2873ff..085a328 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2039,9 +2039,9 @@ static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
- tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
+ tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
#else
- tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
+ tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
TCGV_HIGH(addr), mem_index);
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
#endif
@@ -2050,9 +2050,9 @@ static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
{
#if TARGET_LONG_BITS == 32
- tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
+ tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
#else
- tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
+ tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
TCGV_HIGH(addr), mem_index);
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
#endif
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 2682bd7..d232695 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -230,9 +230,9 @@ DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#endif
#if TARGET_LONG_BITS == 32
-DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#else
-DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF2(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
#endif
#if TARGET_LONG_BITS == 32
DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
@@ -267,6 +267,7 @@ DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
+DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index a664168..fff9bd0 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -1231,6 +1231,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
+ case INDEX_op_qemu_ld32:
case INDEX_op_qemu_ld32u:
tcg_out_qemu_ld(s, args, 2);
break;
@@ -1404,6 +1405,7 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
{ INDEX_op_qemu_ld32s, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "L" } },
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 6/9] tcg: Use not_i32 to implement not_i64.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (4 preceding siblings ...)
2010-03-19 19:00 ` [Qemu-devel] [PATCH 5/9] tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs Richard Henderson
@ 2010-03-19 19:44 ` Richard Henderson
2010-03-19 20:02 ` [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV Richard Henderson
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 19:44 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg-op.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 085a328..dc81f3e 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1653,6 +1653,9 @@ static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
{
#ifdef TCG_TARGET_HAS_not_i64
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
+#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
+ tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
#else
tcg_gen_xori_i64(ret, arg, -1);
#endif
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (5 preceding siblings ...)
2010-03-19 19:44 ` [Qemu-devel] [PATCH 6/9] tcg: Use not_i32 to implement not_i64 Richard Henderson
@ 2010-03-19 20:02 ` Richard Henderson
2010-03-19 20:03 ` [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND Richard Henderson
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 20:02 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/README | 2 +-
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 1 +
tcg/mips/tcg-target.h | 1 +
tcg/ppc/tcg-target.h | 1 +
tcg/ppc64/tcg-target.h | 2 ++
tcg/s390/tcg-target.h | 2 ++
tcg/sparc/tcg-target.h | 2 ++
tcg/tcg-op.h | 11 +++++++++++
tcg/tcg-opc.h | 6 ++++++
tcg/x86_64/tcg-target.h | 2 ++
11 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/tcg/README b/tcg/README
index 43f769a..c0e998c 100644
--- a/tcg/README
+++ b/tcg/README
@@ -208,7 +208,7 @@ t0=t1&~t2
* eqv_i32/i64 t0, t1, t2
-t0=~(t1^t2)
+t0=~(t1^t2), or equivalently, t0=t1^~t2
* nand_i32/i64 t0, t1, t2
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 4cad967..57a9189 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -67,6 +67,7 @@ enum {
// #define TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index e994fd5..1356ce9 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -57,6 +57,7 @@ enum {
#define TCG_TARGET_HAS_not_i32
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 377b0c8..97256a5 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -87,6 +87,7 @@ enum {
#undef TCG_TARGET_HAS_bswap16_i32
#undef TCG_TARGET_HAS_andc_i32
#undef TCG_TARGET_HAS_orc_i32
+#undef TCG_TARGET_HAS_eqv_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0c71a11..d2c6fd2 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -89,6 +89,7 @@ enum {
#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
+/* #define TCG_TARGET_HAS_eqv_i32 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index f5de642..51280af 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -80,6 +80,7 @@ enum {
#define TCG_TARGET_HAS_neg_i32
/* #define TCG_TARGET_HAS_andc_i32 */
/* #define TCG_TARGET_HAS_orc_i32 */
+/* #define TCG_TARGET_HAS_eqv_i32 */
#define TCG_TARGET_HAS_div_i64
/* #define TCG_TARGET_HAS_rot_i64 */
@@ -96,6 +97,7 @@ enum {
#define TCG_TARGET_HAS_neg_i64
/* #define TCG_TARGET_HAS_andc_i64 */
/* #define TCG_TARGET_HAS_orc_i64 */
+/* #define TCG_TARGET_HAS_eqv_i64 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index e803401..bf8e80b 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -59,6 +59,7 @@ enum {
// #define TCG_TARGET_HAS_neg_i32
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_div_i64
// #define TCG_TARGET_HAS_rot_i64
@@ -75,6 +76,7 @@ enum {
// #define TCG_TARGET_HAS_neg_i64
// #define TCG_TARGET_HAS_andc_i64
// #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index dbc574d..175abc5 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -100,6 +100,7 @@ enum {
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64
@@ -117,6 +118,7 @@ enum {
#define TCG_TARGET_HAS_not_i64
#define TCG_TARGET_HAS_andc_i64
#define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i64
#endif
/* Note: must be synced with dyngen-exec.h and Makefile.target */
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index dc81f3e..63bf614 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1740,14 +1740,25 @@ static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
+#ifdef TCG_TARGET_HAS_eqv_i32
+ tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
+#else
tcg_gen_xor_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret);
+#endif
}
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
+#ifdef TCG_TARGET_HAS_eqv_i64
+ tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+ tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
tcg_gen_xor_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret);
+#endif
}
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d232695..a723b3c 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -114,6 +114,9 @@ DEF2(andc_i32, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_orc_i32
DEF2(orc_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_eqv_i32
+DEF2(eqv_i32, 1, 2, 0, 0)
+#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@@ -196,6 +199,9 @@ DEF2(andc_i64, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_orc_i64
DEF2(orc_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_eqv_i64
+DEF2(eqv_i64, 1, 2, 0, 0)
+#endif
#endif
/* QEMU specific */
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index d1e8b9e..2951fcd 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -84,6 +84,8 @@ enum {
// #define TCG_TARGET_HAS_andc_i64
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_eqv_i64
#define TCG_TARGET_HAS_GUEST_BASE
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (6 preceding siblings ...)
2010-03-19 20:02 ` [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV Richard Henderson
@ 2010-03-19 20:03 ` Richard Henderson
2010-03-19 20:08 ` [Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR Richard Henderson
2010-03-26 22:11 ` [Qemu-devel] [PATCH 0/9] tcg cleanups Aurelien Jarno
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 20:03 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 1 +
tcg/mips/tcg-target.h | 1 +
tcg/ppc/tcg-target.h | 1 +
tcg/ppc64/tcg-target.h | 2 ++
tcg/s390/tcg-target.h | 2 ++
tcg/sparc/tcg-target.h | 2 ++
tcg/tcg-op.h | 11 +++++++++++
tcg/tcg-opc.h | 6 ++++++
tcg/x86_64/tcg-target.h | 2 ++
10 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 57a9189..0e8e1cc 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -68,6 +68,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 1356ce9..8e7ed11 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -58,6 +58,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 97256a5..179151c 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -88,6 +88,7 @@ enum {
#undef TCG_TARGET_HAS_andc_i32
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
+#undef TCG_TARGET_HAS_nand_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index d2c6fd2..1087c00 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -90,6 +90,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
/* #define TCG_TARGET_HAS_eqv_i32 */
+/* #define TCG_TARGET_HAS_nand_i32 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 51280af..acd1f57 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -81,6 +81,7 @@ enum {
/* #define TCG_TARGET_HAS_andc_i32 */
/* #define TCG_TARGET_HAS_orc_i32 */
/* #define TCG_TARGET_HAS_eqv_i32 */
+/* #define TCG_TARGET_HAS_nand_i32 */
#define TCG_TARGET_HAS_div_i64
/* #define TCG_TARGET_HAS_rot_i64 */
@@ -98,6 +99,7 @@ enum {
/* #define TCG_TARGET_HAS_andc_i64 */
/* #define TCG_TARGET_HAS_orc_i64 */
/* #define TCG_TARGET_HAS_eqv_i64 */
+/* #define TCG_TARGET_HAS_nand_i64 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index bf8e80b..b0d2866 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -60,6 +60,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_div_i64
// #define TCG_TARGET_HAS_rot_i64
@@ -77,6 +78,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i64
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
+// #define TCG_TARGET_HAS_nand_i64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 175abc5..b0b6c94 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -101,6 +101,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_nand_i32
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64
@@ -119,6 +120,7 @@ enum {
#define TCG_TARGET_HAS_andc_i64
#define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
+// #define TCG_TARGET_HAS_nand_i64
#endif
/* Note: must be synced with dyngen-exec.h and Makefile.target */
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 63bf614..7bd498d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1763,14 +1763,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
+#ifdef TCG_TARGET_HAS_nand_i32
+ tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
+#else
tcg_gen_and_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret);
+#endif
}
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
+#ifdef TCG_TARGET_HAS_nand_i64
+ tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+ tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
tcg_gen_and_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret);
+#endif
}
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index a723b3c..37ff0eb 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -117,6 +117,9 @@ DEF2(orc_i32, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_eqv_i32
DEF2(eqv_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nand_i32
+DEF2(nand_i32, 1, 2, 0, 0)
+#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@@ -202,6 +205,9 @@ DEF2(orc_i64, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_eqv_i64
DEF2(eqv_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nand_i64
+DEF2(nand_i64, 1, 2, 0, 0)
+#endif
#endif
/* QEMU specific */
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index 2951fcd..119b50a 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -86,6 +86,8 @@ enum {
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_eqv_i64
+// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nand_i64
#define TCG_TARGET_HAS_GUEST_BASE
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR.
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (7 preceding siblings ...)
2010-03-19 20:03 ` [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND Richard Henderson
@ 2010-03-19 20:08 ` Richard Henderson
2010-03-26 22:11 ` [Qemu-devel] [PATCH 0/9] tcg cleanups Aurelien Jarno
9 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 20:08 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 1 +
tcg/mips/tcg-target.h | 1 +
tcg/ppc/tcg-target.h | 1 +
tcg/ppc64/tcg-target.h | 2 ++
tcg/s390/tcg-target.h | 2 ++
tcg/sparc/tcg-target.h | 2 ++
tcg/tcg-op.h | 11 +++++++++++
tcg/tcg-opc.h | 6 ++++++
tcg/x86_64/tcg-target.h | 2 ++
10 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 0e8e1cc..c7bcc7f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -69,6 +69,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 8e7ed11..d4fc348 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -59,6 +59,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 179151c..b65e085 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -89,6 +89,7 @@ enum {
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
#undef TCG_TARGET_HAS_nand_i32
+#undef TCG_TARGET_HAS_nor_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 1087c00..a3c7093 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -91,6 +91,7 @@ enum {
#define TCG_TARGET_HAS_orc_i32
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
+/* #define TCG_TARGET_HAS_nor_i32 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index acd1f57..4bf676b 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -82,6 +82,7 @@ enum {
/* #define TCG_TARGET_HAS_orc_i32 */
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
+/* #define TCG_TARGET_HAS_nor_i32 */
#define TCG_TARGET_HAS_div_i64
/* #define TCG_TARGET_HAS_rot_i64 */
@@ -100,6 +101,7 @@ enum {
/* #define TCG_TARGET_HAS_orc_i64 */
/* #define TCG_TARGET_HAS_eqv_i64 */
/* #define TCG_TARGET_HAS_nand_i64 */
+/* #define TCG_TARGET_HAS_nor_i64 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index b0d2866..6fa4231 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -61,6 +61,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
// #define TCG_TARGET_HAS_div_i64
// #define TCG_TARGET_HAS_rot_i64
@@ -79,6 +80,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index b0b6c94..a4d1f36 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -102,6 +102,7 @@ enum {
#define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64
@@ -121,6 +122,7 @@ enum {
#define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i64
#endif
/* Note: must be synced with dyngen-exec.h and Makefile.target */
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 7bd498d..bafac2b 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1786,14 +1786,25 @@ static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
+#ifdef TCG_TARGET_HAS_nor_i32
+ tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
+#else
tcg_gen_or_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret);
+#endif
}
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
+#ifdef TCG_TARGET_HAS_nor_i64
+ tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+ tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
tcg_gen_or_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret);
+#endif
}
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 37ff0eb..5643d5d 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -120,6 +120,9 @@ DEF2(eqv_i32, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_nand_i32
DEF2(nand_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nor_i32
+DEF2(nor_i32, 1, 2, 0, 0)
+#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@@ -208,6 +211,9 @@ DEF2(eqv_i64, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_nand_i64
DEF2(nand_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nor_i64
+DEF2(nor_i64, 1, 2, 0, 0)
+#endif
#endif
/* QEMU specific */
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index 119b50a..223e667 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -88,6 +88,8 @@ enum {
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i32
+// #define TCG_TARGET_HAS_nor_i64
#define TCG_TARGET_HAS_GUEST_BASE
--
1.6.6.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH 0/9] tcg cleanups
@ 2010-03-19 20:10 Richard Henderson
2010-03-19 17:40 ` [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode Richard Henderson
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Richard Henderson @ 2010-03-19 20:10 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, aurelien
Three of the patches improve the debugging of TCG by using enumerations
where it makes sense. This avoids having to grovel through header files
to figure out what a given constant refers to.
Four of the patches have previously been posted by Nathan Froyd. Since
my ANDC and ORC patches were accepted on 2010-02-20, it seems silly to
not complete the job with the existing compound logical operaions
already defined in tcg-op.h.
One patch is required to make the uncommitted Alpha TCG port function.
r~
Richard Henderson (9):
tcg: Remove jmp opcode.
tcg: Name the opcode enumeration.
tcg: Use TCGCond where appropriate.
tcg: Change TCGType to an enumeration.
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
tcg: Use not_i32 to implement not_i64.
tcg: Allow target-specific implementation of EQV.
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of NOR.
tcg/README | 19 +++---
tcg/arm/tcg-target.c | 13 +---
tcg/arm/tcg-target.h | 3 +
tcg/hppa/tcg-target.c | 13 +---
tcg/i386/tcg-target.c | 21 ++----
tcg/i386/tcg-target.h | 3 +
tcg/mips/tcg-target.c | 21 ++----
tcg/mips/tcg-target.h | 3 +
tcg/ppc/tcg-target.c | 25 ++-----
tcg/ppc/tcg-target.h | 3 +
tcg/ppc64/tcg-target.c | 21 ++----
tcg/ppc64/tcg-target.h | 6 ++
tcg/s390/tcg-target.c | 2 +-
tcg/s390/tcg-target.h | 6 ++
tcg/sparc/tcg-target.c | 22 ++++---
tcg/sparc/tcg-target.h | 6 ++
tcg/tcg-op.h | 164 ++++++++++++++++++++++++++++-------------------
tcg/tcg-opc.h | 24 ++++++-
tcg/tcg.c | 33 +++++++---
tcg/tcg.h | 25 ++++---
tcg/x86_64/tcg-target.c | 16 ++---
tcg/x86_64/tcg-target.h | 6 ++
22 files changed, 258 insertions(+), 197 deletions(-)
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode.
2010-03-19 17:40 ` [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode Richard Henderson
@ 2010-03-26 21:30 ` Aurelien Jarno
0 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2010-03-26 21:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: blauwirbel, qemu-devel
On Fri, Mar 19, 2010 at 10:40:59AM -0700, Richard Henderson wrote:
> This opcode is unused. It was incorrectly implemented
> on at least one host. Just remove it.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/README | 7 +------
> tcg/arm/tcg-target.c | 7 -------
> tcg/hppa/tcg-target.c | 5 -----
> tcg/i386/tcg-target.c | 9 ---------
> tcg/mips/tcg-target.c | 5 -----
> tcg/ppc/tcg-target.c | 10 ----------
> tcg/ppc64/tcg-target.c | 10 ----------
> tcg/sparc/tcg-target.c | 2 --
> tcg/tcg-opc.h | 1 -
> tcg/x86_64/tcg-target.c | 8 --------
> 10 files changed, 1 insertions(+), 63 deletions(-)
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
> diff --git a/tcg/README b/tcg/README
> index 281c114..53737fb 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -88,8 +88,7 @@ supported.
>
> * Branches:
>
> -Use the instruction 'br' to jump to a label. Use 'jmp' to jump to an
> -explicit address. Conditional branches can only jump to labels.
> +Use the instruction 'br' to jump to a label.
>
> 3.3) Code Optimizations
>
> @@ -129,10 +128,6 @@ call function 'ptr' (pointer type)
>
> ********* Jumps/Labels
>
> -* jmp t0
> -
> -Absolute jump to address t0 (pointer type).
> -
> * set_label $label
>
> Define label 'label' at the current program point.
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 35e14c1..167728a 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -1312,12 +1312,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
> else
> tcg_out_callr(s, COND_AL, args[0]);
> break;
> - case INDEX_op_jmp:
> - if (const_args[0])
> - tcg_out_goto(s, COND_AL, args[0]);
> - else
> - tcg_out_bx(s, COND_AL, args[0]);
> - break;
> case INDEX_op_br:
> tcg_out_goto_label(s, COND_AL, args[0]);
> break;
> @@ -1540,7 +1534,6 @@ static const TCGTargetOpDef arm_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } },
> - { INDEX_op_jmp, { "ri" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
> index 4677971..98f04fe 100644
> --- a/tcg/hppa/tcg-target.c
> +++ b/tcg/hppa/tcg-target.c
> @@ -753,10 +753,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
> tcg_out32(s, BLE_SR4 | INSN_R2(args[0]));
> tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
> break;
> - case INDEX_op_jmp:
> - fprintf(stderr, "unimplemented jmp\n");
> - tcg_abort();
> - break;
> case INDEX_op_br:
> fprintf(stderr, "unimplemented br\n");
> tcg_abort();
> @@ -892,7 +888,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
> { INDEX_op_goto_tb, { } },
>
> { INDEX_op_call, { "r" } },
> - { INDEX_op_jmp, { "r" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index 09c73b4..c7af11c 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -1001,14 +1001,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
> tcg_out_modrm(s, 0xff, 2, args[0]);
> }
> break;
> - case INDEX_op_jmp:
> - if (const_args[0]) {
> - tcg_out8(s, 0xe9);
> - tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
> - } else {
> - tcg_out_modrm(s, 0xff, 4, args[0]);
> - }
> - break;
> case INDEX_op_br:
> tcg_out_jxx(s, JCC_JMP, args[0], 0);
> break;
> @@ -1226,7 +1218,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } },
> - { INDEX_op_jmp, { "ri" } },
> { INDEX_op_br, { } },
> { INDEX_op_mov_i32, { "r", "r" } },
> { INDEX_op_movi_i32, { "r" } },
> diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
> index ec687ad..cb3adf3 100644
> --- a/tcg/mips/tcg-target.c
> +++ b/tcg/mips/tcg-target.c
> @@ -1115,10 +1115,6 @@ static inline void tcg_out_op(TCGContext *s, int opc,
> tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, args[0], 0);
> tcg_out_nop(s);
> break;
> - case INDEX_op_jmp:
> - tcg_out_opc_reg(s, OPC_JR, 0, args[0], 0);
> - tcg_out_nop(s);
> - break;
> case INDEX_op_br:
> tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, args[0]);
> break;
> @@ -1326,7 +1322,6 @@ static const TCGTargetOpDef mips_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "C" } },
> - { INDEX_op_jmp, { "r" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 81633ed..4098a4f 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -1331,15 +1331,6 @@ static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
> case INDEX_op_call:
> tcg_out_call (s, args[0], const_args[0]);
> break;
> - case INDEX_op_jmp:
> - if (const_args[0]) {
> - tcg_out_b (s, 0, args[0]);
> - }
> - else {
> - tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
> - tcg_out32 (s, BCCTR | BO_ALWAYS);
> - }
> - break;
> case INDEX_op_movi_i32:
> tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
> break;
> @@ -1721,7 +1712,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } },
> - { INDEX_op_jmp, { "ri" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index cf36c55..4087d17 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1242,15 +1242,6 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
> case INDEX_op_call:
> tcg_out_call (s, args[0], const_args[0]);
> break;
> - case INDEX_op_jmp:
> - if (const_args[0]) {
> - tcg_out_b (s, 0, args[0]);
> - }
> - else {
> - tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
> - tcg_out32 (s, BCCTR | BO_ALWAYS);
> - }
> - break;
> case INDEX_op_movi_i32:
> tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
> break;
> @@ -1575,7 +1566,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } },
> - { INDEX_op_jmp, { "ri" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 620c666..e119166 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -1169,7 +1169,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
> TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
> sizeof(long), HOST_LD_OP);
> break;
> - case INDEX_op_jmp:
> case INDEX_op_br:
> tcg_out_branch_i32(s, COND_A, args[0]);
> tcg_out_nop(s);
> @@ -1431,7 +1430,6 @@ static const TCGTargetOpDef sparc_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } },
> - { INDEX_op_jmp, { "ri" } },
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 01fea1e..2682bd7 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -37,7 +37,6 @@ DEF2(discard, 1, 0, 0, 0)
>
> DEF2(set_label, 0, 0, 1, 0)
> DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
> -DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
>
> DEF2(mov_i32, 1, 1, 0, 0)
> diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
> index ea313fa..b1f2c12 100644
> --- a/tcg/x86_64/tcg-target.c
> +++ b/tcg/x86_64/tcg-target.c
> @@ -935,13 +935,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
> tcg_out_modrm(s, 0xff, 2, args[0]);
> }
> break;
> - case INDEX_op_jmp:
> - if (const_args[0]) {
> - tcg_out_goto(s, 0, (void *) args[0]);
> - } else {
> - tcg_out_modrm(s, 0xff, 4, args[0]);
> - }
> - break;
> case INDEX_op_br:
> tcg_out_jxx(s, JCC_JMP, args[0]);
> break;
> @@ -1320,7 +1313,6 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
> { INDEX_op_exit_tb, { } },
> { INDEX_op_goto_tb, { } },
> { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
> - { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
> { INDEX_op_br, { } },
>
> { INDEX_op_mov_i32, { "r", "r" } },
> --
> 1.6.6.1
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH 0/9] tcg cleanups
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
` (8 preceding siblings ...)
2010-03-19 20:08 ` [Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR Richard Henderson
@ 2010-03-26 22:11 ` Aurelien Jarno
9 siblings, 0 replies; 12+ messages in thread
From: Aurelien Jarno @ 2010-03-26 22:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: blauwirbel, qemu-devel
On Fri, Mar 19, 2010 at 01:10:56PM -0700, Richard Henderson wrote:
> Three of the patches improve the debugging of TCG by using enumerations
> where it makes sense. This avoids having to grovel through header files
> to figure out what a given constant refers to.
>
> Four of the patches have previously been posted by Nathan Froyd. Since
> my ANDC and ORC patches were accepted on 2010-02-20, it seems silly to
> not complete the job with the existing compound logical operaions
> already defined in tcg-op.h.
>
> One patch is required to make the uncommitted Alpha TCG port function.
I have applied patches 2-9. The patch 1 probably needs more ack first,
at it removes a "feature".
> r~
>
>
> Richard Henderson (9):
> tcg: Remove jmp opcode.
> tcg: Name the opcode enumeration.
> tcg: Use TCGCond where appropriate.
> tcg: Change TCGType to an enumeration.
> tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
> tcg: Use not_i32 to implement not_i64.
> tcg: Allow target-specific implementation of EQV.
> tcg: Allow target-specific implementation of NAND.
> tcg: Allow target-specific implementation of NOR.
>
> tcg/README | 19 +++---
> tcg/arm/tcg-target.c | 13 +---
> tcg/arm/tcg-target.h | 3 +
> tcg/hppa/tcg-target.c | 13 +---
> tcg/i386/tcg-target.c | 21 ++----
> tcg/i386/tcg-target.h | 3 +
> tcg/mips/tcg-target.c | 21 ++----
> tcg/mips/tcg-target.h | 3 +
> tcg/ppc/tcg-target.c | 25 ++-----
> tcg/ppc/tcg-target.h | 3 +
> tcg/ppc64/tcg-target.c | 21 ++----
> tcg/ppc64/tcg-target.h | 6 ++
> tcg/s390/tcg-target.c | 2 +-
> tcg/s390/tcg-target.h | 6 ++
> tcg/sparc/tcg-target.c | 22 ++++---
> tcg/sparc/tcg-target.h | 6 ++
> tcg/tcg-op.h | 164 ++++++++++++++++++++++++++++-------------------
> tcg/tcg-opc.h | 24 ++++++-
> tcg/tcg.c | 33 +++++++---
> tcg/tcg.h | 25 ++++---
> tcg/x86_64/tcg-target.c | 16 ++---
> tcg/x86_64/tcg-target.h | 6 ++
> 22 files changed, 258 insertions(+), 197 deletions(-)
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2010-03-26 22:11 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-03-19 20:10 [Qemu-devel] [PATCH 0/9] tcg cleanups Richard Henderson
2010-03-19 17:40 ` [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode Richard Henderson
2010-03-26 21:30 ` Aurelien Jarno
2010-03-19 18:12 ` [Qemu-devel] [PATCH 2/9] tcg: Name the opcode enumeration Richard Henderson
2010-03-19 18:26 ` [Qemu-devel] [PATCH 3/9] tcg: Use TCGCond where appropriate Richard Henderson
2010-03-19 18:36 ` [Qemu-devel] [PATCH 4/9] tcg: Change TCGType to an enumeration Richard Henderson
2010-03-19 19:00 ` [Qemu-devel] [PATCH 5/9] tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs Richard Henderson
2010-03-19 19:44 ` [Qemu-devel] [PATCH 6/9] tcg: Use not_i32 to implement not_i64 Richard Henderson
2010-03-19 20:02 ` [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV Richard Henderson
2010-03-19 20:03 ` [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND Richard Henderson
2010-03-19 20:08 ` [Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR Richard Henderson
2010-03-26 22:11 ` [Qemu-devel] [PATCH 0/9] tcg cleanups Aurelien Jarno
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