From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
To: <nicolas.ferre@atmel.com>, <broonie@kernel.org>,
<linux-spi@vger.kernel.org>, <dwmw2@infradead.org>,
<computersforpeace@gmail.com>, <zajec5@gmail.com>,
<beanhuo@micron.com>, <juhosg@openwrt.org>, <marex@denx.de>,
<shijie.huang@intel.com>, <ben@decadent.org.uk>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux-mtd@lists.infradead.org>,
Cyrille Pitchen <cyrille.pitchen@atmel.com>
Subject: [PATCH 0/7] add driver for Atmel QSPI controller
Date: Thu, 16 Jul 2015 17:27:47 +0200 [thread overview]
Message-ID: <cover.1437059658.git.cyrille.pitchen@atmel.com> (raw)
Hi all,
in order to be able to use Micron Quad SPI memories with the new Atmel QSPI
controller I added a new set_protocol() callback into struct spi_nor.
Indeed, once the quad I/O mode has been enabled on a Micron QSPI flash by
clearing bit 7 in its Enhanced Volatile Configuration Register, this memory
expects all the following commands to use the QSPI 4-4-4 protocol. So the
QSPI controller needs to be notified about this protocol change before
reading the Status register, 0x05 command sent by the
spi_nor_wail_till_ready() function, in micron_quad_enable().
Reading spi-nor.h, I saw an interesting struct spi_nor_xfer_cfg and its
associated callbacks write_xfer() and read_xfer(). However these callbacks
don't seem to be used at all for now. They look to have been designed to
add QSPI support to the generic spi-nor framework. So before extending the
framework with my own callback, I'd like to know whether I should have
tried to used the read_xfer()/write_xfer() callbacks to join an already
existing effort to add QSPI support.
If so, I think either the read/write_reg() prototypes should be updated or
new callbacks should be added for register reads/writes. As explained
above, even for reading the Status register the QSPI 4-4-4 protocol must be
used with Micron memories in quad I/O mode. So the framework has to find a
way to tell the QSPI controller which protocol it should use.
So I'm interested in your comments! :)
Best Regards,
Cyrille
ChangeLog
v1:
This series of patches add support for the new Atmel QSPI controller
embedded inside sama5d2x SoCs.
These patches were first developped for linux-3.18-at91 and tested on a
sama5d27 Xplained ultra board, which embeds a Micron n25q128a13 QSPI NOR
flash memory. Then the series was adapted for mainline.
Cyrille Pitchen (7):
Documentation: mtd: add a DT property to set the number of dummy
cycles
mtd: spi-nor: notify (Q)SPI controller about protocol change
mtd: spi-nor: allow to tune the number of dummy cycles
Documentation: mtd: add a DT property to set the latency code of
Spansion memory
mtd: spi-nor: allow the set the latency code on Spansion memories
Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
mtd: atmel-quadspi: add driver for Atmel QSPI controller
.../devicetree/bindings/mtd/atmel-quadspi.txt | 29 +
.../devicetree/bindings/mtd/jedec,spi-nor.txt | 6 +
.../devicetree/bindings/mtd/spansion-nor.txt | 22 +
drivers/mtd/spi-nor/Kconfig | 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/atmel-quadspi.c | 901 +++++++++++++++++++++
drivers/mtd/spi-nor/spi-nor.c | 160 +++-
include/linux/mtd/spi-nor.h | 15 +
8 files changed, 1122 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt
create mode 100644 drivers/mtd/spi-nor/atmel-quadspi.c
--
1.8.2.2
WARNING: multiple messages have this Message-ID (diff)
From: Cyrille Pitchen <cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
To: <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>,
<broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
<linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
<zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
<beanhuo-AL4WhLSQfzjQT0dZR+AlfA@public.gmane.org>,
<juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>,
<marex-ynQEQJNshbs@public.gmane.org>,
<shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
<ben-/+tVBieCtBitmTQ+vhA3Yw@public.gmane.org>
Cc: <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
<pawel.moll-5wv7dgnIgG8@public.gmane.org>,
<mark.rutland-5wv7dgnIgG8@public.gmane.org>,
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
<galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Cyrille Pitchen
<cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Subject: [PATCH 0/7] add driver for Atmel QSPI controller
Date: Thu, 16 Jul 2015 17:27:47 +0200 [thread overview]
Message-ID: <cover.1437059658.git.cyrille.pitchen@atmel.com> (raw)
Hi all,
in order to be able to use Micron Quad SPI memories with the new Atmel QSPI
controller I added a new set_protocol() callback into struct spi_nor.
Indeed, once the quad I/O mode has been enabled on a Micron QSPI flash by
clearing bit 7 in its Enhanced Volatile Configuration Register, this memory
expects all the following commands to use the QSPI 4-4-4 protocol. So the
QSPI controller needs to be notified about this protocol change before
reading the Status register, 0x05 command sent by the
spi_nor_wail_till_ready() function, in micron_quad_enable().
Reading spi-nor.h, I saw an interesting struct spi_nor_xfer_cfg and its
associated callbacks write_xfer() and read_xfer(). However these callbacks
don't seem to be used at all for now. They look to have been designed to
add QSPI support to the generic spi-nor framework. So before extending the
framework with my own callback, I'd like to know whether I should have
tried to used the read_xfer()/write_xfer() callbacks to join an already
existing effort to add QSPI support.
If so, I think either the read/write_reg() prototypes should be updated or
new callbacks should be added for register reads/writes. As explained
above, even for reading the Status register the QSPI 4-4-4 protocol must be
used with Micron memories in quad I/O mode. So the framework has to find a
way to tell the QSPI controller which protocol it should use.
So I'm interested in your comments! :)
Best Regards,
Cyrille
ChangeLog
v1:
This series of patches add support for the new Atmel QSPI controller
embedded inside sama5d2x SoCs.
These patches were first developped for linux-3.18-at91 and tested on a
sama5d27 Xplained ultra board, which embeds a Micron n25q128a13 QSPI NOR
flash memory. Then the series was adapted for mainline.
Cyrille Pitchen (7):
Documentation: mtd: add a DT property to set the number of dummy
cycles
mtd: spi-nor: notify (Q)SPI controller about protocol change
mtd: spi-nor: allow to tune the number of dummy cycles
Documentation: mtd: add a DT property to set the latency code of
Spansion memory
mtd: spi-nor: allow the set the latency code on Spansion memories
Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
mtd: atmel-quadspi: add driver for Atmel QSPI controller
.../devicetree/bindings/mtd/atmel-quadspi.txt | 29 +
.../devicetree/bindings/mtd/jedec,spi-nor.txt | 6 +
.../devicetree/bindings/mtd/spansion-nor.txt | 22 +
drivers/mtd/spi-nor/Kconfig | 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/atmel-quadspi.c | 901 +++++++++++++++++++++
drivers/mtd/spi-nor/spi-nor.c | 160 +++-
include/linux/mtd/spi-nor.h | 15 +
8 files changed, 1122 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt
create mode 100644 drivers/mtd/spi-nor/atmel-quadspi.c
--
1.8.2.2
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: cyrille.pitchen@atmel.com (Cyrille Pitchen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/7] add driver for Atmel QSPI controller
Date: Thu, 16 Jul 2015 17:27:47 +0200 [thread overview]
Message-ID: <cover.1437059658.git.cyrille.pitchen@atmel.com> (raw)
Hi all,
in order to be able to use Micron Quad SPI memories with the new Atmel QSPI
controller I added a new set_protocol() callback into struct spi_nor.
Indeed, once the quad I/O mode has been enabled on a Micron QSPI flash by
clearing bit 7 in its Enhanced Volatile Configuration Register, this memory
expects all the following commands to use the QSPI 4-4-4 protocol. So the
QSPI controller needs to be notified about this protocol change before
reading the Status register, 0x05 command sent by the
spi_nor_wail_till_ready() function, in micron_quad_enable().
Reading spi-nor.h, I saw an interesting struct spi_nor_xfer_cfg and its
associated callbacks write_xfer() and read_xfer(). However these callbacks
don't seem to be used at all for now. They look to have been designed to
add QSPI support to the generic spi-nor framework. So before extending the
framework with my own callback, I'd like to know whether I should have
tried to used the read_xfer()/write_xfer() callbacks to join an already
existing effort to add QSPI support.
If so, I think either the read/write_reg() prototypes should be updated or
new callbacks should be added for register reads/writes. As explained
above, even for reading the Status register the QSPI 4-4-4 protocol must be
used with Micron memories in quad I/O mode. So the framework has to find a
way to tell the QSPI controller which protocol it should use.
So I'm interested in your comments! :)
Best Regards,
Cyrille
ChangeLog
v1:
This series of patches add support for the new Atmel QSPI controller
embedded inside sama5d2x SoCs.
These patches were first developped for linux-3.18-at91 and tested on a
sama5d27 Xplained ultra board, which embeds a Micron n25q128a13 QSPI NOR
flash memory. Then the series was adapted for mainline.
Cyrille Pitchen (7):
Documentation: mtd: add a DT property to set the number of dummy
cycles
mtd: spi-nor: notify (Q)SPI controller about protocol change
mtd: spi-nor: allow to tune the number of dummy cycles
Documentation: mtd: add a DT property to set the latency code of
Spansion memory
mtd: spi-nor: allow the set the latency code on Spansion memories
Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
mtd: atmel-quadspi: add driver for Atmel QSPI controller
.../devicetree/bindings/mtd/atmel-quadspi.txt | 29 +
.../devicetree/bindings/mtd/jedec,spi-nor.txt | 6 +
.../devicetree/bindings/mtd/spansion-nor.txt | 22 +
drivers/mtd/spi-nor/Kconfig | 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/atmel-quadspi.c | 901 +++++++++++++++++++++
drivers/mtd/spi-nor/spi-nor.c | 160 +++-
include/linux/mtd/spi-nor.h | 15 +
8 files changed, 1122 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt
create mode 100644 drivers/mtd/spi-nor/atmel-quadspi.c
--
1.8.2.2
WARNING: multiple messages have this Message-ID (diff)
From: Cyrille Pitchen <cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
To: nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org,
broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
beanhuo-AL4WhLSQfzjQT0dZR+AlfA@public.gmane.org,
juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org,
marex-ynQEQJNshbs@public.gmane.org,
shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
ben-/+tVBieCtBitmTQ+vhA3Yw@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Cyrille Pitchen
<cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Subject: [PATCH 0/7] add driver for Atmel QSPI controller
Date: Thu, 16 Jul 2015 17:27:47 +0200 [thread overview]
Message-ID: <cover.1437059658.git.cyrille.pitchen@atmel.com> (raw)
Hi all,
in order to be able to use Micron Quad SPI memories with the new Atmel QSPI
controller I added a new set_protocol() callback into struct spi_nor.
Indeed, once the quad I/O mode has been enabled on a Micron QSPI flash by
clearing bit 7 in its Enhanced Volatile Configuration Register, this memory
expects all the following commands to use the QSPI 4-4-4 protocol. So the
QSPI controller needs to be notified about this protocol change before
reading the Status register, 0x05 command sent by the
spi_nor_wail_till_ready() function, in micron_quad_enable().
Reading spi-nor.h, I saw an interesting struct spi_nor_xfer_cfg and its
associated callbacks write_xfer() and read_xfer(). However these callbacks
don't seem to be used at all for now. They look to have been designed to
add QSPI support to the generic spi-nor framework. So before extending the
framework with my own callback, I'd like to know whether I should have
tried to used the read_xfer()/write_xfer() callbacks to join an already
existing effort to add QSPI support.
If so, I think either the read/write_reg() prototypes should be updated or
new callbacks should be added for register reads/writes. As explained
above, even for reading the Status register the QSPI 4-4-4 protocol must be
used with Micron memories in quad I/O mode. So the framework has to find a
way to tell the QSPI controller which protocol it should use.
So I'm interested in your comments! :)
Best Regards,
Cyrille
ChangeLog
v1:
This series of patches add support for the new Atmel QSPI controller
embedded inside sama5d2x SoCs.
These patches were first developped for linux-3.18-at91 and tested on a
sama5d27 Xplained ultra board, which embeds a Micron n25q128a13 QSPI NOR
flash memory. Then the series was adapted for mainline.
Cyrille Pitchen (7):
Documentation: mtd: add a DT property to set the number of dummy
cycles
mtd: spi-nor: notify (Q)SPI controller about protocol change
mtd: spi-nor: allow to tune the number of dummy cycles
Documentation: mtd: add a DT property to set the latency code of
Spansion memory
mtd: spi-nor: allow the set the latency code on Spansion memories
Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
mtd: atmel-quadspi: add driver for Atmel QSPI controller
.../devicetree/bindings/mtd/atmel-quadspi.txt | 29 +
.../devicetree/bindings/mtd/jedec,spi-nor.txt | 6 +
.../devicetree/bindings/mtd/spansion-nor.txt | 22 +
drivers/mtd/spi-nor/Kconfig | 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/atmel-quadspi.c | 901 +++++++++++++++++++++
drivers/mtd/spi-nor/spi-nor.c | 160 +++-
include/linux/mtd/spi-nor.h | 15 +
8 files changed, 1122 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt
create mode 100644 drivers/mtd/spi-nor/atmel-quadspi.c
--
1.8.2.2
--
To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next reply other threads:[~2015-07-16 15:27 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-16 15:27 Cyrille Pitchen [this message]
2015-07-16 15:27 ` [PATCH 0/7] add driver for Atmel QSPI controller Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 1/7] Documentation: mtd: add a DT property to set the number of dummy cycles Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 2/7] mtd: spi-nor: notify (Q)SPI controller about protocol change Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 3/7] mtd: spi-nor: allow to tune the number of dummy cycles Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 4/7] Documentation: mtd: add a DT property to set the latency code of Spansion memory Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 17:44 ` Marek Vasut
2015-07-16 17:44 ` Marek Vasut
2015-07-16 17:44 ` Marek Vasut
2015-07-20 9:23 ` Cyrille Pitchen
2015-07-20 9:23 ` Cyrille Pitchen
2015-07-20 9:23 ` Cyrille Pitchen
2015-07-20 9:23 ` Cyrille Pitchen
2015-07-20 19:29 ` Marek Vasut
2015-07-20 19:29 ` Marek Vasut
2015-07-20 19:29 ` Marek Vasut
2015-07-16 15:27 ` [PATCH 5/7] mtd: spi-nor: allow the set the latency code on Spansion memories Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 6/7] Documentation: atmel-quadspi: add binding file for Atmel QSPI driver Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-17 11:44 ` Sergei Shtylyov
2015-07-17 11:44 ` Sergei Shtylyov
2015-07-17 11:44 ` Sergei Shtylyov
2015-07-20 8:54 ` Cyrille Pitchen
2015-07-20 8:54 ` Cyrille Pitchen
2015-07-20 8:54 ` Cyrille Pitchen
2015-07-20 8:54 ` Cyrille Pitchen
2015-07-16 15:27 ` [PATCH 7/7] mtd: atmel-quadspi: add driver for Atmel QSPI controller Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-16 15:27 ` Cyrille Pitchen
2015-07-17 9:04 ` Paul Bolle
2015-07-17 9:04 ` Paul Bolle
2015-07-17 9:04 ` Paul Bolle
2015-07-20 8:55 ` Cyrille Pitchen
2015-07-20 8:55 ` Cyrille Pitchen
2015-07-20 8:55 ` Cyrille Pitchen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1437059658.git.cyrille.pitchen@atmel.com \
--to=cyrille.pitchen@atmel.com \
--cc=beanhuo@micron.com \
--cc=ben@decadent.org.uk \
--cc=broonie@kernel.org \
--cc=computersforpeace@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=dwmw2@infradead.org \
--cc=galak@codeaurora.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=juhosg@openwrt.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=marex@denx.de \
--cc=mark.rutland@arm.com \
--cc=nicolas.ferre@atmel.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=shijie.huang@intel.com \
--cc=zajec5@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.