[Intel-gfx] [PATCH v2 0/5] drm/i915: eDP DPCD aux backlight fixes

[Intel-gfx] [PATCH v2 0/5] drm/i915: eDP DPCD aux backlight fixes

[Jani Nikula]

v2 of Lyude's series [1]. I've postponed reviewing the series so long
that I was too embarrassed to ask for a small fix in patch 1. Otherwise
it's just rebasing. :|

BR,
Jani.


[1] https://patchwork.freedesktop.org/series/69914/


Cc: Lyude Paul <lyude@redhat.com>


Lyude Paul (5):
  drm/i915: Fix eDP DPCD aux max backlight calculations
  drm/i915: Assume 100% brightness when not in DPCD control mode
  drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight()
  drm/i915: Auto detect DPCD backlight support by default
  drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED
    panel

 drivers/gpu/drm/drm_dp_helper.c               |   4 +
 .../drm/i915/display/intel_display_types.h    |   3 +
 .../drm/i915/display/intel_dp_aux_backlight.c | 167 ++++++++++++------
 drivers/gpu/drm/i915/i915_params.c            |   2 +-
 drivers/gpu/drm/i915/i915_params.h            |   2 +-
 include/drm/drm_dp_helper.h                   |   8 +
 6 files changed, 134 insertions(+), 52 deletions(-)

-- 
2.20.1

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[Intel-gfx] [PATCH v2 1/5] drm/i915: Fix eDP DPCD aux max backlight calculations

[Jani Nikula]

From: Lyude Paul <lyude@redhat.com>

Max backlight value for the panel was being calculated using byte
count i.e. 0xffff if 2 bytes are supported for backlight brightness
and 0xff if 1 byte is supported. However, EDP_PWMGEN_BIT_COUNT
determines the number of active control bits used for the brightness
setting. Thus, even if the panel uses 2 byte setting, it might not use
all the control bits. Thus, max backlight should be set based on the
value of EDP_PWMGEN_BIT_COUNT instead of assuming 65535 or 255.

Additionally, EDP_PWMGEN_BIT_COUNT was being updated based on the VBT
frequency which results in a different max backlight value. Thus,
setting of EDP_PWMGEN_BIT_COUNT is moved to setup phase instead of
enable so that max backlight can be calculated correctly. Only the
frequency divider is set during the enable phase using the value of
EDP_PWMGEN_BIT_COUNT.

This is based off the original patch series from Furquan Shaikh
<furquan@google.com>:

https://patchwork.freedesktop.org/patch/317255/?series=62326&rev=3

Changes since original patch:
* Remove unused intel_dp variable in intel_dp_aux_setup_backlight()
* Fix checkpatch issues
* Make sure that we rewrite the pwmgen bit count whenever we bring the
  panel out of D3 mode

v2 by Jani:
* rebase
* fix readb return value check

Cc: Furquan Shaikh <furquan@google.com>
Tested-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: Perry Yuan <pyuan@redhat.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |   3 +
 .../drm/i915/display/intel_dp_aux_backlight.c | 139 ++++++++++++------
 2 files changed, 95 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fdd943a17de3..155ce49ae764 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -214,6 +214,9 @@ struct intel_panel {
 		u8 controller;		/* bxt+ only */
 		struct pwm_device *pwm;
 
+		/* DPCD backlight */
+		u8 pwmgen_bit_count;
+
 		struct backlight_device *device;
 
 		/* Connector and platform specific backlight functions */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 7c653f8c307f..345eed641455 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -111,61 +111,28 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
-	int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
-	u8 pn, pn_min, pn_max;
+	const u8 pn = connector->panel.backlight.pwmgen_bit_count;
+	int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
 
-	/* Find desired value of (F x P)
-	 * Note that, if F x P is out of supported range, the maximum value or
-	 * minimum value will applied automatically. So no need to check that.
-	 */
 	freq = dev_priv->vbt.backlight.pwm_freq_hz;
-	DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
 	if (!freq) {
 		DRM_DEBUG_KMS("Use panel default backlight frequency\n");
 		return false;
 	}
 
 	fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
+	f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+	fxp_actual = f << pn;
 
-	/* Use highest possible value of Pn for more granularity of brightness
-	 * adjustment while satifying the conditions below.
-	 * - Pn is in the range of Pn_min and Pn_max
-	 * - F is in the range of 1 and 255
-	 * - FxP is within 25% of desired value.
-	 *   Note: 25% is arbitrary value and may need some tweak.
-	 */
-	if (drm_dp_dpcd_readb(&intel_dp->aux,
-			       DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
-		DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
-		return false;
-	}
-	if (drm_dp_dpcd_readb(&intel_dp->aux,
-			       DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
-		DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
-		return false;
-	}
-	pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-	pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-
+	/* Ensure frequency is within 25% of desired value */
 	fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
 	fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-	if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
-		DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
-		return false;
-	}
 
-	for (pn = pn_max; pn >= pn_min; pn--) {
-		f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
-		fxp_actual = f << pn;
-		if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
-			break;
-	}
-
-	if (drm_dp_dpcd_writeb(&intel_dp->aux,
-			       DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
-		DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
+	if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
+		DRM_DEBUG_KMS("Actual frequency out of range\n");
 		return false;
 	}
+
 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
 			       DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
 		DRM_DEBUG_KMS("Failed to write aux backlight freq\n");
@@ -179,6 +146,7 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st
 {
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
+	struct intel_panel *panel = &connector->panel;
 	u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
 
 	if (drm_dp_dpcd_readb(&intel_dp->aux,
@@ -197,6 +165,12 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st
 	case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
 		new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
 		new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+
+		if (drm_dp_dpcd_writeb(&intel_dp->aux,
+				       DP_EDP_PWMGEN_BIT_COUNT,
+				       panel->backlight.pwmgen_bit_count) < 0)
+			DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
+
 		break;
 
 	/* Do nothing when it is already DPCD mode */
@@ -226,20 +200,91 @@ static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old
 				 false);
 }
 
+static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector)
+{
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
+	struct intel_panel *panel = &connector->panel;
+	u32 max_backlight = 0;
+	int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+	u8 pn, pn_min, pn_max;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) {
+		pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+		max_backlight = (1 << pn) - 1;
+	}
+
+	/* Find desired value of (F x P)
+	 * Note that, if F x P is out of supported range, the maximum value or
+	 * minimum value will applied automatically. So no need to check that.
+	 */
+	freq = i915->vbt.backlight.pwm_freq_hz;
+	DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
+	if (!freq) {
+		DRM_DEBUG_KMS("Use panel default backlight frequency\n");
+		return max_backlight;
+	}
+
+	fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
+
+	/* Use highest possible value of Pn for more granularity of brightness
+	 * adjustment while satifying the conditions below.
+	 * - Pn is in the range of Pn_min and Pn_max
+	 * - F is in the range of 1 and 255
+	 * - FxP is within 25% of desired value.
+	 *   Note: 25% is arbitrary value and may need some tweak.
+	 */
+	if (drm_dp_dpcd_readb(&intel_dp->aux,
+			      DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
+		DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
+		return max_backlight;
+	}
+	if (drm_dp_dpcd_readb(&intel_dp->aux,
+			      DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
+		DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
+		return max_backlight;
+	}
+	pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+	pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+	fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+	fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+	if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+		DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
+		return max_backlight;
+	}
+
+	for (pn = pn_max; pn >= pn_min; pn--) {
+		f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+		fxp_actual = f << pn;
+		if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+			break;
+	}
+
+	DRM_DEBUG_KMS("Using eDP pwmgen bit count of %d\n", pn);
+	if (drm_dp_dpcd_writeb(&intel_dp->aux,
+			       DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+		DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
+		return max_backlight;
+	}
+	panel->backlight.pwmgen_bit_count = pn;
+
+	max_backlight = (1 << pn) - 1;
+
+	return max_backlight;
+}
+
 static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
 					enum pipe pipe)
 {
-	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
 	struct intel_panel *panel = &connector->panel;
 
-	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
-		panel->backlight.max = 0xFFFF;
-	else
-		panel->backlight.max = 0xFF;
+	panel->backlight.max = intel_dp_aux_calc_max_backlight(connector);
+	if (!panel->backlight.max)
+		return -ENODEV;
 
 	panel->backlight.min = 0;
 	panel->backlight.level = intel_dp_aux_get_backlight(connector);
-
 	panel->backlight.enabled = panel->backlight.level != 0;
 
 	return 0;
-- 
2.20.1

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[Intel-gfx] [PATCH v2 2/5] drm/i915: Assume 100% brightness when not in DPCD control mode

[Jani Nikula]

From: Lyude Paul <lyude@redhat.com>

Currently we always determine the initial panel brightness level by
simply reading the value from DP_EDP_BACKLIGHT_BRIGHTNESS_MSB/LSB. This
seems wrong though, because if the panel is not currently in DPCD
control mode there's not really any reason why there would be any
brightness value programmed in the first place.

This appears to be the case on the Lenovo ThinkPad X1 Extreme 2nd
Generation, where the default value in these registers is always 0 on
boot despite the fact the panel runs at max brightness by default.
Getting the initial brightness value correct here is important as well,
since the panel on this laptop doesn't behave well if it's ever put into
DPCD control mode while the brightness level is programmed to 0.

So, let's fix this by checking what the current backlight control mode
is before reading the brightness level. If it's in DPCD control mode, we
return the programmed brightness level. Otherwise we assume 100%
brightness and return the highest possible brightness level. This also
prevents us from accidentally programming a brightness level of 0.

This is one of the many fixes that gets backlight controls working on
the ThinkPad X1 Extreme 2nd Generation with optional 4K AMOLED screen.

Changes since v1:
* s/DP_EDP_DISPLAY_CONTROL_REGISTER/DP_EDP_BACKLIGHT_MODE_SET_REGISTER/
  - Jani

Tested-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: Perry Yuan <pyuan@redhat.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/i915/display/intel_dp_aux_backlight.c   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 345eed641455..5d4db5f8a165 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -59,8 +59,25 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
 	u8 read_val[2] = { 0x0 };
+	u8 mode_reg;
 	u16 level = 0;
 
+	if (drm_dp_dpcd_readb(&intel_dp->aux,
+			      DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+			      &mode_reg) != 1) {
+		DRM_DEBUG_KMS("Failed to read the DPCD register 0x%x\n",
+			      DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+		return 0;
+	}
+
+	/*
+	 * If we're not in DPCD control mode yet, the programmed brightness
+	 * value is meaningless and we should assume max brightness
+	 */
+	if ((mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) !=
+	    DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD)
+		return connector->panel.backlight.max;
+
 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
 			     &read_val, sizeof(read_val)) < 0) {
 		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
-- 
2.20.1

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[Intel-gfx] [PATCH v2 3/5] drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight()

[Jani Nikula]

From: Lyude Paul <lyude@redhat.com>

For eDP panels, it appears it's expected that so long as the panel is in
DPCD control mode that the brightness value is never set to 0. Instead,
if the desired effect is to set the panel's backlight to 0 we're
expected to simply turn off the backlight through the
DP_EDP_DISPLAY_CONTROL_REGISTER.

We already do the latter correctly in intel_dp_aux_disable_backlight().
But, we make the mistake of writing the DPCD registers in the wrong
order when enabling the backlight in intel_dp_aux_enable_backlight()
since we currently enable the backlight through
DP_EDP_DISPLAY_CONTROL_REGISTER before writing the brightness level. On
the X1 Extreme 2nd Generation, this appears to have the potential of
confusing the panel in such a way that further attempts to set the
brightness don't actually change the backlight as expected and leave it
off. Presumably, this happens because the incorrect register writing
order briefly leaves the panel with DPCD mode enabled and a 0 brightness
level set.

So, reverse the order we write the DPCD registers when enabling the
panel backlight so that we write the brightness value first, and enable
the backlight second. This fix appears to be the final bit needed to get
the backlight on the ThinkPad X1 Extreme 2nd Generation's AMOLED screen
working.

Tested-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: Perry Yuan <pyuan@redhat.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 5d4db5f8a165..77a759361c5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -207,8 +207,9 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st
 		}
 	}
 
+	intel_dp_aux_set_backlight(conn_state,
+				   connector->panel.backlight.level);
 	set_aux_backlight_enable(intel_dp, true);
-	intel_dp_aux_set_backlight(conn_state, connector->panel.backlight.level);
 }
 
 static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state)
-- 
2.20.1

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[Intel-gfx] [PATCH v2 4/5] drm/i915: Auto detect DPCD backlight support by default

[Jani Nikula]

From: Lyude Paul <lyude@redhat.com>

Turns out we actually already have some companies, such as Lenovo,
shipping machines with AMOLED screens that don't allow controlling the
backlight through the usual PWM interface and only allow controlling it
through the standard EDP DPCD interface. One example of one of these
laptops is the X1 Extreme 2nd Generation.

Since we've got systems that need this turned on by default now to have
backlight controls working out of the box, let's start auto-detecting it
for systems by default based on what the VBT tells us. We do this by
changing the default value for the enable_dpcd_backlight module param
from 0 to -1.

Tested-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: Perry Yuan <pyuan@redhat.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 2 +-
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1dd1f3652795..31eed60c167e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -172,7 +172,7 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400,
 
 i915_param_named(enable_dpcd_backlight, int, 0600,
 	"Enable support for DPCD backlight control"
-	"(-1=use per-VBT LFP backlight type setting, 0=disabled [default], 1=enabled)");
+	"(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 1=enabled)");
 
 #if IS_ENABLED(CONFIG_DRM_I915_GVT)
 i915_param_named(enable_gvt, bool, 0400,
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 31b88f297fbc..a79d0867f77a 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,7 @@ struct drm_printer;
 	param(int, reset, 3) \
 	param(unsigned int, inject_probe_failure, 0) \
 	param(int, fastboot, -1) \
-	param(int, enable_dpcd_backlight, 0) \
+	param(int, enable_dpcd_backlight, -1) \
 	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE) \
 	param(unsigned long, fake_lmem_start, 0) \
 	/* leave bools at the end to not create holes */ \
-- 
2.20.1

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[Intel-gfx] [PATCH v2 5/5] drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel

[Jani Nikula]

From: Lyude Paul <lyude@redhat.com>

Annoyingly, the VBT on the ThinkPad X1 Extreme 2nd Gen indicates that
the system uses plain PWM based backlight controls, when in reality the
only backlight controls that work are the standard VESA eDP DPCD
backlight controls.

Honestly, this makes me wonder how many other systems have these issues
or lie about this in their VBT. Not sure we have any good way of finding
out until panels like this become more common place in the laptop
market. For now, just add a DRM DP quirk to indicate that this panel is
telling the truth and is being a good LCD.

v2 by Jani:
- rebase

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112376
Closes: https://gitlab.freedesktop.org/drm/intel/issues/642
Tested-by: AceLan Kao <acelan.kao@canonical.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c                       | 4 ++++
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 8 ++++++--
 include/drm/drm_dp_helper.h                           | 8 ++++++++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..90e122809fa4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1179,6 +1179,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
 	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
+	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
+	 * only supports DPCD backlight controls, despite advertising otherwise
+	 */
+	{ OUI(0xba, 0x41, 0x59), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 77a759361c5c..57774003e8c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -328,11 +328,15 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector)
 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
 {
 	struct intel_panel *panel = &intel_connector->panel;
-	struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder);
+	struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
 
 	if (i915_modparams.enable_dpcd_backlight == 0 ||
 	    (i915_modparams.enable_dpcd_backlight == -1 &&
-	    dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
+	     i915->vbt.backlight.type !=
+	     INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
+	     !drm_dp_has_quirk(&intel_dp->desc,
+			       DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT)))
 		return -ENODEV;
 
 	if (!intel_dp_aux_display_control_capable(intel_connector))
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..bb081921f53d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1532,6 +1532,14 @@ enum drm_dp_quirk {
 	 * The DSC caps can be read from the physical aux instead.
 	 */
 	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
+	/**
+	 * @DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT:
+	 *
+	 * The device is telling the truth when it says that it uses DPCD
+	 * backlight controls, even if the system's firmware disagrees.
+	 * The driver should honor the DPCD backlight capabilities advertised.
+	 */
+	DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT,
 };
 
 /**
-- 
2.20.1

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Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel

[Lyude Paul]

fwiw - I got some feedback from one of the vendors that we work with that I
haven't gone through yet, but I'm hoping to figure out whether we want to
trust the vbt/dpcd based off that once I do. Once we've made up the decision
on that (and I send out a reroll if needed), think this is good to merge? (I
don't see any issues with any of the changes you've made, and they seem to
work fine on my machines)

On Tue, 2020-01-14 at 16:01 +0200, Jani Nikula wrote:
> From: Lyude Paul <lyude@redhat.com>
> 
> Annoyingly, the VBT on the ThinkPad X1 Extreme 2nd Gen indicates that
> the system uses plain PWM based backlight controls, when in reality the
> only backlight controls that work are the standard VESA eDP DPCD
> backlight controls.
> 
> Honestly, this makes me wonder how many other systems have these issues
> or lie about this in their VBT. Not sure we have any good way of finding
> out until panels like this become more common place in the laptop
> market. For now, just add a DRM DP quirk to indicate that this panel is
> telling the truth and is being a good LCD.
> 
> v2 by Jani:
> - rebase
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112376
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/642
> Tested-by: AceLan Kao <acelan.kao@canonical.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c                       | 4 ++++
>  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 8 ++++++--
>  include/drm/drm_dp_helper.h                           | 8 ++++++++
>  3 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..90e122809fa4 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1179,6 +1179,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
>  	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'),
> false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
>  	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
>  	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
> BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
> +	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
> +	 * only supports DPCD backlight controls, despite advertising
> otherwise
> +	 */
> +	{ OUI(0xba, 0x41, 0x59), DEVICE_ID_ANY, false,
> BIT(DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT) },
>  };
>  
>  #undef OUI
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 77a759361c5c..57774003e8c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -328,11 +328,15 @@ intel_dp_aux_display_control_capable(struct
> intel_connector *connector)
>  int intel_dp_aux_init_backlight_funcs(struct intel_connector
> *intel_connector)
>  {
>  	struct intel_panel *panel = &intel_connector->panel;
> -	struct drm_i915_private *dev_priv = to_i915(intel_connector-
> >base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder);
> +	struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
>  
>  	if (i915_modparams.enable_dpcd_backlight == 0 ||
>  	    (i915_modparams.enable_dpcd_backlight == -1 &&
> -	    dev_priv->vbt.backlight.type !=
> INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
> +	     i915->vbt.backlight.type !=
> +	     INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
> +	     !drm_dp_has_quirk(&intel_dp->desc,
> +			       DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT)))
>  		return -ENODEV;
>  
>  	if (!intel_dp_aux_display_control_capable(intel_connector))
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 262faf9e5e94..bb081921f53d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1532,6 +1532,14 @@ enum drm_dp_quirk {
>  	 * The DSC caps can be read from the physical aux instead.
>  	 */
>  	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
> +	/**
> +	 * @DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT:
> +	 *
> +	 * The device is telling the truth when it says that it uses DPCD
> +	 * backlight controls, even if the system's firmware disagrees.
> +	 * The driver should honor the DPCD backlight capabilities advertised.
> +	 */
> +	DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT,
>  };
>  
>  /**
-- 
Cheers,
	Lyude Paul

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Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel

[Jani Nikula]

On Tue, 14 Jan 2020, Lyude Paul <lyude@redhat.com> wrote:
> fwiw - I got some feedback from one of the vendors that we work with that I
> haven't gone through yet, but I'm hoping to figure out whether we want to
> trust the vbt/dpcd based off that once I do. Once we've made up the decision
> on that (and I send out a reroll if needed), think this is good to merge? (I
> don't see any issues with any of the changes you've made, and they seem to
> work fine on my machines)

Thanks, yes, my idea was that I'd merge this after CI says good to
go. But do let me know if you get more information.

BR,
Jani.


>
> On Tue, 2020-01-14 at 16:01 +0200, Jani Nikula wrote:
>> From: Lyude Paul <lyude@redhat.com>
>> 
>> Annoyingly, the VBT on the ThinkPad X1 Extreme 2nd Gen indicates that
>> the system uses plain PWM based backlight controls, when in reality the
>> only backlight controls that work are the standard VESA eDP DPCD
>> backlight controls.
>> 
>> Honestly, this makes me wonder how many other systems have these issues
>> or lie about this in their VBT. Not sure we have any good way of finding
>> out until panels like this become more common place in the laptop
>> market. For now, just add a DRM DP quirk to indicate that this panel is
>> telling the truth and is being a good LCD.
>> 
>> v2 by Jani:
>> - rebase
>> 
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112376
>> Closes: https://gitlab.freedesktop.org/drm/intel/issues/642
>> Tested-by: AceLan Kao <acelan.kao@canonical.com>
>> Signed-off-by: Lyude Paul <lyude@redhat.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/drm_dp_helper.c                       | 4 ++++
>>  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 8 ++++++--
>>  include/drm/drm_dp_helper.h                           | 8 ++++++++
>>  3 files changed, 18 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c
>> index 5a103e9b3c86..90e122809fa4 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1179,6 +1179,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
>>  	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'),
>> false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
>>  	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
>>  	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
>> BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
>> +	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
>> +	 * only supports DPCD backlight controls, despite advertising
>> otherwise
>> +	 */
>> +	{ OUI(0xba, 0x41, 0x59), DEVICE_ID_ANY, false,
>> BIT(DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT) },
>>  };
>>  
>>  #undef OUI
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 77a759361c5c..57774003e8c5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -328,11 +328,15 @@ intel_dp_aux_display_control_capable(struct
>> intel_connector *connector)
>>  int intel_dp_aux_init_backlight_funcs(struct intel_connector
>> *intel_connector)
>>  {
>>  	struct intel_panel *panel = &intel_connector->panel;
>> -	struct drm_i915_private *dev_priv = to_i915(intel_connector-
>> >base.dev);
>> +	struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder);
>> +	struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
>>  
>>  	if (i915_modparams.enable_dpcd_backlight == 0 ||
>>  	    (i915_modparams.enable_dpcd_backlight == -1 &&
>> -	    dev_priv->vbt.backlight.type !=
>> INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
>> +	     i915->vbt.backlight.type !=
>> +	     INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
>> +	     !drm_dp_has_quirk(&intel_dp->desc,
>> +			       DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT)))
>>  		return -ENODEV;
>>  
>>  	if (!intel_dp_aux_display_control_capable(intel_connector))
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 262faf9e5e94..bb081921f53d 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -1532,6 +1532,14 @@ enum drm_dp_quirk {
>>  	 * The DSC caps can be read from the physical aux instead.
>>  	 */
>>  	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
>> +	/**
>> +	 * @DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT:
>> +	 *
>> +	 * The device is telling the truth when it says that it uses DPCD
>> +	 * backlight controls, even if the system's firmware disagrees.
>> +	 * The driver should honor the DPCD backlight capabilities advertised.
>> +	 */
>> +	DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT,
>>  };
>>  
>>  /**

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel

[Lyude Paul]

sigh… so I just went through the correspondence with the vendor I mentioned
and unfortunately the answer is still unclear. It looks like that for some of
these panels there might actually be some bits in the EDID (!?!?) that are
supposed to correspond to the backlight interface. weird. on top of that I'm
not even sure if these EDID bits are actually standard. Interestingly enough
it seems like they're also intending for some of their panels to be able to be
used in both PWM and DPCD mode, and will eventually drop the PWM
compatibility.

Note this vendor isn't Lenovo, so I'm assuming that's probably why pwm mode
doesn't work at all on this X1 extreme.

That being said all I've seen are systems that don't specify this correctly in
the vbt but do in the dpcd, so I'm going to go ahead and change this patch
series over to using the dpcd by default instead. If this actually breaks any
systems out there we can change the default behavior later. I will do a respin
of the series asap (will have it on the list today or tommorrow, will merge
after CI gives the OK).

On Wed, 2020-01-15 at 10:32 +0200, Jani Nikula wrote:
> On Tue, 14 Jan 2020, Lyude Paul <lyude@redhat.com> wrote:
> > fwiw - I got some feedback from one of the vendors that we work with that
> > I
> > haven't gone through yet, but I'm hoping to figure out whether we want to
> > trust the vbt/dpcd based off that once I do. Once we've made up the
> > decision
> > on that (and I send out a reroll if needed), think this is good to merge?
> > (I
> > don't see any issues with any of the changes you've made, and they seem to
> > work fine on my machines)
> 
> Thanks, yes, my idea was that I'd merge this after CI says good to
> go. But do let me know if you get more information.
> 
> BR,
> Jani.
> 
> 
> > On Tue, 2020-01-14 at 16:01 +0200, Jani Nikula wrote:
> > > From: Lyude Paul <lyude@redhat.com>
> > > 
> > > Annoyingly, the VBT on the ThinkPad X1 Extreme 2nd Gen indicates that
> > > the system uses plain PWM based backlight controls, when in reality the
> > > only backlight controls that work are the standard VESA eDP DPCD
> > > backlight controls.
> > > 
> > > Honestly, this makes me wonder how many other systems have these issues
> > > or lie about this in their VBT. Not sure we have any good way of finding
> > > out until panels like this become more common place in the laptop
> > > market. For now, just add a DRM DP quirk to indicate that this panel is
> > > telling the truth and is being a good LCD.
> > > 
> > > v2 by Jani:
> > > - rebase
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112376
> > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/642
> > > Tested-by: AceLan Kao <acelan.kao@canonical.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_dp_helper.c                       | 4 ++++
> > >  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 8 ++++++--
> > >  include/drm/drm_dp_helper.h                           | 8 ++++++++
> > >  3 files changed, 18 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > > b/drivers/gpu/drm/drm_dp_helper.c
> > > index 5a103e9b3c86..90e122809fa4 100644
> > > --- a/drivers/gpu/drm/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > > @@ -1179,6 +1179,10 @@ static const struct dpcd_quirk dpcd_quirk_list[]
> > > = {
> > >  	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'),
> > > false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
> > >  	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
> > >  	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
> > > BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
> > > +	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
> > > +	 * only supports DPCD backlight controls, despite advertising
> > > otherwise
> > > +	 */
> > > +	{ OUI(0xba, 0x41, 0x59), DEVICE_ID_ANY, false,
> > > BIT(DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT) },
> > >  };
> > >  
> > >  #undef OUI
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > index 77a759361c5c..57774003e8c5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > @@ -328,11 +328,15 @@ intel_dp_aux_display_control_capable(struct
> > > intel_connector *connector)
> > >  int intel_dp_aux_init_backlight_funcs(struct intel_connector
> > > *intel_connector)
> > >  {
> > >  	struct intel_panel *panel = &intel_connector->panel;
> > > -	struct drm_i915_private *dev_priv = to_i915(intel_connector-
> > > > base.dev);
> > > +	struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder);
> > > +	struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
> > >  
> > >  	if (i915_modparams.enable_dpcd_backlight == 0 ||
> > >  	    (i915_modparams.enable_dpcd_backlight == -1 &&
> > > -	    dev_priv->vbt.backlight.type !=
> > > INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
> > > +	     i915->vbt.backlight.type !=
> > > +	     INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
> > > +	     !drm_dp_has_quirk(&intel_dp->desc,
> > > +			       DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT)))
> > >  		return -ENODEV;
> > >  
> > >  	if (!intel_dp_aux_display_control_capable(intel_connector))
> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > > index 262faf9e5e94..bb081921f53d 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -1532,6 +1532,14 @@ enum drm_dp_quirk {
> > >  	 * The DSC caps can be read from the physical aux instead.
> > >  	 */
> > >  	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
> > > +	/**
> > > +	 * @DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT:
> > > +	 *
> > > +	 * The device is telling the truth when it says that it uses DPCD
> > > +	 * backlight controls, even if the system's firmware disagrees.
> > > +	 * The driver should honor the DPCD backlight capabilities advertised.
> > > +	 */
> > > +	DP_DPCD_QUIRK_FORCE_DPCD_BACKLIGHT,
> > >  };
> > >  
> > >  /**
-- 
Cheers,
	Lyude Paul

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Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel

[Jani Nikula]

On Wed, 15 Jan 2020, Lyude Paul <lyude@redhat.com> wrote:
> sigh… so I just went through the correspondence with the vendor I mentioned
> and unfortunately the answer is still unclear. It looks like that for some of
> these panels there might actually be some bits in the EDID (!?!?) that are
> supposed to correspond to the backlight interface. weird. on top of that I'm
> not even sure if these EDID bits are actually standard. Interestingly enough
> it seems like they're also intending for some of their panels to be able to be
> used in both PWM and DPCD mode, and will eventually drop the PWM
> compatibility.
>
> Note this vendor isn't Lenovo, so I'm assuming that's probably why pwm mode
> doesn't work at all on this X1 extreme.
>
> That being said all I've seen are systems that don't specify this correctly in
> the vbt but do in the dpcd, so I'm going to go ahead and change this patch
> series over to using the dpcd by default instead. If this actually breaks any
> systems out there we can change the default behavior later. I will do a respin
> of the series asap (will have it on the list today or tommorrow, will merge
> after CI gives the OK).

Don't worry, nothing about displays really surprises me anymore.

I'm fine with the idea of trying to use the DPCD alone to enable aux
backlight. We need to try to make this work out of the box, without
module parameters.

Just make sure it's reasonably easy to revert in case issues do arise...

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: eDP DPCD aux backlight fixes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: eDP DPCD aux backlight fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/69914/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7739 -> Patchwork_16093
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/index.html

Known issues
------------

  Here are the changes found in Patchwork_16093 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [PASS][1] -> [TIMEOUT][2] ([fdo#112271] / [i915#816])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@gem_mmap_gtt@basic:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-tgl-y/igt@gem_mmap_gtt@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-tgl-y/igt@gem_mmap_gtt@basic.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-bxt-dsi:         [PASS][5] -> [DMESG-WARN][6] ([i915#889])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live_gt_lrc:
    - fi-skl-6600u:       [PASS][7] -> [DMESG-FAIL][8] ([i915#889]) +7 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html

  * igt@i915_selftest@live_late_gt_pm:
    - fi-skl-6600u:       [PASS][9] -> [DMESG-WARN][10] ([i915#889]) +23 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [PASS][11] -> [FAIL][12] ([i915#217])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][13] -> [FAIL][14] ([fdo#111096] / [i915#323])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-snb-2600:        [PASS][15] -> [DMESG-WARN][16] ([i915#42])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-snb-2600/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-snb-2600/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][17] ([i915#178]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [DMESG-FAIL][19] ([i915#553] / [i915#725]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  * igt@vgem_basic@dmabuf-export:
    - fi-tgl-y:           [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-tgl-y/igt@vgem_basic@dmabuf-export.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-tgl-y/igt@vgem_basic@dmabuf-export.html

  
#### Warnings ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][23] ([i915#725]) -> [DMESG-FAIL][24] ([i915#770])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889


Participating hosts (53 -> 38)
------------------------------

  Missing    (15): fi-ilk-m540 fi-ehl-1 fi-bdw-5557u fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-whl-u fi-gdg-551 fi-ivb-3770 fi-bsw-kefka fi-skl-lmem fi-blb-e6850 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7739 -> Patchwork_16093

  CI-20190529: 20190529
  CI_DRM_7739: 757c25a357ea6e34d5eba9b6efee6f45e7961334 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5365: e9ec0ed63b25c86861ffac3c8601cc4d1b910b65 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16093: 213de11f3073d76fce7ecd3d521cbf86f9dd1269 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_16093/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

213de11f3073 drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panel
8a1e3fe11546 drm/i915: Auto detect DPCD backlight support by default
c37314bdc01a drm/i915: Fix DPCD register order in intel_dp_aux_enable_backlight()
2f08b1334736 drm/i915: Assume 100% brightness when not in DPCD control mode
cb1ed8a4e812 drm/i915: Fix eDP DPCD aux max backlight calculations

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: eDP DPCD aux backlight fixes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: eDP DPCD aux backlight fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/69914/
State : warning

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: eDP DPCD aux backlight fixes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: eDP DPCD aux backlight fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/69914/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7739_full -> Patchwork_16093_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16093_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16093_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16093_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_cs_tlb@vcs0:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb4/igt@gem_cs_tlb@vcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb4/igt@gem_cs_tlb@vcs0.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_pm_rc6_residency@rc6-idle}:
    - shard-hsw:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-hsw5/igt@i915_pm_rc6_residency@rc6-idle.html

  
Known issues
------------

  Here are the changes found in Patchwork_16093_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@close-race:
    - shard-tglb:         [PASS][4] -> [INCOMPLETE][5] ([i915#977])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb5/igt@gem_busy@close-race.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb6/igt@gem_busy@close-race.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-reset:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb2/igt@gem_ctx_isolation@vcs1-reset.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb5/igt@gem_ctx_isolation@vcs1-reset.html

  * igt@gem_ctx_persistence@vecs0-mixed-process:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#679])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-glk9/igt@gem_ctx_persistence@vecs0-mixed-process.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-glk5/igt@gem_ctx_persistence@vecs0-mixed-process.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#110841])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [PASS][14] -> [FAIL][15] ([i915#232])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-snb4/igt@gem_eio@reset-stress.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-snb6/igt@gem_eio@reset-stress.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-hsw:          [PASS][16] -> [FAIL][17] ([i915#694])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-hsw5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_gttfill@basic:
    - shard-tglb:         [PASS][18] -> [INCOMPLETE][19] ([fdo#111593] / [i915#472])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb5/igt@gem_exec_gttfill@basic.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb8/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_parallel@basic:
    - shard-tglb:         [PASS][20] -> [INCOMPLETE][21] ([i915#472] / [i915#476])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb1/igt@gem_exec_parallel@basic.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb9/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_reuse@single:
    - shard-tglb:         [PASS][22] -> [INCOMPLETE][23] ([i915#472])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb4/igt@gem_exec_reuse@single.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb8/igt@gem_exec_reuse@single.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][24] -> [SKIP][25] ([fdo#109276]) +12 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [PASS][26] -> [SKIP][27] ([i915#677]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb3/igt@gem_exec_schedule@pi-common-bsd.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][28] -> [SKIP][29] ([fdo#112146]) +5 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_exec_schedule@smoketest-bsd1:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([i915#463] / [i915#472])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb2/igt@gem_exec_schedule@smoketest-bsd1.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb6/igt@gem_exec_schedule@smoketest-bsd1.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [PASS][32] -> [INCOMPLETE][33] ([i915#472] / [i915#707])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb7/igt@gem_sync@basic-each.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb3/igt@gem_sync@basic-each.html

  * igt@i915_pm_rpm@cursor:
    - shard-skl:          [PASS][34] -> [INCOMPLETE][35] ([i915#151])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl2/igt@i915_pm_rpm@cursor.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl9/igt@i915_pm_rpm@cursor.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [PASS][36] -> [FAIL][37] ([i915#413])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb1/igt@i915_pm_rps@waitboost.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb1/igt@i915_pm_rps@waitboost.html

  * igt@kms_color@pipe-b-ctm-0-25:
    - shard-skl:          [PASS][38] -> [DMESG-WARN][39] ([i915#109]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl7/igt@kms_color@pipe-b-ctm-0-25.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl3/igt@kms_color@pipe-b-ctm-0-25.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
    - shard-tglb:         [PASS][40] -> [FAIL][41] ([fdo#111703])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb9/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [PASS][42] -> [FAIL][43] ([i915#34])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl3/igt@kms_flip@plain-flip-fb-recreate.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [PASS][44] -> [FAIL][45] ([i915#49])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([i915#247])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl6/igt@kms_plane@plane-position-covered-pipe-c-planes.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl4/igt@kms_plane@plane-position-covered-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][50] -> [FAIL][51] ([fdo#108145] / [i915#265])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][52] -> [SKIP][53] ([fdo#109441]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb5/igt@kms_psr@psr2_sprite_render.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][54] -> [SKIP][55] ([fdo#112080]) +5 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb1/igt@perf_pmu@busy-vcs1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb8/igt@perf_pmu@busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@vcs0-mixed-process:
    - shard-skl:          [FAIL][56] ([i915#679]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl9/igt@gem_ctx_persistence@vcs0-mixed-process.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl8/igt@gem_ctx_persistence@vcs0-mixed-process.html

  * igt@gem_ctx_persistence@vcs1-hostile-preempt:
    - shard-iclb:         [SKIP][58] ([fdo#109276] / [fdo#112080]) -> [PASS][59] +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb6/igt@gem_ctx_persistence@vcs1-hostile-preempt.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@gem_ctx_persistence@vcs1-hostile-preempt.html

  * igt@gem_eio@in-flight-1us:
    - shard-tglb:         [INCOMPLETE][60] ([i915#534] / [i915#707]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb6/igt@gem_eio@in-flight-1us.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb4/igt@gem_eio@in-flight-1us.html

  * igt@gem_exec_schedule@pi-userfault-bsd:
    - shard-iclb:         [SKIP][62] ([i915#677]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb3/igt@gem_exec_schedule@pi-userfault-bsd.html

  * igt@gem_exec_schedule@preempt-queue-contexts-render:
    - shard-tglb:         [INCOMPLETE][64] ([fdo#111606] / [fdo#111677] / [i915#472]) -> [PASS][65] +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-render.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][66] ([fdo#112146]) -> [PASS][67] +5 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - shard-tglb:         [INCOMPLETE][68] ([i915#463] / [i915#472]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb2/igt@gem_exec_schedule@smoketest-all.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb4/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_exec_schedule@smoketest-bsd2:
    - shard-tglb:         [INCOMPLETE][70] ([i915#472] / [i915#707]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb6/igt@gem_exec_schedule@smoketest-bsd2.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb8/igt@gem_exec_schedule@smoketest-bsd2.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [TIMEOUT][72] ([fdo#112271] / [i915#530]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-tglb:         [INCOMPLETE][74] ([i915#707] / [i915#796]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb3/igt@gem_pipe_control_store_loop@reused-buffer.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb1/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][76] ([i915#644]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [INCOMPLETE][78] ([i915#470] / [i915#472]) -> [PASS][79] +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb3/igt@gem_sync@basic-all.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb5/igt@gem_sync@basic-all.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-hsw:          [FAIL][80] ([i915#694]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-hsw7/igt@gen7_exec_parse@basic-offset.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-hsw1/igt@gen7_exec_parse@basic-offset.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-kbl:          [DMESG-WARN][82] ([i915#716]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-kbl7/igt@gen9_exec_parse@allowed-all.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-kbl6/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [FAIL][84] ([i915#447]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb6/igt@i915_pm_dc@dc5-dpms.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][86] ([i915#180]) -> [PASS][87] +4 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-apl2/igt@i915_suspend@sysfs-reader.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][88] ([i915#109]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl8/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [FAIL][90] ([i915#72]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [FAIL][92] ([i915#79]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][94] ([i915#79]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [INCOMPLETE][96] ([fdo#103927]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-skl:          [FAIL][98] ([i915#34]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
    - shard-tglb:         [FAIL][100] ([i915#49]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][102] ([fdo#108145]) -> [PASS][103] +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][104] ([fdo#109441]) -> [PASS][105] +2 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-tglb:         [FAIL][106] ([i915#31]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb3/igt@kms_setmode@basic.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb1/igt@kms_setmode@basic.html
    - shard-apl:          [FAIL][108] ([i915#31]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-apl1/igt@kms_setmode@basic.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-apl1/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +10 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [SKIP][112] ([fdo#112080]) -> [PASS][113] +9 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb5/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@perf_pmu@busy-no-semaphores-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][114] ([fdo#109276]) -> [PASS][115] +12 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [SKIP][116] ([i915#468]) -> [FAIL][117] ([i915#454])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@i2c:
    - shard-snb:          [INCOMPLETE][118] ([i915#82]) -> [SKIP][119] ([fdo#109271])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-snb2/igt@i915_pm_rpm@i2c.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-snb5/igt@i915_pm_rpm@i2c.html

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-tglb:         [FAIL][120] ([i915#576] / [i915#598]) -> [FAIL][121] ([i915#598])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-tglb5/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-tglb3/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][122], [FAIL][123]) ([i915#716] / [i915#974]) -> [FAIL][124] ([i915#974])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-kbl2/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7739/shard-kbl7/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/shard-kbl1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
  [i915#247]: https://gitlab.freedesktop.org/drm/intel/issues/247
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
  [i915#534]: https://gitlab.freedesktop.org/drm/intel/issues/534
  [i915#576]: https://gitlab.freedesktop.org/drm/intel/issues/576
  [i915#598]: https://gitlab.freedesktop.org/drm/intel/issues/598
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#796]: https://gitlab.freedesktop.org/drm/intel/issues/796
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#974]: https://gitlab.freedesktop.org/drm/intel/issues/974
  [i915#977]: https://gitlab.freedesktop.org/drm/intel/issues/977


Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-snb-2600 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7739 -> Patchwork_16093

  CI-20190529: 20190529
  CI_DRM_7739: 757c25a357ea6e34d5eba9b6efee6f45e7961334 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5365: e9ec0ed63b25c86861ffac3c8601cc4d1b910b65 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16093: 213de11f3073d76fce7ecd3d521cbf86f9dd1269 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16093/index.html
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