* [PATCH v1 0/2] e1000 base code update
@ 2025-06-09 10:16 Anatoly Burakov
2025-06-09 10:16 ` [PATCH v1 1/2] net/e1000: better clock synchronization workaround Anatoly Burakov
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Anatoly Burakov @ 2025-06-09 10:16 UTC (permalink / raw)
To: dev
Update e1000 base code version to 2025-06-04-14.40
Anatoly Burakov (1):
net/e1000: update README
Vitaly Lifshits (1):
net/e1000: better clock synchronization workaround
drivers/net/intel/e1000/base/README | 4 +-
drivers/net/intel/e1000/base/e1000_ich8lan.c | 82 +++++++++++++++++---
drivers/net/intel/e1000/base/e1000_ich8lan.h | 4 +
3 files changed, 76 insertions(+), 14 deletions(-)
--
2.47.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v1 1/2] net/e1000: better clock synchronization workaround 2025-06-09 10:16 [PATCH v1 0/2] e1000 base code update Anatoly Burakov @ 2025-06-09 10:16 ` Anatoly Burakov 2025-06-09 16:23 ` Stephen Hemminger 2025-06-09 10:16 ` [PATCH v1 2/2] net/e1000: update README Anatoly Burakov 2025-06-09 15:53 ` [PATCH v1 0/2] e1000 base code update Bruce Richardson 2 siblings, 1 reply; 6+ messages in thread From: Anatoly Burakov @ 2025-06-09 10:16 UTC (permalink / raw) To: dev, Bruce Richardson, Vitaly Lifshits From: Vitaly Lifshits <vitaly.lifshits@intel.com> There was a workaround for clock synchronization issue already in place, however this workaround has a high power penalty. Fix the issue by reconfiguring the k1 exit timeout, thereby avoiding the side effect of high power draw. Fixes: 90f456cea0c2 ("net/e1000/base: correct clock synchronization") Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com> Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com> --- drivers/net/intel/e1000/base/e1000_ich8lan.c | 82 +++++++++++++++++--- drivers/net/intel/e1000/base/e1000_ich8lan.h | 4 + 2 files changed, 74 insertions(+), 12 deletions(-) diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c index 6b7eb245a6..ece61650f7 100644 --- a/drivers/net/intel/e1000/base/e1000_ich8lan.c +++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c @@ -284,6 +284,43 @@ STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) } } +/** + * e1000_reconfigure_k1_exit_timeout + * @hw: pointer to the HW structure + * + * Reconfigure K1 exit timeout as a workaround to the PHY sycndhronization issue + * on MTL, LNL, PTL and WCL. + * + * Assuming PHY semaphore is taken prior to this function call. + **/ +STATIC s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u32 fextnvm12; + u16 phy_timeout; + + DEBUGFUNC("e1000_reconfigure_k1_exit_timeout"); + + if (hw->mac.type < e1000_pch_mtp) + return E1000_SUCCESS; + + fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12); + fextnvm12 |= (1 << 23); + fextnvm12 &= ~((1 << 22)); + E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12); + + msec_delay_irq(1); + + ret_val = hw->phy.ops.read_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, + &phy_timeout); + phy_timeout &= ~E1000_PHY_TIMEOUTS_K1_EXIT_TO_MASK; + phy_timeout |= 0xF00; + ret_val = hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, + phy_timeout); + + return ret_val; +} + /** * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds * @hw: pointer to the HW structure @@ -332,6 +369,14 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) case e1000_pch_adp: case e1000_pch_mtp: case e1000_pch_ptp: + /* Due to clock synchronization issue on MTL and above prior to + * disabling k1 it is required to disable P0s state and + * reconfigure PHY k1 exit timeout. At this point the PHY might + * be inaccessible so don't propagate the failure. + */ + if (hw->mac.type >= e1000_pch_mtp) + e1000_reconfigure_k1_exit_timeout(hw); + if (e1000_phy_is_accessible_pchlan(hw)) break; @@ -417,6 +462,16 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) ret_val = hw->phy.ops.check_reset_block(hw); if (ret_val) ERROR_REPORT("ME blocked access to PHY after reset\n"); + + if (hw->mac.type >= e1000_pch_mtp) { + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) { + DEBUGOUT("Failed to reconfigure K1 exit timeout\n"); + goto out; + } + ret_val = e1000_reconfigure_k1_exit_timeout(hw); + hw->phy.ops.release(hw); + } } out: @@ -2463,18 +2518,6 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) DEBUGFUNC("e1000_configure_k1_ich8lan"); - /* Due to clock synchronization issue on MTL and above prior to - * disabling k1 it is required to disable P0s state - */ - if ((!k1_enable) && (hw->mac.type >= e1000_pch_mtp)) { - u32 fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12); - fextnvm12 |= (1 << 23); - fextnvm12 &= ~((1 << 22)); - E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12); - - usec_delay(100); - } - ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, &kmrn_reg); if (ret_val) @@ -5086,6 +5129,21 @@ STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) e1000_initialize_hw_bits_ich8lan(hw); + + if (hw->mac.type >= e1000_pch_mtp) { + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + return ret_val; + + ret_val = e1000_reconfigure_k1_exit_timeout(hw); + hw->phy.ops.release(hw); + + if (ret_val) { + DEBUGOUT("Error reconfiguring PHY K1 exit timeout\n"); + return ret_val; + } + } + /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); /* An error is not fatal and we should not stop init due to this */ diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.h b/drivers/net/intel/e1000/base/e1000_ich8lan.h index fbe118723c..f2ba910ea6 100644 --- a/drivers/net/intel/e1000/base/e1000_ich8lan.h +++ b/drivers/net/intel/e1000/base/e1000_ich8lan.h @@ -218,6 +218,10 @@ #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) #define I217_PLL_CLOCK_GATE_MASK 0x07FF +/* PHY Timeouts */ +#define E1000_PHY_TIMEOUTS_REG PHY_REG(770, 21) +#define E1000_PHY_TIMEOUTS_K1_EXIT_TO_MASK 0x0FC0 + #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ /* Inband Control */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] net/e1000: better clock synchronization workaround 2025-06-09 10:16 ` [PATCH v1 1/2] net/e1000: better clock synchronization workaround Anatoly Burakov @ 2025-06-09 16:23 ` Stephen Hemminger 2025-06-12 11:16 ` Burakov, Anatoly 0 siblings, 1 reply; 6+ messages in thread From: Stephen Hemminger @ 2025-06-09 16:23 UTC (permalink / raw) To: Anatoly Burakov; +Cc: dev, Bruce Richardson, Vitaly Lifshits On Mon, 9 Jun 2025 11:16:41 +0100 Anatoly Burakov <anatoly.burakov@intel.com> wrote: > + ret_val = hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, > + phy_timeout); > + > + return ret_val; Why use temporary value (ret_val) and not just a return statement? return hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, phy_timeout); ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] net/e1000: better clock synchronization workaround 2025-06-09 16:23 ` Stephen Hemminger @ 2025-06-12 11:16 ` Burakov, Anatoly 0 siblings, 0 replies; 6+ messages in thread From: Burakov, Anatoly @ 2025-06-12 11:16 UTC (permalink / raw) To: Stephen Hemminger; +Cc: dev, Bruce Richardson, Vitaly Lifshits On 6/9/2025 6:23 PM, Stephen Hemminger wrote: > On Mon, 9 Jun 2025 11:16:41 +0100 > Anatoly Burakov <anatoly.burakov@intel.com> wrote: > >> + ret_val = hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, >> + phy_timeout); >> + >> + return ret_val; > > Why use temporary value (ret_val) and not just a return statement? > > return hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG, phy_timeout); I agree with you, but this is not our code, so we can't modify it too much to avoid maintaining huge deltas with the base code. -- Thanks, Anatoly ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] net/e1000: update README 2025-06-09 10:16 [PATCH v1 0/2] e1000 base code update Anatoly Burakov 2025-06-09 10:16 ` [PATCH v1 1/2] net/e1000: better clock synchronization workaround Anatoly Burakov @ 2025-06-09 10:16 ` Anatoly Burakov 2025-06-09 15:53 ` [PATCH v1 0/2] e1000 base code update Bruce Richardson 2 siblings, 0 replies; 6+ messages in thread From: Anatoly Burakov @ 2025-06-09 10:16 UTC (permalink / raw) To: dev Update the last shared code update date. Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com> --- drivers/net/intel/e1000/base/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/intel/e1000/base/README b/drivers/net/intel/e1000/base/README index 23a6604121..976391b170 100644 --- a/drivers/net/intel/e1000/base/README +++ b/drivers/net/intel/e1000/base/README @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2010-2020 Intel Corporation + * Copyright(c) 2010-2025 Intel Corporation */ This directory contains source code of the base driver code for em/igb/igc, -with this snapshot generated on 2025-01-24-09.44. +with this snapshot generated on 2025-06-04-14.40. This driver is valid for the product(s) listed below * Intel® Ethernet Controller 82540 -- 2.47.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 0/2] e1000 base code update 2025-06-09 10:16 [PATCH v1 0/2] e1000 base code update Anatoly Burakov 2025-06-09 10:16 ` [PATCH v1 1/2] net/e1000: better clock synchronization workaround Anatoly Burakov 2025-06-09 10:16 ` [PATCH v1 2/2] net/e1000: update README Anatoly Burakov @ 2025-06-09 15:53 ` Bruce Richardson 2 siblings, 0 replies; 6+ messages in thread From: Bruce Richardson @ 2025-06-09 15:53 UTC (permalink / raw) To: Anatoly Burakov; +Cc: dev On Mon, Jun 09, 2025 at 11:16:40AM +0100, Anatoly Burakov wrote: > Update e1000 base code version to 2025-06-04-14.40 > > Anatoly Burakov (1): > net/e1000: update README > > Vitaly Lifshits (1): > net/e1000: better clock synchronization workaround > > drivers/net/intel/e1000/base/README | 4 +- > drivers/net/intel/e1000/base/e1000_ich8lan.c | 82 +++++++++++++++++--- > drivers/net/intel/e1000/base/e1000_ich8lan.h | 4 + > 3 files changed, 76 insertions(+), 14 deletions(-) > Series-acked-by: Bruce Richardson <bruce.richardson@intel.com> Applied to dpdk-next-net-intel. Thanks, /Bruce ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-06-12 11:16 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-06-09 10:16 [PATCH v1 0/2] e1000 base code update Anatoly Burakov 2025-06-09 10:16 ` [PATCH v1 1/2] net/e1000: better clock synchronization workaround Anatoly Burakov 2025-06-09 16:23 ` Stephen Hemminger 2025-06-12 11:16 ` Burakov, Anatoly 2025-06-09 10:16 ` [PATCH v1 2/2] net/e1000: update README Anatoly Burakov 2025-06-09 15:53 ` [PATCH v1 0/2] e1000 base code update Bruce Richardson
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