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* [PATCH v2 0/2] Fix LT PHY related SSC writes
@ 2026-07-01  9:15 Suraj Kandpal
  2026-07-01  9:15 ` [PATCH v2 1/2] drm/i915/ltphy: Readout ssc_enabled for LT PHY Suraj Kandpal
                   ` (6 more replies)
  0 siblings, 7 replies; 10+ messages in thread
From: Suraj Kandpal @ 2026-07-01  9:15 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal

Xe3P onwards we only write on SSC Enable PLLA on PORT
CLOCK CTL. Fix this register write. Along with that add
ssc_enabled readout.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (2):
  drm/i915/ltphy: Readout ssc_enabled for LT PHY
  drm/i915/ltphy: Fix SSC Enablement bit in PORT_CLOCK_CTL

 drivers/gpu/drm/i915/display/intel_lt_phy.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2026-07-02  2:51 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-01  9:15 [PATCH v2 0/2] Fix LT PHY related SSC writes Suraj Kandpal
2026-07-01  9:15 ` [PATCH v2 1/2] drm/i915/ltphy: Readout ssc_enabled for LT PHY Suraj Kandpal
2026-07-02  2:51   ` Nautiyal, Ankit K
2026-07-01  9:15 ` [PATCH v2 2/2] drm/i915/ltphy: Fix SSC Enablement bit in PORT_CLOCK_CTL Suraj Kandpal
2026-07-02  2:50   ` Nautiyal, Ankit K
2026-07-01 10:06 ` ✓ CI.KUnit: success for Fix LT PHY related SSC writes (rev2) Patchwork
2026-07-01 11:04 ` ✓ Xe.CI.BAT: " Patchwork
2026-07-01 12:09 ` ✓ i915.CI.BAT: " Patchwork
2026-07-02  0:39 ` ✗ i915.CI.Full: failure " Patchwork
2026-07-02  2:30 ` ✓ Xe.CI.FULL: success " Patchwork

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