* [Intel-gfx] [v4 0/2] Re-enable FBC on TGL
@ 2020-12-01 14:30 Uma Shankar
2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Uma Shankar @ 2020-12-01 14:30 UTC (permalink / raw)
To: intel-gfx
FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.
Bspec: 50422 HSD: 14010260002
v2: Addressed review comments and added bspec links
v3: Addressed Ville's review comments
v4: Change the WA as per Jose's recommendation.
Uma Shankar (2):
drm/i915/display/tgl: Disable FBC with PSR2
Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
drivers/gpu/drm/i915/display/intel_fbc.c | 36 +++++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 30 insertions(+), 7 deletions(-)
--
2.26.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar @ 2020-12-01 14:30 ` Uma Shankar 2020-12-01 15:51 ` Souza, Jose 2020-12-01 14:30 ` [Intel-gfx] [v4 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar ` (3 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Uma Shankar @ 2020-12-01 14:30 UTC (permalink / raw) To: intel-gfx There are some corner cases wrt underrun when we enable FBC with PSR2 on TGL. Recommendation from hardware is to keep this combination disabled. Bspec: 50422 HSD: 14010260002 v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec link and HSD referneces (Jose) v3: Moved the logic to disable fbc to intel_fbc_update_state_cache and removed the crtc->config usages, as per Ville's recommendation. v4: Introduced a variable in fbc state_cache instead of the earlier plane.visible WA, as suggested by Jose. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a5b072816a7b..ff2f2c00a10e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -700,7 +700,21 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, struct intel_fbc_state_cache *cache = &fbc->state_cache; struct drm_framebuffer *fb = plane_state->hw.fb; + if (crtc_state->has_psr2) + cache->psr2_active = true; + else + cache->psr2_active = false; + + /* + * Tigerlake is not supporting FBC with PSR2. + * Recommendation is to keep this combination disabled + * Bspec: 50422 HSD: 14010260002 + */ + if (IS_TIGERLAKE(dev_priv) && cache->psr2_active) + return; + cache->plane.visible = plane_state->uapi.visible; + if (!cache->plane.visible) return; @@ -799,6 +813,16 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) struct intel_fbc *fbc = &dev_priv->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; + /* + * Tigerlake is not supporting FBC with PSR2. + * Recommendation is to keep this combination disabled + * Bspec: 50422 HSD: 14010260002 + */ + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { + fbc->no_fbc_reason = "not supported with PSR2"; + return false; + } + if (!intel_fbc_can_enable(dev_priv)) return false; @@ -1273,6 +1297,11 @@ void intel_fbc_enable(struct intel_atomic_state *state, if (!cache->plane.visible) goto out; + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { + fbc->no_fbc_reason = "not supported with PSR2"; + goto out; + } + if (intel_fbc_alloc_cfb(dev_priv, intel_fbc_calculate_cfb_size(dev_priv, cache), plane_state->hw.fb->format->cpp[0])) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 15be8debae54..f4e08c1a5867 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -416,6 +416,7 @@ struct intel_fbc { u16 gen9_wa_cfb_stride; u16 interval; s8 fence_id; + bool psr2_active; } state_cache; /* -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar @ 2020-12-01 15:51 ` Souza, Jose 2020-12-01 15:55 ` Souza, Jose 0 siblings, 1 reply; 9+ messages in thread From: Souza, Jose @ 2020-12-01 15:51 UTC (permalink / raw) To: Shankar, Uma, intel-gfx@lists.freedesktop.org On Tue, 2020-12-01 at 20:00 +0530, Uma Shankar wrote: > There are some corner cases wrt underrun when we enable > FBC with PSR2 on TGL. Recommendation from hardware is to > keep this combination disabled. > > Bspec: 50422 HSD: 14010260002 > > v2: Added psr2 enabled check from crtc_state (Anshuman) > Added Bspec link and HSD referneces (Jose) > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache > and removed the crtc->config usages, as per Ville's recommendation. > > v4: Introduced a variable in fbc state_cache instead of the earlier > plane.visible WA, as suggested by Jose. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > 2 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index a5b072816a7b..ff2f2c00a10e 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -700,7 +700,21 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, > struct intel_fbc_state_cache *cache = &fbc->state_cache; > struct drm_framebuffer *fb = plane_state->hw.fb; > > > > > + if (crtc_state->has_psr2) > + cache->psr2_active = true; > + else > + cache->psr2_active = false; cache->psr2_active = crtc_state->has_psr2; > + > + /* > + * Tigerlake is not supporting FBC with PSR2. > + * Recommendation is to keep this combination disabled > + * Bspec: 50422 HSD: 14010260002 > + */ > + if (IS_TIGERLAKE(dev_priv) && cache->psr2_active) > + return; Here you should only set psr2_active, add it to the bottom of intel_fbc_update_state_cache. The check should only be done in intel_fbc_can_activate(). > + > cache->plane.visible = plane_state->uapi.visible; > + > if (!cache->plane.visible) > return; > > > > > > > > > @@ -799,6 +813,16 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > struct intel_fbc *fbc = &dev_priv->fbc; > struct intel_fbc_state_cache *cache = &fbc->state_cache; > > > > > > > > > + /* > + * Tigerlake is not supporting FBC with PSR2. > + * Recommendation is to keep this combination disabled > + * Bspec: 50422 HSD: 14010260002 > + */ > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > + fbc->no_fbc_reason = "not supported with PSR2"; > + return false; > + } > + > if (!intel_fbc_can_enable(dev_priv)) > return false; > > > > > > > > > @@ -1273,6 +1297,11 @@ void intel_fbc_enable(struct intel_atomic_state *state, > if (!cache->plane.visible) > goto out; > > > > > > > > > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > + fbc->no_fbc_reason = "not supported with PSR2"; > + goto out; > + } > + > if (intel_fbc_alloc_cfb(dev_priv, > intel_fbc_calculate_cfb_size(dev_priv, cache), > plane_state->hw.fb->format->cpp[0])) { > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 15be8debae54..f4e08c1a5867 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -416,6 +416,7 @@ struct intel_fbc { > u16 gen9_wa_cfb_stride; > u16 interval; > s8 fence_id; > + bool psr2_active; > } state_cache; > > > > > > > > > /* _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 2020-12-01 15:51 ` Souza, Jose @ 2020-12-01 15:55 ` Souza, Jose 2020-12-01 16:00 ` Shankar, Uma 0 siblings, 1 reply; 9+ messages in thread From: Souza, Jose @ 2020-12-01 15:55 UTC (permalink / raw) To: Shankar, Uma, intel-gfx@lists.freedesktop.org On Tue, 2020-12-01 at 07:51 -0800, José Roberto de Souza wrote: > On Tue, 2020-12-01 at 20:00 +0530, Uma Shankar wrote: > > There are some corner cases wrt underrun when we enable > > FBC with PSR2 on TGL. Recommendation from hardware is to > > keep this combination disabled. > > > > Bspec: 50422 HSD: 14010260002 > > > > v2: Added psr2 enabled check from crtc_state (Anshuman) > > Added Bspec link and HSD referneces (Jose) > > > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache > > and removed the crtc->config usages, as per Ville's recommendation. > > > > v4: Introduced a variable in fbc state_cache instead of the earlier > > plane.visible WA, as suggested by Jose. > > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++++++++++++++++ > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > 2 files changed, 30 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index a5b072816a7b..ff2f2c00a10e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -700,7 +700,21 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, > > struct intel_fbc_state_cache *cache = &fbc->state_cache; > > struct drm_framebuffer *fb = plane_state->hw.fb; > > > > > > > > > > + if (crtc_state->has_psr2) > > + cache->psr2_active = true; > > + else > > + cache->psr2_active = false; > > cache->psr2_active = crtc_state->has_psr2; > > > > + > > + /* > > + * Tigerlake is not supporting FBC with PSR2. > > + * Recommendation is to keep this combination disabled > > + * Bspec: 50422 HSD: 14010260002 > > + */ > > + if (IS_TIGERLAKE(dev_priv) && cache->psr2_active) > > + return; > > > Here you should only set psr2_active, add it to the bottom of intel_fbc_update_state_cache. > The check should only be done in intel_fbc_can_activate(). > > > + > > cache->plane.visible = plane_state->uapi.visible; > > + > > if (!cache->plane.visible) > > return; > > > > > > > > > > > > > > > > > > @@ -799,6 +813,16 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > > struct intel_fbc *fbc = &dev_priv->fbc; > > struct intel_fbc_state_cache *cache = &fbc->state_cache; > > > > > > > > > > > > > > > > > > + /* > > + * Tigerlake is not supporting FBC with PSR2. > > + * Recommendation is to keep this combination disabled > > + * Bspec: 50422 HSD: 14010260002 > > + */ > > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > > + fbc->no_fbc_reason = "not supported with PSR2"; > > + return false; > > + } > > + > > if (!intel_fbc_can_enable(dev_priv)) > > return false; > > > > > > > > > > > > > > > > > > @@ -1273,6 +1297,11 @@ void intel_fbc_enable(struct intel_atomic_state *state, > > if (!cache->plane.visible) > > goto out; > > > > > > > > > > > > > > > > > > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > > + fbc->no_fbc_reason = "not supported with PSR2"; > > + goto out; > > + } Also no need to check it here, only in intel_fbc_can_activate. We already allocate the cfb even when other reasons do not allow FBC to be activated. > > + > > if (intel_fbc_alloc_cfb(dev_priv, > > intel_fbc_calculate_cfb_size(dev_priv, cache), > > plane_state->hw.fb->format->cpp[0])) { > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 15be8debae54..f4e08c1a5867 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -416,6 +416,7 @@ struct intel_fbc { > > u16 gen9_wa_cfb_stride; > > u16 interval; > > s8 fence_id; > > + bool psr2_active; > > } state_cache; > > > > > > > > > > > > > > > > > > /* > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 2020-12-01 15:55 ` Souza, Jose @ 2020-12-01 16:00 ` Shankar, Uma 0 siblings, 0 replies; 9+ messages in thread From: Shankar, Uma @ 2020-12-01 16:00 UTC (permalink / raw) To: Souza, Jose, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Souza, Jose <jose.souza@intel.com> > Sent: Tuesday, December 1, 2020 9:25 PM > To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com > Subject: Re: [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 > > On Tue, 2020-12-01 at 07:51 -0800, José Roberto de Souza wrote: > > On Tue, 2020-12-01 at 20:00 +0530, Uma Shankar wrote: > > > There are some corner cases wrt underrun when we enable FBC with > > > PSR2 on TGL. Recommendation from hardware is to keep this > > > combination disabled. > > > > > > Bspec: 50422 HSD: 14010260002 > > > > > > v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec > > > link and HSD referneces (Jose) > > > > > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache > > > and removed the crtc->config usages, as per Ville's recommendation. > > > > > > v4: Introduced a variable in fbc state_cache instead of the earlier > > > plane.visible WA, as suggested by Jose. > > > > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++++++++++++++++ > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > 2 files changed, 30 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index a5b072816a7b..ff2f2c00a10e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -700,7 +700,21 @@ static void intel_fbc_update_state_cache(struct > intel_crtc *crtc, > > > struct intel_fbc_state_cache *cache = &fbc->state_cache; > > > struct drm_framebuffer *fb = plane_state->hw.fb; > > > > > > > > > > > > > > > + if (crtc_state->has_psr2) > > > + cache->psr2_active = true; > > > + else > > > + cache->psr2_active = false; > > > > cache->psr2_active = crtc_state->has_psr2; Yeah sure, will update this. > > > > > + > > > + /* > > > + * Tigerlake is not supporting FBC with PSR2. > > > + * Recommendation is to keep this combination disabled > > > + * Bspec: 50422 HSD: 14010260002 > > > + */ > > > + if (IS_TIGERLAKE(dev_priv) && cache->psr2_active) > > > + return; > > > > > > Here you should only set psr2_active, add it to the bottom of > intel_fbc_update_state_cache. > > The check should only be done in intel_fbc_can_activate(). Ok, I will drop the explicit return here. > > > + > > > cache->plane.visible = plane_state->uapi.visible; > > > + > > > if (!cache->plane.visible) > > > return; > > > > > > > > > > > > > > > > > > > > > > > > > > > @@ -799,6 +813,16 @@ static bool intel_fbc_can_activate(struct intel_crtc > *crtc) > > > struct intel_fbc *fbc = &dev_priv->fbc; > > > struct intel_fbc_state_cache *cache = &fbc->state_cache; > > > > > > > > > > > > > > > > > > > > > > > > > > > + /* > > > + * Tigerlake is not supporting FBC with PSR2. > > > + * Recommendation is to keep this combination disabled > > > + * Bspec: 50422 HSD: 14010260002 > > > + */ > > > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > > > + fbc->no_fbc_reason = "not supported with PSR2"; > > > + return false; > > > + } > > > + > > > if (!intel_fbc_can_enable(dev_priv)) > > > return false; > > > > > > > > > > > > > > > > > > > > > > > > > > > @@ -1273,6 +1297,11 @@ void intel_fbc_enable(struct intel_atomic_state > *state, > > > if (!cache->plane.visible) > > > goto out; > > > > > > > > > > > > > > > > > > > > > > > > > > > + if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { > > > + fbc->no_fbc_reason = "not supported with PSR2"; > > > + goto out; > > > + } > > Also no need to check it here, only in intel_fbc_can_activate. > We already allocate the cfb even when other reasons do not allow FBC to be > activated. Ok got it, will drop the check here as well. Thanks Jose for the feedback, will re-send the next version with updates. Regards, Uma Shankar > > > + > > > if (intel_fbc_alloc_cfb(dev_priv, > > > intel_fbc_calculate_cfb_size(dev_priv, cache), > > > plane_state->hw.fb->format->cpp[0])) { diff --git > > > a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > > index 15be8debae54..f4e08c1a5867 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -416,6 +416,7 @@ struct intel_fbc { > > > u16 gen9_wa_cfb_stride; > > > u16 interval; > > > s8 fence_id; > > > + bool psr2_active; > > > } state_cache; > > > > > > > > > > > > > > > > > > > > > > > > > > > /* > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [v4 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar 2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar @ 2020-12-01 14:30 ` Uma Shankar 2020-12-01 14:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Re-enable FBC on TGL (rev4) Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Uma Shankar @ 2020-12-01 14:30 UTC (permalink / raw) To: intel-gfx FBC can be re-enabled on TGL with WA of keeping it disabled while PSR2 is enabled. This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ff2f2c00a10e..9ac778f425f0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1462,13 +1462,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - /* - * Fbc is causing random underruns in CI execution on TGL platforms. - * Disabling the same while the problem is being debugged and analyzed. - */ - if (IS_TIGERLAKE(dev_priv)) - return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) return 1; -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Re-enable FBC on TGL (rev4) 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar 2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar 2020-12-01 14:30 ` [Intel-gfx] [v4 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar @ 2020-12-01 14:39 ` Patchwork 2020-12-01 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-01 18:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2020-12-01 14:39 UTC (permalink / raw) To: Uma Shankar; +Cc: intel-gfx == Series Details == Series: Re-enable FBC on TGL (rev4) URL : https://patchwork.freedesktop.org/series/83510/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1447:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1501:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL (rev4) 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar ` (2 preceding siblings ...) 2020-12-01 14:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Re-enable FBC on TGL (rev4) Patchwork @ 2020-12-01 15:08 ` Patchwork 2020-12-01 18:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2020-12-01 15:08 UTC (permalink / raw) To: Uma Shankar; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6645 bytes --] == Series Details == Series: Re-enable FBC on TGL (rev4) URL : https://patchwork.freedesktop.org/series/83510/ State : success == Summary == CI Bug Log - changes from CI_DRM_9412 -> Patchwork_19026 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/index.html New tests --------- New tests have been introduced between CI_DRM_9412 and Patchwork_19026: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 40 pass(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_19026 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@reload: - fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-bxt-dsi/igt@i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-bxt-dsi/igt@i915_module_load@reload.html - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [k.org#205379]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-tgl-y/igt@i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-tgl-y/igt@i915_module_load@reload.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt@kms_frontbuffer_tracking@basic: - fi-kbl-soraka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#165]) +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-tgl-y/igt@prime_vgem@basic-read.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-tgl-y/igt@prime_vgem@basic-read.html #### Possible fixes #### * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html * igt@i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-byt-j1900/igt@i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-byt-j1900/igt@i915_module_load@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-n3050: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html - fi-tgl-y: [DMESG-WARN][19] ([i915#1982] / [i915#2411]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-snb-2520m: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-snb-2520m/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-snb-2520m/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt@vgem_basic@dmabuf-export: - fi-tgl-y: [DMESG-WARN][25] ([i915#402]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/fi-tgl-y/igt@vgem_basic@dmabuf-export.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/fi-tgl-y/igt@vgem_basic@dmabuf-export.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379 Participating hosts (45 -> 41) ------------------------------ Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes ------------- * Linux: CI_DRM_9412 -> Patchwork_19026 CI-20190529: 20190529 CI_DRM_9412: 62a57fc697819341ffabadc2b734f2288fdf19ce @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5877: c36f7973d1ee7886ec65fa16c7b1fd8dc5a33caa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19026: 4c8806b5e83bf82221aa6942b34b848b4c7eafd6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4c8806b5e83b Revert "drm/i915/display/fbc: Disable fbc by default on TGL" 5ed2151ae73d drm/i915/display/tgl: Disable FBC with PSR2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/index.html [-- Attachment #1.2: Type: text/html, Size: 8272 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Re-enable FBC on TGL (rev4) 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar ` (3 preceding siblings ...) 2020-12-01 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-12-01 18:36 ` Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2020-12-01 18:36 UTC (permalink / raw) To: Uma Shankar; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 18763 bytes --] == Series Details == Series: Re-enable FBC on TGL (rev4) URL : https://patchwork.freedesktop.org/series/83510/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9412_full -> Patchwork_19026_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_19026_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19026_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_19026_full: ### IGT changes ### #### Possible regressions #### * igt@i915_pm_sseu@full-enable: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl6/igt@i915_pm_sseu@full-enable.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl9/igt@i915_pm_sseu@full-enable.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@gem_userptr_blits@huge-split}: - shard-snb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-snb6/igt@gem_userptr_blits@huge-split.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-snb6/igt@gem_userptr_blits@huge-split.html New tests --------- New tests have been introduced between CI_DRM_9412_full and Patchwork_19026_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_19026_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#2389]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-hsw6/igt@gem_exec_reloc@basic-many-active@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-hsw2/igt@gem_exec_reloc@basic-many-active@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][7] -> [SKIP][8] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-tglb2/igt@gem_huc_copy@huc-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-tglb6/igt@gem_huc_copy@huc-copy.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-random: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html * igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-hsw2/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-hsw1/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][17] -> [FAIL][18] ([i915#2370]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-tglb7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-tglb5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl9/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-apl7/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-apl7/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-kbl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-kbl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#1188]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982] / [i915#533]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109642] / [fdo#111068]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb4/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html #### Possible fixes #### * igt@i915_module_load@reload: - shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +5 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl9/igt@i915_module_load@reload.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl1/igt@i915_module_load@reload.html * igt@i915_selftest@live@gt_heartbeat: - shard-glk: [DMESG-FAIL][41] ([i915#2291]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk4/igt@i915_selftest@live@gt_heartbeat.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk2/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-kbl3/igt@i915_suspend@debugfs-reader.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-kbl6/igt@i915_suspend@debugfs-reader.html * {igt@kms_async_flips@alternate-sync-async-flip}: - shard-tglb: [FAIL][45] ([i915#2521]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-tglb1/igt@kms_async_flips@alternate-sync-async-flip.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-tglb5/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-random: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - shard-kbl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-kbl6/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-kbl1/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-glk: [FAIL][51] ([i915#2346]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk2/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html - shard-apl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-apl7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-apl4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html - shard-iclb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb3/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [FAIL][59] ([i915#2598]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][63] ([i915#1188]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_psr@psr2_suspend: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb1/igt@kms_psr@psr2_suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb2/igt@kms_psr@psr2_suspend.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][67] ([i915#2681] / [i915#2684]) -> [WARN][68] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][69] ([i915#2684]) -> [WARN][70] ([i915#1804] / [i915#2684]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-skl: [FAIL][71] ([i915#2346]) -> [DMESG-FAIL][72] ([i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt@runner@aborted: - shard-glk: ([FAIL][73], [FAIL][74], [FAIL][75]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2722] / [k.org#202321]) -> ([FAIL][76], [FAIL][77], [FAIL][78]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2722] / [i915#483] / [k.org#202321]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk4/igt@runner@aborted.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk5/igt@runner@aborted.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-glk8/igt@runner@aborted.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk5/igt@runner@aborted.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk9/igt@runner@aborted.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-glk3/igt@runner@aborted.html - shard-skl: [FAIL][79] ([i915#2295] / [i915#2722]) -> ([FAIL][80], [FAIL][81]) ([i915#1436] / [i915#2295] / [i915#2426] / [i915#2722]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9412/shard-skl1/igt@runner@aborted.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl3/igt@runner@aborted.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/shard-skl8/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_9412 -> Patchwork_19026 CI-20190529: 20190529 CI_DRM_9412: 62a57fc697819341ffabadc2b734f2288fdf19ce @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5877: c36f7973d1ee7886ec65fa16c7b1fd8dc5a33caa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19026: 4c8806b5e83bf82221aa6942b34b848b4c7eafd6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19026/index.html [-- Attachment #1.2: Type: text/html, Size: 22721 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-12-01 18:36 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar 2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar 2020-12-01 15:51 ` Souza, Jose 2020-12-01 15:55 ` Souza, Jose 2020-12-01 16:00 ` Shankar, Uma 2020-12-01 14:30 ` [Intel-gfx] [v4 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar 2020-12-01 14:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Re-enable FBC on TGL (rev4) Patchwork 2020-12-01 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-01 18:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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