* [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller
@ 2025-06-19 7:58 dongxuyang
2025-06-19 8:00 ` [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: dongxuyang @ 2025-06-19 7:58 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: ningyu, linmin, huangyifeng, Xuyang Dong
From: Xuyang Dong <dongxuyang@eswincomputing.com>
There are some register offsets in reset dt-bindings. It could be used.
Therefore, we want to keep these bindings. I don't known if it meets
the requirements.
PIPE_RST_CTRL, TBU_RST_CTRL and TEST_RST_CTRL are not used in this
driver. Therefore, these are left out.
Updates:
dt-bindings: reset: eswin: Documentation for eic7700 SoC
v2 -> v3:
1. Drop syscon and simple-mfd from yaml and code, because these are
not necessary.
2. Update description to introduce reset controller.
3. Add reset control indices for dt-bindings.
4. Keep the register offsets in dt-bindings.
v1 -> v2:
1. Clear warnings/errors for using "make dt_binding_check".
2. Update example, change parent node from sys-crg to reset-controller
for reset yaml.
3. Drop the child node and add '#reset-cells' to the parent node.
4. Drop the description, because sys-crg block is changed to reset-
controller.
5. Change hex numbers to decimal numbers going from 0, and drop the
not needed hardware numbers.
reset: eswin: Add eic7700 reset driver
v2 -> v3:
1. Change syscon_node_to_regmap() to MMIO regmap functions, because
droped syscon.
2. Add BIT() in function eswin_reset_set() to shift the reset
control indices.
3. Remove forced type conversions from function eswin_reset_of_
xlate_lookup_id().
v1 -> v2:
1. Modify the code according to the suggestions.
2. Use eswin_reset_assert() and eswin_reset_deassert in function
eswin_reset_reset().
3. Place RESET_EIC7700 in Kconfig and Makefile in order.
4. Use dev_err_probe() in probe function.
Xuyang Dong (2):
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: eswin: Add eic7700 reset driver
.../bindings/reset/eswin,eic7700-reset.yaml | 42 ++
drivers/reset/Kconfig | 10 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-eic7700.c | 243 +++++++++
.../dt-bindings/reset/eswin,eic7700-reset.h | 460 ++++++++++++++++++
5 files changed, 756 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
create mode 100644 drivers/reset/reset-eic7700.c
create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC
2025-06-19 7:58 [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang
@ 2025-06-19 8:00 ` dongxuyang
2025-06-19 17:39 ` Krzysztof Kozlowski
2025-06-19 8:01 ` [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver dongxuyang
2025-06-19 17:40 ` [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski
2 siblings, 1 reply; 6+ messages in thread
From: dongxuyang @ 2025-06-19 8:00 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: ningyu, linmin, huangyifeng, Xuyang Dong
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add device tree binding documentation and header file for the ESWIN
eic7700 reset controller module.
Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
.../bindings/reset/eswin,eic7700-reset.yaml | 42 ++
.../dt-bindings/reset/eswin,eic7700-reset.h | 460 ++++++++++++++++++
2 files changed, 502 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
diff --git a/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
new file mode 100644
index 000000000000..b844a9c5a169
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 SoC reset controller
+
+maintainers:
+ - Yifeng Huang <huangyifeng@eswincomputing.com>
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+ The system reset controller can be used to reset various peripheral
+ controllers in ESWIN eic7700 SoC.
+
+properties:
+ compatible:
+ const: eswin,eic7700-reset
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/eswin,eic7700-reset.h>
+
+ reset-controller@51828000 {
+ compatible = "eswin,eic7700-reset";
+ reg = <0x51828000 0x80000>;
+ #reset-cells = <2>;
+ };
diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h
new file mode 100644
index 000000000000..8c3aa3c87ea4
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-reset.h
@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 reset controller.
+ *
+ * Authors:
+ * Yifeng Huang <huangyifeng@eswincomputing.com>
+ * Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef __DT_ESWIN_EIC7700_RESET_H__
+#define __DT_ESWIN_EIC7700_RESET_H__
+
+#define SNOC_RST_CTRL 0
+#define GPU_RST_CTRL 1
+#define DSP_RST_CTRL 2
+#define D2D_RST_CTRL 3
+#define DDR_RST_CTRL 4
+#define TCU_RST_CTRL 5
+#define NPU_RST_CTRL 6
+#define HSPDMA_RST_CTRL 7
+#define PCIE_RST_CTRL 8
+#define I2C_RST_CTRL 9
+#define FAN_RST_CTRL 10
+#define PVT_RST_CTRL 11
+#define MBOX_RST_CTRL 12
+#define UART_RST_CTRL 13
+#define GPIO_RST_CTRL 14
+#define TIMER_RST_CTRL 15
+#define SSI_RST_CTRL 16
+#define WDT_RST_CTRL 17
+#define LSP_CFGRST_CTRL 18
+#define U84_RST_CTRL 19
+#define SCPU_RST_CTRL 20
+#define LPCPU_RST_CTRL 21
+#define VC_RST_CTRL 22
+#define JD_RST_CTRL 23
+#define JE_RST_CTRL 24
+#define VD_RST_CTRL 25
+#define VE_RST_CTRL 26
+#define G2D_RST_CTRL 27
+#define VI_RST_CTRL 28
+#define DVP_RST_CTRL 29
+#define ISP0_RST_CTRL 30
+#define ISP1_RST_CTRL 31
+#define SHUTTER_RST_CTRL 32
+#define VO_PHYRST_CTRL 33
+#define VO_I2SRST_CTRL 34
+#define VO_RST_CTRL 35
+#define BOOTSPI_RST_CTRL 36
+#define I2C1_RST_CTRL 37
+#define I2C0_RST_CTRL 38
+#define DMA1_RST_CTRL 39
+#define FPRT_RST_CTRL 40
+#define HBLOCK_RST_CTRL 41
+#define SECSR_RST_CTRL 42
+#define OTP_RST_CTRL 43
+#define PKA_RST_CTRL 44
+#define SPACC_RST_CTRL 45
+#define TRNG_RST_CTRL 46
+#define RESERVED 47
+#define TIMER0_RST_CTRL 48
+#define TIMER1_RST_CTRL 49
+#define TIMER2_RST_CTRL 50
+#define TIMER3_RST_CTRL 51
+#define RTC_RST_CTRL 52
+#define MNOC_RST_CTRL 53
+#define RNOC_RST_CTRL 54
+#define CNOC_RST_CTRL 55
+#define LNOC_RST_CTRL 56
+
+/*
+ * CONSUMER RESET CONTROL BIT
+ */
+/*SNOC*/
+#define SW_NOC_NSP_RSTN 0
+#define SW_NOC_CFG_RSTN 1
+#define SW_RNOC_NSP_RSTN 2
+#define SW_SNOC_TCU_ARSTN 3
+#define SW_SNOC_U84_ARSTN 4
+#define SW_SNOC_PCIET_XSRSTN 5
+#define SW_SNOC_PCIET_XMRSTN 6
+#define SW_SNOC_PCIET_PRSTN 7
+#define SW_SNOC_NPU_ARSTN 8
+#define SW_SNOC_JTAG_ARSTN 9
+#define SW_SNOC_DSPT_ARSTN 10
+#define SW_SNOC_DDRC1_P2_ARSTN 11
+#define SW_SNOC_DDRC1_P1_ARSTN 12
+#define SW_SNOC_DDRC0_P2_ARSTN 13
+#define SW_SNOC_DDRC0_P1_ARSTN 14
+#define SW_SNOC_D2D_ARSTN 15
+#define SW_SNOC_AON_ARSTN 16
+
+/*GPU*/
+#define SW_GPU_AXI_RSTN 0
+#define SW_GPU_CFG_RSTN 1
+#define SW_GPU_GRAY_RSTN 2
+#define SW_GPU_JONES_RSTN 3
+#define SW_GPU_SPU_RSTN 4
+
+/*DSP*/
+#define SW_DSP_AXI_RSTN 0
+#define SW_DSP_CFG_RSTN 1
+#define SW_DSP_DIV4_RSTN 2
+#define SW_DSP_DIV_RSTN_0 4
+#define SW_DSP_DIV_RSTN_1 5
+#define SW_DSP_DIV_RSTN_2 6
+#define SW_DSP_DIV_RSTN_3 7
+
+/*D2D*/
+#define SW_D2D_AXI_RSTN 0
+#define SW_D2D_CFG_RSTN 1
+#define SW_D2D_PRST_N 2
+#define SW_D2D_RAW_PCS_RST_N 4
+#define SW_D2D_RX_RST_N 5
+#define SW_D2D_TX_RST_N 6
+#define SW_D2D_CORE_RST_N 7
+
+/*TCU*/
+#define SW_TCU_AXI_RSTN 0
+#define SW_TCU_CFG_RSTN 1
+#define TBU_RSTN_0 4
+#define TBU_RSTN_1 5
+#define TBU_RSTN_2 6
+#define TBU_RSTN_3 7
+#define TBU_RSTN_4 8
+#define TBU_RSTN_5 9
+#define TBU_RSTN_6 10
+#define TBU_RSTN_7 11
+#define TBU_RSTN_8 12
+#define TBU_RSTN_9 13
+#define TBU_RSTN_10 14
+#define TBU_RSTN_11 15
+#define TBU_RSTN_12 16
+#define TBU_RSTN_13 17
+#define TBU_RSTN_14 18
+#define TBU_RSTN_15 19
+#define TBU_RSTN_16 20
+
+/*NPU*/
+#define SW_NPU_AXI_RSTN 0
+#define SW_NPU_CFG_RSTN 1
+#define SW_NPU_CORE_RSTN 2
+#define SW_NPU_E31CORE_RSTN 3
+#define SW_NPU_E31BUS_RSTN 4
+#define SW_NPU_E31DBG_RSTN 5
+#define SW_NPU_LLC_RSTN 6
+
+/*HSP DMA*/
+#define SW_HSP_AXI_RSTN 0
+#define SW_HSP_CFG_RSTN 1
+#define SW_HSP_POR_RSTN 2
+#define SW_MSHC0_PHY_RSTN 3
+#define SW_MSHC1_PHY_RSTN 4
+#define SW_MSHC2_PHY_RSTN 5
+#define SW_MSHC0_TXRX_RSTN 6
+#define SW_MSHC1_TXRX_RSTN 7
+#define SW_MSHC2_TXRX_RSTN 8
+#define SW_SATA_ASIC0_RSTN 9
+#define SW_SATA_OOB_RSTN 10
+#define SW_SATA_PMALIVE_RSTN 11
+#define SW_SATA_RBC_RSTN 12
+#define SW_DMA0_RST_N 13
+#define SW_HSP_DMA0_RSTN 14
+#define SW_USB0_VAUX_RSTN 15
+#define SW_USB1_VAUX_RSTN 16
+#define SW_HSP_SD1_PRSTN 17
+#define SW_HSP_SD0_PRSTN 18
+#define SW_HSP_EMMC_PRSTN 19
+#define SW_HSP_DMA_PRSTN 20
+#define SW_HSP_SD1_ARSTN 21
+#define SW_HSP_SD0_ARSTN 22
+#define SW_HSP_EMMC_ARSTN 23
+#define SW_HSP_DMA_ARSTN 24
+#define SW_HSP_ETH1_ARSTN 25
+#define SW_HSP_ETH0_ARSTN 26
+#define SW_HSP_SATA_ARSTN 27
+
+/*PCIE*/
+#define SW_PCIE_CFG_RSTN 0
+#define SW_PCIE_POWERUP_RSTN 1
+#define SW_PCIE_PERST_N 2
+
+/*I2C*/
+#define SW_I2C_RST_N_0 0
+#define SW_I2C_RST_N_1 1
+#define SW_I2C_RST_N_2 2
+#define SW_I2C_RST_N_3 3
+#define SW_I2C_RST_N_4 4
+#define SW_I2C_RST_N_5 5
+#define SW_I2C_RST_N_6 6
+#define SW_I2C_RST_N_7 7
+#define SW_I2C_RST_N_8 8
+#define SW_I2C_RST_N_9 9
+
+/*FAN*/
+#define SW_FAN_RST_N 0
+
+/*PVT*/
+#define SW_PVT_RST_N_0 0
+#define SW_PVT_RST_N_1 1
+
+/*MBOX*/
+#define SW_MBOX_RST_N_0 0
+#define SW_MBOX_RST_N_1 1
+#define SW_MBOX_RST_N_2 2
+#define SW_MBOX_RST_N_3 3
+#define SW_MBOX_RST_N_4 4
+#define SW_MBOX_RST_N_5 5
+#define SW_MBOX_RST_N_6 6
+#define SW_MBOX_RST_N_7 7
+#define SW_MBOX_RST_N_8 8
+#define SW_MBOX_RST_N_9 9
+#define SW_MBOX_RST_N_10 10
+#define SW_MBOX_RST_N_11 11
+#define SW_MBOX_RST_N_12 12
+#define SW_MBOX_RST_N_13 13
+#define SW_MBOX_RST_N_14 14
+#define SW_MBOX_RST_N_15 15
+
+/*UART*/
+#define SW_UART_RST_N_0 0
+#define SW_UART_RST_N_1 1
+#define SW_UART_RST_N_2 2
+#define SW_UART_RST_N_3 3
+#define SW_UART_RST_N_4 4
+
+/*GPIO*/
+#define SW_GPIO_RST_N_0 0
+#define SW_GPIO_RST_N_1 1
+
+/*TIMER*/
+#define SW_TIMER_RST_N 0
+
+/*SSI*/
+#define SW_SSI_RST_N_0 0
+#define SW_SSI_RST_N_1 1
+
+/*WDT*/
+#define SW_WDT_RST_N_0 0
+#define SW_WDT_RST_N_1 1
+#define SW_WDT_RST_N_2 2
+#define SW_WDT_RST_N_3 3
+
+/*LSP CFG*/
+#define SW_LSP_CFG_RSTN 0
+
+/*U84 CFG*/
+#define SW_U84_CORE_RSTN_0 0
+#define SW_U84_CORE_RSTN_1 1
+#define SW_U84_CORE_RSTN_2 2
+#define SW_U84_CORE_RSTN_3 3
+#define SW_U84_BUS_RSTN 4
+#define SW_U84_DBG_RSTN 5
+#define SW_U84_TRACECOM_RSTN 6
+#define SW_U84_TRACE_RSTN_0 8
+#define SW_U84_TRACE_RSTN_1 9
+#define SW_U84_TRACE_RSTN_2 10
+#define SW_U84_TRACE_RSTN_3 11
+
+/*SCPU*/
+#define SW_SCPU_CORE_RSTN 0
+#define SW_SCPU_BUS_RSTN 1
+#define SW_SCPU_DBG_RSTN 2
+
+/*LPCPU*/
+#define SW_LPCPU_CORE_RSTN 0
+#define SW_LPCPU_BUS_RSTN 1
+#define SW_LPCPU_DBG_RSTN 2
+
+/*VC*/
+#define SW_VC_CFG_RSTN 0
+#define SW_VC_AXI_RSTN 1
+#define SW_VC_MONCFG_RSTN 2
+
+/*JD*/
+#define SW_JD_CFG_RSTN 0
+#define SW_JD_AXI_RSTN 1
+
+/*JE*/
+#define SW_JE_CFG_RSTN 0
+#define SW_JE_AXI_RSTN 1
+
+/*VD*/
+#define SW_VD_CFG_RSTN 0
+#define SW_VD_AXI_RSTN 1
+
+/*VE*/
+#define SW_VE_AXI_RSTN 0
+#define SW_VE_CFG_RSTN 1
+
+/*G2D*/
+#define SW_G2D_CORE_RSTN 0
+#define SW_G2D_CFG_RSTN 1
+#define SW_G2D_AXI_RSTN 2
+
+/*VI*/
+#define SW_VI_AXI_RSTN 0
+#define SW_VI_CFG_RSTN 1
+#define SW_VI_DWE_RSTN 2
+
+/*DVP*/
+#define SW_VI_DVP_RSTN 0
+
+/*ISP0*/
+#define SW_VI_ISP0_RSTN 0
+
+/*ISP1*/
+#define SW_VI_ISP1_RSTN 0
+
+/*SHUTTR*/
+#define SW_VI_SHUTTER_RSTN_0 0
+#define SW_VI_SHUTTER_RSTN_1 1
+#define SW_VI_SHUTTER_RSTN_2 2
+#define SW_VI_SHUTTER_RSTN_3 3
+#define SW_VI_SHUTTER_RSTN_4 4
+#define SW_VI_SHUTTER_RSTN_5 5
+
+/*VO PHY*/
+#define SW_VO_MIPI_PRSTN 0
+#define SW_VO_PRSTN 1
+#define SW_VO_HDMI_PRSTN 3
+#define SW_HDMI_PHYCTRL_RSTN 4
+#define SW_VO_HDMI_RSTN 5
+
+/*VO I2S*/
+#define SW_VO_I2S_RSTN 0
+#define SW_VO_I2S_PRSTN 1
+
+/*VO*/
+#define SW_VO_AXI_RSTN 0
+#define SW_VO_CFG_RSTN 1
+#define SW_VO_DC_RSTN 2
+#define SW_VO_DC_PRSTN 3
+
+/*BOOTSPI*/
+#define SW_BOOTSPI_HRSTN 0
+#define SW_BOOTSPI_RSTN 1
+
+/*I2C1*/
+#define SW_I2C1_PRSTN 0
+
+/*I2C0*/
+#define SW_I2C0_PRSTN 0
+
+/*DMA1*/
+#define SW_DMA1_ARSTN 0
+#define SW_DMA1_HRSTN 1
+
+/*FPRT*/
+#define SW_FP_PRT_HRSTN 0
+
+/*HBLOCK*/
+#define SW_HBLOCK_HRSTN 0
+
+/*SECSR*/
+#define SW_SECSR_HRSTN 0
+
+/*OTP*/
+#define SW_OTP_PRSTN 0
+
+/*PKA*/
+#define SW_PKA_HRSTN 0
+
+/*SPACC*/
+#define SW_SPACC_RSTN 0
+
+/*TRNG*/
+#define SW_TRNG_HRSTN 0
+
+/*TIMER0*/
+#define SW_TIMER0_RSTN_0 0
+#define SW_TIMER0_RSTN_1 1
+#define SW_TIMER0_RSTN_2 2
+#define SW_TIMER0_RSTN_3 3
+#define SW_TIMER0_RSTN_4 4
+#define SW_TIMER0_RSTN_5 5
+#define SW_TIMER0_RSTN_6 6
+#define SW_TIMER0_RSTN_7 7
+#define SW_TIMER0_PRSTN 8
+
+/*TIMER1*/
+#define SW_TIMER1_RSTN_0 0
+#define SW_TIMER1_RSTN_1 1
+#define SW_TIMER1_RSTN_2 2
+#define SW_TIMER1_RSTN_3 3
+#define SW_TIMER1_RSTN_4 4
+#define SW_TIMER1_RSTN_5 5
+#define SW_TIMER1_RSTN_6 6
+#define SW_TIMER1_RSTN_7 7
+#define SW_TIMER1_PRSTN 8
+
+/*TIMER2*/
+#define SW_TIMER2_RSTN_0 0
+#define SW_TIMER2_RSTN_1 1
+#define SW_TIMER2_RSTN_2 2
+#define SW_TIMER2_RSTN_3 3
+#define SW_TIMER2_RSTN_4 4
+#define SW_TIMER2_RSTN_5 5
+#define SW_TIMER2_RSTN_6 6
+#define SW_TIMER2_RSTN_7 7
+#define SW_TIMER2_PRSTN 8
+
+/*TIMER3*/
+#define SW_TIMER3_RSTN_0 0
+#define SW_TIMER3_RSTN_1 1
+#define SW_TIMER3_RSTN_2 2
+#define SW_TIMER3_RSTN_3 3
+#define SW_TIMER3_RSTN_4 4
+#define SW_TIMER3_RSTN_5 5
+#define SW_TIMER3_RSTN_6 6
+#define SW_TIMER3_RSTN_7 7
+#define SW_TIMER3_PRSTN 8
+
+/*RTC*/
+#define SW_RTC_RSTN 0
+
+/*MNOC*/
+#define SW_MNOC_SNOC_NSP_RSTN 0
+#define SW_MNOC_VC_ARSTN 1
+#define SW_MNOC_CFG_RSTN 2
+#define SW_MNOC_HSP_ARSTN 3
+#define SW_MNOC_GPU_ARSTN 4
+#define SW_MNOC_DDRC1_P3_ARSTN 5
+#define SW_MNOC_DDRC0_P3_ARSTN 6
+
+/*RNOC*/
+#define SW_RNOC_VO_ARSTN 0
+#define SW_RNOC_VI_ARSTN 1
+#define SW_RNOC_SNOC_NSP_RSTN 2
+#define SW_RNOC_CFG_RSTN 3
+#define SW_MNOC_DDRC1_P4_ARSTN 4
+#define SW_MNOC_DDRC0_P4_ARSTN 5
+
+/*CNOC*/
+#define SW_CNOC_VO_CFG_RSTN 0
+#define SW_CNOC_VI_CFG_RSTN 1
+#define SW_CNOC_VC_CFG_RSTN 2
+#define SW_CNOC_TCU_CFG_RSTN 3
+#define SW_CNOC_PCIET_CFG_RSTN 4
+#define SW_CNOC_NPU_CFG_RSTN 5
+#define SW_CNOC_LSP_CFG_RSTN 6
+#define SW_CNOC_HSP_CFG_RSTN 7
+#define SW_CNOC_GPU_CFG_RSTN 8
+#define SW_CNOC_DSPT_CFG_RSTN 9
+#define SW_CNOC_DDRT1_CFG_RSTN 10
+#define SW_CNOC_DDRT0_CFG_RSTN 11
+#define SW_CNOC_D2D_CFG_RSTN 12
+#define SW_CNOC_CFG_RSTN 13
+#define SW_CNOC_CLMM_CFG_RSTN 14
+#define SW_CNOC_AON_CFG_RSTN 15
+
+/*LNOC*/
+#define SW_LNOC_CFG_RSTN 0
+#define SW_LNOC_NPU_LLC_ARSTN 1
+#define SW_LNOC_DDRC1_P0_ARSTN 2
+#define SW_LNOC_DDRC0_P0_ARSTN 3
+
+#endif /*endif __DT_ESWIN_EIC7700_RESET_H__*/
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver
2025-06-19 7:58 [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang
2025-06-19 8:00 ` [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
@ 2025-06-19 8:01 ` dongxuyang
2025-06-19 17:41 ` Krzysztof Kozlowski
2025-06-19 17:40 ` [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski
2 siblings, 1 reply; 6+ messages in thread
From: dongxuyang @ 2025-06-19 8:01 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: ningyu, linmin, huangyifeng, Xuyang Dong
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add support for reset controller in eic7700 series chips.
Provide functionality for asserting and deasserting resets
on the chip.
Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-eic7700.c | 243 ++++++++++++++++++++++++++++++++++
3 files changed, 254 insertions(+)
create mode 100644 drivers/reset/reset-eic7700.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d85be5899da6..82f829f4c9f0 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -66,6 +66,16 @@ config RESET_BRCMSTB_RESCAL
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
BCM7216.
+config RESET_EIC7700
+ bool "Reset controller driver for ESWIN SoCs"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ default ARCH_ESWIN
+ help
+ This enables the reset controller driver for ESWIN SoCs. This driver is
+ specific to ESWIN SoCs and should only be enabled if using such hardware.
+ The driver supports eic7700 series chips and provides functionality for
+ asserting and deasserting resets on the chip.
+
config RESET_EYEQ
bool "Mobileye EyeQ reset controller"
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 91e6348e3351..ceafbad0555c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
+obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
diff --git a/drivers/reset/reset-eic7700.c b/drivers/reset/reset-eic7700.c
new file mode 100644
index 000000000000..61513746c06c
--- /dev/null
+++ b/drivers/reset/reset-eic7700.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ *
+ * ESWIN Reset Driver
+ *
+ * Authors:
+ * Yifeng Huang <huangyifeng@eswincomputing.com>
+ * Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0x30C
+#define CLEAR_BOOT_FLAG_BIT BIT(0)
+#define SYSCRG_RESET_OFFSET 0x400
+
+/**
+ * struct eswin_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @dev: reset controller device pointer
+ * @idr: idr structure for mapping ids to reset control structures
+ * @regmap: reset controller device register map
+ */
+struct eswin_reset_data {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct idr idr;
+ struct regmap *regmap;
+};
+
+/**
+ * struct eswin_reset_control - reset control structure
+ * @dev_id: SoC-specific device identifier
+ * @reset_bit: reset mask to use for toggling reset
+ */
+struct eswin_reset_control {
+ u32 dev_id;
+ u32 reset_bit;
+};
+
+static const struct regmap_config eswin_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .max_register = 0x8000000,
+};
+
+#define to_eswin_reset_data(p) container_of((p), struct eswin_reset_data, rcdev)
+
+/**
+ * eswin_reset_set() - program a device's reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to toggle
+ * @assert: boolean flag to indicate assert or deassert
+ *
+ * This is a common internal function used to assert or deassert a device's
+ * reset by clear and set the reset bit. The device's reset is asserted if the
+ * @assert argument is true, or deasserted if @assert argument is false.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned long id,
+ bool assert)
+{
+ struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+ struct eswin_reset_control *control;
+ int ret;
+
+ control = idr_find(&data->idr, id);
+
+ if (!control)
+ return -EINVAL;
+
+ if (assert)
+ ret = regmap_clear_bits(data->regmap, SYSCRG_RESET_OFFSET +
+ control->dev_id * sizeof(u32),
+ BIT(control->reset_bit));
+ else
+ ret = regmap_set_bits(data->regmap, SYSCRG_RESET_OFFSET +
+ control->dev_id * sizeof(u32),
+ BIT(control->reset_bit));
+
+ return ret;
+}
+
+static int eswin_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return eswin_reset_set(rcdev, id, true);
+}
+
+static int eswin_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return eswin_reset_set(rcdev, id, false);
+}
+
+static int eswin_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = eswin_reset_assert(rcdev, id);
+ if (ret != 0)
+ return ret;
+
+ usleep_range(10, 15);
+ ret = eswin_reset_deassert(rcdev, id);
+ if (ret != 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct reset_control_ops eswin_reset_ops = {
+ .reset = eswin_reset_reset,
+ .assert = eswin_reset_assert,
+ .deassert = eswin_reset_deassert,
+};
+
+static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data)
+{
+ struct of_phandle_args *reset_spec = data;
+ struct eswin_reset_control *slot_control = p;
+
+ if (reset_spec->args[0] == slot_control->dev_id &&
+ reset_spec->args[1] == slot_control->reset_bit)
+ return id;
+
+ return 0;
+}
+
+/**
+ * eswin_reset_of_xlate() - translate a set of OF arguments to a reset ID
+ * @rcdev: reset controller entity
+ * @reset_spec: OF reset argument specifier
+ *
+ * This function performs the translation of the reset argument specifier
+ * values defined in a reset consumer device node. The function allocates a
+ * reset control structure for that device reset, and will be used by the
+ * driver for performing any reset functions on that reset. An idr structure
+ * is allocated and used to map to the reset control structure. This idr
+ * is used by the driver to do reset lookups.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_of_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+ struct eswin_reset_control *control;
+ int ret;
+
+ if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+ return -EINVAL;
+
+ ret = idr_for_each(&data->idr, eswin_reset_of_xlate_lookup_id,
+ (void *)reset_spec);
+ if (ret)
+ return ret;
+
+ control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
+ if (!control)
+ return -ENOMEM;
+
+ control->dev_id = reset_spec->args[0];
+ control->reset_bit = reset_spec->args[1];
+
+ return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
+}
+
+static const struct of_device_id eswin_reset_dt_ids[] = {
+ {
+ .compatible = "eswin,eic7700-reset",
+ },
+ { /* sentinel */ }
+};
+
+static int eswin_reset_probe(struct platform_device *pdev)
+{
+ struct eswin_reset_data *data;
+ struct device *dev = &pdev->dev;
+ void __iomem *base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ data->regmap = devm_regmap_init_mmio(dev, base, &eswin_regmap_config);
+ if (IS_ERR(data->regmap))
+ return dev_err_probe(dev, PTR_ERR(data->regmap), "failed to get regmap!\n");
+
+ platform_set_drvdata(pdev, data);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &eswin_reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+ data->rcdev.of_reset_n_cells = 2;
+ data->rcdev.of_xlate = eswin_reset_of_xlate;
+ data->rcdev.dev = &pdev->dev;
+ data->dev = &pdev->dev;
+ idr_init(&data->idr);
+
+ /* clear boot flag so u84 and scpu could be reseted by software */
+ regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
+ CLEAR_BOOT_FLAG_BIT);
+ msleep(50);
+
+ return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+
+static void eswin_reset_remove(struct platform_device *pdev)
+{
+ struct eswin_reset_data *data = platform_get_drvdata(pdev);
+
+ idr_destroy(&data->idr);
+}
+
+static struct platform_driver eswin_reset_driver = {
+ .probe = eswin_reset_probe,
+ .remove = eswin_reset_remove,
+ .driver = {
+ .name = "eswin-reset",
+ .of_match_table = eswin_reset_dt_ids,
+ },
+};
+
+static int __init eswin_reset_init(void)
+{
+ return platform_driver_register(&eswin_reset_driver);
+}
+arch_initcall(eswin_reset_init);
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC
2025-06-19 8:00 ` [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
@ 2025-06-19 17:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-19 17:39 UTC (permalink / raw)
To: dongxuyang, p.zabel, robh, krzk+dt, conor+dt, devicetree,
linux-kernel
Cc: ningyu, linmin, huangyifeng
On 19/06/2025 10:00, dongxuyang@eswincomputing.com wrote:
> +
> + reg:
> + maxItems: 1
> +
> + '#reset-cells':
> + const: 2
What is the meaning of the cells?
> +
> +required:
> + - compatible
> + - reg
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/eswin,eic7700-reset.h>
> +
> + reset-controller@51828000 {
> + compatible = "eswin,eic7700-reset";
> + reg = <0x51828000 0x80000>;
> + #reset-cells = <2>;
> + };
> diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h
> new file mode 100644
> index 000000000000..8c3aa3c87ea4
> --- /dev/null
> +++ b/include/dt-bindings/reset/eswin,eic7700-reset.h
> @@ -0,0 +1,460 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
2025
> + *
> + * Device Tree binding constants for EIC7700 reset controller.
> + *
> + * Authors:
> + * Yifeng Huang <huangyifeng@eswincomputing.com>
> + * Xuyang Dong <dongxuyang@eswincomputing.com>
> + */
> +
> +#ifndef __DT_ESWIN_EIC7700_RESET_H__
> +#define __DT_ESWIN_EIC7700_RESET_H__
> +
> +#define SNOC_RST_CTRL 0
> +#define GPU_RST_CTRL 1
> +#define DSP_RST_CTRL 2
> +#define D2D_RST_CTRL 3
> +#define DDR_RST_CTRL 4
> +#define TCU_RST_CTRL 5
> +#define NPU_RST_CTRL 6
> +#define HSPDMA_RST_CTRL 7
> +#define PCIE_RST_CTRL 8
> +#define I2C_RST_CTRL 9
> +#define FAN_RST_CTRL 10
> +#define PVT_RST_CTRL 11
> +#define MBOX_RST_CTRL 12
> +#define UART_RST_CTRL 13
...
> +
> +/*TIMER1*/
> +#define SW_TIMER1_RSTN_0 0
> +#define SW_TIMER1_RSTN_1 1
> +#define SW_TIMER1_RSTN_2 2
> +#define SW_TIMER1_RSTN_3 3
> +#define SW_TIMER1_RSTN_4 4
> +#define SW_TIMER1_RSTN_5 5
> +#define SW_TIMER1_RSTN_6 6
> +#define SW_TIMER1_RSTN_7 7
> +#define SW_TIMER1_PRSTN 8
> +
> +/*TIMER2*/
> +#define SW_TIMER2_RSTN_0 0
> +#define SW_TIMER2_RSTN_1 1
> +#define SW_TIMER2_RSTN_2 2
> +#define SW_TIMER2_RSTN_3 3
> +#define SW_TIMER2_RSTN_4 4
> +#define SW_TIMER2_RSTN_5 5
> +#define SW_TIMER2_RSTN_6 6
> +#define SW_TIMER2_RSTN_7 7
> +#define SW_TIMER2_PRSTN 8
That's unreadable - missing indent before the value. Ids equal to block
number are not useful anyway.
The problem is: you still do not use this as an ABI. No driver usage at
all and (comment which I repeat very often) no point to add it to the
bindings. Look at other bindings how this is supposed to look like.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller
2025-06-19 7:58 [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang
2025-06-19 8:00 ` [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
2025-06-19 8:01 ` [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver dongxuyang
@ 2025-06-19 17:40 ` Krzysztof Kozlowski
2 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-19 17:40 UTC (permalink / raw)
To: dongxuyang, p.zabel, robh, krzk+dt, conor+dt, devicetree,
linux-kernel
Cc: ningyu, linmin, huangyifeng
On 19/06/2025 09:58, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
>
> There are some register offsets in reset dt-bindings. It could be used.
> Therefore, we want to keep these bindings. I don't known if it meets
> the requirements.
>
> PIPE_RST_CTRL, TBU_RST_CTRL and TEST_RST_CTRL are not used in this
> driver. Therefore, these are left out.
>
> Updates:
>
> dt-bindings: reset: eswin: Documentation for eic7700 SoC
> v2 -> v3:
> 1. Drop syscon and simple-mfd from yaml and code, because these are
> not necessary.
> 2. Update description to introduce reset controller.
> 3. Add reset control indices for dt-bindings.
> 4. Keep the register offsets in dt-bindings.
No, drop. Register offsets are not bindings. That was last comment, so
don't keep them. Remove them.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver
2025-06-19 8:01 ` [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver dongxuyang
@ 2025-06-19 17:41 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-19 17:41 UTC (permalink / raw)
To: dongxuyang, p.zabel, robh, krzk+dt, conor+dt, devicetree,
linux-kernel
Cc: ningyu, linmin, huangyifeng
On 19/06/2025 10:01, dongxuyang@eswincomputing.com wrote:
> +
> +static const struct reset_control_ops eswin_reset_ops = {
> + .reset = eswin_reset_reset,
> + .assert = eswin_reset_assert,
> + .deassert = eswin_reset_deassert,
> +};
> +
> +static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data)
> +{
> + struct of_phandle_args *reset_spec = data;
Still wrong cast.
What is the type? You got exactly that question. How did you resolve it?
> + struct eswin_reset_control *slot_control = p;
> +
> + if (reset_spec->args[0] == slot_control->dev_id &&
> + reset_spec->args[1] == slot_control->reset_bit)
> + return id;
> +
> + return 0;
> +}
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-06-19 17:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-19 7:58 [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang
2025-06-19 8:00 ` [PATCH v3 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
2025-06-19 17:39 ` Krzysztof Kozlowski
2025-06-19 8:01 ` [PATCH v3 2/2] reset: eswin: Add eic7700 reset driver dongxuyang
2025-06-19 17:41 ` Krzysztof Kozlowski
2025-06-19 17:40 ` [PATCH v3 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.