* [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-05-07 8:37 ` Chee, Tien Fong
2026-04-28 3:48 ` [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes alif.zakuan.yuslaimi
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Migrate the legacy Stratix10 platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.
This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 158 +++++++
arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------------
.../dts/socfpga_stratix10_socdk-u-boot.dtsi | 143 +++++-
arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ------
configs/socfpga_stratix10_defconfig | 3 +-
6 files changed, 286 insertions(+), 594 deletions(-)
delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bff341d6118..2832123218f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_vining_fpga.dtb \
socfpga_cyclone5_ac501soc.dtb \
socfpga_cyclone5_ac550soc.dtb \
- socfpga_n5x_socdk.dtb \
- socfpga_stratix10_socdk.dtb
+ socfpga_n5x_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index 3e3a3780469..a3b4c0564f9 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -3,6 +3,164 @@
* U-Boot additions
*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ i2c0 = &i2c1;
+ freeze_br0 = &freeze_controller;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ bootph-all;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ };
+
+ soc@0 {
+ bootph-all;
+
+ freeze_controller: freeze_controller@f9000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0xf9000450 0x00000010>;
+ status = "disabled";
+ };
+ };
+};
+
+&clkmgr {
+ bootph-all;
+};
+
+&gmac0 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
+ clock-names = "stmmaceth";
+ /* PHY delays is configured via skew properties */
+ phy-mode = "rgmii";
+ max-frame-size = <3800>;
+ status = "okay";
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&gmac1 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+};
+
+&gmac2 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+ status = "okay";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+ fifo-mode;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ bootph-all;
+ compatible = "cdns,qspi-nor";
+ flash0: flash@0 {
+ };
+};
+
+&flash0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x20>;
+ bootph-all;
+};
+
+&sdr {
+ compatible = "altr,sdr-ctl-s10";
+ reg = <0xf8000400 0x80>,
+ <0xf8010000 0x190>,
+ <0xf8011000 0x500>;
+ resets = <&rst DDRSCH_RESET>;
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <100000000>;
+};
+
+&watchdog0 {
+ bootph-all;
+};
+
+&usb0 {
+ compatible = "snps,dwc2";
+};
+
+&usb1 {
+ compatible = "snps,dwc2";
+};
+
+&spi0 {
+ compatible = "intel,stratix10-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+};
+
+&spi1 {
+ compatible = "intel,stratix10-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+};
+
+&binman {
+ /delete-node/ kernel;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
deleted file mode 100644
index ea80d1bed15..00000000000
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ /dev/null
@@ -1,430 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2018 Intel Corporation
- */
-
-/dts-v1/;
-#include <dt-bindings/reset/altr,rst-mgr-s10.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "altr,socfpga-stratix10";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x1>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x2>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x3>;
- };
- };
-
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <0 120 8>,
- <0 121 8>,
- <0 122 8>,
- <0 123 8>;
- interrupt-affinity = <&cpu0>,
- <&cpu1>,
- <&cpu2>,
- <&cpu3>;
- interrupt-parent = <&intc>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- intc: intc@fffc1000 {
- compatible = "arm,gic-400", "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x0 0xfffc1000 0x0 0x1000>,
- <0x0 0xfffc2000 0x0 0x2000>,
- <0x0 0xfffc4000 0x0 0x2000>,
- <0x0 0xfffc6000 0x0 0x2000>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- device_type = "soc";
- interrupt-parent = <&intc>;
- ranges = <0 0 0 0xffffffff>;
- bootph-all;
-
- clkmgr: clkmgr@ffd10000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd10000 0x1000>;
- };
-
- gmac0: ethernet@ff800000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
- reg = <0xff800000 0x2000>;
- interrupts = <0 90 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
- reset-names = "stmmaceth";
- altr,sysmgr-syscon = <&sysmgr 0x44 0>;
- status = "disabled";
- };
-
- gmac1: ethernet@ff802000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
- reg = <0xff802000 0x2000>;
- interrupts = <0 91 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
- reset-names = "stmmaceth";
- altr,sysmgr-syscon = <&sysmgr 0x48 0>;
- status = "disabled";
- };
-
- gmac2: ethernet@ff804000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
- reg = <0xff804000 0x2000>;
- interrupts = <0 92 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
- reset-names = "stmmaceth";
- altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
- status = "disabled";
- };
-
- gpio0: gpio@ffc03200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dw-apb-gpio";
- reg = <0xffc03200 0x100>;
- resets = <&rst GPIO0_RESET>;
- status = "disabled";
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <24>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 110 4>;
- bank-name = "porta";
- };
- };
-
- gpio1: gpio@ffc03300 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dw-apb-gpio";
- reg = <0xffc03300 0x100>;
- resets = <&rst GPIO1_RESET>;
- status = "disabled";
-
- portb: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <24>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 111 4>;
- bank-name = "portb";
- };
- };
-
- i2c0: i2c@ffc02800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc02800 0x100>;
- interrupts = <0 103 4>;
- resets = <&rst I2C0_RESET>;
- reset-names = "i2c";
- status = "disabled";
- };
-
- i2c1: i2c@ffc02900 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc02900 0x100>;
- interrupts = <0 104 4>;
- resets = <&rst I2C1_RESET>;
- reset-names = "i2c";
- status = "disabled";
- };
-
- i2c2: i2c@ffc02a00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc02a00 0x100>;
- interrupts = <0 105 4>;
- resets = <&rst I2C2_RESET>;
- reset-names = "i2c";
- status = "disabled";
- };
-
- i2c3: i2c@ffc02b00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc02b00 0x100>;
- interrupts = <0 106 4>;
- resets = <&rst I2C3_RESET>;
- reset-names = "i2c";
- status = "disabled";
- };
-
- i2c4: i2c@ffc02c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc02c00 0x100>;
- interrupts = <0 107 4>;
- resets = <&rst I2C4_RESET>;
- reset-names = "i2c";
- status = "disabled";
- };
-
- mmc: dwmmc0@ff808000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "altr,socfpga-dw-mshc";
- reg = <0xff808000 0x1000>;
- interrupts = <0 96 4>;
- fifo-depth = <0x400>;
- resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
- bootph-all;
- status = "disabled";
- };
-
- nand: nand@ffb90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "altr,socfpga-denali-nand";
- reg = <0xffb90000 0x10000>,
- <0xffb80000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- interrupts = <0 97 4>;
- resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
- status = "disabled";
- };
-
- ocram: sram@ffe00000 {
- compatible = "mmio-sram";
- reg = <0xffe00000 0x100000>;
- };
-
- qspi: spi@ff8d2000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xff8d2000 0x100>,
- <0xff900000 0x100000>;
- interrupts = <0 3 4>;
- cdns,fifo-depth = <128>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x00000000>;
- status = "disabled";
- };
-
- rst: rstmgr@ffd11000 {
- #reset-cells = <1>;
- compatible = "altr,rst-mgr";
- reg = <0xffd11000 0x1000>;
- altr,modrst-offset = <0x20>;
- bootph-all;
- };
-
- sdr: sdr@f8000400 {
- compatible = "altr,sdr-ctl-s10";
- reg = <0xf8000400 0x80>,
- <0xf8010000 0x190>,
- <0xf8011000 0x500>;
- resets = <&rst DDRSCH_RESET>;
- bootph-all;
- };
-
- spi0: spi@ffda4000 {
- compatible = "intel,stratix10-spi",
- "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xffda4000 0x1000>;
- interrupts = <0 99 4>;
- resets = <&rst SPIM0_RESET>;
- reg-io-width = <4>;
- num-chipselect = <4>;
- bus-num = <0>;
- status = "disabled";
- };
-
- spi1: spi@ffda5000 {
- compatible = "intel,stratix10-spi",
- "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xffda5000 0x1000>;
- interrupts = <0 100 4>;
- resets = <&rst SPIM1_RESET>;
- reg-io-width = <4>;
- num-chipselect = <4>;
- bus-num = <0>;
- status = "disabled";
- };
-
- sysmgr: sysmgr@ffd12000 {
- compatible = "altr,sys-mgr", "syscon";
- reg = <0xffd12000 0x1000>;
- };
-
- /* Local timer */
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- };
-
- timer0: timer0@ffc03000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 113 4>;
- reg = <0xffc03000 0x100>;
- };
-
- timer1: timer1@ffc03100 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 114 4>;
- reg = <0xffc03100 0x100>;
- };
-
- timer2: timer2@ffd00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 115 4>;
- reg = <0xffd00000 0x100>;
- };
-
- timer3: timer3@ffd00100 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 116 4>;
- reg = <0xffd00100 0x100>;
- };
-
- uart0: serial0@ffc02000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc02000 0x100>;
- interrupts = <0 108 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- resets = <&rst UART0_RESET>;
- clock-frequency = <100000000>;
- bootph-all;
- status = "disabled";
- };
-
- uart1: serial1@ffc02100 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc02100 0x100>;
- interrupts = <0 109 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- resets = <&rst UART1_RESET>;
- status = "disabled";
- };
-
- usbphy0: usbphy@0 {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- status = "okay";
- };
-
- usb0: usb@ffb00000 {
- compatible = "snps,dwc2";
- reg = <0xffb00000 0x40000>;
- interrupts = <0 93 4>;
- phys = <&usbphy0>;
- phy-names = "usb2-phy";
- resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
- reset-names = "dwc2", "dwc2-ecc";
- status = "disabled";
- };
-
- usb1: usb@ffb40000 {
- compatible = "snps,dwc2";
- reg = <0xffb40000 0x40000>;
- interrupts = <0 94 4>;
- phys = <&usbphy0>;
- phy-names = "usb2-phy";
- resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
- reset-names = "dwc2", "dwc2-ecc";
- status = "disabled";
- };
-
- watchdog0: watchdog@ffd00200 {
- compatible = "snps,dw-wdt";
- reg = <0xffd00200 0x100>;
- interrupts = <0 117 4>;
- resets = <&rst WATCHDOG0_RESET>;
- status = "disabled";
- };
-
- watchdog1: watchdog@ffd00300 {
- compatible = "snps,dw-wdt";
- reg = <0xffd00300 0x100>;
- interrupts = <0 118 4>;
- resets = <&rst WATCHDOG1_RESET>;
- status = "disabled";
- };
-
- watchdog2: watchdog@ffd00400 {
- compatible = "snps,dw-wdt";
- reg = <0xffd00400 0x100>;
- interrupts = <0 125 4>;
- resets = <&rst WATCHDOG2_RESET>;
- status = "disabled";
- };
-
- watchdog3: watchdog@ffd00500 {
- compatible = "snps,dw-wdt";
- reg = <0xffd00500 0x100>;
- interrupts = <0 126 4>;
- resets = <&rst WATCHDOG3_RESET>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index ef0df769762..da19943ec3b 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -3,47 +3,154 @@
* U-Boot additions
*
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*/
#include "socfpga_stratix10-u-boot.dtsi"
/{
- aliases {
- spi0 = &qspi;
- freeze_br0 = &freeze_controller;
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,&nand;
};
- soc {
- freeze_controller: freeze_controller@f9000450 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0xf9000450 0x00000010>;
- status = "disabled";
+ memory@0 {
+ /* 4GB */
+ reg = <0 0x00000000 0 0x80000000>,
+ <1 0x80000000 0 0x80000000>;
+ };
+};
+
+&qspi {
+ status = "okay";
+};
+
+&gmac0 {
+ mdio0 {
+ ethernet_phy0: ethernet-phy@0 {
+ reg = <4>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
};
};
};
-&clkmgr {
+&mmc {
+ drvsel = <3>;
+ smplsel = <2>;
bootph-all;
};
&qspi {
- status = "okay";
- bootph-all;
+ /delete-property/ clocks;
};
&flash0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <100000000>;
+ reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ /delete-property/ cdns,read-delay;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0BE00000>;
+ };
+ };
};
-&sysmgr {
- bootph-all;
+&fdt_0_blob {
+ filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dtb";
};
-&watchdog0 {
- status = "okay";
- bootph-all;
+&images {
+ fdt-1 {
+ description = "socfpga_socdk_nand";
+ type = "flat_dt";
+ compression = "none";
+ fdt_1_blob: blob-ext {
+ filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dtb";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-2 {
+ description = "socfpga_socdk_emmc";
+ type = "flat_dt";
+ compression = "none";
+ fdt_2_blob: blob-ext {
+ filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_emmc.dtb";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+};
+
+&board_config {
+ board-1 {
+ description = "board_1";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt-1";
+ signature {
+ algo = "crc32";
+ key-name-hint = "dev";
+ sign-images = "atf", "uboot", "fdt-1";
+ };
+ };
+
+ board-2 {
+ description = "board_2";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt-2";
+ signature {
+ algo = "crc32";
+ key-name-hint = "dev";
+ sign-images = "atf", "uboot", "fdt-2";
+ };
+ };
+
+ board-4 {
+ description = "board_4";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ signature {
+ algo = "crc32";
+ key-name-hint = "dev";
+ sign-images = "atf", "uboot", "fdt-0";
+ };
+ };
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
deleted file mode 100644
index 864f4093ef8..00000000000
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ /dev/null
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2018 Intel Corporation
- */
-
-#include "socfpga_stratix10.dtsi"
-
-/ {
- model = "SoCFPGA Stratix 10 SoCDK";
-
- aliases {
- ethernet0 = &gmac0;
- i2c0 = &i2c1;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- hps0 {
- label = "hps_led0";
- gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
- };
-
- hps1 {
- label = "hps_led1";
- gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
- };
-
- hps2 {
- label = "hps_led2";
- gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory {
- #address-cells = <2>;
- #size-cells = <2>;
- device_type = "memory";
- /* 4GB */
- reg = <0 0x00000000 0 0x80000000>,
- <1 0x80000000 0 0x80000000>;
- bootph-all;
- };
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
-
- max-frame-size = <3800>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <4>;
-
- txd0-skew-ps = <0>; /* -420ps */
- txd1-skew-ps = <0>; /* -420ps */
- txd2-skew-ps = <0>; /* -420ps */
- txd3-skew-ps = <0>; /* -420ps */
- rxd0-skew-ps = <420>; /* 0ps */
- rxd1-skew-ps = <420>; /* 0ps */
- rxd2-skew-ps = <420>; /* 0ps */
- rxd3-skew-ps = <420>; /* 0ps */
- txen-skew-ps = <0>; /* -420ps */
- txc-skew-ps = <900>; /* 0ps */
- rxdv-skew-ps = <420>; /* 0ps */
- rxc-skew-ps = <1680>; /* 780ps */
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&mmc {
- status = "okay";
- cap-sd-highspeed;
- cap-mmc-highspeed;
- broken-cd;
- bus-width = <4>;
- drvsel = <3>;
- smplsel = <2>;
-};
-
-&qspi {
- flash0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q00a";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
- cdns,read-delay = <1>;
- cdns,tshsl-ns = <50>;
- cdns,tsd2d-ns = <50>;
- cdns,tchsh-ns = <4>;
- cdns,tslch-ns = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qspi_boot: partition@0 {
- label = "Boot and fpga data";
- reg = <0x0 0x4000000>;
- };
-
- qspi_rootfs: partition@4000000 {
- label = "Root Filesystem - JFFS2";
- reg = <0x4000000 0x4000000>;
- };
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&watchdog0 {
- status = "okay";
-};
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index e360048078c..ef21dc92493 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -10,7 +10,8 @@ CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="altera/socfpga_stratix10_socdk"
+CONFIG_OF_UPSTREAM=y
CONFIG_DM_RESET=y
CONFIG_SPL_STACK=0xffe3f000
CONFIG_SPL_TEXT_BASE=0xFFE00000
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config
2026-04-28 3:48 ` [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config alif.zakuan.yuslaimi
@ 2026-05-07 8:37 ` Chee, Tien Fong
2026-05-14 5:35 ` Yuslaimi, Alif Zakuan
0 siblings, 1 reply; 19+ messages in thread
From: Chee, Tien Fong @ 2026-05-07 8:37 UTC (permalink / raw)
To: alif.zakuan.yuslaimi, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Alif,
On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>
> Migrate the legacy Stratix10 platform to use the upstream Linux device tree
> configuration. This helps reduce maintenance overhead and aligns U-Boot
> with the Linux kernel's DTS hierarchy and naming conventions.
>
> This change improves consistency between U-Boot and Linux by removing
> custom/legacy DTS handling and instead relying on the standardized
> definitions provided by the upstream Linux DTS.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
> ---
Please add the change log for each version.
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 158 +++++++
> arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------------
> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 143 +++++-
> arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ------
> configs/socfpga_stratix10_defconfig | 3 +-
> 6 files changed, 286 insertions(+), 594 deletions(-)
> delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
> delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index bff341d6118..2832123218f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
> socfpga_cyclone5_vining_fpga.dtb \
> socfpga_cyclone5_ac501soc.dtb \
> socfpga_cyclone5_ac550soc.dtb \
> - socfpga_n5x_socdk.dtb \
> - socfpga_stratix10_socdk.dtb
> + socfpga_n5x_socdk.dtb
>
> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> index 3e3a3780469..a3b4c0564f9 100644
> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> @@ -3,6 +3,164 @@
> * U-Boot additions
> *
> * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> */
>
> #include "socfpga_soc64_fit-u-boot.dtsi"
> +
> +/{
> + aliases {
> + spi0 = &qspi;
> + i2c0 = &i2c1;
> + freeze_br0 = &freeze_controller;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + #address-cells = <2>;
> + #size-cells = <2>;
make dtbs_check (Linux dt-validate) will flag it as a schema violation
since memory nodes must not define #address-cells / #size-cells because
no child node according to the dt spec.
Remove both properties from the memory@0
[...]
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> index ef0df769762..da19943ec3b 100644
> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -3,47 +3,154 @@
> * U-Boot additions
> *
> * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> */
>
> #include "socfpga_stratix10-u-boot.dtsi"
>
> /{
> - aliases {
> - spi0 = &qspi;
> - freeze_br0 = &freeze_controller;
> + chosen {
> + stdout-path = "serial0:115200n8";
> + u-boot,spl-boot-order = &mmc,&flash0,&nand;
> };
>
> - soc {
> - freeze_controller: freeze_controller@f9000450 {
> - compatible = "altr,freeze-bridge-controller";
> - reg = <0xf9000450 0x00000010>;
> - status = "disabled";
> + memory@0 {
> + /* 4GB */
> + reg = <0 0x00000000 0 0x80000000>,
> + <1 0x80000000 0 0x80000000>;
> + };
> +};
> +
> +&qspi {
> + status = "okay";
> +};
> +
> +&gmac0 {
> + mdio0 {
> + ethernet_phy0: ethernet-phy@0 {
> + reg = <4>;
> + txd0-skew-ps = <0>; /* -420ps */
> + txd1-skew-ps = <0>; /* -420ps */
> + txd2-skew-ps = <0>; /* -420ps */
> + txd3-skew-ps = <0>; /* -420ps */
> + rxd0-skew-ps = <420>; /* 0ps */
> + rxd1-skew-ps = <420>; /* 0ps */
> + rxd2-skew-ps = <420>; /* 0ps */
> + rxd3-skew-ps = <420>; /* 0ps */
> + txen-skew-ps = <0>; /* -420ps */
> + txc-skew-ps = <900>; /* 0ps */
> + rxdv-skew-ps = <420>; /* 0ps */
> + rxc-skew-ps = <1680>; /* 780ps */
> };
> };
> };
>
> -&clkmgr {
> +&mmc {
> + drvsel = <3>;
> + smplsel = <2>;
> bootph-all;
> };
>
> &qspi {
> - status = "okay";
> - bootph-all;
> + /delete-property/ clocks;
> };
>
> &flash0 {
> - compatible = "jedec,spi-nor";
> - spi-max-frequency = <100000000>;
> + reg = <0>;
> spi-tx-bus-width = <4>;
> spi-rx-bus-width = <4>;
> bootph-all;
> +
> + m25p,fast-read;
> + cdns,page-size = <256>;
> + cdns,block-size = <16>;
> + cdns,tshsl-ns = <50>;
> + cdns,tsd2d-ns = <50>;
> + cdns,tchsh-ns = <4>;
> + cdns,tslch-ns = <4>;
> + /delete-property/ cdns,read-delay;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qspi_boot: partition@0 {
> + label = "u-boot";
> + reg = <0x0 0x04200000>;
> + };
> +
> + root: partition@4200000 {
> + label = "root";
> + reg = <0x04200000 0x0BE00000>;
> + };
> + };
> };
>
> -&sysmgr {
> - bootph-all;
> +&fdt_0_blob {
> + filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dtb";
> };
>
> -&watchdog0 {
> - status = "okay";
> - bootph-all;
> +&images {
> + fdt-1 {
> + description = "socfpga_socdk_nand";
> + type = "flat_dt";
> + compression = "none";
> + fdt_1_blob: blob-ext {
> + filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dtb";
> + };
> + hash {
> + algo = "crc32";
> + };
> + };
> +
> + fdt-2 {
> + description = "socfpga_socdk_emmc";
> + type = "flat_dt";
> + compression = "none";
> + fdt_2_blob: blob-ext {
> + filename = "dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_emmc.dtb";
This file is absent. Binman references
dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_emmc.dtb.
If those source DTS files do not exist in the upstream tree, binman
fails with a file-not-found error at image build time
Best regards,
Tien Fong
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config
2026-05-07 8:37 ` Chee, Tien Fong
@ 2026-05-14 5:35 ` Yuslaimi, Alif Zakuan
2026-05-14 6:45 ` Yuslaimi, Alif Zakuan
0 siblings, 1 reply; 19+ messages in thread
From: Yuslaimi, Alif Zakuan @ 2026-05-14 5:35 UTC (permalink / raw)
To: Chee, Tien Fong, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Tien Fong,
On 7/5/2026 4:37 pm, Chee, Tien Fong wrote:
> Hi Alif,
>
>
> On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>
>> Migrate the legacy Stratix10 platform to use the upstream Linux device
>> tree
>> configuration. This helps reduce maintenance overhead and aligns U-Boot
>> with the Linux kernel's DTS hierarchy and naming conventions.
>>
>> This change improves consistency between U-Boot and Linux by removing
>> custom/legacy DTS handling and instead relying on the standardized
>> definitions provided by the upstream Linux DTS.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>> ---
>
>
> Please add the change log for each version.
>
>
Noted, I will add change log for related patches in v3.
>> arch/arm/dts/Makefile | 3 +-
>> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 158 +++++++
>> arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------------
>> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 143 +++++-
>> arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ------
>> configs/socfpga_stratix10_defconfig | 3 +-
>> 6 files changed, 286 insertions(+), 594 deletions(-)
>> delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
>> delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index bff341d6118..2832123218f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
>> socfpga_cyclone5_vining_fpga.dtb \
>> socfpga_cyclone5_ac501soc.dtb \
>> socfpga_cyclone5_ac550soc.dtb \
>> - socfpga_n5x_socdk.dtb \
>> - socfpga_stratix10_socdk.dtb
>> + socfpga_n5x_socdk.dtb
>> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
>> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
>> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/
>> dts/socfpga_stratix10-u-boot.dtsi
>> index 3e3a3780469..a3b4c0564f9 100644
>> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>> @@ -3,6 +3,164 @@
>> * U-Boot additions
>> *
>> * Copyright (C) 2020 Intel Corporation <www.intel.com>
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> */
>> #include "socfpga_soc64_fit-u-boot.dtsi"
>> +
>> +/{
>> + aliases {
>> + spi0 = &qspi;
>> + i2c0 = &i2c1;
>> + freeze_br0 = &freeze_controller;
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
>
> make dtbs_check (Linux dt-validate) will flag it as a schema violation
> since memory nodes must not define #address-cells / #size-cells because
> no child node according to the dt spec.
>
> Remove both properties from the memory@0
>
> [...]
>
>
Removing these properties will result in boot failure in SPL during DDR
init.
fdtdec_decode_ram_size() in lib/fdtdec.c applied #cells to the wrong DT
node, triggering libfdt’s default #size-cells = 1, which misparses reg
encoded for #size-cells = <2> which is the way to describe 64-bit
physical addresses and sizes ≥ 4 GiB for Stratix10.
Refer commit - 90c08fa038451d6d7b7d8711bfd829b61d64c490
>> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/
>> arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>> index ef0df769762..da19943ec3b 100644
>> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>> @@ -3,47 +3,154 @@
>> * U-Boot additions
>> *
>> * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> */
>> #include "socfpga_stratix10-u-boot.dtsi"
>> /{
>> - aliases {
>> - spi0 = &qspi;
>> - freeze_br0 = &freeze_controller;
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + u-boot,spl-boot-order = &mmc,&flash0,&nand;
>> };
>> - soc {
>> - freeze_controller: freeze_controller@f9000450 {
>> - compatible = "altr,freeze-bridge-controller";
>> - reg = <0xf9000450 0x00000010>;
>> - status = "disabled";
>> + memory@0 {
>> + /* 4GB */
>> + reg = <0 0x00000000 0 0x80000000>,
>> + <1 0x80000000 0 0x80000000>;
>> + };
>> +};
>> +
>> +&qspi {
>> + status = "okay";
>> +};
>> +
>> +&gmac0 {
>> + mdio0 {
>> + ethernet_phy0: ethernet-phy@0 {
>> + reg = <4>;
>> + txd0-skew-ps = <0>; /* -420ps */
>> + txd1-skew-ps = <0>; /* -420ps */
>> + txd2-skew-ps = <0>; /* -420ps */
>> + txd3-skew-ps = <0>; /* -420ps */
>> + rxd0-skew-ps = <420>; /* 0ps */
>> + rxd1-skew-ps = <420>; /* 0ps */
>> + rxd2-skew-ps = <420>; /* 0ps */
>> + rxd3-skew-ps = <420>; /* 0ps */
>> + txen-skew-ps = <0>; /* -420ps */
>> + txc-skew-ps = <900>; /* 0ps */
>> + rxdv-skew-ps = <420>; /* 0ps */
>> + rxc-skew-ps = <1680>; /* 780ps */
>> };
>> };
>> };
>> -&clkmgr {
>> +&mmc {
>> + drvsel = <3>;
>> + smplsel = <2>;
>> bootph-all;
>> };
>> &qspi {
>> - status = "okay";
>> - bootph-all;
>> + /delete-property/ clocks;
>> };
>> &flash0 {
>> - compatible = "jedec,spi-nor";
>> - spi-max-frequency = <100000000>;
>> + reg = <0>;
>> spi-tx-bus-width = <4>;
>> spi-rx-bus-width = <4>;
>> bootph-all;
>> +
>> + m25p,fast-read;
>> + cdns,page-size = <256>;
>> + cdns,block-size = <16>;
>> + cdns,tshsl-ns = <50>;
>> + cdns,tsd2d-ns = <50>;
>> + cdns,tchsh-ns = <4>;
>> + cdns,tslch-ns = <4>;
>> + /delete-property/ cdns,read-delay;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + qspi_boot: partition@0 {
>> + label = "u-boot";
>> + reg = <0x0 0x04200000>;
>> + };
>> +
>> + root: partition@4200000 {
>> + label = "root";
>> + reg = <0x04200000 0x0BE00000>;
>> + };
>> + };
>> };
>> -&sysmgr {
>> - bootph-all;
>> +&fdt_0_blob {
>> + filename = "dts/upstream/src/arm64/altera/
>> socfpga_stratix10_socdk.dtb";
>> };
>> -&watchdog0 {
>> - status = "okay";
>> - bootph-all;
>> +&images {
>> + fdt-1 {
>> + description = "socfpga_socdk_nand";
>> + type = "flat_dt";
>> + compression = "none";
>> + fdt_1_blob: blob-ext {
>> + filename = "dts/upstream/src/arm64/altera/
>> socfpga_stratix10_socdk_nand.dtb";
>> + };
>> + hash {
>> + algo = "crc32";
>> + };
>> + };
>> +
>> + fdt-2 {
>> + description = "socfpga_socdk_emmc";
>> + type = "flat_dt";
>> + compression = "none";
>> + fdt_2_blob: blob-ext {
>> + filename = "dts/upstream/src/arm64/altera/
>> socfpga_stratix10_socdk_emmc.dtb";
>
>
> This file is absent. Binman references dts/upstream/src/arm64/altera/
> socfpga_stratix10_socdk_emmc.dtb.
>
> If those source DTS files do not exist in the upstream tree, binman
> fails with a file-not-found error at image build time
>
>
> Best regards,
>
> Tien Fong
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config
2026-05-14 5:35 ` Yuslaimi, Alif Zakuan
@ 2026-05-14 6:45 ` Yuslaimi, Alif Zakuan
0 siblings, 0 replies; 19+ messages in thread
From: Yuslaimi, Alif Zakuan @ 2026-05-14 6:45 UTC (permalink / raw)
To: Chee, Tien Fong, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
On 14/5/2026 1:35 pm, Yuslaimi, Alif Zakuan wrote:
> Hi Tien Fong,
>
> On 7/5/2026 4:37 pm, Chee, Tien Fong wrote:
>> Hi Alif,
>>
>>
>> On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
>>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>>
>>> Migrate the legacy Stratix10 platform to use the upstream Linux
>>> device tree
>>> configuration. This helps reduce maintenance overhead and aligns U-Boot
>>> with the Linux kernel's DTS hierarchy and naming conventions.
>>>
>>> This change improves consistency between U-Boot and Linux by removing
>>> custom/legacy DTS handling and instead relying on the standardized
>>> definitions provided by the upstream Linux DTS.
>>>
>>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>> ---
>>
>>
>> Please add the change log for each version.
>>
>>
> Noted, I will add change log for related patches in v3.
>
>>> arch/arm/dts/Makefile | 3 +-
>>> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 158 +++++++
>>> arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------------
>>> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 143 +++++-
>>> arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ------
>>> configs/socfpga_stratix10_defconfig | 3 +-
>>> 6 files changed, 286 insertions(+), 594 deletions(-)
>>> delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
>>> delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index bff341d6118..2832123218f 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
>>> socfpga_cyclone5_vining_fpga.dtb \
>>> socfpga_cyclone5_ac501soc.dtb \
>>> socfpga_cyclone5_ac550soc.dtb \
>>> - socfpga_n5x_socdk.dtb \
>>> - socfpga_stratix10_socdk.dtb
>>> + socfpga_n5x_socdk.dtb
>>> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
>>> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
>>> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/
>>> dts/socfpga_stratix10-u-boot.dtsi
>>> index 3e3a3780469..a3b4c0564f9 100644
>>> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>>> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>>> @@ -3,6 +3,164 @@
>>> * U-Boot additions
>>> *
>>> * Copyright (C) 2020 Intel Corporation <www.intel.com>
>>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>>> */
>>> #include "socfpga_soc64_fit-u-boot.dtsi"
>>> +
>>> +/{
>>> + aliases {
>>> + spi0 = &qspi;
>>> + i2c0 = &i2c1;
>>> + freeze_br0 = &freeze_controller;
>>> + };
>>> +
>>> + memory@0 {
>>> + device_type = "memory";
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>
>>
>> make dtbs_check (Linux dt-validate) will flag it as a schema violation
>> since memory nodes must not define #address-cells / #size-cells
>> because no child node according to the dt spec.
>>
>> Remove both properties from the memory@0
>>
>> [...]
>>
>>
> Removing these properties will result in boot failure in SPL during DDR
> init.
>
> fdtdec_decode_ram_size() in lib/fdtdec.c applied #cells to the wrong DT
> node, triggering libfdt’s default #size-cells = 1, which misparses reg
> encoded for #size-cells = <2> which is the way to describe 64-bit
> physical addresses and sizes ≥ 4 GiB for Stratix10.
>
> Refer commit - 90c08fa038451d6d7b7d8711bfd829b61d64c490
>
>>> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/
>>> arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>>> index ef0df769762..da19943ec3b 100644
>>> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>>> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
>>> @@ -3,47 +3,154 @@
>>> * U-Boot additions
>>> *
>>> * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
>>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>>> */
>>> #include "socfpga_stratix10-u-boot.dtsi"
>>> /{
>>> - aliases {
>>> - spi0 = &qspi;
>>> - freeze_br0 = &freeze_controller;
>>> + chosen {
>>> + stdout-path = "serial0:115200n8";
>>> + u-boot,spl-boot-order = &mmc,&flash0,&nand;
>>> };
>>> - soc {
>>> - freeze_controller: freeze_controller@f9000450 {
>>> - compatible = "altr,freeze-bridge-controller";
>>> - reg = <0xf9000450 0x00000010>;
>>> - status = "disabled";
>>> + memory@0 {
>>> + /* 4GB */
>>> + reg = <0 0x00000000 0 0x80000000>,
>>> + <1 0x80000000 0 0x80000000>;
>>> + };
>>> +};
>>> +
>>> +&qspi {
>>> + status = "okay";
>>> +};
>>> +
>>> +&gmac0 {
>>> + mdio0 {
>>> + ethernet_phy0: ethernet-phy@0 {
>>> + reg = <4>;
>>> + txd0-skew-ps = <0>; /* -420ps */
>>> + txd1-skew-ps = <0>; /* -420ps */
>>> + txd2-skew-ps = <0>; /* -420ps */
>>> + txd3-skew-ps = <0>; /* -420ps */
>>> + rxd0-skew-ps = <420>; /* 0ps */
>>> + rxd1-skew-ps = <420>; /* 0ps */
>>> + rxd2-skew-ps = <420>; /* 0ps */
>>> + rxd3-skew-ps = <420>; /* 0ps */
>>> + txen-skew-ps = <0>; /* -420ps */
>>> + txc-skew-ps = <900>; /* 0ps */
>>> + rxdv-skew-ps = <420>; /* 0ps */
>>> + rxc-skew-ps = <1680>; /* 780ps */
>>> };
>>> };
>>> };
>>> -&clkmgr {
>>> +&mmc {
>>> + drvsel = <3>;
>>> + smplsel = <2>;
>>> bootph-all;
>>> };
>>> &qspi {
>>> - status = "okay";
>>> - bootph-all;
>>> + /delete-property/ clocks;
>>> };
>>> &flash0 {
>>> - compatible = "jedec,spi-nor";
>>> - spi-max-frequency = <100000000>;
>>> + reg = <0>;
>>> spi-tx-bus-width = <4>;
>>> spi-rx-bus-width = <4>;
>>> bootph-all;
>>> +
>>> + m25p,fast-read;
>>> + cdns,page-size = <256>;
>>> + cdns,block-size = <16>;
>>> + cdns,tshsl-ns = <50>;
>>> + cdns,tsd2d-ns = <50>;
>>> + cdns,tchsh-ns = <4>;
>>> + cdns,tslch-ns = <4>;
>>> + /delete-property/ cdns,read-delay;
>>> +
>>> + partitions {
>>> + compatible = "fixed-partitions";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + qspi_boot: partition@0 {
>>> + label = "u-boot";
>>> + reg = <0x0 0x04200000>;
>>> + };
>>> +
>>> + root: partition@4200000 {
>>> + label = "root";
>>> + reg = <0x04200000 0x0BE00000>;
>>> + };
>>> + };
>>> };
>>> -&sysmgr {
>>> - bootph-all;
>>> +&fdt_0_blob {
>>> + filename = "dts/upstream/src/arm64/altera/
>>> socfpga_stratix10_socdk.dtb";
>>> };
>>> -&watchdog0 {
>>> - status = "okay";
>>> - bootph-all;
>>> +&images {
>>> + fdt-1 {
>>> + description = "socfpga_socdk_nand";
>>> + type = "flat_dt";
>>> + compression = "none";
>>> + fdt_1_blob: blob-ext {
>>> + filename = "dts/upstream/src/arm64/altera/
>>> socfpga_stratix10_socdk_nand.dtb";
>>> + };
>>> + hash {
>>> + algo = "crc32";
>>> + };
>>> + };
>>> +
>>> + fdt-2 {
>>> + description = "socfpga_socdk_emmc";
>>> + type = "flat_dt";
>>> + compression = "none";
>>> + fdt_2_blob: blob-ext {
>>> + filename = "dts/upstream/src/arm64/altera/
>>> socfpga_stratix10_socdk_emmc.dtb";
>>
>>
>> This file is absent. Binman references dts/upstream/src/arm64/altera/
>> socfpga_stratix10_socdk_emmc.dtb.
>>
>> If those source DTS files do not exist in the upstream tree, binman
>> fails with a file-not-found error at image build time
>>
I will remove this in v3 while waiting for
socfpga_stratix10_socdk_emmc.dts upstream on Linux side. I will
introduce a new patch to enable eMMC on Stratix10 once this file is
available
>>
>> Best regards,
>>
>> Tien Fong
>>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-05-07 9:31 ` Chee, Tien Fong
2026-04-28 3:48 ` [PATCH v2 3/9] arm: socfpga: Move firmware register settings from source code to device tree alif.zakuan.yuslaimi
` (6 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Combine all MMC and QSPI configs into single defconfig which is named
as "socfpga_stratix10_defconfig". This will be the default defconfig to
use.
This will support booting from all three flashes using ARM Trusted Firmware
(ATF) as the secure runtime monitor.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
configs/socfpga_stratix10_atf_defconfig | 90 ----------------------
configs/socfpga_stratix10_defconfig | 99 +++++++++++++++----------
2 files changed, 58 insertions(+), 131 deletions(-)
delete mode 100644 configs/socfpga_stratix10_atf_defconfig
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
deleted file mode 100644
index 206343885d9..00000000000
--- a/configs/socfpga_stratix10_atf_defconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=400000000
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_TEXT_BASE=0x200000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
-CONFIG_SF_DEFAULT_MODE=0x2003
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x200
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_DM_RESET=y
-CONFIG_SPL_STACK=0xffe3f000
-CONFIG_SPL_TEXT_BASE=0xFFE00000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x3ff00000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_SYS_LOAD_ADDR=0x02000000
-CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
-CONFIG_IDENT_STRING="socfpga_stratix10"
-CONFIG_SPL_FS_FAT=y
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="earlycon"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
-CONFIG_SYS_PBSIZE=2085
-CONFIG_SPL_MAX_SIZE=0x40000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_ALTERA_SDRAM=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_SYS_MMC_MAX_BLK_COUNT=256
-CONFIG_MMC_DW=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550_MEM32=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_DESIGNWARE_WATCHDOG=y
-CONFIG_WDT=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-CONFIG_PANIC_HANG=y
-CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index ef21dc92493..02a1875a72e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -1,93 +1,110 @@
CONFIG_ARM=y
CONFIG_COUNTER_FREQUENCY=400000000
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TEXT_BASE=0x1000
-CONFIG_SYS_MALLOC_LEN=0x500000
+CONFIG_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
-CONFIG_SF_DEFAULT_MODE=0x2003
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x200
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x04100000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="altera/socfpga_stratix10_socdk"
CONFIG_OF_UPSTREAM=y
-CONFIG_DM_RESET=y
-CONFIG_SPL_STACK=0xffe3f000
CONFIG_SPL_TEXT_BASE=0xFFE00000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x3ff00000
-CONFIG_SPL_BSS_MAX_SIZE=0x100000
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_SYS_MEMTEST_START=0x00000000
-CONFIG_SYS_MEMTEST_END=0x3fe00000
-CONFIG_OPTIMIZE_INLINING=y
-CONFIG_SPL_OPTIMIZE_INLINING=y
-CONFIG_REMAKE_ELF=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="earlycon"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
-CONFIG_SYS_PBSIZE=2085
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x3ff00000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_STACK=0xffe3f000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
+CONFIG_SPL_BSS_MAX_SIZE=0x100000
+CONFIG_BOOTARGS="earlycon panic=-1"
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_CRC32=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
-CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_NVEDIT_SELECT=y
CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="Image"
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_MTD=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_LIST=""
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_UBI_PART="root"
+CONFIG_ENV_UBI_VOLUME="env"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_SYS_MMC_MAX_BLK_COUNT=256
+CONFIG_MISC=y
CONFIG_MMC_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
+CONFIG_DM_RESET=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
-CONFIG_SPL_CRC32=y
+# CONFIG_TOOLS_MKEFICAPSULE is not set
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes
2026-04-28 3:48 ` [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes alif.zakuan.yuslaimi
@ 2026-05-07 9:31 ` Chee, Tien Fong
2026-05-14 5:42 ` Yuslaimi, Alif Zakuan
0 siblings, 1 reply; 19+ messages in thread
From: Chee, Tien Fong @ 2026-05-07 9:31 UTC (permalink / raw)
To: alif.zakuan.yuslaimi, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Alif,
On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>
> Combine all MMC and QSPI configs into single defconfig which is named
> as "socfpga_stratix10_defconfig". This will be the default defconfig to
> use.
>
> This will support booting from all three flashes using ARM Trusted Firmware
> (ATF) as the secure runtime monitor.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
> ---
> configs/socfpga_stratix10_atf_defconfig | 90 ----------------------
> configs/socfpga_stratix10_defconfig | 99 +++++++++++++++----------
> 2 files changed, 58 insertions(+), 131 deletions(-)
> delete mode 100644 configs/socfpga_stratix10_atf_defconfig
>
> diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
> deleted file mode 100644
> index 206343885d9..00000000000
> --- a/configs/socfpga_stratix10_atf_defconfig
> +++ /dev/null
> @@ -1,90 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_COUNTER_FREQUENCY=400000000
> -CONFIG_ARCH_SOCFPGA=y
> -CONFIG_TEXT_BASE=0x200000
> -CONFIG_SYS_MALLOC_LEN=0x500000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> -CONFIG_SF_DEFAULT_MODE=0x2003
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x200
> -CONFIG_DM_GPIO=y
> -CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
> -CONFIG_DM_RESET=y
> -CONFIG_SPL_STACK=0xffe3f000
> -CONFIG_SPL_TEXT_BASE=0xFFE00000
> -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> -CONFIG_SPL_BSS_START_ADDR=0x3ff00000
> -CONFIG_SPL_BSS_MAX_SIZE=0x100000
> -CONFIG_SYS_BOOTM_LEN=0x2000000
> -CONFIG_SYS_LOAD_ADDR=0x02000000
> -CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
> -CONFIG_IDENT_STRING="socfpga_stratix10"
> -CONFIG_SPL_FS_FAT=y
> -CONFIG_REMAKE_ELF=y
> -CONFIG_FIT=y
> -CONFIG_SPL_FIT_SIGNATURE=y
> -CONFIG_SPL_LOAD_FIT=y
> -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> -CONFIG_BOOTDELAY=5
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="earlycon"
> -CONFIG_USE_BOOTCOMMAND=y
> -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
> -CONFIG_SYS_PBSIZE=2085
> -CONFIG_SPL_MAX_SIZE=0x40000
> -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> -CONFIG_SPL_HAVE_INIT_STACK=y
> -CONFIG_SPL_SYS_MALLOC=y
> -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
> -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
> -CONFIG_SPL_SPI_LOAD=y
> -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
> -CONFIG_SPL_ATF=y
> -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SPI=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_ENV_RELOC_GD_ENV_ADDR=y
> -CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_SPL_DM_SEQ_ALIAS=y
> -CONFIG_SPL_ALTERA_SDRAM=y
> -CONFIG_DWAPB_GPIO=y
> -CONFIG_DM_I2C=y
> -CONFIG_SYS_I2C_DW=y
> -CONFIG_SYS_MMC_MAX_BLK_COUNT=256
> -CONFIG_MMC_DW=y
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHY_MICREL=y
> -CONFIG_PHY_MICREL_KSZ90X1=y
> -CONFIG_ETH_DESIGNWARE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550_MEM32=y
> -CONFIG_SPI=y
> -CONFIG_CADENCE_QSPI=y
> -CONFIG_DESIGNWARE_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_DWC2=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_DESIGNWARE_WATCHDOG=y
> -CONFIG_WDT=y
> -# CONFIG_SPL_USE_TINY_PRINTF is not set
> -CONFIG_PANIC_HANG=y
> -CONFIG_SPL_CRC32=y
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index ef21dc92493..02a1875a72e 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -1,93 +1,110 @@
> CONFIG_ARM=y
> CONFIG_COUNTER_FREQUENCY=400000000
> +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_TEXT_BASE=0x1000
> -CONFIG_SYS_MALLOC_LEN=0x500000
> +CONFIG_TEXT_BASE=0x200000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_NR_DRAM_BANKS=2
> -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
> -CONFIG_SF_DEFAULT_MODE=0x2003
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x200
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0x04100000
> +CONFIG_ENV_SECT_SIZE=0x20000
> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
> CONFIG_DM_GPIO=y
> CONFIG_DEFAULT_DEVICE_TREE="altera/socfpga_stratix10_socdk"
> CONFIG_OF_UPSTREAM=y
> -CONFIG_DM_RESET=y
> -CONFIG_SPL_STACK=0xffe3f000
> CONFIG_SPL_TEXT_BASE=0xFFE00000
> -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> -CONFIG_SPL_BSS_START_ADDR=0x3ff00000
> -CONFIG_SPL_BSS_MAX_SIZE=0x100000
> -CONFIG_SYS_BOOTM_LEN=0x2000000
> -CONFIG_SYS_LOAD_ADDR=0x02000000
> CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
> CONFIG_IDENT_STRING="socfpga_stratix10"
> CONFIG_SPL_FS_FAT=y
> -# CONFIG_PSCI_RESET is not set
> -CONFIG_SYS_MEMTEST_START=0x00000000
> -CONFIG_SYS_MEMTEST_END=0x3fe00000
> -CONFIG_OPTIMIZE_INLINING=y
> -CONFIG_SPL_OPTIMIZE_INLINING=y
> -CONFIG_REMAKE_ELF=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_QSPI_BOOT=y
> CONFIG_BOOTDELAY=5
> CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="earlycon"
> -CONFIG_USE_BOOTCOMMAND=y
> -CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
> -CONFIG_SYS_PBSIZE=2085
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x3ff00000
> # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> CONFIG_SPL_HAVE_INIT_STACK=y
> +CONFIG_SPL_STACK=0xffe3f000
> CONFIG_SPL_SYS_MALLOC=y
> CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
> CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
> +CONFIG_SPL_BSS_MAX_SIZE=0x100000
> +CONFIG_BOOTARGS="earlycon panic=-1"
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Remove one of the two identical # CONFIG_SPL_RAW_IMAGE_SUPPORT lines.
Regenerate defconfig with make savedefconfig
> +CONFIG_SPL_CRC32=y
> +CONFIG_SPL_MTD=y
> +CONFIG_SPL_MTD_SUPPORT=y
> CONFIG_SPL_SPI_LOAD=y
> -CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
> -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
> -CONFIG_HUSH_PARSER=y
> +CONFIG_SPL_ATF=y
> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
> +CONFIG_CMD_NVEDIT_SELECT=y
> CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> CONFIG_CMD_GPIO=y
> CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> +CONFIG_CMD_MTD=y
> CONFIG_CMD_SPI=y
> CONFIG_CMD_USB=y
> -CONFIG_CMD_WDT=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_ENV_RELOC_GD_ENV_ADDR=y
> -CONFIG_USE_BOOTFILE=y
> -CONFIG_BOOTFILE="Image"
> +CONFIG_SPL_SPI_FLASH_MTD=y
> +CONFIG_SPI_FLASH_MTD=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_CMD_UBI=y
> +CONFIG_CMD_UBIFS=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_WL_THRESHOLD=4096
> +CONFIG_MTD_UBI_BEB_LIMIT=20
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_OF_LIST=""
> +CONFIG_ENV_IS_IN_FAT=y
> +CONFIG_ENV_IS_IN_UBI=y
> +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
> +CONFIG_ENV_UBI_PART="root"
> +CONFIG_ENV_UBI_VOLUME="env"
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_SPL_ALTERA_SDRAM=y
> +CONFIG_FPGA_INTEL_PR=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_DM_I2C=y
> CONFIG_SYS_I2C_DW=y
> -CONFIG_SYS_MMC_MAX_BLK_COUNT=256
> +CONFIG_MISC=y
> CONFIG_MMC_DW=y
> +CONFIG_SYS_MMC_MAX_BLK_COUNT=256
> +CONFIG_MTD=y
> +CONFIG_DM_MTD=y
> +CONFIG_SF_DEFAULT_MODE=0x2003
> CONFIG_SPI_FLASH_SPANSION=y
> CONFIG_SPI_FLASH_STMICRO=y
> CONFIG_PHY_MICREL=y
> CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_ETH=y
> CONFIG_ETH_DESIGNWARE=y
> CONFIG_MII=y
> +CONFIG_DM_RESET=y
> CONFIG_SYS_NS16550_MEM32=y
> CONFIG_SPI=y
> CONFIG_CADENCE_QSPI=y
> CONFIG_DESIGNWARE_SPI=y
> CONFIG_USB=y
> +CONFIG_DM_USB=y
> CONFIG_USB_DWC2=y
> -CONFIG_USB_STORAGE=y
missing vs ATF defconfig, why dropping this?
Best regards,
Tien Fong
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes
2026-05-07 9:31 ` Chee, Tien Fong
@ 2026-05-14 5:42 ` Yuslaimi, Alif Zakuan
0 siblings, 0 replies; 19+ messages in thread
From: Yuslaimi, Alif Zakuan @ 2026-05-14 5:42 UTC (permalink / raw)
To: Chee, Tien Fong, u-boot@lists.denx.de
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Tien Fong,
On 7/5/2026 5:31 pm, Chee, Tien Fong wrote:
> Hi Alif,
>
>
> On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>
>> Combine all MMC and QSPI configs into single defconfig which is named
>> as "socfpga_stratix10_defconfig". This will be the default defconfig to
>> use.
>>
>> This will support booting from all three flashes using ARM Trusted Firmware
>> (ATF) as the secure runtime monitor.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>> ---
>> configs/socfpga_stratix10_atf_defconfig | 90 ----------------------
>> configs/socfpga_stratix10_defconfig | 99 +++++++++++++++----------
>> 2 files changed, 58 insertions(+), 131 deletions(-)
>> delete mode 100644 configs/socfpga_stratix10_atf_defconfig
>>
>> diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
>> deleted file mode 100644
>> index 206343885d9..00000000000
>> --- a/configs/socfpga_stratix10_atf_defconfig
>> +++ /dev/null
>> @@ -1,90 +0,0 @@
>> -CONFIG_ARM=y
>> -CONFIG_COUNTER_FREQUENCY=400000000
>> -CONFIG_ARCH_SOCFPGA=y
>> -CONFIG_TEXT_BASE=0x200000
>> -CONFIG_SYS_MALLOC_LEN=0x500000
>> -CONFIG_NR_DRAM_BANKS=2
>> -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
>> -CONFIG_SF_DEFAULT_MODE=0x2003
>> -CONFIG_ENV_SIZE=0x1000
>> -CONFIG_ENV_OFFSET=0x200
>> -CONFIG_DM_GPIO=y
>> -CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
>> -CONFIG_DM_RESET=y
>> -CONFIG_SPL_STACK=0xffe3f000
>> -CONFIG_SPL_TEXT_BASE=0xFFE00000
>> -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>> -CONFIG_SPL_BSS_START_ADDR=0x3ff00000
>> -CONFIG_SPL_BSS_MAX_SIZE=0x100000
>> -CONFIG_SYS_BOOTM_LEN=0x2000000
>> -CONFIG_SYS_LOAD_ADDR=0x02000000
>> -CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
>> -CONFIG_IDENT_STRING="socfpga_stratix10"
>> -CONFIG_SPL_FS_FAT=y
>> -CONFIG_REMAKE_ELF=y
>> -CONFIG_FIT=y
>> -CONFIG_SPL_FIT_SIGNATURE=y
>> -CONFIG_SPL_LOAD_FIT=y
>> -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
>> -CONFIG_BOOTDELAY=5
>> -CONFIG_USE_BOOTARGS=y
>> -CONFIG_BOOTARGS="earlycon"
>> -CONFIG_USE_BOOTCOMMAND=y
>> -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
>> -CONFIG_SYS_PBSIZE=2085
>> -CONFIG_SPL_MAX_SIZE=0x40000
>> -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>> -CONFIG_SPL_HAVE_INIT_STACK=y
>> -CONFIG_SPL_SYS_MALLOC=y
>> -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
>> -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
>> -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
>> -CONFIG_SPL_SPI_LOAD=y
>> -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
>> -CONFIG_SPL_ATF=y
>> -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
>> -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
>> -CONFIG_HUSH_PARSER=y
>> -CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
>> -CONFIG_CMD_MEMTEST=y
>> -CONFIG_CMD_GPIO=y
>> -CONFIG_CMD_I2C=y
>> -CONFIG_CMD_MMC=y
>> -CONFIG_CMD_SPI=y
>> -CONFIG_CMD_USB=y
>> -CONFIG_CMD_DHCP=y
>> -CONFIG_CMD_MII=y
>> -CONFIG_CMD_PING=y
>> -CONFIG_CMD_CACHE=y
>> -CONFIG_CMD_EXT4=y
>> -CONFIG_CMD_FAT=y
>> -CONFIG_CMD_FS_GENERIC=y
>> -CONFIG_ENV_IS_IN_MMC=y
>> -CONFIG_ENV_RELOC_GD_ENV_ADDR=y
>> -CONFIG_NET_RANDOM_ETHADDR=y
>> -CONFIG_SPL_DM_SEQ_ALIAS=y
>> -CONFIG_SPL_ALTERA_SDRAM=y
>> -CONFIG_DWAPB_GPIO=y
>> -CONFIG_DM_I2C=y
>> -CONFIG_SYS_I2C_DW=y
>> -CONFIG_SYS_MMC_MAX_BLK_COUNT=256
>> -CONFIG_MMC_DW=y
>> -CONFIG_SPI_FLASH_SPANSION=y
>> -CONFIG_SPI_FLASH_STMICRO=y
>> -CONFIG_PHY_MICREL=y
>> -CONFIG_PHY_MICREL_KSZ90X1=y
>> -CONFIG_ETH_DESIGNWARE=y
>> -CONFIG_MII=y
>> -CONFIG_SYS_NS16550_MEM32=y
>> -CONFIG_SPI=y
>> -CONFIG_CADENCE_QSPI=y
>> -CONFIG_DESIGNWARE_SPI=y
>> -CONFIG_USB=y
>> -CONFIG_USB_DWC2=y
>> -CONFIG_USB_STORAGE=y
>> -CONFIG_DESIGNWARE_WATCHDOG=y
>> -CONFIG_WDT=y
>> -# CONFIG_SPL_USE_TINY_PRINTF is not set
>> -CONFIG_PANIC_HANG=y
>> -CONFIG_SPL_CRC32=y
>> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
>> index ef21dc92493..02a1875a72e 100644
>> --- a/configs/socfpga_stratix10_defconfig
>> +++ b/configs/socfpga_stratix10_defconfig
>> @@ -1,93 +1,110 @@
>> CONFIG_ARM=y
>> CONFIG_COUNTER_FREQUENCY=400000000
>> +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
>> CONFIG_ARCH_SOCFPGA=y
>> -CONFIG_TEXT_BASE=0x1000
>> -CONFIG_SYS_MALLOC_LEN=0x500000
>> +CONFIG_TEXT_BASE=0x200000
>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>> CONFIG_NR_DRAM_BANKS=2
>> -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000
>> -CONFIG_SF_DEFAULT_MODE=0x2003
>> -CONFIG_ENV_SIZE=0x1000
>> -CONFIG_ENV_OFFSET=0x200
>> +CONFIG_ENV_SIZE=0x2000
>> +CONFIG_ENV_OFFSET=0x04100000
>> +CONFIG_ENV_SECT_SIZE=0x20000
>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
>> CONFIG_DM_GPIO=y
>> CONFIG_DEFAULT_DEVICE_TREE="altera/socfpga_stratix10_socdk"
>> CONFIG_OF_UPSTREAM=y
>> -CONFIG_DM_RESET=y
>> -CONFIG_SPL_STACK=0xffe3f000
>> CONFIG_SPL_TEXT_BASE=0xFFE00000
>> -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>> -CONFIG_SPL_BSS_START_ADDR=0x3ff00000
>> -CONFIG_SPL_BSS_MAX_SIZE=0x100000
>> -CONFIG_SYS_BOOTM_LEN=0x2000000
>> -CONFIG_SYS_LOAD_ADDR=0x02000000
>> CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
>> CONFIG_IDENT_STRING="socfpga_stratix10"
>> CONFIG_SPL_FS_FAT=y
>> -# CONFIG_PSCI_RESET is not set
>> -CONFIG_SYS_MEMTEST_START=0x00000000
>> -CONFIG_SYS_MEMTEST_END=0x3fe00000
>> -CONFIG_OPTIMIZE_INLINING=y
>> -CONFIG_SPL_OPTIMIZE_INLINING=y
>> -CONFIG_REMAKE_ELF=y
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_FIT=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
>> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
>> +CONFIG_QSPI_BOOT=y
>> CONFIG_BOOTDELAY=5
>> CONFIG_USE_BOOTARGS=y
>> -CONFIG_BOOTARGS="earlycon"
>> -CONFIG_USE_BOOTCOMMAND=y
>> -CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
>> -CONFIG_SYS_PBSIZE=2085
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
>> CONFIG_SPL_MAX_SIZE=0x40000
>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>> +CONFIG_SPL_BSS_START_ADDR=0x3ff00000
>> # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>> CONFIG_SPL_HAVE_INIT_STACK=y
>> +CONFIG_SPL_STACK=0xffe3f000
>> CONFIG_SPL_SYS_MALLOC=y
>> CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
>> CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
>> CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
>> +CONFIG_SPL_BSS_MAX_SIZE=0x100000
>> +CONFIG_BOOTARGS="earlycon panic=-1"
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>
>
> Remove one of the two identical # CONFIG_SPL_RAW_IMAGE_SUPPORT lines.
> Regenerate defconfig with make savedefconfig
>
>
Noted, I will clean this up with savedefconfig for v3.
>> +CONFIG_SPL_CRC32=y
>> +CONFIG_SPL_MTD=y
>> +CONFIG_SPL_MTD_SUPPORT=y
>> CONFIG_SPL_SPI_LOAD=y
>> -CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
>> -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex"
>> -CONFIG_HUSH_PARSER=y
>> +CONFIG_SPL_ATF=y
>> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
>> CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
>> +CONFIG_CMD_NVEDIT_SELECT=y
>> CONFIG_CMD_MEMTEST=y
>> +# CONFIG_CMD_FLASH is not set
>> CONFIG_CMD_GPIO=y
>> CONFIG_CMD_I2C=y
>> CONFIG_CMD_MMC=y
>> +CONFIG_CMD_MTD=y
>> CONFIG_CMD_SPI=y
>> CONFIG_CMD_USB=y
>> -CONFIG_CMD_WDT=y
>> -CONFIG_CMD_DHCP=y
>> -CONFIG_CMD_MII=y
>> -CONFIG_CMD_PING=y
>> CONFIG_CMD_CACHE=y
>> -CONFIG_CMD_EXT4=y
>> -CONFIG_CMD_FAT=y
>> -CONFIG_CMD_FS_GENERIC=y
>> -CONFIG_ENV_IS_IN_MMC=y
>> -CONFIG_ENV_RELOC_GD_ENV_ADDR=y
>> -CONFIG_USE_BOOTFILE=y
>> -CONFIG_BOOTFILE="Image"
>> +CONFIG_SPL_SPI_FLASH_MTD=y
>> +CONFIG_SPI_FLASH_MTD=y
>> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
>> +CONFIG_CMD_UBI=y
>> +CONFIG_CMD_UBIFS=y
>> +CONFIG_MTD_UBI=y
>> +CONFIG_MTD_UBI_WL_THRESHOLD=4096
>> +CONFIG_MTD_UBI_BEB_LIMIT=20
>> +# CONFIG_ISO_PARTITION is not set
>> +# CONFIG_EFI_PARTITION is not set
>> +CONFIG_OF_LIST=""
>> +CONFIG_ENV_IS_IN_FAT=y
>> +CONFIG_ENV_IS_IN_UBI=y
>> +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
>> +CONFIG_ENV_UBI_PART="root"
>> +CONFIG_ENV_UBI_VOLUME="env"
>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> CONFIG_NET_RANDOM_ETHADDR=y
>> CONFIG_SPL_DM_SEQ_ALIAS=y
>> CONFIG_SPL_ALTERA_SDRAM=y
>> +CONFIG_FPGA_INTEL_PR=y
>> CONFIG_DWAPB_GPIO=y
>> CONFIG_DM_I2C=y
>> CONFIG_SYS_I2C_DW=y
>> -CONFIG_SYS_MMC_MAX_BLK_COUNT=256
>> +CONFIG_MISC=y
>> CONFIG_MMC_DW=y
>> +CONFIG_SYS_MMC_MAX_BLK_COUNT=256
>> +CONFIG_MTD=y
>> +CONFIG_DM_MTD=y
>> +CONFIG_SF_DEFAULT_MODE=0x2003
>> CONFIG_SPI_FLASH_SPANSION=y
>> CONFIG_SPI_FLASH_STMICRO=y
>> CONFIG_PHY_MICREL=y
>> CONFIG_PHY_MICREL_KSZ90X1=y
>> +CONFIG_DM_ETH=y
>> CONFIG_ETH_DESIGNWARE=y
>> CONFIG_MII=y
>> +CONFIG_DM_RESET=y
>> CONFIG_SYS_NS16550_MEM32=y
>> CONFIG_SPI=y
>> CONFIG_CADENCE_QSPI=y
>> CONFIG_DESIGNWARE_SPI=y
>> CONFIG_USB=y
>> +CONFIG_DM_USB=y
>> CONFIG_USB_DWC2=y
>> -CONFIG_USB_STORAGE=y
>
>
> missing vs ATF defconfig, why dropping this?
>
>
> Best regards,
>
> Tien Fong
>
This is not needed to be enabled as CONFIG_DISTRO_DEFAULTS is enabled in
this defconfig.
CONFIG_DISTRO_DEFAULTS -> BOOT_DEFAULTS_FEATURES -> USB_STORAGE in
boot/Kconfig
Thanks,
Alif
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/9] arm: socfpga: Move firmware register settings from source code to device tree
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 1/9] arch: arm: dts: stratix10: Switch to using upstream Linux DT config alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 2/9] configs: stratix10: Combine defconfig for all boot flashes alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 4/9] arm: socfpga: Update Stratix10 SPL data save and restore implementation alif.zakuan.yuslaimi
` (5 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Migrate the CCU, firewall, and high privilege register configurations from
hardcoded values in the source code to the device tree.
This helps to centralize hardware configuration, improves maintainability,
and allows easier customization for different platforms.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 149 +++++++++++++++++++++
arch/arm/mach-socfpga/spl_s10.c | 29 ++--
drivers/ddr/altera/sdram_s10.c | 44 ------
3 files changed, 165 insertions(+), 57 deletions(-)
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index a3b4c0564f9..ad4b383f704 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -6,6 +6,7 @@
* Copyright (C) 2026 Altera Corporation <www.altera.com>
*/
+#include "socfpga_soc64_u-boot.dtsi"
#include "socfpga_soc64_fit-u-boot.dtsi"
/{
@@ -134,6 +135,154 @@
bootph-all;
};
+&socfpga_l3interconnect_firewall {
+ i_ccu_noc_registers@f7000000 {
+ reg = <0xf7000000 0x00049e60>;
+ intel,offset-settings =
+ /* Enable access to DDR reg from CPU */
+ <0x0004400 0xF8000000 0xffffffff>,
+
+ /* Enable access to DDR region from CPU */
+ <0x00045c0 0x00000000 0xffffffdf>,
+ <0x00045e0 0x00000000 0xffffffdf>,
+ <0x0004600 0x00000000 0xffffffdf>,
+ <0x0004620 0x00000000 0xffffffdf>,
+ <0x0004640 0x00000000 0xffffffdf>,
+ <0x0004660 0x00000000 0xffffffdf>,
+
+ /* Disable ocram security at CCU for non secure access */
+ <0x0004688 0xfffc0000 0xffffffcf>,
+ <0x0018628 0xfffc0000 0xffffffcf>,
+
+ /* Enable access to DDR region from IO master */
+ <0x00018560 0x00000000 0xffffffdf>,
+ <0x00018580 0x00000000 0xffffffdf>,
+ <0x000185a0 0x00000000 0xffffffdf>,
+ <0x000185c0 0x00000000 0xffffffdf>,
+ <0x000185e0 0x00000000 0xffffffdf>,
+ <0x00018600 0x00000000 0xffffffdf>,
+
+ /* Enable access to DDR region from TCU */
+ <0x0002c520 0x00000000 0xffffffdf>,
+ <0x0002c540 0x00000000 0xffffffdf>,
+ <0x0002c560 0x00000000 0xffffffdf>,
+ <0x0002c580 0x00000000 0xffffffdf>,
+ <0x0002c5a0 0x00000000 0xffffffdf>,
+ <0x0002c5c0 0x00000000 0xffffffdf>,
+
+ /* Enable access to DDR region from FPGA */
+ <0x000105a0 0x00000000 0xffffffdf>,
+ <0x000105c0 0x00000000 0xffffffdf>,
+ <0x000105e0 0x00000000 0xffffffdf>,
+ <0x00010600 0x00000000 0xffffffdf>,
+ <0x00010620 0x00000000 0xffffffdf>,
+ <0x00010640 0x00000000 0xffffffdf>;
+ bootph-all;
+ };
+
+ /*
+ * Both firewall and QOS regs accessed by CPU in MPFE has
+ * dependency on CCU configuration above.
+ *
+ * Below are all fpga2sdram firewall settings with default
+ * reset value for the sake of easy reference by users.
+ * Users may choose to remove any of these register configurations
+ * that they do not require in their specific implementation.
+ */
+ soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 {
+ reg = <0xf8020200 0x00000050>;
+ intel,offset-settings =
+ <0x0000000 0x00000000 0x0000000f>,
+ <0x0000004 0x00000000 0x0000000f>,
+ <0x0000008 0x00000000 0x0000000f>,
+ <0x0000010 0x00000000 0xffff0000>,
+ <0x0000014 0x00000000 0x0000001f>,
+ <0x0000018 0x00000000 0xffff0000>,
+ <0x000001c 0x00000000 0x0000001f>,
+ <0x0000020 0x00000000 0xffff0000>,
+ <0x0000024 0x00000000 0x0000001f>,
+ <0x0000028 0x00000000 0xffff0000>,
+ <0x000002c 0x00000000 0x0000001f>,
+ <0x0000030 0x00000000 0xffff0000>,
+ <0x0000034 0x00000000 0x0000001f>,
+ <0x0000038 0x00000000 0xffff0000>,
+ <0x000003c 0x00000000 0x0000001f>,
+ <0x0000040 0x00000000 0xffff0000>,
+ <0x0000044 0x00000000 0x0000001f>,
+ <0x0000048 0x00000000 0xffff0000>,
+ <0x000004c 0x00000000 0x0000001f>;
+ bootph-all;
+ };
+
+ soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 {
+ reg = <0xf8020300 0x00000050>;
+ intel,offset-settings =
+ <0x0000000 0x00000000 0x0000000f>,
+ <0x0000004 0x00000000 0x0000000f>,
+ <0x0000008 0x00000000 0x0000000f>,
+ <0x0000010 0x00000000 0xffff0000>,
+ <0x0000014 0x00000000 0x0000001f>,
+ <0x0000018 0x00000000 0xffff0000>,
+ <0x000001c 0x00000000 0x0000001f>,
+ <0x0000020 0x00000000 0xffff0000>,
+ <0x0000024 0x00000000 0x0000001f>,
+ <0x0000028 0x00000000 0xffff0000>,
+ <0x000002c 0x00000000 0x0000001f>,
+ <0x0000030 0x00000000 0xffff0000>,
+ <0x0000034 0x00000000 0x0000001f>,
+ <0x0000038 0x00000000 0xffff0000>,
+ <0x000003c 0x00000000 0x0000001f>,
+ <0x0000040 0x00000000 0xffff0000>,
+ <0x0000044 0x00000000 0x0000001f>,
+ <0x0000048 0x00000000 0xffff0000>,
+ <0x000004c 0x00000000 0x0000001f>;
+ bootph-all;
+ };
+
+ soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 {
+ reg = <0xf8020400 0x00000050>;
+ intel,offset-settings =
+ <0x0000000 0x00000000 0x0000000f>,
+ <0x0000004 0x00000000 0x0000000f>,
+ <0x0000008 0x00000000 0x0000000f>,
+ <0x0000010 0x00000000 0xffff0000>,
+ <0x0000014 0x00000000 0x0000001f>,
+ <0x0000018 0x00000000 0xffff0000>,
+ <0x000001c 0x00000000 0x0000001f>,
+ <0x0000020 0x00000000 0xffff0000>,
+ <0x0000024 0x00000000 0x0000001f>,
+ <0x0000028 0x00000000 0xffff0000>,
+ <0x000002c 0x00000000 0x0000001f>,
+ <0x0000030 0x00000000 0xffff0000>,
+ <0x0000034 0x00000000 0x0000001f>,
+ <0x0000038 0x00000000 0xffff0000>,
+ <0x000003c 0x00000000 0x0000001f>,
+ <0x0000040 0x00000000 0xffff0000>,
+ <0x0000044 0x00000000 0x0000001f>,
+ <0x0000048 0x00000000 0xffff0000>,
+ <0x000004c 0x00000000 0x0000001f>;
+ bootph-all;
+ };
+
+ /*
+ * Example of ccu_mem0_I_main QOS settings with
+ * default reset value for the sake of easy reference
+ * by users. Users may choose to remove any of these register
+ * configurations that they do not require in their specific
+ * implementation.
+ */
+ soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
+ reg = <0xf8022080 0x0000001c>;
+ intel,offset-settings =
+ <0x0000008 0x00000000 0x00000303>,
+ <0x000000c 0x00000001 0x00000003>,
+ <0x0000010 0x00000BFE 0x00001fff>,
+ <0x0000014 0x00000008 0x000003ff>,
+ <0x0000018 0x00000000 0x00000007>;
+ bootph-all;
+ };
+};
+
&uart0 {
bootph-all;
clock-frequency = <100000000>;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a0d3c96d456..8ab80740c6e 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -25,6 +25,7 @@ void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
+ struct udevice *dev;
ret = spl_early_init();
if (ret)
@@ -67,22 +68,24 @@ void board_init_f(ulong dummy)
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
+ if (ret) {
+ printf("System manager firewall configuration failed: %d\n", ret);
+ hang();
+ }
- /* disable ocram security at CCU for non secure access */
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
+ if (ret) {
+ printf("L3 interconnect firewall configuration failed: %d\n", ret);
+ hang();
+ }
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- struct udevice *dev;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- hang();
- }
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ hang();
+ }
#endif
#ifdef CONFIG_CADENCE_QSPI
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 4ac4c79e0ac..1497a8e4aab 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -78,50 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)
phys_size_t hw_size;
struct bd_info bd = {0};
- /* Enable access to DDR from CPU master */
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
- CCU_ADBASE_DI_MASK);
-
- /* Enable access to DDR from IO master */
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
- CCU_ADBASE_DI_MASK);
-
- /* Enable access to DDR from TCU */
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
- CCU_ADBASE_DI_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
- CCU_ADBASE_DI_MASK);
-
/* this enables nonsecure access to DDR */
/* mpuregion0addr_limit */
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 4/9] arm: socfpga: Update Stratix10 SPL data save and restore implementation
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (2 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 3/9] arm: socfpga: Move firmware register settings from source code to device tree alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10 alif.zakuan.yuslaimi
` (4 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Enable backup for data section to support warm reset in Stratix10 SPL as
no SPL image would be reloaded in warm reset.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
arch/arm/mach-socfpga/spl_s10.c | 17 +++++++++++++++++
configs/socfpga_stratix10_defconfig | 2 +-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 8ab80740c6e..ce1d5d4c8ff 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -21,12 +21,29 @@
#include <watchdog.h>
#include <dm/uclass.h>
+u32 reset_flag(void)
+{
+ /* Check rstmgr.stat for warm reset status */
+ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
+
+ /* Check whether any L4 watchdogs or SDM had triggered warm reset */
+ u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
+
+ if (status & warm_reset_mask)
+ return 0;
+
+ return 1;
+}
+
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
struct udevice *dev;
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
+ spl_save_restore_data();
+
ret = spl_early_init();
if (ret)
hang();
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 02a1875a72e..6a6f1d98c16 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_COUNTER_FREQUENCY=400000000
-CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_TEXT_BASE=0x200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -16,6 +15,7 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (3 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 4/9] arm: socfpga: Update Stratix10 SPL data save and restore implementation alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-05-08 4:18 ` Chee, Tien Fong
2026-04-28 3:48 ` [PATCH v2 6/9] ddr: altera: soc64: Add secure region support for ATF flow alif.zakuan.yuslaimi
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
The base address of system manager can be retrieved
using DT framework through the system manager driver.
Enable system manager support for Stratix10 by probing the
system manager driver to initialize during SPL boot up.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
MAINTAINERS | 1 +
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 6 ++++++
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/misc.c | 3 ++-
arch/arm/mach-socfpga/spl_s10.c | 1 +
board/altera/stratix10-socdk/Makefile | 7 +++++++
board/altera/stratix10-socdk/socfpga.c | 12 ++++++++++++
configs/socfpga_stratix10_defconfig | 1 +
8 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 board/altera/stratix10-socdk/Makefile
create mode 100644 board/altera/stratix10-socdk/socfpga.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 056902f6ef2..d1173126fc6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -156,6 +156,7 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/dts/socfpga_*
F: arch/arm/mach-socfpga/
+F: board/altera/stratix10-socdk/
F: board/intel/agilex-socdk/
F: configs/socfpga_*
F: drivers/ddr/altera/
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index ad4b383f704..89fa0e829f6 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -13,6 +13,7 @@
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
+ sysmgr = &sysmgr;
freeze_br0 = &freeze_controller;
};
@@ -283,6 +284,11 @@
};
};
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ bootph-all;
+};
+
&uart0 {
bootph-all;
clock-frequency = <100000000>;
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b6f35ddacc4..962dce67c64 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -39,6 +39,7 @@ obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
+obj-y += altera-sysmgr.o
endif
ifdef CONFIG_ARCH_SOCFPGA_AGILEX
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 1eef7893e54..418d7dfb572 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -263,7 +263,8 @@ void socfpga_get_managers_addr(void)
if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
- !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) {
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
ret = socfpga_get_base_addr("altr,sys-mgr",
&socfpga_sysmgr_base);
if (ret)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index ce1d5d4c8ff..b05bec2cbc1 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -48,6 +48,7 @@ void board_init_f(ulong dummy)
if (ret)
hang();
+ socfpga_get_sys_mgr_addr();
socfpga_get_managers_addr();
/* Ensure watchdog is paused when debugging is happening */
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 00000000000..416c121406a
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2026 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 00000000000..f8facf79204
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
+ */
+
+#include <asm/arch/misc.h>
+
+int board_early_init_f(void)
+{
+ socfpga_get_sys_mgr_addr();
+ return 0;
+}
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 6a6f1d98c16..726dd7d7c9f 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -28,6 +28,7 @@ CONFIG_USE_BOOTARGS=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10
2026-04-28 3:48 ` [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10 alif.zakuan.yuslaimi
@ 2026-05-08 4:18 ` Chee, Tien Fong
2026-05-14 5:43 ` Yuslaimi, Alif Zakuan
0 siblings, 1 reply; 19+ messages in thread
From: Chee, Tien Fong @ 2026-05-08 4:18 UTC (permalink / raw)
To: alif.zakuan.yuslaimi, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Alif,
On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>
> The base address of system manager can be retrieved
> using DT framework through the system manager driver.
>
> Enable system manager support for Stratix10 by probing the
> system manager driver to initialize during SPL boot up.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
> ---
> MAINTAINERS | 1 +
> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 6 ++++++
> arch/arm/mach-socfpga/Makefile | 1 +
> arch/arm/mach-socfpga/misc.c | 3 ++-
> arch/arm/mach-socfpga/spl_s10.c | 1 +
> board/altera/stratix10-socdk/Makefile | 7 +++++++
> board/altera/stratix10-socdk/socfpga.c | 12 ++++++++++++
> configs/socfpga_stratix10_defconfig | 1 +
> 8 files changed, 31 insertions(+), 1 deletion(-)
> create mode 100644 board/altera/stratix10-socdk/Makefile
> create mode 100644 board/altera/stratix10-socdk/socfpga.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 056902f6ef2..d1173126fc6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -156,6 +156,7 @@ S: Maintained
> T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
> F: arch/arm/dts/socfpga_*
> F: arch/arm/mach-socfpga/
> +F: board/altera/stratix10-socdk/
> F: board/intel/agilex-socdk/
> F: configs/socfpga_*
> F: drivers/ddr/altera/
> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> index ad4b383f704..89fa0e829f6 100644
> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> @@ -13,6 +13,7 @@
> aliases {
> spi0 = &qspi;
> i2c0 = &i2c1;
> + sysmgr = &sysmgr;
> freeze_br0 = &freeze_controller;
> };
>
> @@ -283,6 +284,11 @@
> };
> };
>
> +&sysmgr {
> + compatible = "altr,sys-mgr", "syscon";
> + bootph-all;
> +};
> +
> &uart0 {
> bootph-all;
> clock-frequency = <100000000>;
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b6f35ddacc4..962dce67c64 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -39,6 +39,7 @@ obj-y += system_manager_soc64.o
> obj-y += timer_s10.o
> obj-y += wrap_handoff_soc64.o
> obj-y += wrap_pll_config_soc64.o
> +obj-y += altera-sysmgr.o
> endif
>
> ifdef CONFIG_ARCH_SOCFPGA_AGILEX
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 1eef7893e54..418d7dfb572 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -263,7 +263,8 @@ void socfpga_get_managers_addr(void)
>
> if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
> !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
> - !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) {
> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
> ret = socfpga_get_base_addr("altr,sys-mgr",
> &socfpga_sysmgr_base);
> if (ret)
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index ce1d5d4c8ff..b05bec2cbc1 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -48,6 +48,7 @@ void board_init_f(ulong dummy)
> if (ret)
> hang();
>
> + socfpga_get_sys_mgr_addr();
> socfpga_get_managers_addr();
>
> /* Ensure watchdog is paused when debugging is happening */
> diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
> new file mode 100644
> index 00000000000..416c121406a
> --- /dev/null
> +++ b/board/altera/stratix10-socdk/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2026 Altera Corporation <www.altera.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0
SPDX-License-Identifier appears on line 4, not line 1
Best regards,
Tien Fong
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10
2026-05-08 4:18 ` Chee, Tien Fong
@ 2026-05-14 5:43 ` Yuslaimi, Alif Zakuan
0 siblings, 0 replies; 19+ messages in thread
From: Yuslaimi, Alif Zakuan @ 2026-05-14 5:43 UTC (permalink / raw)
To: Chee, Tien Fong, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Tien Fong,
On 8/5/2026 12:18 pm, Chee, Tien Fong wrote:
> Hi Alif,
>
>
> On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>
>> The base address of system manager can be retrieved
>> using DT framework through the system manager driver.
>>
>> Enable system manager support for Stratix10 by probing the
>> system manager driver to initialize during SPL boot up.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>> ---
>> MAINTAINERS | 1 +
>> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 6 ++++++
>> arch/arm/mach-socfpga/Makefile | 1 +
>> arch/arm/mach-socfpga/misc.c | 3 ++-
>> arch/arm/mach-socfpga/spl_s10.c | 1 +
>> board/altera/stratix10-socdk/Makefile | 7 +++++++
>> board/altera/stratix10-socdk/socfpga.c | 12 ++++++++++++
>> configs/socfpga_stratix10_defconfig | 1 +
>> 8 files changed, 31 insertions(+), 1 deletion(-)
>> create mode 100644 board/altera/stratix10-socdk/Makefile
>> create mode 100644 board/altera/stratix10-socdk/socfpga.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 056902f6ef2..d1173126fc6 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -156,6 +156,7 @@ S: Maintained
>> T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
>> F: arch/arm/dts/socfpga_*
>> F: arch/arm/mach-socfpga/
>> +F: board/altera/stratix10-socdk/
>> F: board/intel/agilex-socdk/
>> F: configs/socfpga_*
>> F: drivers/ddr/altera/
>> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/
>> dts/socfpga_stratix10-u-boot.dtsi
>> index ad4b383f704..89fa0e829f6 100644
>> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
>> @@ -13,6 +13,7 @@
>> aliases {
>> spi0 = &qspi;
>> i2c0 = &i2c1;
>> + sysmgr = &sysmgr;
>> freeze_br0 = &freeze_controller;
>> };
>> @@ -283,6 +284,11 @@
>> };
>> };
>> +&sysmgr {
>> + compatible = "altr,sys-mgr", "syscon";
>> + bootph-all;
>> +};
>> +
>> &uart0 {
>> bootph-all;
>> clock-frequency = <100000000>;
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/
>> Makefile
>> index b6f35ddacc4..962dce67c64 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -39,6 +39,7 @@ obj-y += system_manager_soc64.o
>> obj-y += timer_s10.o
>> obj-y += wrap_handoff_soc64.o
>> obj-y += wrap_pll_config_soc64.o
>> +obj-y += altera-sysmgr.o
>> endif
>> ifdef CONFIG_ARCH_SOCFPGA_AGILEX
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index 1eef7893e54..418d7dfb572 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -263,7 +263,8 @@ void socfpga_get_managers_addr(void)
>> if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
>> !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
>> - !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) {
>> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
>> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
>> ret = socfpga_get_base_addr("altr,sys-mgr",
>> &socfpga_sysmgr_base);
>> if (ret)
>> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/
>> spl_s10.c
>> index ce1d5d4c8ff..b05bec2cbc1 100644
>> --- a/arch/arm/mach-socfpga/spl_s10.c
>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>> @@ -48,6 +48,7 @@ void board_init_f(ulong dummy)
>> if (ret)
>> hang();
>> + socfpga_get_sys_mgr_addr();
>> socfpga_get_managers_addr();
>> /* Ensure watchdog is paused when debugging is happening */
>> diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/
>> stratix10-socdk/Makefile
>> new file mode 100644
>> index 00000000000..416c121406a
>> --- /dev/null
>> +++ b/board/altera/stratix10-socdk/Makefile
>> @@ -0,0 +1,7 @@
>> +#
>> +# Copyright (C) 2026 Altera Corporation <www.altera.com>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0
>
>
> SPDX-License-Identifier appears on line 4, not line 1
>
>
> Best regards,
>
> Tien Fong
>
Noted, I will correct this for v3 submission.
Thanks,
Alif
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 6/9] ddr: altera: soc64: Add secure region support for ATF flow
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (4 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 5/9] arm: socfpga: s10: Enable system manager driver for Stratix10 alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 7/9] clk: s10: Refactor S10 clock driver alif.zakuan.yuslaimi
` (2 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
drivers/ddr/altera/sdram_s10.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 1497a8e4aab..aed53ae58eb 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -78,20 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)
phys_size_t hw_size;
struct bd_info bd = {0};
- /* this enables nonsecure access to DDR */
- /* mpuregion0addr_limit */
- FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
- FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
-
- /* nonmpuregion0addr_limit */
- FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
- FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
- FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
-
- /* Enable mpuregion0enable and nonmpuregion0enable */
- FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
- FW_MPU_DDR_SCR_EN_SET);
-
/* Ensure HMC clock is running */
if (poll_hmc_clock_status()) {
puts("DDR: Error as HMC clock not running\n");
@@ -284,6 +270,8 @@ int sdram_mmr_init_full(struct udevice *dev)
sdram_size_check(&bd);
+ sdram_set_firewall(&bd);
+
priv->info.base = bd.bi_dram[0].start;
priv->info.size = gd->ram_size;
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 7/9] clk: s10: Refactor S10 clock driver
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (5 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 6/9] ddr: altera: soc64: Add secure region support for ATF flow alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-05-08 5:48 ` Chee, Tien Fong
2026-04-28 3:48 ` [PATCH v2 8/9] mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 9/9] spl: s10: Enhance watchdog support in SPL for Stratix 10 alif.zakuan.yuslaimi
8 siblings, 1 reply; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Refactor Stratix10 clock manager driver to support driver model, following
Agilex clock driver.
Create a new clock driver, clk-s10.c, for Stratix10 which supports the
driver model. This allows several APIs such as enable/disable clock, and
get clock rate to be supported.
This driver will be initialized during SPL to bring up the clock as early
as possible. The clock initialization process are refactored into this new
driver from clock_manager_s10.c during clock driver probe.
Excluding Stratix10 from legacy method of obtaining clkmgr base address in
mach-socfpga/misc.c as the base address is already obtained during clock
driver probe during SPL initialization.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
MAINTAINERS | 1 +
arch/arm/mach-socfpga/Kconfig | 2 +
arch/arm/mach-socfpga/clock_manager_s10.c | 449 ++-----------
.../include/mach/clock_manager_s10.h | 176 +----
arch/arm/mach-socfpga/misc.c | 3 +-
arch/arm/mach-socfpga/spl_s10.c | 7 +-
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-s10.c | 603 ++++++++++++++++++
drivers/clk/altera/clk-s10.h | 202 ++++++
9 files changed, 873 insertions(+), 571 deletions(-)
create mode 100644 drivers/clk/altera/clk-s10.c
create mode 100644 drivers/clk/altera/clk-s10.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d1173126fc6..032f0ee97fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -159,6 +159,7 @@ F: arch/arm/mach-socfpga/
F: board/altera/stratix10-socdk/
F: board/intel/agilex-socdk/
F: configs/socfpga_*
+F: drivers/clk/altera/
F: drivers/ddr/altera/
F: drivers/power/domain/altr-pmgr-agilex5.c
F: drivers/sysreset/sysreset_socfpga*
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fb98b647442..aa1f3e761cd 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -146,8 +146,10 @@ config ARCH_SOCFPGA_STRATIX10
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
+ select CLK
select FPGA_INTEL_SDM_MAILBOX
select GICV2
+ select SPL_CLK if SPL
select ARCH_SOCFPGA_SOC64
choice
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index fd27470f967..df636f14f93 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -1,425 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*
*/
-#include <compiler.h>
-#include <dm/device.h>
-#include <linux/errno.h>
-#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
#include <asm/arch/clock_manager.h>
-#include <asm/arch/handoff_soc64.h>
#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/stratix10-clock.h>
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass_mainpll(u32 val)
-{
- writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
- cm_wait_for_fsm();
-}
-
-static void cm_write_bypass_perpll(u32 val)
-{
- writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
- cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(u32 val)
-{
- writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
- cm_wait_for_fsm();
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- */
-void cm_basic_init(const struct cm_config * const cfg)
-{
- u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
-
- if (cfg == 0)
- return;
-
- /* Put all plls in bypass */
- cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
- cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
-
- /* setup main PLL dividers where calculate the vcocalib value */
- mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
- CLKMGR_FDBCK_MDIV_MASK;
- refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
- CLKMGR_PLLGLOB_REFCLKDIV_MASK;
- mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
- hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
- CLKMGR_HSCNT_CONST;
- vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
- ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
- CLKMGR_VCOCALIB_MSCNT_OFFSET);
-
- writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
- ~CLKMGR_PLLGLOB_RST_MASK),
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
- writel(cfg->main_pll_fdbck,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
- writel(vcocalib,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
- writel(cfg->main_pll_pllc0,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
- writel(cfg->main_pll_pllc1,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
- writel(cfg->main_pll_nocdiv,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
-
- /* setup peripheral PLL dividers */
- /* calculate the vcocalib value */
- mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
- CLKMGR_FDBCK_MDIV_MASK;
- refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
- CLKMGR_PLLGLOB_REFCLKDIV_MASK;
- mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
- hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
- CLKMGR_HSCNT_CONST;
- vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
- ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
- CLKMGR_VCOCALIB_MSCNT_OFFSET);
-
- writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
- ~CLKMGR_PLLGLOB_RST_MASK),
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
- writel(cfg->per_pll_fdbck,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
- writel(vcocalib,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
- writel(cfg->per_pll_pllc0,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
- writel(cfg->per_pll_pllc1,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
- writel(cfg->per_pll_emacctl,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
- writel(cfg->per_pll_gpiodiv,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
-
- /* Take both PLL out of reset and power up */
- setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
- CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
- setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
- CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
-
-#define LOCKED_MASK \
- (CLKMGR_STAT_MAINPLL_LOCKED | \
- CLKMGR_STAT_PERPLL_LOCKED)
-
- cm_wait_for_lock(LOCKED_MASK);
-
- /*
- * Dividers for C2 to C9 only init after PLLs are lock. As dividers
- * only take effect upon value change, we shall set a maximum value as
- * default value.
- */
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
- writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
-
- writel(cfg->main_pll_mpuclk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
- writel(cfg->main_pll_nocclk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
- writel(cfg->main_pll_cntr2clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
- writel(cfg->main_pll_cntr3clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
- writel(cfg->main_pll_cntr4clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
- writel(cfg->main_pll_cntr5clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
- writel(cfg->main_pll_cntr6clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
- writel(cfg->main_pll_cntr7clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
- writel(cfg->main_pll_cntr8clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
- writel(cfg->main_pll_cntr9clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
- writel(cfg->per_pll_cntr2clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
- writel(cfg->per_pll_cntr3clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
- writel(cfg->per_pll_cntr4clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
- writel(cfg->per_pll_cntr5clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
- writel(cfg->per_pll_cntr6clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
- writel(cfg->per_pll_cntr7clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
- writel(cfg->per_pll_cntr8clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
- writel(cfg->per_pll_cntr9clk,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
-
- /* Take all PLLs out of bypass */
- cm_write_bypass_mainpll(0);
- cm_write_bypass_perpll(0);
-
- /* clear safe mode / out of boot mode */
- cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
- ~(CLKMGR_CTRL_SAFEMODE));
-
- /* Now ungate non-hw-managed clocks */
- writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
- writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
-
- /* Clear the loss of lock bits (write 1 to clear) */
- writel(CLKMGR_INTER_PERPLLLOST_MASK |
- CLKMGR_INTER_MAINPLLLOST_MASK,
- socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
-}
-
-static unsigned long cm_get_main_vco_clk_hz(void)
+static ulong cm_get_rate_dm(u32 id)
{
- unsigned long fref, refdiv, mdiv, reg, vco;
-
- reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
-
- fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
- CLKMGR_PLLGLOB_VCO_PSRC_MASK;
- switch (fref) {
- case CLKMGR_VCO_PSRC_EOSC1:
- fref = cm_get_osc_clk_hz();
- break;
- case CLKMGR_VCO_PSRC_INTOSC:
- fref = cm_get_intosc_clk_hz();
- break;
- case CLKMGR_VCO_PSRC_F2S:
- fref = cm_get_fpga_clk_hz();
- break;
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(socfpga_s10_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
}
- refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
- CLKMGR_PLLGLOB_REFCLKDIV_MASK;
-
- reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
- mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
-
- vco = fref / refdiv;
- vco = vco * (CLKMGR_MDIV_CONST + mdiv);
- return vco;
+ return rate;
}
-static unsigned long cm_get_per_vco_clk_hz(void)
+static u32 cm_get_rate_dm_khz(u32 id)
{
- unsigned long fref, refdiv, mdiv, reg, vco;
-
- reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
-
- fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
- CLKMGR_PLLGLOB_VCO_PSRC_MASK;
- switch (fref) {
- case CLKMGR_VCO_PSRC_EOSC1:
- fref = cm_get_osc_clk_hz();
- break;
- case CLKMGR_VCO_PSRC_INTOSC:
- fref = cm_get_intosc_clk_hz();
- break;
- case CLKMGR_VCO_PSRC_F2S:
- fref = cm_get_fpga_clk_hz();
- break;
- }
-
- refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
- CLKMGR_PLLGLOB_REFCLKDIV_MASK;
-
- reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
- mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
-
- vco = fref / refdiv;
- vco = vco * (CLKMGR_MDIV_CONST + mdiv);
- return vco;
+ return cm_get_rate_dm(id) / 1000;
}
unsigned long cm_get_mpu_clk_hz(void)
{
- unsigned long clock = readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_MPUCLK);
-
- clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
-
- switch (clock) {
- case CLKMGR_CLKSRC_MAIN:
- clock = cm_get_main_vco_clk_hz();
- clock /= (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_PLLC0) &
- CLKMGR_PLLC0_DIV_MASK);
- break;
-
- case CLKMGR_CLKSRC_PER:
- clock = cm_get_per_vco_clk_hz();
- clock /= (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_PERPLL_PLLC0) &
- CLKMGR_CLKCNT_MSK);
- break;
-
- case CLKMGR_CLKSRC_OSC1:
- clock = cm_get_osc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_INTOSC:
- clock = cm_get_intosc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_FPGA:
- clock = cm_get_fpga_clk_hz();
- break;
- }
-
- clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
- return clock;
-}
-
-unsigned int cm_get_l3_main_clk_hz(void)
-{
- u32 clock = readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_NOCCLK);
-
- clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
-
- switch (clock) {
- case CLKMGR_CLKSRC_MAIN:
- clock = cm_get_main_vco_clk_hz();
- clock /= (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_PLLC1) &
- CLKMGR_PLLC0_DIV_MASK);
- break;
-
- case CLKMGR_CLKSRC_PER:
- clock = cm_get_per_vco_clk_hz();
- clock /= (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
- break;
-
- case CLKMGR_CLKSRC_OSC1:
- clock = cm_get_osc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_INTOSC:
- clock = cm_get_intosc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_FPGA:
- clock = cm_get_fpga_clk_hz();
- break;
- }
-
- clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
- return clock;
-}
-
-unsigned int cm_get_mmc_controller_clk_hz(void)
-{
- u32 clock = readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_PERPLL_CNTR6CLK);
-
- clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
-
- switch (clock) {
- case CLKMGR_CLKSRC_MAIN:
- clock = cm_get_l3_main_clk_hz();
- clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_CNTR6CLK) &
- CLKMGR_CLKCNT_MSK);
- break;
-
- case CLKMGR_CLKSRC_PER:
- clock = cm_get_l3_main_clk_hz();
- clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_PERPLL_CNTR6CLK) &
- CLKMGR_CLKCNT_MSK);
- break;
-
- case CLKMGR_CLKSRC_OSC1:
- clock = cm_get_osc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_INTOSC:
- clock = cm_get_intosc_clk_hz();
- break;
-
- case CLKMGR_CLKSRC_FPGA:
- clock = cm_get_fpga_clk_hz();
- break;
- }
- return clock / 4;
-}
-
-unsigned int cm_get_l4_sp_clk_hz(void)
-{
- u32 clock = cm_get_l3_main_clk_hz();
-
- clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_NOCDIV) >>
- CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
- return clock;
-}
-
-unsigned int cm_get_spi_controller_clk_hz(void)
-{
- u32 clock = cm_get_l3_main_clk_hz();
-
- clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
- CLKMGR_S10_MAINPLL_NOCDIV) >>
- CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
- return clock;
+ return cm_get_rate_dm(STRATIX10_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_l3_main_clk_hz() / 4;
-}
-
-/*
- * Override weak dw_spi_get_clk implementation in designware_spi.c driver
- */
-
-int dw_spi_get_clk(struct udevice *bus, ulong *rate)
-{
- *rate = cm_get_spi_controller_clk_hz();
- if (!*rate) {
- printf("SPI: clock rate is zero");
- return -EINVAL;
- }
-
- return 0;
+ return cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
- printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
- printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
- printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
- printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
- printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000);
- printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
- printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+ printf("MPU %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_MPU_CLK));
+ printf("L3 main %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_NOC_CLK));
+ printf("Main VCO %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_MAIN_PLL_CLK));
+ printf("Per VCO %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_PERIPH_PLL_CLK));
+ printf("EOSC1 %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_OSC1));
+ printf("HPS MMC %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));
+ printf("UART %d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 5dcbda9473e..e5ff0648b86 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,177 +1,13 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*
*/
-#ifndef _CLOCK_MANAGER_S10_
-#define _CLOCK_MANAGER_S10_
+#ifndef _CLOCK_MANAGER_S10_
+#define _CLOCK_MANAGER_S10_
#include <asm/arch/clock_manager_soc64.h>
-#include <linux/bitops.h>
-
-/* Clock speed accessors */
-unsigned long cm_get_sdram_clk_hz(void);
-unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_spi_controller_clk_hz(void);
-
-struct cm_config {
- /* main group */
- u32 main_pll_mpuclk;
- u32 main_pll_nocclk;
- u32 main_pll_cntr2clk;
- u32 main_pll_cntr3clk;
- u32 main_pll_cntr4clk;
- u32 main_pll_cntr5clk;
- u32 main_pll_cntr6clk;
- u32 main_pll_cntr7clk;
- u32 main_pll_cntr8clk;
- u32 main_pll_cntr9clk;
- u32 main_pll_nocdiv;
- u32 main_pll_pllglob;
- u32 main_pll_fdbck;
- u32 main_pll_pllc0;
- u32 main_pll_pllc1;
- u32 spare;
-
- /* peripheral group */
- u32 per_pll_cntr2clk;
- u32 per_pll_cntr3clk;
- u32 per_pll_cntr4clk;
- u32 per_pll_cntr5clk;
- u32 per_pll_cntr6clk;
- u32 per_pll_cntr7clk;
- u32 per_pll_cntr8clk;
- u32 per_pll_cntr9clk;
- u32 per_pll_emacctl;
- u32 per_pll_gpiodiv;
- u32 per_pll_pllglob;
- u32 per_pll_fdbck;
- u32 per_pll_pllc0;
- u32 per_pll_pllc1;
-
- /* incoming clock */
- u32 hps_osc_clk_hz;
- u32 fpga_clk_hz;
-};
-
-void cm_basic_init(const struct cm_config * const cfg);
-
-/* Control status */
-#define CLKMGR_S10_CTRL 0x00
-#define CLKMGR_S10_STAT 0x04
-#define CLKMGR_S10_INTRCLR 0x14
-/* Mainpll group */
-#define CLKMGR_S10_MAINPLL_EN 0x30
-#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
-#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
-#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
-#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
-#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
-#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
-#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
-#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
-#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
-#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
-#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
-#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
-#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
-#define CLKMGR_S10_MAINPLL_FDBCK 0x78
-#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
-#define CLKMGR_S10_MAINPLL_PLLC0 0x84
-#define CLKMGR_S10_MAINPLL_PLLC1 0x88
-#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
-/* Periphpll group */
-#define CLKMGR_S10_PERPLL_EN 0xa4
-#define CLKMGR_S10_PERPLL_BYPASS 0xb0
-#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
-#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
-#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
-#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
-#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
-#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
-#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
-#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
-#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
-#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
-#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
-#define CLKMGR_S10_PERPLL_FDBCK 0xe8
-#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
-#define CLKMGR_S10_PERPLL_PLLC0 0xf4
-#define CLKMGR_S10_PERPLL_PLLC1 0xf8
-#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
-
-#define CLKMGR_STAT CLKMGR_S10_STAT
-#define CLKMGR_INTER CLKMGR_S10_INTER
-#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
-
-#define CLKMGR_CTRL_SAFEMODE BIT(0)
-#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
-#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
-
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
-#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
-#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
-#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
-#define CLKMGR_STAT_BUSY BIT(0)
-#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
-#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
-
-#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
-#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
-#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3
-#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
-#define CLKMGR_VCO_PSRC_EOSC1 0
-#define CLKMGR_VCO_PSRC_INTOSC 1
-#define CLKMGR_VCO_PSRC_F2S 2
-#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f
-#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
-
-#define CLKMGR_CLKSRC_MASK 0x7
-#define CLKMGR_CLKSRC_OFFSET 16
-#define CLKMGR_CLKSRC_MAIN 0
-#define CLKMGR_CLKSRC_PER 1
-#define CLKMGR_CLKSRC_OSC1 2
-#define CLKMGR_CLKSRC_INTOSC 3
-#define CLKMGR_CLKSRC_FPGA 4
-#define CLKMGR_CLKCNT_MSK 0x7ff
-
-#define CLKMGR_FDBCK_MDIV_MASK 0xff
-#define CLKMGR_FDBCK_MDIV_OFFSET 24
-
-#define CLKMGR_PLLC0_DIV_MASK 0xff
-#define CLKMGR_PLLC1_DIV_MASK 0xff
-#define CLKMGR_PLLC0_EN_OFFSET 27
-#define CLKMGR_PLLC1_EN_OFFSET 24
-
-#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
-#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
-#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
-#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
-#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
-#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
-
-#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3
-#define CLKMGR_NOCDIV_DIV1 0
-#define CLKMGR_NOCDIV_DIV2 1
-#define CLKMGR_NOCDIV_DIV4 2
-#define CLKMGR_NOCDIV_DIV8 3
-#define CLKMGR_CSPDBGCLK_DIV1 0
-#define CLKMGR_CSPDBGCLK_DIV4 1
-
-#define CLKMGR_MSCNT_CONST 200
-#define CLKMGR_MDIV_CONST 6
-#define CLKMGR_HSCNT_CONST 9
-
-#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
-#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
-#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
-
-#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
-#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
-#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
-
-#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#include "../../../../../drivers/clk/altera/clk-s10.h"
#endif /* _CLOCK_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 418d7dfb572..6d7128c77be 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -276,7 +276,8 @@ void socfpga_get_managers_addr(void)
&socfpga_clkmgr_base);
else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
- !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10))
ret = socfpga_get_base_addr("altr,clk-mgr",
&socfpga_clkmgr_base);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index b05bec2cbc1..ace029557f3 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -37,7 +37,6 @@ u32 reset_flag(void)
void board_init_f(ulong dummy)
{
- const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
struct udevice *dev;
@@ -75,7 +74,11 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
/* configuring the HPS clocks */
- cm_basic_init(cm_default_cfg);
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ hang();
+ }
#ifdef CONFIG_DEBUG_UART
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 693446b3d89..e961d059820 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o
obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o
obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o
+obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += clk-s10.o
diff --git a/drivers/clk/altera/clk-s10.c b/drivers/clk/altera/clk-s10.c
new file mode 100644
index 00000000000..c6492e0cb43
--- /dev/null
+++ b/drivers/clk/altera/clk-s10.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <log.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <dt-bindings/clock/stratix10-clock.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <asm/arch/clock_manager.h>
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+ int pllgrp;
+ int bitmask;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ void __iomem *base = plat->regs;
+
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+
+ wait_for_bit_le32(base + CLKMGR_STAT,
+ CLKMGR_STAT_BUSY, false, 20000, false);
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ void __iomem *base = plat->regs;
+
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+
+ wait_for_bit_le32(base + CLKMGR_STAT,
+ CLKMGR_STAT_BUSY, false, 20000, false);
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ void __iomem *base = plat->regs;
+
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+
+ wait_for_bit_le32(base + CLKMGR_STAT,
+ CLKMGR_STAT_BUSY, false, 20000, false);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+ u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+
+ if (!cfg)
+ return;
+
+ /* Put all plls in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* setup main PLL dividers where calculate the vcocalib value */
+ mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+ CLKMGR_FDBCK_MDIV_MASK;
+ refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+ mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+ hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+ CLKMGR_HSCNT_CONST;
+ vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+ ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+ CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+ writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+ ~CLKMGR_PLLGLOB_RST_MASK),
+ base_addr + CLKMGR_MAINPLL_PLLGLOB);
+ writel(cfg->main_pll_fdbck,
+ base_addr + CLKMGR_MAINPLL_FDBCK);
+ writel(vcocalib,
+ base_addr + CLKMGR_MAINPLL_VCOCALIB);
+ writel(cfg->main_pll_pllc0,
+ base_addr + CLKMGR_MAINPLL_PLLC0);
+ writel(cfg->main_pll_pllc1,
+ base_addr + CLKMGR_MAINPLL_PLLC1);
+ writel(cfg->main_pll_nocdiv,
+ base_addr + CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral PLL dividers */
+ /* calculate the vcocalib value */
+ mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+ CLKMGR_FDBCK_MDIV_MASK;
+ refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+ mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+ hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+ CLKMGR_HSCNT_CONST;
+ vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+ ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+ CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+ writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+ ~CLKMGR_PLLGLOB_RST_MASK),
+ base_addr + CLKMGR_PERPLL_PLLGLOB);
+ writel(cfg->per_pll_fdbck,
+ base_addr + CLKMGR_PERPLL_FDBCK);
+ writel(vcocalib,
+ base_addr + CLKMGR_PERPLL_VCOCALIB);
+ writel(cfg->per_pll_pllc0,
+ base_addr + CLKMGR_PERPLL_PLLC0);
+ writel(cfg->per_pll_pllc1,
+ base_addr + CLKMGR_PERPLL_PLLC1);
+ writel(cfg->per_pll_emacctl,
+ base_addr + CLKMGR_PERPLL_EMACCTL);
+ writel(cfg->per_pll_gpiodiv,
+ base_addr + CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ setbits_le32(base_addr + CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+ setbits_le32(base_addr + CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+ CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
+
+ /*
+ * Dividers for C2 to C9 only init after PLLs are lock. As dividers
+ * only take effect upon value change, we shall set a maximum value as
+ * default value.
+ */
+ writel(0xff, base_addr + CLKMGR_MAINPLL_MPUCLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_NOCCLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR2CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR3CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR4CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR5CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR6CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR7CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR8CLK);
+ writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR9CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR2CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR3CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR4CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR5CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR6CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR7CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR8CLK);
+ writel(0xff, base_addr + CLKMGR_PERPLL_CNTR9CLK);
+
+ writel(cfg->main_pll_mpuclk,
+ base_addr + CLKMGR_MAINPLL_MPUCLK);
+ writel(cfg->main_pll_nocclk,
+ base_addr + CLKMGR_MAINPLL_NOCCLK);
+ writel(cfg->main_pll_cntr2clk,
+ base_addr + CLKMGR_MAINPLL_CNTR2CLK);
+ writel(cfg->main_pll_cntr3clk,
+ base_addr + CLKMGR_MAINPLL_CNTR3CLK);
+ writel(cfg->main_pll_cntr4clk,
+ base_addr + CLKMGR_MAINPLL_CNTR4CLK);
+ writel(cfg->main_pll_cntr5clk,
+ base_addr + CLKMGR_MAINPLL_CNTR5CLK);
+ writel(cfg->main_pll_cntr6clk,
+ base_addr + CLKMGR_MAINPLL_CNTR6CLK);
+ writel(cfg->main_pll_cntr7clk,
+ base_addr + CLKMGR_MAINPLL_CNTR7CLK);
+ writel(cfg->main_pll_cntr8clk,
+ base_addr + CLKMGR_MAINPLL_CNTR8CLK);
+ writel(cfg->main_pll_cntr9clk,
+ base_addr + CLKMGR_MAINPLL_CNTR9CLK);
+ writel(cfg->per_pll_cntr2clk,
+ base_addr + CLKMGR_PERPLL_CNTR2CLK);
+ writel(cfg->per_pll_cntr3clk,
+ base_addr + CLKMGR_PERPLL_CNTR3CLK);
+ writel(cfg->per_pll_cntr4clk,
+ base_addr + CLKMGR_PERPLL_CNTR4CLK);
+ writel(cfg->per_pll_cntr5clk,
+ base_addr + CLKMGR_PERPLL_CNTR5CLK);
+ writel(cfg->per_pll_cntr6clk,
+ base_addr + CLKMGR_PERPLL_CNTR6CLK);
+ writel(cfg->per_pll_cntr7clk,
+ base_addr + CLKMGR_PERPLL_CNTR7CLK);
+ writel(cfg->per_pll_cntr8clk,
+ base_addr + CLKMGR_PERPLL_CNTR8CLK);
+ writel(cfg->per_pll_cntr9clk,
+ base_addr + CLKMGR_PERPLL_CNTR9CLK);
+
+ /* Take all PLLs out of bypass */
+ clk_write_bypass_mainpll(plat, 0);
+ clk_write_bypass_perpll(plat, 0);
+
+#ifdef COUNTER_FREQUENCY_REAL
+ u32 cntfrq = COUNTER_FREQUENCY_REAL;
+ u32 counter_freq = 0;
+
+ /* Update with accurate clock frequency */
+ if (current_el() == 3) {
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq));
+ debug("Counter freq = 0x%x\n", counter_freq);
+ }
+#endif
+
+ /* clear safe mode / out of boot mode */
+ clk_write_ctrl(plat, readl(base_addr + CLKMGR_CTRL) &
+ ~(CLKMGR_CTRL_SAFEMODE));
+
+ /* Now ungate non-hw-managed clocks */
+ writel(~0, base_addr + CLKMGR_MAINPLL_EN);
+ writel(~0, base_addr + CLKMGR_PERPLL_EN);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ writel(CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK,
+ base_addr + CLKMGR_INTRCLR);
+}
+
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
+ u32 pllglob_reg, u32 fdbck_reg)
+{
+ u64 fref, refdiv, mdiv, reg, vco;
+
+ reg = CM_REG_READL(plat, pllglob_reg);
+
+ fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+ CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+
+ switch (fref) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ fref = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_INTOSC:
+ fref = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_F2S:
+ fref = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+ reg = CM_REG_READL(plat, fdbck_reg);
+ mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+ vco = fref / refdiv;
+ vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+
+ return vco;
+}
+
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
+{
+ return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_MAINPLL_FDBCK);
+}
+
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
+{
+ return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PERPLL_FDBCK);
+}
+
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
+{
+ u32 clksrc = CM_REG_READL(plat, reg);
+
+ return (clksrc >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+}
+
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock;
+ u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_MPUCLK);
+
+ switch (clklsrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_main_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) &
+ CLKMGR_PLLC0_DIV_MASK);
+ break;
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_per_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ default:
+ return 0;
+ }
+
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock;
+}
+
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock;
+ u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_NOCCLK);
+
+ switch (clklsrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_main_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) &
+ CLKMGR_PLLC0_DIV_MASK);
+ break;
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_per_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ default:
+ return 0;
+ }
+
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_NOCCLK) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock;
+}
+
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u32 clock;
+ u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_PERPLL_CNTR6CLK);
+
+ switch (clklsrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_l3_main_clk_hz(plat);
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);
+ break;
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_l3_main_clk_hz(plat);
+ clock /= 1 + (CM_REG_READL(plat, CLKMGR_PERPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);
+ break;
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ default:
+ return 0;
+ }
+
+ return clock / 4;
+}
+
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock;
+}
+
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
+{
+ if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
+ return clk_get_l3_main_clk_hz(plat) / 2;
+
+ return clk_get_l3_main_clk_hz(plat) / 4;
+}
+
+static ulong socfpga_clk_get_rate(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case STRATIX10_MPU_CLK:
+ return clk_get_mpu_clk_hz(plat);
+ case STRATIX10_NOC_CLK:
+ return clk_get_l3_main_clk_hz(plat);
+ case STRATIX10_MAIN_PLL_CLK:
+ return clk_get_main_vco_clk_hz(plat);
+ case STRATIX10_PERIPH_PLL_CLK:
+ return clk_get_per_vco_clk_hz(plat);
+ case STRATIX10_OSC1:
+ return cm_get_osc_clk_hz();
+ case STRATIX10_SDMMC_CLK:
+ return clk_get_sdmmc_clk_hz(plat);
+ case STRATIX10_L4_SP_CLK:
+ return clk_get_l4_sp_clk_hz(plat);
+ case STRATIX10_L4_SYS_FREE_CLK:
+ return clk_get_l4_sys_free_clk_hz(plat);
+ default:
+ return -ENXIO;
+ }
+}
+
+static int bitmask_from_clk_id(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case STRATIX10_MPU_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
+ break;
+ case STRATIX10_L4_MAIN_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
+ break;
+ case STRATIX10_L4_MP_CLK:
+ case STRATIX10_NAND_X_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
+ break;
+ case STRATIX10_L4_SP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
+ break;
+ case STRATIX10_CS_AT_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case STRATIX10_CS_TRACE_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case STRATIX10_CS_PDBG_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case STRATIX10_CS_TIMER_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
+ break;
+ case STRATIX10_S2F_USER0_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
+ break;
+ case STRATIX10_EMAC0_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
+ break;
+ case STRATIX10_EMAC1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
+ break;
+ case STRATIX10_EMAC2_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
+ break;
+ case STRATIX10_EMAC_PTP_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
+ break;
+ case STRATIX10_GPIO_DB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
+ break;
+ case STRATIX10_SDMMC_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
+ break;
+ case STRATIX10_S2F_USER1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
+ break;
+ case STRATIX10_PSI_REF_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
+ break;
+ case STRATIX10_USB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
+ break;
+ case STRATIX10_SPI_M_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
+ break;
+ case STRATIX10_NAND_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
+ break;
+ case STRATIX10_L4_SYS_FREE_CLK:
+ return -EOPNOTSUPP;
+ default:
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static int socfpga_clk_enable(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret == -EOPNOTSUPP)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
+ return 0;
+}
+
+static int socfpga_clk_disable(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret == -EOPNOTSUPP)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
+ return 0;
+}
+
+static int socfpga_clk_probe(struct udevice *dev)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+ clk_basic_init(dev, cm_default_cfg);
+
+ return 0;
+}
+
+static int socfpga_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_clk_ops = {
+ .enable = socfpga_clk_enable,
+ .disable = socfpga_clk_disable,
+ .get_rate = socfpga_clk_get_rate,
+};
+
+static const struct udevice_id socfpga_clk_match[] = {
+ { .compatible = "intel,stratix10-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_s10_clk) = {
+ .name = "clk-s10",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_clk_match,
+ .ops = &socfpga_clk_ops,
+ .probe = socfpga_clk_probe,
+ .of_to_plat = socfpga_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_clk_plat),
+};
diff --git a/drivers/clk/altera/clk-s10.h b/drivers/clk/altera/clk-s10.h
new file mode 100644
index 00000000000..f5be1e68500
--- /dev/null
+++ b/drivers/clk/altera/clk-s10.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
+ *
+ */
+
+#ifndef _CLK_S10_
+#define _CLK_S10_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define COUNTER_FREQUENCY_REAL 400000000
+
+#define CM_REG_READL(plat, reg) \
+ readl((plat)->regs + (reg))
+
+#define CM_REG_WRITEL(plat, data, reg) \
+ writel(data, (plat)->regs + (reg))
+
+#define CM_REG_CLRBITS(plat, reg, clear) \
+ clrbits_le32((plat)->regs + (reg), (clear))
+
+#define CM_REG_SETBITS(plat, reg, set) \
+ setbits_le32((plat)->regs + (reg), (set))
+
+struct cm_config {
+ /* main group */
+ u32 main_pll_mpuclk;
+ u32 main_pll_nocclk;
+ u32 main_pll_cntr2clk;
+ u32 main_pll_cntr3clk;
+ u32 main_pll_cntr4clk;
+ u32 main_pll_cntr5clk;
+ u32 main_pll_cntr6clk;
+ u32 main_pll_cntr7clk;
+ u32 main_pll_cntr8clk;
+ u32 main_pll_cntr9clk;
+ u32 main_pll_nocdiv;
+ u32 main_pll_pllglob;
+ u32 main_pll_fdbck;
+ u32 main_pll_pllc0;
+ u32 main_pll_pllc1;
+ u32 spare;
+
+ /* peripheral group */
+ u32 per_pll_cntr2clk;
+ u32 per_pll_cntr3clk;
+ u32 per_pll_cntr4clk;
+ u32 per_pll_cntr5clk;
+ u32 per_pll_cntr6clk;
+ u32 per_pll_cntr7clk;
+ u32 per_pll_cntr8clk;
+ u32 per_pll_cntr9clk;
+ u32 per_pll_emacctl;
+ u32 per_pll_gpiodiv;
+ u32 per_pll_pllglob;
+ u32 per_pll_fdbck;
+ u32 per_pll_pllc0;
+ u32 per_pll_pllc1;
+
+ /* incoming clock */
+ u32 hps_osc_clk_hz;
+ u32 fpga_clk_hz;
+};
+
+/* Control status */
+#define CLKMGR_CTRL 0x00
+#define CLKMGR_STAT 0x04
+#define CLKMGR_INTRCLR 0x14
+/* Mainpll group */
+#define CLKMGR_MAINPLL_EN 0x30
+#define CLKMGR_MAINPLL_BYPASS 0x3c
+#define CLKMGR_MAINPLL_MPUCLK 0x48
+#define CLKMGR_MAINPLL_NOCCLK 0x4c
+#define CLKMGR_MAINPLL_CNTR2CLK 0x50
+#define CLKMGR_MAINPLL_CNTR3CLK 0x54
+#define CLKMGR_MAINPLL_CNTR4CLK 0x58
+#define CLKMGR_MAINPLL_CNTR5CLK 0x5c
+#define CLKMGR_MAINPLL_CNTR6CLK 0x60
+#define CLKMGR_MAINPLL_CNTR7CLK 0x64
+#define CLKMGR_MAINPLL_CNTR8CLK 0x68
+#define CLKMGR_MAINPLL_CNTR9CLK 0x6c
+#define CLKMGR_MAINPLL_NOCDIV 0x70
+#define CLKMGR_MAINPLL_PLLGLOB 0x74
+#define CLKMGR_MAINPLL_FDBCK 0x78
+#define CLKMGR_MAINPLL_MEMSTAT 0x80
+#define CLKMGR_MAINPLL_PLLC0 0x84
+#define CLKMGR_MAINPLL_PLLC1 0x88
+#define CLKMGR_MAINPLL_VCOCALIB 0x8c
+/* Periphpll group */
+#define CLKMGR_PERPLL_EN 0xa4
+#define CLKMGR_PERPLL_BYPASS 0xb0
+#define CLKMGR_PERPLL_CNTR2CLK 0xbc
+#define CLKMGR_PERPLL_CNTR3CLK 0xc0
+#define CLKMGR_PERPLL_CNTR4CLK 0xc4
+#define CLKMGR_PERPLL_CNTR5CLK 0xc8
+#define CLKMGR_PERPLL_CNTR6CLK 0xcc
+#define CLKMGR_PERPLL_CNTR7CLK 0xd0
+#define CLKMGR_PERPLL_CNTR8CLK 0xd4
+#define CLKMGR_PERPLL_CNTR9CLK 0xd8
+#define CLKMGR_PERPLL_EMACCTL 0xdc
+#define CLKMGR_PERPLL_GPIODIV 0xe0
+#define CLKMGR_PERPLL_PLLGLOB 0xe4
+#define CLKMGR_PERPLL_FDBCK 0xe8
+#define CLKMGR_PERPLL_MEMSTAT 0xf0
+#define CLKMGR_PERPLL_PLLC0 0xf4
+#define CLKMGR_PERPLL_PLLC1 0xf8
+#define CLKMGR_PERPLL_VCOCALIB 0xfc
+
+#define CLKMGR_CTRL_SAFEMODE BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
+#define CLKMGR_STAT_BUSY BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
+#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
+#define CLKMGR_STAT_BOOTMODE BIT(16)
+
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
+ (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
+
+#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
+#define CLKMGR_VCO_PSRC_EOSC1 0
+#define CLKMGR_VCO_PSRC_INTOSC 1
+#define CLKMGR_VCO_PSRC_F2S 2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
+
+#define CLKMGR_CLKSRC_MASK 0x7
+#define CLKMGR_CLKSRC_OFFSET 16
+#define CLKMGR_CLKSRC_MAIN 0
+#define CLKMGR_CLKSRC_PER 1
+#define CLKMGR_CLKSRC_OSC1 2
+#define CLKMGR_CLKSRC_INTOSC 3
+#define CLKMGR_CLKSRC_FPGA 4
+#define CLKMGR_CLKCNT_MSK 0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK 0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET 24
+
+#define CLKMGR_PLLC0_DIV_MASK 0xff
+#define CLKMGR_PLLC1_DIV_MASK 0xff
+#define CLKMGR_PLLC0_EN_OFFSET 27
+#define CLKMGR_PLLC1_EN_OFFSET 24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3
+#define CLKMGR_NOCDIV_DIV1 0
+#define CLKMGR_NOCDIV_DIV2 1
+#define CLKMGR_NOCDIV_DIV4 2
+#define CLKMGR_NOCDIV_DIV8 3
+#define CLKMGR_CSPDBGCLK_DIV1 0
+#define CLKMGR_CSPDBGCLK_DIV4 1
+
+#define CLKMGR_MSCNT_CONST 200
+#define CLKMGR_MDIV_CONST 6
+#define CLKMGR_HSCNT_CONST 9
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
+#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
+
+#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1)
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3)
+#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6)
+
+#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0)
+#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1)
+#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2)
+#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3)
+#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4)
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6)
+#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7)
+#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8)
+#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9)
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10)
+
+#endif /* _CLK_S10_ */
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 7/9] clk: s10: Refactor S10 clock driver
2026-04-28 3:48 ` [PATCH v2 7/9] clk: s10: Refactor S10 clock driver alif.zakuan.yuslaimi
@ 2026-05-08 5:48 ` Chee, Tien Fong
2026-05-14 5:47 ` Yuslaimi, Alif Zakuan
0 siblings, 1 reply; 19+ messages in thread
From: Chee, Tien Fong @ 2026-05-08 5:48 UTC (permalink / raw)
To: alif.zakuan.yuslaimi, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Alif,
On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>
> Refactor Stratix10 clock manager driver to support driver model, following
> Agilex clock driver.
>
> Create a new clock driver, clk-s10.c, for Stratix10 which supports the
> driver model. This allows several APIs such as enable/disable clock, and
> get clock rate to be supported.
>
> This driver will be initialized during SPL to bring up the clock as early
> as possible. The clock initialization process are refactored into this new
> driver from clock_manager_s10.c during clock driver probe.
>
> Excluding Stratix10 from legacy method of obtaining clkmgr base address in
> mach-socfpga/misc.c as the base address is already obtained during clock
> driver probe during SPL initialization.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
> ---
> MAINTAINERS | 1 +
> arch/arm/mach-socfpga/Kconfig | 2 +
> arch/arm/mach-socfpga/clock_manager_s10.c | 449 ++-----------
> .../include/mach/clock_manager_s10.h | 176 +----
> arch/arm/mach-socfpga/misc.c | 3 +-
> arch/arm/mach-socfpga/spl_s10.c | 7 +-
> drivers/clk/altera/Makefile | 1 +
> drivers/clk/altera/clk-s10.c | 603 ++++++++++++++++++
> drivers/clk/altera/clk-s10.h | 202 ++++++
> 9 files changed, 873 insertions(+), 571 deletions(-)
> create mode 100644 drivers/clk/altera/clk-s10.c
> create mode 100644 drivers/clk/altera/clk-s10.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d1173126fc6..032f0ee97fc 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -159,6 +159,7 @@ F: arch/arm/mach-socfpga/
> F: board/altera/stratix10-socdk/
> F: board/intel/agilex-socdk/
> F: configs/socfpga_*
> +F: drivers/clk/altera/
> F: drivers/ddr/altera/
> F: drivers/power/domain/altr-pmgr-agilex5.c
> F: drivers/sysreset/sysreset_socfpga*
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index fb98b647442..aa1f3e761cd 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -146,8 +146,10 @@ config ARCH_SOCFPGA_STRATIX10
> select ARMV8_MULTIENTRY
> select ARMV8_SET_SMPEN
> select BINMAN if SPL_ATF
> + select CLK
> select FPGA_INTEL_SDM_MAILBOX
> select GICV2
> + select SPL_CLK if SPL
> select ARCH_SOCFPGA_SOC64
>
> choice
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> index fd27470f967..df636f14f93 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -1,425 +1,78 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
all prior copyright notices to be retained
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> *
> */
>
> -#include <compiler.h>
> -#include <dm/device.h>
> -#include <linux/errno.h>
> -#include <asm/io.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <log.h>
> +#include <malloc.h>
> #include <asm/arch/clock_manager.h>
> -#include <asm/arch/handoff_soc64.h>
> #include <asm/arch/system_manager.h>
> +#include <asm/io.h>
> +#include <dt-bindings/clock/stratix10-clock.h>
>
> -/*
> - * function to write the bypass register which requires a poll of the
> - * busy bit
> - */
> -static void cm_write_bypass_mainpll(u32 val)
> -{
> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
> - cm_wait_for_fsm();
> -}
> -
> -static void cm_write_bypass_perpll(u32 val)
> -{
> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
> - cm_wait_for_fsm();
> -}
> -
> -/* function to write the ctrl register which requires a poll of the busy bit */
> -static void cm_write_ctrl(u32 val)
> -{
> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
> - cm_wait_for_fsm();
> -}
> -
> -/*
> - * Setup clocks while making no assumptions about previous state of the clocks.
> - */
> -void cm_basic_init(const struct cm_config * const cfg)
> -{
> - u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
> -
> - if (cfg == 0)
> - return;
> -
> - /* Put all plls in bypass */
> - cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
> - cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
> -
> - /* setup main PLL dividers where calculate the vcocalib value */
> - mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> - CLKMGR_FDBCK_MDIV_MASK;
> - refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> - mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> - hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> - CLKMGR_HSCNT_CONST;
> - vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> - ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> - CLKMGR_VCOCALIB_MSCNT_OFFSET);
> -
> - writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> - ~CLKMGR_PLLGLOB_RST_MASK),
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
> - writel(cfg->main_pll_fdbck,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
> - writel(vcocalib,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
> - writel(cfg->main_pll_pllc0,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
> - writel(cfg->main_pll_pllc1,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
> - writel(cfg->main_pll_nocdiv,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
> -
> - /* setup peripheral PLL dividers */
> - /* calculate the vcocalib value */
> - mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> - CLKMGR_FDBCK_MDIV_MASK;
> - refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> - mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> - hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> - CLKMGR_HSCNT_CONST;
> - vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> - ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> - CLKMGR_VCOCALIB_MSCNT_OFFSET);
> -
> - writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> - ~CLKMGR_PLLGLOB_RST_MASK),
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
> - writel(cfg->per_pll_fdbck,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
> - writel(vcocalib,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
> - writel(cfg->per_pll_pllc0,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
> - writel(cfg->per_pll_pllc1,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
> - writel(cfg->per_pll_emacctl,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
> - writel(cfg->per_pll_gpiodiv,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
> -
> - /* Take both PLL out of reset and power up */
> - setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
> - CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> - setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
> - CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> -
> -#define LOCKED_MASK \
> - (CLKMGR_STAT_MAINPLL_LOCKED | \
> - CLKMGR_STAT_PERPLL_LOCKED)
> -
> - cm_wait_for_lock(LOCKED_MASK);
> -
> - /*
> - * Dividers for C2 to C9 only init after PLLs are lock. As dividers
> - * only take effect upon value change, we shall set a maximum value as
> - * default value.
> - */
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
> -
> - writel(cfg->main_pll_mpuclk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
> - writel(cfg->main_pll_nocclk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
> - writel(cfg->main_pll_cntr2clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
> - writel(cfg->main_pll_cntr3clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
> - writel(cfg->main_pll_cntr4clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
> - writel(cfg->main_pll_cntr5clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
> - writel(cfg->main_pll_cntr6clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
> - writel(cfg->main_pll_cntr7clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
> - writel(cfg->main_pll_cntr8clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
> - writel(cfg->main_pll_cntr9clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
> - writel(cfg->per_pll_cntr2clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
> - writel(cfg->per_pll_cntr3clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
> - writel(cfg->per_pll_cntr4clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
> - writel(cfg->per_pll_cntr5clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
> - writel(cfg->per_pll_cntr6clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
> - writel(cfg->per_pll_cntr7clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
> - writel(cfg->per_pll_cntr8clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
> - writel(cfg->per_pll_cntr9clk,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
> -
> - /* Take all PLLs out of bypass */
> - cm_write_bypass_mainpll(0);
> - cm_write_bypass_perpll(0);
> -
> - /* clear safe mode / out of boot mode */
> - cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
> - ~(CLKMGR_CTRL_SAFEMODE));
> -
> - /* Now ungate non-hw-managed clocks */
> - writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
> - writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
> -
> - /* Clear the loss of lock bits (write 1 to clear) */
> - writel(CLKMGR_INTER_PERPLLLOST_MASK |
> - CLKMGR_INTER_MAINPLLLOST_MASK,
> - socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
> -}
> -
> -static unsigned long cm_get_main_vco_clk_hz(void)
> +static ulong cm_get_rate_dm(u32 id)
> {
> - unsigned long fref, refdiv, mdiv, reg, vco;
> -
> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
> -
> - fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> - CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> - switch (fref) {
> - case CLKMGR_VCO_PSRC_EOSC1:
> - fref = cm_get_osc_clk_hz();
> - break;
> - case CLKMGR_VCO_PSRC_INTOSC:
> - fref = cm_get_intosc_clk_hz();
> - break;
> - case CLKMGR_VCO_PSRC_F2S:
> - fref = cm_get_fpga_clk_hz();
> - break;
> + struct udevice *dev;
> + struct clk clk;
> + ulong rate;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(socfpga_s10_clk),
> + &dev);
> + if (ret)
> + return 0;
> +
> + clk.id = id;
> + ret = clk_request(dev, &clk);
> + if (ret < 0)
> + return 0;
> +
> + rate = clk_get_rate(&clk);
> +
> + if ((rate == (unsigned long)-ENOSYS) ||
> + (rate == (unsigned long)-ENXIO) ||
> + (rate == (unsigned long)-EIO)) {
> + debug("%s id %u: clk_get_rate err: %ld\n",
> + __func__, id, rate);
> + return 0;
> }
>
> - refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> -
> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
> - mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> -
> - vco = fref / refdiv;
> - vco = vco * (CLKMGR_MDIV_CONST + mdiv);
> - return vco;
> + return rate;
> }
>
> -static unsigned long cm_get_per_vco_clk_hz(void)
> +static u32 cm_get_rate_dm_khz(u32 id)
> {
> - unsigned long fref, refdiv, mdiv, reg, vco;
> -
> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
> -
> - fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> - CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> - switch (fref) {
> - case CLKMGR_VCO_PSRC_EOSC1:
> - fref = cm_get_osc_clk_hz();
> - break;
> - case CLKMGR_VCO_PSRC_INTOSC:
> - fref = cm_get_intosc_clk_hz();
> - break;
> - case CLKMGR_VCO_PSRC_F2S:
> - fref = cm_get_fpga_clk_hz();
> - break;
> - }
> -
> - refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> -
> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
> - mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> -
> - vco = fref / refdiv;
> - vco = vco * (CLKMGR_MDIV_CONST + mdiv);
> - return vco;
> + return cm_get_rate_dm(id) / 1000;
> }
>
> unsigned long cm_get_mpu_clk_hz(void)
> {
> - unsigned long clock = readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_MPUCLK);
> -
> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> -
> - switch (clock) {
> - case CLKMGR_CLKSRC_MAIN:
> - clock = cm_get_main_vco_clk_hz();
> - clock /= (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_PLLC0) &
> - CLKMGR_PLLC0_DIV_MASK);
> - break;
> -
> - case CLKMGR_CLKSRC_PER:
> - clock = cm_get_per_vco_clk_hz();
> - clock /= (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_PERPLL_PLLC0) &
> - CLKMGR_CLKCNT_MSK);
> - break;
> -
> - case CLKMGR_CLKSRC_OSC1:
> - clock = cm_get_osc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_INTOSC:
> - clock = cm_get_intosc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_FPGA:
> - clock = cm_get_fpga_clk_hz();
> - break;
> - }
> -
> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
> - return clock;
> -}
> -
> -unsigned int cm_get_l3_main_clk_hz(void)
> -{
> - u32 clock = readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_NOCCLK);
> -
> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> -
> - switch (clock) {
> - case CLKMGR_CLKSRC_MAIN:
> - clock = cm_get_main_vco_clk_hz();
> - clock /= (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_PLLC1) &
> - CLKMGR_PLLC0_DIV_MASK);
> - break;
> -
> - case CLKMGR_CLKSRC_PER:
> - clock = cm_get_per_vco_clk_hz();
> - clock /= (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
> - break;
> -
> - case CLKMGR_CLKSRC_OSC1:
> - clock = cm_get_osc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_INTOSC:
> - clock = cm_get_intosc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_FPGA:
> - clock = cm_get_fpga_clk_hz();
> - break;
> - }
> -
> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
> - return clock;
> -}
> -
> -unsigned int cm_get_mmc_controller_clk_hz(void)
> -{
> - u32 clock = readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_PERPLL_CNTR6CLK);
> -
> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> -
> - switch (clock) {
> - case CLKMGR_CLKSRC_MAIN:
> - clock = cm_get_l3_main_clk_hz();
> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_CNTR6CLK) &
> - CLKMGR_CLKCNT_MSK);
> - break;
> -
> - case CLKMGR_CLKSRC_PER:
> - clock = cm_get_l3_main_clk_hz();
> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_PERPLL_CNTR6CLK) &
> - CLKMGR_CLKCNT_MSK);
> - break;
> -
> - case CLKMGR_CLKSRC_OSC1:
> - clock = cm_get_osc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_INTOSC:
> - clock = cm_get_intosc_clk_hz();
> - break;
> -
> - case CLKMGR_CLKSRC_FPGA:
> - clock = cm_get_fpga_clk_hz();
> - break;
> - }
> - return clock / 4;
> -}
> -
> -unsigned int cm_get_l4_sp_clk_hz(void)
> -{
> - u32 clock = cm_get_l3_main_clk_hz();
> -
> - clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_NOCDIV) >>
> - CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> - return clock;
> -}
> -
> -unsigned int cm_get_spi_controller_clk_hz(void)
> -{
> - u32 clock = cm_get_l3_main_clk_hz();
> -
> - clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
> - CLKMGR_S10_MAINPLL_NOCDIV) >>
> - CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
> - return clock;
> + return cm_get_rate_dm(STRATIX10_MPU_CLK);
> }
>
> unsigned int cm_get_l4_sys_free_clk_hz(void)
> {
> - return cm_get_l3_main_clk_hz() / 4;
> -}
> -
> -/*
> - * Override weak dw_spi_get_clk implementation in designware_spi.c driver
> - */
> -
> -int dw_spi_get_clk(struct udevice *bus, ulong *rate)
> -{
> - *rate = cm_get_spi_controller_clk_hz();
> - if (!*rate) {
> - printf("SPI: clock rate is zero");
> - return -EINVAL;
> - }
> -
> - return 0;
The dw_spi_get_clk() removal and the missing STRATIX10_L4_MAIN_CLK(from
upstream dts) in socfpga_clk_get_rate() have impacted
the use case where someone enables spi@ffda4000 or spi@ffda5000 in a
board DTS for a general-purpose SPI peripheral (not the use case spi0 =
&qspi alias)
> + return cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);
> }
>
> void cm_print_clock_quick_summary(void)
> {
> - printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
> - printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
> - printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
> - printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
> - printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000);
> - printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
> - printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
> + printf("MPU %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_MPU_CLK));
> + printf("L3 main %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_NOC_CLK));
> + printf("Main VCO %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_MAIN_PLL_CLK));
> + printf("Per VCO %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_PERIPH_PLL_CLK));
> + printf("EOSC1 %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_OSC1));
> + printf("HPS MMC %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));
> + printf("UART %d kHz\n",
> + cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));
> }
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index 5dcbda9473e..e5ff0648b86 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -1,177 +1,13 @@
> -/* SPDX-License-Identifier: GPL-2.0
> - *
> - * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
all prior copyright notices to be retained
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> *
> */
>
> -#ifndef _CLOCK_MANAGER_S10_
> -#define _CLOCK_MANAGER_S10_
> +#ifndef _CLOCK_MANAGER_S10_
> +#define _CLOCK_MANAGER_S10_
>
> #include <asm/arch/clock_manager_soc64.h>
> -#include <linux/bitops.h>
> -
> -/* Clock speed accessors */
> -unsigned long cm_get_sdram_clk_hz(void);
> -unsigned int cm_get_l4_sp_clk_hz(void);
> -unsigned int cm_get_mmc_controller_clk_hz(void);
> -unsigned int cm_get_spi_controller_clk_hz(void);
> -
> -struct cm_config {
> - /* main group */
> - u32 main_pll_mpuclk;
> - u32 main_pll_nocclk;
> - u32 main_pll_cntr2clk;
> - u32 main_pll_cntr3clk;
> - u32 main_pll_cntr4clk;
> - u32 main_pll_cntr5clk;
> - u32 main_pll_cntr6clk;
> - u32 main_pll_cntr7clk;
> - u32 main_pll_cntr8clk;
> - u32 main_pll_cntr9clk;
> - u32 main_pll_nocdiv;
> - u32 main_pll_pllglob;
> - u32 main_pll_fdbck;
> - u32 main_pll_pllc0;
> - u32 main_pll_pllc1;
> - u32 spare;
> -
> - /* peripheral group */
> - u32 per_pll_cntr2clk;
> - u32 per_pll_cntr3clk;
> - u32 per_pll_cntr4clk;
> - u32 per_pll_cntr5clk;
> - u32 per_pll_cntr6clk;
> - u32 per_pll_cntr7clk;
> - u32 per_pll_cntr8clk;
> - u32 per_pll_cntr9clk;
> - u32 per_pll_emacctl;
> - u32 per_pll_gpiodiv;
> - u32 per_pll_pllglob;
> - u32 per_pll_fdbck;
> - u32 per_pll_pllc0;
> - u32 per_pll_pllc1;
> -
> - /* incoming clock */
> - u32 hps_osc_clk_hz;
> - u32 fpga_clk_hz;
> -};
> -
> -void cm_basic_init(const struct cm_config * const cfg);
> -
> -/* Control status */
> -#define CLKMGR_S10_CTRL 0x00
> -#define CLKMGR_S10_STAT 0x04
> -#define CLKMGR_S10_INTRCLR 0x14
> -/* Mainpll group */
> -#define CLKMGR_S10_MAINPLL_EN 0x30
> -#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
> -#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
> -#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
> -#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
> -#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
> -#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
> -#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
> -#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
> -#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
> -#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
> -#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
> -#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
> -#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
> -#define CLKMGR_S10_MAINPLL_FDBCK 0x78
> -#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
> -#define CLKMGR_S10_MAINPLL_PLLC0 0x84
> -#define CLKMGR_S10_MAINPLL_PLLC1 0x88
> -#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
> -/* Periphpll group */
> -#define CLKMGR_S10_PERPLL_EN 0xa4
> -#define CLKMGR_S10_PERPLL_BYPASS 0xb0
> -#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
> -#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
> -#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
> -#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
> -#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
> -#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
> -#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
> -#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
> -#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
> -#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
> -#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
> -#define CLKMGR_S10_PERPLL_FDBCK 0xe8
> -#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
> -#define CLKMGR_S10_PERPLL_PLLC0 0xf4
> -#define CLKMGR_S10_PERPLL_PLLC1 0xf8
> -#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
> -
> -#define CLKMGR_STAT CLKMGR_S10_STAT
> -#define CLKMGR_INTER CLKMGR_S10_INTER
> -#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
> -
> -#define CLKMGR_CTRL_SAFEMODE BIT(0)
> -#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
> -#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
> -
> -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
> -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
> -#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
> -#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
> -#define CLKMGR_STAT_BUSY BIT(0)
> -#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
> -#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
> -
> -#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
> -#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
> -#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3
> -#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
> -#define CLKMGR_VCO_PSRC_EOSC1 0
> -#define CLKMGR_VCO_PSRC_INTOSC 1
> -#define CLKMGR_VCO_PSRC_F2S 2
> -#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f
> -#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
> -
> -#define CLKMGR_CLKSRC_MASK 0x7
> -#define CLKMGR_CLKSRC_OFFSET 16
> -#define CLKMGR_CLKSRC_MAIN 0
> -#define CLKMGR_CLKSRC_PER 1
> -#define CLKMGR_CLKSRC_OSC1 2
> -#define CLKMGR_CLKSRC_INTOSC 3
> -#define CLKMGR_CLKSRC_FPGA 4
> -#define CLKMGR_CLKCNT_MSK 0x7ff
> -
> -#define CLKMGR_FDBCK_MDIV_MASK 0xff
> -#define CLKMGR_FDBCK_MDIV_OFFSET 24
> -
> -#define CLKMGR_PLLC0_DIV_MASK 0xff
> -#define CLKMGR_PLLC1_DIV_MASK 0xff
> -#define CLKMGR_PLLC0_EN_OFFSET 27
> -#define CLKMGR_PLLC1_EN_OFFSET 24
> -
> -#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
> -#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
> -#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
> -#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
> -#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
> -#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
> -
> -#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3
> -#define CLKMGR_NOCDIV_DIV1 0
> -#define CLKMGR_NOCDIV_DIV2 1
> -#define CLKMGR_NOCDIV_DIV4 2
> -#define CLKMGR_NOCDIV_DIV8 3
> -#define CLKMGR_CSPDBGCLK_DIV1 0
> -#define CLKMGR_CSPDBGCLK_DIV4 1
> -
> -#define CLKMGR_MSCNT_CONST 200
> -#define CLKMGR_MDIV_CONST 6
> -#define CLKMGR_HSCNT_CONST 9
> -
> -#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
> -#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
> -#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
> -
> -#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
> -#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
> -#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
> -
> -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
> +#include "../../../../../drivers/clk/altera/clk-s10.h"
>
> #endif /* _CLOCK_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 418d7dfb572..6d7128c77be 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -276,7 +276,8 @@ void socfpga_get_managers_addr(void)
> &socfpga_clkmgr_base);
> else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
> !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
> - !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))
> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10))
> ret = socfpga_get_base_addr("altr,clk-mgr",
> &socfpga_clkmgr_base);
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index b05bec2cbc1..ace029557f3 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -37,7 +37,6 @@ u32 reset_flag(void)
>
> void board_init_f(ulong dummy)
> {
> - const struct cm_config *cm_default_cfg = cm_get_default_config();
> int ret;
> struct udevice *dev;
>
> @@ -75,7 +74,11 @@ void board_init_f(ulong dummy)
> sysmgr_pinmux_init();
>
> /* configuring the HPS clocks */
> - cm_basic_init(cm_default_cfg);
> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> + if (ret) {
> + debug("Clock init failed: %d\n", ret);
> + hang();
> + }
>
> #ifdef CONFIG_DEBUG_UART
> socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
> index 693446b3d89..e961d059820 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o
> obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o
> obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o
> obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o
> +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += clk-s10.o
> diff --git a/drivers/clk/altera/clk-s10.c b/drivers/clk/altera/clk-s10.c
> new file mode 100644
> index 00000000000..c6492e0cb43
> --- /dev/null
> +++ b/drivers/clk/altera/clk-s10.c
> @@ -0,0 +1,603 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
NEW FILE, but derived from Intel code
Copyright (C) 2016-2023 Intel Corporation <www.intel.com> ← must add
(code origin)
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> + *
> + */
> +
> +#include <log.h>
> +#include <wait_bit.h>
> +#include <asm/io.h>
> +#include <asm/system.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <dm/lists.h>
> +#include <dm/util.h>
> +#include <dt-bindings/clock/stratix10-clock.h>
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <asm/arch/clock_manager.h>
> +
> +struct socfpga_clk_plat {
> + void __iomem *regs;
> + int pllgrp;
> + int bitmask;
> +};
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
> +{
> + void __iomem *base = plat->regs;
> +
> + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
> +
> + wait_for_bit_le32(base + CLKMGR_STAT,
> + CLKMGR_STAT_BUSY, false, 20000, false);
> +}
> +
> +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
> +{
> + void __iomem *base = plat->regs;
> +
> + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
> +
> + wait_for_bit_le32(base + CLKMGR_STAT,
> + CLKMGR_STAT_BUSY, false, 20000, false);
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit */
> +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
> +{
> + void __iomem *base = plat->regs;
> +
> + CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
> +
> + wait_for_bit_le32(base + CLKMGR_STAT,
> + CLKMGR_STAT_BUSY, false, 20000, false);
> +}
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the clocks.
> + */
> +static void clk_basic_init(struct udevice *dev,
> + const struct cm_config * const cfg)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
> + u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
> + uintptr_t base_addr = (uintptr_t)plat->regs;
> +
> + if (!cfg)
> + return;
> +
> + /* Put all plls in bypass */
> + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
> + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
> +
> + /* setup main PLL dividers where calculate the vcocalib value */
> + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> + CLKMGR_FDBCK_MDIV_MASK;
> + refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> + CLKMGR_HSCNT_CONST;
> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> + CLKMGR_VCOCALIB_MSCNT_OFFSET);
> +
> + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> + ~CLKMGR_PLLGLOB_RST_MASK),
> + base_addr + CLKMGR_MAINPLL_PLLGLOB);
> + writel(cfg->main_pll_fdbck,
> + base_addr + CLKMGR_MAINPLL_FDBCK);
> + writel(vcocalib,
> + base_addr + CLKMGR_MAINPLL_VCOCALIB);
> + writel(cfg->main_pll_pllc0,
> + base_addr + CLKMGR_MAINPLL_PLLC0);
> + writel(cfg->main_pll_pllc1,
> + base_addr + CLKMGR_MAINPLL_PLLC1);
> + writel(cfg->main_pll_nocdiv,
> + base_addr + CLKMGR_MAINPLL_NOCDIV);
> +
> + /* setup peripheral PLL dividers */
> + /* calculate the vcocalib value */
> + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> + CLKMGR_FDBCK_MDIV_MASK;
> + refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> + CLKMGR_HSCNT_CONST;
> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> + CLKMGR_VCOCALIB_MSCNT_OFFSET);
> +
> + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> + ~CLKMGR_PLLGLOB_RST_MASK),
> + base_addr + CLKMGR_PERPLL_PLLGLOB);
> + writel(cfg->per_pll_fdbck,
> + base_addr + CLKMGR_PERPLL_FDBCK);
> + writel(vcocalib,
> + base_addr + CLKMGR_PERPLL_VCOCALIB);
> + writel(cfg->per_pll_pllc0,
> + base_addr + CLKMGR_PERPLL_PLLC0);
> + writel(cfg->per_pll_pllc1,
> + base_addr + CLKMGR_PERPLL_PLLC1);
> + writel(cfg->per_pll_emacctl,
> + base_addr + CLKMGR_PERPLL_EMACCTL);
> + writel(cfg->per_pll_gpiodiv,
> + base_addr + CLKMGR_PERPLL_GPIODIV);
> +
> + /* Take both PLL out of reset and power up */
> + setbits_le32(base_addr + CLKMGR_MAINPLL_PLLGLOB,
> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> + setbits_le32(base_addr + CLKMGR_PERPLL_PLLGLOB,
> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> +
> + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
> + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
> +
> + /*
> + * Dividers for C2 to C9 only init after PLLs are lock. As dividers
> + * only take effect upon value change, we shall set a maximum value as
> + * default value.
> + */
> + writel(0xff, base_addr + CLKMGR_MAINPLL_MPUCLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_NOCCLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR2CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR3CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR4CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR5CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR6CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR7CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR8CLK);
> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR9CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR2CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR3CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR4CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR5CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR6CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR7CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR8CLK);
> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR9CLK);
> +
> + writel(cfg->main_pll_mpuclk,
> + base_addr + CLKMGR_MAINPLL_MPUCLK);
> + writel(cfg->main_pll_nocclk,
> + base_addr + CLKMGR_MAINPLL_NOCCLK);
> + writel(cfg->main_pll_cntr2clk,
> + base_addr + CLKMGR_MAINPLL_CNTR2CLK);
> + writel(cfg->main_pll_cntr3clk,
> + base_addr + CLKMGR_MAINPLL_CNTR3CLK);
> + writel(cfg->main_pll_cntr4clk,
> + base_addr + CLKMGR_MAINPLL_CNTR4CLK);
> + writel(cfg->main_pll_cntr5clk,
> + base_addr + CLKMGR_MAINPLL_CNTR5CLK);
> + writel(cfg->main_pll_cntr6clk,
> + base_addr + CLKMGR_MAINPLL_CNTR6CLK);
> + writel(cfg->main_pll_cntr7clk,
> + base_addr + CLKMGR_MAINPLL_CNTR7CLK);
> + writel(cfg->main_pll_cntr8clk,
> + base_addr + CLKMGR_MAINPLL_CNTR8CLK);
> + writel(cfg->main_pll_cntr9clk,
> + base_addr + CLKMGR_MAINPLL_CNTR9CLK);
> + writel(cfg->per_pll_cntr2clk,
> + base_addr + CLKMGR_PERPLL_CNTR2CLK);
> + writel(cfg->per_pll_cntr3clk,
> + base_addr + CLKMGR_PERPLL_CNTR3CLK);
> + writel(cfg->per_pll_cntr4clk,
> + base_addr + CLKMGR_PERPLL_CNTR4CLK);
> + writel(cfg->per_pll_cntr5clk,
> + base_addr + CLKMGR_PERPLL_CNTR5CLK);
> + writel(cfg->per_pll_cntr6clk,
> + base_addr + CLKMGR_PERPLL_CNTR6CLK);
> + writel(cfg->per_pll_cntr7clk,
> + base_addr + CLKMGR_PERPLL_CNTR7CLK);
> + writel(cfg->per_pll_cntr8clk,
> + base_addr + CLKMGR_PERPLL_CNTR8CLK);
> + writel(cfg->per_pll_cntr9clk,
> + base_addr + CLKMGR_PERPLL_CNTR9CLK);
> +
> + /* Take all PLLs out of bypass */
> + clk_write_bypass_mainpll(plat, 0);
> + clk_write_bypass_perpll(plat, 0);
> +
> +#ifdef COUNTER_FREQUENCY_REAL
> + u32 cntfrq = COUNTER_FREQUENCY_REAL;
> + u32 counter_freq = 0;
> +
> + /* Update with accurate clock frequency */
> + if (current_el() == 3) {
> + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
> + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq));
> + debug("Counter freq = 0x%x\n", counter_freq);
> + }
> +#endif
> +
> + /* clear safe mode / out of boot mode */
> + clk_write_ctrl(plat, readl(base_addr + CLKMGR_CTRL) &
> + ~(CLKMGR_CTRL_SAFEMODE));
> +
> + /* Now ungate non-hw-managed clocks */
> + writel(~0, base_addr + CLKMGR_MAINPLL_EN);
> + writel(~0, base_addr + CLKMGR_PERPLL_EN);
> +
> + /* Clear the loss of lock bits (write 1 to clear) */
> + writel(CLKMGR_INTER_PERPLLLOST_MASK |
> + CLKMGR_INTER_MAINPLLLOST_MASK,
> + base_addr + CLKMGR_INTRCLR);
> +}
> +
> +static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
> + u32 pllglob_reg, u32 fdbck_reg)
> +{
> + u64 fref, refdiv, mdiv, reg, vco;
> +
> + reg = CM_REG_READL(plat, pllglob_reg);
> +
> + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> + CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> +
> + switch (fref) {
> + case CLKMGR_VCO_PSRC_EOSC1:
> + fref = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_INTOSC:
> + fref = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_F2S:
> + fref = cm_get_fpga_clk_hz();
> + break;
> + }
> +
> + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +
> + reg = CM_REG_READL(plat, fdbck_reg);
> + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> +
> + vco = fref / refdiv;
> + vco = vco * (CLKMGR_MDIV_CONST + mdiv);
> +
> + return vco;
> +}
> +
> +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
> + CLKMGR_MAINPLL_FDBCK);
> +}
> +
> +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
> + CLKMGR_PERPLL_FDBCK);
> +}
> +
> +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
> +{
> + u32 clksrc = CM_REG_READL(plat, reg);
> +
> + return (clksrc >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> +}
> +
> +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock;
> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_MPUCLK);
> +
> + switch (clklsrc) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_main_vco_clk_hz(plat);
> + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) &
> + CLKMGR_PLLC0_DIV_MASK);
> + break;
> + case CLKMGR_CLKSRC_PER:
> + clock = clk_get_per_vco_clk_hz(plat);
> + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) &
> + CLKMGR_CLKCNT_MSK);
> + break;
> + case CLKMGR_CLKSRC_OSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_FPGA:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + default:
> + return 0;
> + }
> +
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
> + CLKMGR_CLKCNT_MSK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock;
> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_NOCCLK);
> +
> + switch (clklsrc) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_main_vco_clk_hz(plat);
> + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) &
> + CLKMGR_PLLC0_DIV_MASK);
> + break;
> + case CLKMGR_CLKSRC_PER:
> + clock = clk_get_per_vco_clk_hz(plat);
> + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) &
> + CLKMGR_CLKCNT_MSK);
> + break;
> + case CLKMGR_CLKSRC_OSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_FPGA:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + default:
> + return 0;
> + }
> +
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_NOCCLK) &
> + CLKMGR_CLKCNT_MSK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u32 clock;
> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_PERPLL_CNTR6CLK);
> +
> + switch (clklsrc) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_l3_main_clk_hz(plat);
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);
> + break;
> + case CLKMGR_CLKSRC_PER:
> + clock = clk_get_l3_main_clk_hz(plat);
> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_PERPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);
> + break;
> + case CLKMGR_CLKSRC_OSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_CLKSRC_FPGA:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + default:
> + return 0;
> + }
> +
> + return clock / 4;
> +}
> +
> +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + u64 clock = clk_get_l3_main_clk_hz(plat);
> +
> + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
> + CLKMGR_CLKCNT_MSK);
> +
> + return clock;
> +}
> +
> +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
> +{
> + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
> + return clk_get_l3_main_clk_hz(plat) / 2;
> +
> + return clk_get_l3_main_clk_hz(plat) / 4;
> +}
> +
> +static ulong socfpga_clk_get_rate(struct clk *clk)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
> +
> + switch (clk->id) {
> + case STRATIX10_MPU_CLK:
> + return clk_get_mpu_clk_hz(plat);
> + case STRATIX10_NOC_CLK:
> + return clk_get_l3_main_clk_hz(plat);
> + case STRATIX10_MAIN_PLL_CLK:
> + return clk_get_main_vco_clk_hz(plat);
> + case STRATIX10_PERIPH_PLL_CLK:
> + return clk_get_per_vco_clk_hz(plat);
> + case STRATIX10_OSC1:
> + return cm_get_osc_clk_hz();
> + case STRATIX10_SDMMC_CLK:
> + return clk_get_sdmmc_clk_hz(plat);
> + case STRATIX10_L4_SP_CLK:
> + return clk_get_l4_sp_clk_hz(plat);
> + case STRATIX10_L4_SYS_FREE_CLK:
> + return clk_get_l4_sys_free_clk_hz(plat);
missing STRATIX10_L4_MAIN_CLK(from upstream dts for spi0/1), please
check whether is name diff between U-Boot & Linux, or missing.
> + default:
> + return -ENXIO;
> + }
> +}
> +
> +static int bitmask_from_clk_id(struct clk *clk)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
> +
> + switch (clk->id) {
> + case STRATIX10_MPU_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
> + break;
> + case STRATIX10_L4_MAIN_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
> + break;
> + case STRATIX10_L4_MP_CLK:
> + case STRATIX10_NAND_X_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
> + break;
> + case STRATIX10_L4_SP_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
> + break;
> + case STRATIX10_CS_AT_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
> + break;
> + case STRATIX10_CS_TRACE_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
> + break;
> + case STRATIX10_CS_PDBG_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
> + break;
> + case STRATIX10_CS_TIMER_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
> + break;
> + case STRATIX10_S2F_USER0_CLK:
> + plat->pllgrp = CLKMGR_MAINPLL_EN;
> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
> + break;
> + case STRATIX10_EMAC0_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
> + break;
> + case STRATIX10_EMAC1_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
> + break;
> + case STRATIX10_EMAC2_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
> + break;
> + case STRATIX10_EMAC_PTP_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
> + break;
> + case STRATIX10_GPIO_DB_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
> + break;
> + case STRATIX10_SDMMC_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
> + break;
> + case STRATIX10_S2F_USER1_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
> + break;
> + case STRATIX10_PSI_REF_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
> + break;
> + case STRATIX10_USB_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
> + break;
> + case STRATIX10_SPI_M_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
> + break;
> + case STRATIX10_NAND_CLK:
> + plat->pllgrp = CLKMGR_PERPLL_EN;
> + plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
> + break;
> + case STRATIX10_L4_SYS_FREE_CLK:
> + return -EOPNOTSUPP;
> + default:
> + return -ENXIO;
> + }
> +
> + return 0;
> +}
> +
> +static int socfpga_clk_enable(struct clk *clk)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
> + uintptr_t base_addr = (uintptr_t)plat->regs;
> + int ret;
> +
> + ret = bitmask_from_clk_id(clk);
> + if (ret == -EOPNOTSUPP)
> + return 0;
> +
> + if (ret)
> + return ret;
> +
> + setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
> +
> + return 0;
> +}
> +
> +static int socfpga_clk_disable(struct clk *clk)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
> + uintptr_t base_addr = (uintptr_t)plat->regs;
> + int ret;
> +
> + ret = bitmask_from_clk_id(clk);
> + if (ret == -EOPNOTSUPP)
> + return 0;
> +
> + if (ret)
> + return ret;
> +
> + clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
> +
> + return 0;
> +}
> +
> +static int socfpga_clk_probe(struct udevice *dev)
> +{
> + const struct cm_config *cm_default_cfg = cm_get_default_config();
> +
> + clk_basic_init(dev, cm_default_cfg);
> +
> + return 0;
> +}
> +
> +static int socfpga_clk_of_to_plat(struct udevice *dev)
> +{
> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
> + fdt_addr_t addr;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> + plat->regs = (void __iomem *)addr;
> +
> + return 0;
> +}
> +
> +static struct clk_ops socfpga_clk_ops = {
> + .enable = socfpga_clk_enable,
> + .disable = socfpga_clk_disable,
> + .get_rate = socfpga_clk_get_rate,
> +};
> +
> +static const struct udevice_id socfpga_clk_match[] = {
> + { .compatible = "intel,stratix10-clkmgr" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(socfpga_s10_clk) = {
> + .name = "clk-s10",
> + .id = UCLASS_CLK,
> + .of_match = socfpga_clk_match,
> + .ops = &socfpga_clk_ops,
> + .probe = socfpga_clk_probe,
> + .of_to_plat = socfpga_clk_of_to_plat,
> + .plat_auto = sizeof(struct socfpga_clk_plat),
> +};
> diff --git a/drivers/clk/altera/clk-s10.h b/drivers/clk/altera/clk-s10.h
> new file mode 100644
> index 00000000000..f5be1e68500
> --- /dev/null
> +++ b/drivers/clk/altera/clk-s10.h
> @@ -0,0 +1,202 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
NEW FILE, but derived from Intel code
Copyright (C) 2016-2023 Intel Corporation <www.intel.com> ← must add
(code origin)
> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
> + *
> + */
> +
> +#ifndef _CLK_S10_
> +#define _CLK_S10_
> +
Best regards,
Tien Fong
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 7/9] clk: s10: Refactor S10 clock driver
2026-05-08 5:48 ` Chee, Tien Fong
@ 2026-05-14 5:47 ` Yuslaimi, Alif Zakuan
0 siblings, 0 replies; 19+ messages in thread
From: Yuslaimi, Alif Zakuan @ 2026-05-14 5:47 UTC (permalink / raw)
To: Chee, Tien Fong, u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Lukasz Majewski,
Peng Fan, Jaehoon Chung, Simon Glass, Neil Armstrong,
Kory Maincent, Yao Zi
Hi Tien Fong,
On 8/5/2026 1:48 pm, Chee, Tien Fong wrote:
> Hi Alif,
>
>
> On 28/4/2026 11:48 am, alif.zakuan.yuslaimi@altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>>
>> Refactor Stratix10 clock manager driver to support driver model,
>> following
>> Agilex clock driver.
>>
>> Create a new clock driver, clk-s10.c, for Stratix10 which supports the
>> driver model. This allows several APIs such as enable/disable clock, and
>> get clock rate to be supported.
>>
>> This driver will be initialized during SPL to bring up the clock as early
>> as possible. The clock initialization process are refactored into this
>> new
>> driver from clock_manager_s10.c during clock driver probe.
>>
>> Excluding Stratix10 from legacy method of obtaining clkmgr base
>> address in
>> mach-socfpga/misc.c as the base address is already obtained during clock
>> driver probe during SPL initialization.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
>> ---
>> MAINTAINERS | 1 +
>> arch/arm/mach-socfpga/Kconfig | 2 +
>> arch/arm/mach-socfpga/clock_manager_s10.c | 449 ++-----------
>> .../include/mach/clock_manager_s10.h | 176 +----
>> arch/arm/mach-socfpga/misc.c | 3 +-
>> arch/arm/mach-socfpga/spl_s10.c | 7 +-
>> drivers/clk/altera/Makefile | 1 +
>> drivers/clk/altera/clk-s10.c | 603 ++++++++++++++++++
>> drivers/clk/altera/clk-s10.h | 202 ++++++
>> 9 files changed, 873 insertions(+), 571 deletions(-)
>> create mode 100644 drivers/clk/altera/clk-s10.c
>> create mode 100644 drivers/clk/altera/clk-s10.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index d1173126fc6..032f0ee97fc 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -159,6 +159,7 @@ F: arch/arm/mach-socfpga/
>> F: board/altera/stratix10-socdk/
>> F: board/intel/agilex-socdk/
>> F: configs/socfpga_*
>> +F: drivers/clk/altera/
>> F: drivers/ddr/altera/
>> F: drivers/power/domain/altr-pmgr-agilex5.c
>> F: drivers/sysreset/sysreset_socfpga*
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/
>> Kconfig
>> index fb98b647442..aa1f3e761cd 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -146,8 +146,10 @@ config ARCH_SOCFPGA_STRATIX10
>> select ARMV8_MULTIENTRY
>> select ARMV8_SET_SMPEN
>> select BINMAN if SPL_ATF
>> + select CLK
>> select FPGA_INTEL_SDM_MAILBOX
>> select GICV2
>> + select SPL_CLK if SPL
>> select ARCH_SOCFPGA_SOC64
>> choice
>> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/
>> mach-socfpga/clock_manager_s10.c
>> index fd27470f967..df636f14f93 100644
>> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
>> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
>> @@ -1,425 +1,78 @@
>> // SPDX-License-Identifier: GPL-2.0
>> /*
>> - * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
>
>
> all prior copyright notices to be retained
>
>
Noted, I will re-add this in v3.
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> *
>> */
>> -#include <compiler.h>
>> -#include <dm/device.h>
>> -#include <linux/errno.h>
>> -#include <asm/io.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <log.h>
>> +#include <malloc.h>
>> #include <asm/arch/clock_manager.h>
>> -#include <asm/arch/handoff_soc64.h>
>> #include <asm/arch/system_manager.h>
>> +#include <asm/io.h>
>> +#include <dt-bindings/clock/stratix10-clock.h>
>> -/*
>> - * function to write the bypass register which requires a poll of the
>> - * busy bit
>> - */
>> -static void cm_write_bypass_mainpll(u32 val)
>> -{
>> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
>> - cm_wait_for_fsm();
>> -}
>> -
>> -static void cm_write_bypass_perpll(u32 val)
>> -{
>> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
>> - cm_wait_for_fsm();
>> -}
>> -
>> -/* function to write the ctrl register which requires a poll of the
>> busy bit */
>> -static void cm_write_ctrl(u32 val)
>> -{
>> - writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
>> - cm_wait_for_fsm();
>> -}
>> -
>> -/*
>> - * Setup clocks while making no assumptions about previous state of
>> the clocks.
>> - */
>> -void cm_basic_init(const struct cm_config * const cfg)
>> -{
>> - u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
>> -
>> - if (cfg == 0)
>> - return;
>> -
>> - /* Put all plls in bypass */
>> - cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
>> - cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
>> -
>> - /* setup main PLL dividers where calculate the vcocalib value */
>> - mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
>> - CLKMGR_FDBCK_MDIV_MASK;
>> - refclkdiv = (cfg->main_pll_pllglob >>
>> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> - mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
>> - hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
>> - CLKMGR_HSCNT_CONST;
>> - vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
>> - ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
>> - CLKMGR_VCOCALIB_MSCNT_OFFSET);
>> -
>> - writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
>> - ~CLKMGR_PLLGLOB_RST_MASK),
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
>> - writel(cfg->main_pll_fdbck,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
>> - writel(vcocalib,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
>> - writel(cfg->main_pll_pllc0,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
>> - writel(cfg->main_pll_pllc1,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
>> - writel(cfg->main_pll_nocdiv,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
>> -
>> - /* setup peripheral PLL dividers */
>> - /* calculate the vcocalib value */
>> - mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
>> - CLKMGR_FDBCK_MDIV_MASK;
>> - refclkdiv = (cfg->per_pll_pllglob >>
>> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> - mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
>> - hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
>> - CLKMGR_HSCNT_CONST;
>> - vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
>> - ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
>> - CLKMGR_VCOCALIB_MSCNT_OFFSET);
>> -
>> - writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
>> - ~CLKMGR_PLLGLOB_RST_MASK),
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
>> - writel(cfg->per_pll_fdbck,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
>> - writel(vcocalib,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
>> - writel(cfg->per_pll_pllc0,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
>> - writel(cfg->per_pll_pllc1,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
>> - writel(cfg->per_pll_emacctl,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
>> - writel(cfg->per_pll_gpiodiv,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
>> -
>> - /* Take both PLL out of reset and power up */
>> - setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
>> - CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
>> - setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
>> - CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
>> -
>> -#define LOCKED_MASK \
>> - (CLKMGR_STAT_MAINPLL_LOCKED | \
>> - CLKMGR_STAT_PERPLL_LOCKED)
>> -
>> - cm_wait_for_lock(LOCKED_MASK);
>> -
>> - /*
>> - * Dividers for C2 to C9 only init after PLLs are lock. As dividers
>> - * only take effect upon value change, we shall set a maximum
>> value as
>> - * default value.
>> - */
>> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR2CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR3CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR4CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR5CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR6CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR7CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR8CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_MAINPLL_CNTR9CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR2CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR3CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR4CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR5CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR6CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR7CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR8CLK);
>> - writel(0xff, socfpga_get_clkmgr_addr() +
>> CLKMGR_S10_PERPLL_CNTR9CLK);
>> -
>> - writel(cfg->main_pll_mpuclk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
>> - writel(cfg->main_pll_nocclk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
>> - writel(cfg->main_pll_cntr2clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
>> - writel(cfg->main_pll_cntr3clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
>> - writel(cfg->main_pll_cntr4clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
>> - writel(cfg->main_pll_cntr5clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
>> - writel(cfg->main_pll_cntr6clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
>> - writel(cfg->main_pll_cntr7clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
>> - writel(cfg->main_pll_cntr8clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
>> - writel(cfg->main_pll_cntr9clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
>> - writel(cfg->per_pll_cntr2clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
>> - writel(cfg->per_pll_cntr3clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
>> - writel(cfg->per_pll_cntr4clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
>> - writel(cfg->per_pll_cntr5clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
>> - writel(cfg->per_pll_cntr6clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
>> - writel(cfg->per_pll_cntr7clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
>> - writel(cfg->per_pll_cntr8clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
>> - writel(cfg->per_pll_cntr9clk,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
>> -
>> - /* Take all PLLs out of bypass */
>> - cm_write_bypass_mainpll(0);
>> - cm_write_bypass_perpll(0);
>> -
>> - /* clear safe mode / out of boot mode */
>> - cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
>> - ~(CLKMGR_CTRL_SAFEMODE));
>> -
>> - /* Now ungate non-hw-managed clocks */
>> - writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
>> - writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
>> -
>> - /* Clear the loss of lock bits (write 1 to clear) */
>> - writel(CLKMGR_INTER_PERPLLLOST_MASK |
>> - CLKMGR_INTER_MAINPLLLOST_MASK,
>> - socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
>> -}
>> -
>> -static unsigned long cm_get_main_vco_clk_hz(void)
>> +static ulong cm_get_rate_dm(u32 id)
>> {
>> - unsigned long fref, refdiv, mdiv, reg, vco;
>> -
>> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
>> -
>> - fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
>> - CLKMGR_PLLGLOB_VCO_PSRC_MASK;
>> - switch (fref) {
>> - case CLKMGR_VCO_PSRC_EOSC1:
>> - fref = cm_get_osc_clk_hz();
>> - break;
>> - case CLKMGR_VCO_PSRC_INTOSC:
>> - fref = cm_get_intosc_clk_hz();
>> - break;
>> - case CLKMGR_VCO_PSRC_F2S:
>> - fref = cm_get_fpga_clk_hz();
>> - break;
>> + struct udevice *dev;
>> + struct clk clk;
>> + ulong rate;
>> + int ret;
>> +
>> + ret = uclass_get_device_by_driver(UCLASS_CLK,
>> + DM_DRIVER_GET(socfpga_s10_clk),
>> + &dev);
>> + if (ret)
>> + return 0;
>> +
>> + clk.id = id;
>> + ret = clk_request(dev, &clk);
>> + if (ret < 0)
>> + return 0;
>> +
>> + rate = clk_get_rate(&clk);
>> +
>> + if ((rate == (unsigned long)-ENOSYS) ||
>> + (rate == (unsigned long)-ENXIO) ||
>> + (rate == (unsigned long)-EIO)) {
>> + debug("%s id %u: clk_get_rate err: %ld\n",
>> + __func__, id, rate);
>> + return 0;
>> }
>> - refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> -
>> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
>> - mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
>> -
>> - vco = fref / refdiv;
>> - vco = vco * (CLKMGR_MDIV_CONST + mdiv);
>> - return vco;
>> + return rate;
>> }
>> -static unsigned long cm_get_per_vco_clk_hz(void)
>> +static u32 cm_get_rate_dm_khz(u32 id)
>> {
>> - unsigned long fref, refdiv, mdiv, reg, vco;
>> -
>> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
>> -
>> - fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
>> - CLKMGR_PLLGLOB_VCO_PSRC_MASK;
>> - switch (fref) {
>> - case CLKMGR_VCO_PSRC_EOSC1:
>> - fref = cm_get_osc_clk_hz();
>> - break;
>> - case CLKMGR_VCO_PSRC_INTOSC:
>> - fref = cm_get_intosc_clk_hz();
>> - break;
>> - case CLKMGR_VCO_PSRC_F2S:
>> - fref = cm_get_fpga_clk_hz();
>> - break;
>> - }
>> -
>> - refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> - CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> -
>> - reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
>> - mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
>> -
>> - vco = fref / refdiv;
>> - vco = vco * (CLKMGR_MDIV_CONST + mdiv);
>> - return vco;
>> + return cm_get_rate_dm(id) / 1000;
>> }
>> unsigned long cm_get_mpu_clk_hz(void)
>> {
>> - unsigned long clock = readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_MPUCLK);
>> -
>> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>> -
>> - switch (clock) {
>> - case CLKMGR_CLKSRC_MAIN:
>> - clock = cm_get_main_vco_clk_hz();
>> - clock /= (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_PLLC0) &
>> - CLKMGR_PLLC0_DIV_MASK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_PER:
>> - clock = cm_get_per_vco_clk_hz();
>> - clock /= (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_PERPLL_PLLC0) &
>> - CLKMGR_CLKCNT_MSK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_OSC1:
>> - clock = cm_get_osc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_INTOSC:
>> - clock = cm_get_intosc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_FPGA:
>> - clock = cm_get_fpga_clk_hz();
>> - break;
>> - }
>> -
>> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
>> - return clock;
>> -}
>> -
>> -unsigned int cm_get_l3_main_clk_hz(void)
>> -{
>> - u32 clock = readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_NOCCLK);
>> -
>> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>> -
>> - switch (clock) {
>> - case CLKMGR_CLKSRC_MAIN:
>> - clock = cm_get_main_vco_clk_hz();
>> - clock /= (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_PLLC1) &
>> - CLKMGR_PLLC0_DIV_MASK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_PER:
>> - clock = cm_get_per_vco_clk_hz();
>> - clock /= (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_OSC1:
>> - clock = cm_get_osc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_INTOSC:
>> - clock = cm_get_intosc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_FPGA:
>> - clock = cm_get_fpga_clk_hz();
>> - break;
>> - }
>> -
>> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
>> - return clock;
>> -}
>> -
>> -unsigned int cm_get_mmc_controller_clk_hz(void)
>> -{
>> - u32 clock = readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_PERPLL_CNTR6CLK);
>> -
>> - clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>> -
>> - switch (clock) {
>> - case CLKMGR_CLKSRC_MAIN:
>> - clock = cm_get_l3_main_clk_hz();
>> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_CNTR6CLK) &
>> - CLKMGR_CLKCNT_MSK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_PER:
>> - clock = cm_get_l3_main_clk_hz();
>> - clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_PERPLL_CNTR6CLK) &
>> - CLKMGR_CLKCNT_MSK);
>> - break;
>> -
>> - case CLKMGR_CLKSRC_OSC1:
>> - clock = cm_get_osc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_INTOSC:
>> - clock = cm_get_intosc_clk_hz();
>> - break;
>> -
>> - case CLKMGR_CLKSRC_FPGA:
>> - clock = cm_get_fpga_clk_hz();
>> - break;
>> - }
>> - return clock / 4;
>> -}
>> -
>> -unsigned int cm_get_l4_sp_clk_hz(void)
>> -{
>> - u32 clock = cm_get_l3_main_clk_hz();
>> -
>> - clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_NOCDIV) >>
>> - CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
>> - return clock;
>> -}
>> -
>> -unsigned int cm_get_spi_controller_clk_hz(void)
>> -{
>> - u32 clock = cm_get_l3_main_clk_hz();
>> -
>> - clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
>> - CLKMGR_S10_MAINPLL_NOCDIV) >>
>> - CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
>> - return clock;
>> + return cm_get_rate_dm(STRATIX10_MPU_CLK);
>> }
>> unsigned int cm_get_l4_sys_free_clk_hz(void)
>> {
>> - return cm_get_l3_main_clk_hz() / 4;
>> -}
>> -
>> -/*
>> - * Override weak dw_spi_get_clk implementation in designware_spi.c
>> driver
>> - */
>> -
>> -int dw_spi_get_clk(struct udevice *bus, ulong *rate)
>> -{
>> - *rate = cm_get_spi_controller_clk_hz();
>> - if (!*rate) {
>> - printf("SPI: clock rate is zero");
>> - return -EINVAL;
>> - }
>> -
>> - return 0;
>
>
> The dw_spi_get_clk() removal and the missing STRATIX10_L4_MAIN_CLK(from
> upstream dts) in socfpga_clk_get_rate() have impacted
>
> the use case where someone enables spi@ffda4000 or spi@ffda5000 in a
> board DTS for a general-purpose SPI peripheral (not the use case spi0 =
> &qspi alias)
>
>
I get your point, I will introduce a new function to get clock rate for
STRATIX10_L4_MAIN_CLK clock in v3.
>> + return cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);
>> }
>> void cm_print_clock_quick_summary(void)
>> {
>> - printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
>> - printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
>> - printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() /
>> 1000));
>> - printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() /
>> 1000));
>> - printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000);
>> - printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() /
>> 1000);
>> - printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
>> + printf("MPU %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_MPU_CLK));
>> + printf("L3 main %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_NOC_CLK));
>> + printf("Main VCO %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_MAIN_PLL_CLK));
>> + printf("Per VCO %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_PERIPH_PLL_CLK));
>> + printf("EOSC1 %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_OSC1));
>> + printf("HPS MMC %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));
>> + printf("UART %d kHz\n",
>> + cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));
>> }
>> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/
>> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> index 5dcbda9473e..e5ff0648b86 100644
>> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>> @@ -1,177 +1,13 @@
>> -/* SPDX-License-Identifier: GPL-2.0
>> - *
>> - * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
>
>
> all prior copyright notices to be retained
>
>
Sure, I will re-add this in v3.
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> *
>> */
>> -#ifndef _CLOCK_MANAGER_S10_
>> -#define _CLOCK_MANAGER_S10_
>> +#ifndef _CLOCK_MANAGER_S10_
>> +#define _CLOCK_MANAGER_S10_
>> #include <asm/arch/clock_manager_soc64.h>
>> -#include <linux/bitops.h>
>> -
>> -/* Clock speed accessors */
>> -unsigned long cm_get_sdram_clk_hz(void);
>> -unsigned int cm_get_l4_sp_clk_hz(void);
>> -unsigned int cm_get_mmc_controller_clk_hz(void);
>> -unsigned int cm_get_spi_controller_clk_hz(void);
>> -
>> -struct cm_config {
>> - /* main group */
>> - u32 main_pll_mpuclk;
>> - u32 main_pll_nocclk;
>> - u32 main_pll_cntr2clk;
>> - u32 main_pll_cntr3clk;
>> - u32 main_pll_cntr4clk;
>> - u32 main_pll_cntr5clk;
>> - u32 main_pll_cntr6clk;
>> - u32 main_pll_cntr7clk;
>> - u32 main_pll_cntr8clk;
>> - u32 main_pll_cntr9clk;
>> - u32 main_pll_nocdiv;
>> - u32 main_pll_pllglob;
>> - u32 main_pll_fdbck;
>> - u32 main_pll_pllc0;
>> - u32 main_pll_pllc1;
>> - u32 spare;
>> -
>> - /* peripheral group */
>> - u32 per_pll_cntr2clk;
>> - u32 per_pll_cntr3clk;
>> - u32 per_pll_cntr4clk;
>> - u32 per_pll_cntr5clk;
>> - u32 per_pll_cntr6clk;
>> - u32 per_pll_cntr7clk;
>> - u32 per_pll_cntr8clk;
>> - u32 per_pll_cntr9clk;
>> - u32 per_pll_emacctl;
>> - u32 per_pll_gpiodiv;
>> - u32 per_pll_pllglob;
>> - u32 per_pll_fdbck;
>> - u32 per_pll_pllc0;
>> - u32 per_pll_pllc1;
>> -
>> - /* incoming clock */
>> - u32 hps_osc_clk_hz;
>> - u32 fpga_clk_hz;
>> -};
>> -
>> -void cm_basic_init(const struct cm_config * const cfg);
>> -
>> -/* Control status */
>> -#define CLKMGR_S10_CTRL 0x00
>> -#define CLKMGR_S10_STAT 0x04
>> -#define CLKMGR_S10_INTRCLR 0x14
>> -/* Mainpll group */
>> -#define CLKMGR_S10_MAINPLL_EN 0x30
>> -#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
>> -#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
>> -#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
>> -#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
>> -#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
>> -#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
>> -#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
>> -#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
>> -#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
>> -#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
>> -#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
>> -#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
>> -#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
>> -#define CLKMGR_S10_MAINPLL_FDBCK 0x78
>> -#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
>> -#define CLKMGR_S10_MAINPLL_PLLC0 0x84
>> -#define CLKMGR_S10_MAINPLL_PLLC1 0x88
>> -#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
>> -/* Periphpll group */
>> -#define CLKMGR_S10_PERPLL_EN 0xa4
>> -#define CLKMGR_S10_PERPLL_BYPASS 0xb0
>> -#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
>> -#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
>> -#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
>> -#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
>> -#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
>> -#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
>> -#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
>> -#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
>> -#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
>> -#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
>> -#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
>> -#define CLKMGR_S10_PERPLL_FDBCK 0xe8
>> -#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
>> -#define CLKMGR_S10_PERPLL_PLLC0 0xf4
>> -#define CLKMGR_S10_PERPLL_PLLC1 0xf8
>> -#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
>> -
>> -#define CLKMGR_STAT CLKMGR_S10_STAT
>> -#define CLKMGR_INTER CLKMGR_S10_INTER
>> -#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
>> -
>> -#define CLKMGR_CTRL_SAFEMODE BIT(0)
>> -#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
>> -#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
>> -
>> -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
>> -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
>> -#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
>> -#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
>> -#define CLKMGR_STAT_BUSY BIT(0)
>> -#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
>> -#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
>> -
>> -#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
>> -#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
>> -#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3
>> -#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
>> -#define CLKMGR_VCO_PSRC_EOSC1 0
>> -#define CLKMGR_VCO_PSRC_INTOSC 1
>> -#define CLKMGR_VCO_PSRC_F2S 2
>> -#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f
>> -#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
>> -
>> -#define CLKMGR_CLKSRC_MASK 0x7
>> -#define CLKMGR_CLKSRC_OFFSET 16
>> -#define CLKMGR_CLKSRC_MAIN 0
>> -#define CLKMGR_CLKSRC_PER 1
>> -#define CLKMGR_CLKSRC_OSC1 2
>> -#define CLKMGR_CLKSRC_INTOSC 3
>> -#define CLKMGR_CLKSRC_FPGA 4
>> -#define CLKMGR_CLKCNT_MSK 0x7ff
>> -
>> -#define CLKMGR_FDBCK_MDIV_MASK 0xff
>> -#define CLKMGR_FDBCK_MDIV_OFFSET 24
>> -
>> -#define CLKMGR_PLLC0_DIV_MASK 0xff
>> -#define CLKMGR_PLLC1_DIV_MASK 0xff
>> -#define CLKMGR_PLLC0_EN_OFFSET 27
>> -#define CLKMGR_PLLC1_EN_OFFSET 24
>> -
>> -#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
>> -#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
>> -#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
>> -#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
>> -#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
>> -#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
>> -
>> -#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3
>> -#define CLKMGR_NOCDIV_DIV1 0
>> -#define CLKMGR_NOCDIV_DIV2 1
>> -#define CLKMGR_NOCDIV_DIV4 2
>> -#define CLKMGR_NOCDIV_DIV8 3
>> -#define CLKMGR_CSPDBGCLK_DIV1 0
>> -#define CLKMGR_CSPDBGCLK_DIV4 1
>> -
>> -#define CLKMGR_MSCNT_CONST 200
>> -#define CLKMGR_MDIV_CONST 6
>> -#define CLKMGR_HSCNT_CONST 9
>> -
>> -#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
>> -#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
>> -#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
>> -
>> -#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
>> -#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
>> -#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
>> -
>> -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
>> +#include "../../../../../drivers/clk/altera/clk-s10.h"
>> #endif /* _CLOCK_MANAGER_S10_ */
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index 418d7dfb572..6d7128c77be 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -276,7 +276,8 @@ void socfpga_get_managers_addr(void)
>> &socfpga_clkmgr_base);
>> else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
>> !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
>> - !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))
>> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&
>> + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10))
>> ret = socfpga_get_base_addr("altr,clk-mgr",
>> &socfpga_clkmgr_base);
>> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/
>> spl_s10.c
>> index b05bec2cbc1..ace029557f3 100644
>> --- a/arch/arm/mach-socfpga/spl_s10.c
>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>> @@ -37,7 +37,6 @@ u32 reset_flag(void)
>> void board_init_f(ulong dummy)
>> {
>> - const struct cm_config *cm_default_cfg = cm_get_default_config();
>> int ret;
>> struct udevice *dev;
>> @@ -75,7 +74,11 @@ void board_init_f(ulong dummy)
>> sysmgr_pinmux_init();
>> /* configuring the HPS clocks */
>> - cm_basic_init(cm_default_cfg);
>> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
>> + if (ret) {
>> + debug("Clock init failed: %d\n", ret);
>> + hang();
>> + }
>> #ifdef CONFIG_DEBUG_UART
>> socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
>> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
>> index 693446b3d89..e961d059820 100644
>> --- a/drivers/clk/altera/Makefile
>> +++ b/drivers/clk/altera/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o
>> obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o
>> obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o
>> obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o
>> +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += clk-s10.o
>> diff --git a/drivers/clk/altera/clk-s10.c b/drivers/clk/altera/clk-s10.c
>> new file mode 100644
>> index 00000000000..c6492e0cb43
>> --- /dev/null
>> +++ b/drivers/clk/altera/clk-s10.c
>> @@ -0,0 +1,603 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>
>
> NEW FILE, but derived from Intel code
>
> Copyright (C) 2016-2023 Intel Corporation <www.intel.com> ← must add
> (code origin)
>
>
I will add this in v3.
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> + *
>> + */
>> +
>> +#include <log.h>
>> +#include <wait_bit.h>
>> +#include <asm/io.h>
>> +#include <asm/system.h>
>> +#include <clk-uclass.h>
>> +#include <dm.h>
>> +#include <dm/lists.h>
>> +#include <dm/util.h>
>> +#include <dt-bindings/clock/stratix10-clock.h>
>> +#include <linux/bitfield.h>
>> +#include <linux/bitops.h>
>> +#include <asm/arch/clock_manager.h>
>> +
>> +struct socfpga_clk_plat {
>> + void __iomem *regs;
>> + int pllgrp;
>> + int bitmask;
>> +};
>> +
>> +/*
>> + * function to write the bypass register which requires a poll of the
>> + * busy bit
>> + */
>> +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat,
>> u32 val)
>> +{
>> + void __iomem *base = plat->regs;
>> +
>> + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
>> +
>> + wait_for_bit_le32(base + CLKMGR_STAT,
>> + CLKMGR_STAT_BUSY, false, 20000, false);
>> +}
>> +
>> +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat,
>> u32 val)
>> +{
>> + void __iomem *base = plat->regs;
>> +
>> + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
>> +
>> + wait_for_bit_le32(base + CLKMGR_STAT,
>> + CLKMGR_STAT_BUSY, false, 20000, false);
>> +}
>> +
>> +/* function to write the ctrl register which requires a poll of the
>> busy bit */
>> +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
>> +{
>> + void __iomem *base = plat->regs;
>> +
>> + CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
>> +
>> + wait_for_bit_le32(base + CLKMGR_STAT,
>> + CLKMGR_STAT_BUSY, false, 20000, false);
>> +}
>> +
>> +/*
>> + * Setup clocks while making no assumptions about previous state of
>> the clocks.
>> + */
>> +static void clk_basic_init(struct udevice *dev,
>> + const struct cm_config * const cfg)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
>> + u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
>> + uintptr_t base_addr = (uintptr_t)plat->regs;
>> +
>> + if (!cfg)
>> + return;
>> +
>> + /* Put all plls in bypass */
>> + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
>> + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
>> +
>> + /* setup main PLL dividers where calculate the vcocalib value */
>> + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
>> + CLKMGR_FDBCK_MDIV_MASK;
>> + refclkdiv = (cfg->main_pll_pllglob >>
>> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
>> + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
>> + CLKMGR_HSCNT_CONST;
>> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
>> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
>> + CLKMGR_VCOCALIB_MSCNT_OFFSET);
>> +
>> + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
>> + ~CLKMGR_PLLGLOB_RST_MASK),
>> + base_addr + CLKMGR_MAINPLL_PLLGLOB);
>> + writel(cfg->main_pll_fdbck,
>> + base_addr + CLKMGR_MAINPLL_FDBCK);
>> + writel(vcocalib,
>> + base_addr + CLKMGR_MAINPLL_VCOCALIB);
>> + writel(cfg->main_pll_pllc0,
>> + base_addr + CLKMGR_MAINPLL_PLLC0);
>> + writel(cfg->main_pll_pllc1,
>> + base_addr + CLKMGR_MAINPLL_PLLC1);
>> + writel(cfg->main_pll_nocdiv,
>> + base_addr + CLKMGR_MAINPLL_NOCDIV);
>> +
>> + /* setup peripheral PLL dividers */
>> + /* calculate the vcocalib value */
>> + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
>> + CLKMGR_FDBCK_MDIV_MASK;
>> + refclkdiv = (cfg->per_pll_pllglob >>
>> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
>> + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
>> + CLKMGR_HSCNT_CONST;
>> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
>> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
>> + CLKMGR_VCOCALIB_MSCNT_OFFSET);
>> +
>> + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
>> + ~CLKMGR_PLLGLOB_RST_MASK),
>> + base_addr + CLKMGR_PERPLL_PLLGLOB);
>> + writel(cfg->per_pll_fdbck,
>> + base_addr + CLKMGR_PERPLL_FDBCK);
>> + writel(vcocalib,
>> + base_addr + CLKMGR_PERPLL_VCOCALIB);
>> + writel(cfg->per_pll_pllc0,
>> + base_addr + CLKMGR_PERPLL_PLLC0);
>> + writel(cfg->per_pll_pllc1,
>> + base_addr + CLKMGR_PERPLL_PLLC1);
>> + writel(cfg->per_pll_emacctl,
>> + base_addr + CLKMGR_PERPLL_EMACCTL);
>> + writel(cfg->per_pll_gpiodiv,
>> + base_addr + CLKMGR_PERPLL_GPIODIV);
>> +
>> + /* Take both PLL out of reset and power up */
>> + setbits_le32(base_addr + CLKMGR_MAINPLL_PLLGLOB,
>> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
>> + setbits_le32(base_addr + CLKMGR_PERPLL_PLLGLOB,
>> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
>> +
>> + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
>> + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
>> +
>> + /*
>> + * Dividers for C2 to C9 only init after PLLs are lock. As dividers
>> + * only take effect upon value change, we shall set a maximum
>> value as
>> + * default value.
>> + */
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_MPUCLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_NOCCLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR2CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR3CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR4CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR5CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR6CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR7CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR8CLK);
>> + writel(0xff, base_addr + CLKMGR_MAINPLL_CNTR9CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR2CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR3CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR4CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR5CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR6CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR7CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR8CLK);
>> + writel(0xff, base_addr + CLKMGR_PERPLL_CNTR9CLK);
>> +
>> + writel(cfg->main_pll_mpuclk,
>> + base_addr + CLKMGR_MAINPLL_MPUCLK);
>> + writel(cfg->main_pll_nocclk,
>> + base_addr + CLKMGR_MAINPLL_NOCCLK);
>> + writel(cfg->main_pll_cntr2clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR2CLK);
>> + writel(cfg->main_pll_cntr3clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR3CLK);
>> + writel(cfg->main_pll_cntr4clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR4CLK);
>> + writel(cfg->main_pll_cntr5clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR5CLK);
>> + writel(cfg->main_pll_cntr6clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR6CLK);
>> + writel(cfg->main_pll_cntr7clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR7CLK);
>> + writel(cfg->main_pll_cntr8clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR8CLK);
>> + writel(cfg->main_pll_cntr9clk,
>> + base_addr + CLKMGR_MAINPLL_CNTR9CLK);
>> + writel(cfg->per_pll_cntr2clk,
>> + base_addr + CLKMGR_PERPLL_CNTR2CLK);
>> + writel(cfg->per_pll_cntr3clk,
>> + base_addr + CLKMGR_PERPLL_CNTR3CLK);
>> + writel(cfg->per_pll_cntr4clk,
>> + base_addr + CLKMGR_PERPLL_CNTR4CLK);
>> + writel(cfg->per_pll_cntr5clk,
>> + base_addr + CLKMGR_PERPLL_CNTR5CLK);
>> + writel(cfg->per_pll_cntr6clk,
>> + base_addr + CLKMGR_PERPLL_CNTR6CLK);
>> + writel(cfg->per_pll_cntr7clk,
>> + base_addr + CLKMGR_PERPLL_CNTR7CLK);
>> + writel(cfg->per_pll_cntr8clk,
>> + base_addr + CLKMGR_PERPLL_CNTR8CLK);
>> + writel(cfg->per_pll_cntr9clk,
>> + base_addr + CLKMGR_PERPLL_CNTR9CLK);
>> +
>> + /* Take all PLLs out of bypass */
>> + clk_write_bypass_mainpll(plat, 0);
>> + clk_write_bypass_perpll(plat, 0);
>> +
>> +#ifdef COUNTER_FREQUENCY_REAL
>> + u32 cntfrq = COUNTER_FREQUENCY_REAL;
>> + u32 counter_freq = 0;
>> +
>> + /* Update with accurate clock frequency */
>> + if (current_el() == 3) {
>> + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
>> + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq));
>> + debug("Counter freq = 0x%x\n", counter_freq);
>> + }
>> +#endif
>> +
>> + /* clear safe mode / out of boot mode */
>> + clk_write_ctrl(plat, readl(base_addr + CLKMGR_CTRL) &
>> + ~(CLKMGR_CTRL_SAFEMODE));
>> +
>> + /* Now ungate non-hw-managed clocks */
>> + writel(~0, base_addr + CLKMGR_MAINPLL_EN);
>> + writel(~0, base_addr + CLKMGR_PERPLL_EN);
>> +
>> + /* Clear the loss of lock bits (write 1 to clear) */
>> + writel(CLKMGR_INTER_PERPLLLOST_MASK |
>> + CLKMGR_INTER_MAINPLLLOST_MASK,
>> + base_addr + CLKMGR_INTRCLR);
>> +}
>> +
>> +static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
>> + u32 pllglob_reg, u32 fdbck_reg)
>> +{
>> + u64 fref, refdiv, mdiv, reg, vco;
>> +
>> + reg = CM_REG_READL(plat, pllglob_reg);
>> +
>> + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
>> + CLKMGR_PLLGLOB_VCO_PSRC_MASK;
>> +
>> + switch (fref) {
>> + case CLKMGR_VCO_PSRC_EOSC1:
>> + fref = cm_get_osc_clk_hz();
>> + break;
>> + case CLKMGR_VCO_PSRC_INTOSC:
>> + fref = cm_get_intosc_clk_hz();
>> + break;
>> + case CLKMGR_VCO_PSRC_F2S:
>> + fref = cm_get_fpga_clk_hz();
>> + break;
>> + }
>> +
>> + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
>> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>> +
>> + reg = CM_REG_READL(plat, fdbck_reg);
>> + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
>> +
>> + vco = fref / refdiv;
>> + vco = vco * (CLKMGR_MDIV_CONST + mdiv);
>> +
>> + return vco;
>> +}
>> +
>> +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
>> + CLKMGR_MAINPLL_FDBCK);
>> +}
>> +
>> +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
>> + CLKMGR_PERPLL_FDBCK);
>> +}
>> +
>> +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
>> +{
>> + u32 clksrc = CM_REG_READL(plat, reg);
>> +
>> + return (clksrc >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>> +}
>> +
>> +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + u64 clock;
>> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_MPUCLK);
>> +
>> + switch (clklsrc) {
>> + case CLKMGR_CLKSRC_MAIN:
>> + clock = clk_get_main_vco_clk_hz(plat);
>> + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) &
>> + CLKMGR_PLLC0_DIV_MASK);
>> + break;
>> + case CLKMGR_CLKSRC_PER:
>> + clock = clk_get_per_vco_clk_hz(plat);
>> + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) &
>> + CLKMGR_CLKCNT_MSK);
>> + break;
>> + case CLKMGR_CLKSRC_OSC1:
>> + clock = cm_get_osc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_INTOSC:
>> + clock = cm_get_intosc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_FPGA:
>> + clock = cm_get_fpga_clk_hz();
>> + break;
>> + default:
>> + return 0;
>> + }
>> +
>> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
>> + CLKMGR_CLKCNT_MSK);
>> +
>> + return clock;
>> +}
>> +
>> +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + u64 clock;
>> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_NOCCLK);
>> +
>> + switch (clklsrc) {
>> + case CLKMGR_CLKSRC_MAIN:
>> + clock = clk_get_main_vco_clk_hz(plat);
>> + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) &
>> + CLKMGR_PLLC0_DIV_MASK);
>> + break;
>> + case CLKMGR_CLKSRC_PER:
>> + clock = clk_get_per_vco_clk_hz(plat);
>> + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) &
>> + CLKMGR_CLKCNT_MSK);
>> + break;
>> + case CLKMGR_CLKSRC_OSC1:
>> + clock = cm_get_osc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_INTOSC:
>> + clock = cm_get_intosc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_FPGA:
>> + clock = cm_get_fpga_clk_hz();
>> + break;
>> + default:
>> + return 0;
>> + }
>> +
>> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_NOCCLK) &
>> + CLKMGR_CLKCNT_MSK);
>> +
>> + return clock;
>> +}
>> +
>> +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + u32 clock;
>> + u32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_PERPLL_CNTR6CLK);
>> +
>> + switch (clklsrc) {
>> + case CLKMGR_CLKSRC_MAIN:
>> + clock = clk_get_l3_main_clk_hz(plat);
>> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_CNTR6CLK) &
>> CLKMGR_CLKCNT_MSK);
>> + break;
>> + case CLKMGR_CLKSRC_PER:
>> + clock = clk_get_l3_main_clk_hz(plat);
>> + clock /= 1 + (CM_REG_READL(plat, CLKMGR_PERPLL_CNTR6CLK) &
>> CLKMGR_CLKCNT_MSK);
>> + break;
>> + case CLKMGR_CLKSRC_OSC1:
>> + clock = cm_get_osc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_INTOSC:
>> + clock = cm_get_intosc_clk_hz();
>> + break;
>> + case CLKMGR_CLKSRC_FPGA:
>> + clock = cm_get_fpga_clk_hz();
>> + break;
>> + default:
>> + return 0;
>> + }
>> +
>> + return clock / 4;
>> +}
>> +
>> +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + u64 clock = clk_get_l3_main_clk_hz(plat);
>> +
>> + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
>> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
>> + CLKMGR_CLKCNT_MSK);
>> +
>> + return clock;
>> +}
>> +
>> +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
>> +{
>> + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
>> + return clk_get_l3_main_clk_hz(plat) / 2;
>> +
>> + return clk_get_l3_main_clk_hz(plat) / 4;
>> +}
>> +
>> +static ulong socfpga_clk_get_rate(struct clk *clk)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
>> +
>> + switch (clk->id) {
>> + case STRATIX10_MPU_CLK:
>> + return clk_get_mpu_clk_hz(plat);
>> + case STRATIX10_NOC_CLK:
>> + return clk_get_l3_main_clk_hz(plat);
>> + case STRATIX10_MAIN_PLL_CLK:
>> + return clk_get_main_vco_clk_hz(plat);
>> + case STRATIX10_PERIPH_PLL_CLK:
>> + return clk_get_per_vco_clk_hz(plat);
>> + case STRATIX10_OSC1:
>> + return cm_get_osc_clk_hz();
>> + case STRATIX10_SDMMC_CLK:
>> + return clk_get_sdmmc_clk_hz(plat);
>> + case STRATIX10_L4_SP_CLK:
>> + return clk_get_l4_sp_clk_hz(plat);
>> + case STRATIX10_L4_SYS_FREE_CLK:
>> + return clk_get_l4_sys_free_clk_hz(plat);
>
>
> missing STRATIX10_L4_MAIN_CLK(from upstream dts for spi0/1), please
> check whether is name diff between U-Boot & Linux, or missing.
>
>
I will add new case for STRATIX10_L4_MAIN_CLK and its own function to
retrieve the clock rate in v3.
>> + default:
>> + return -ENXIO;
>> + }
>> +}
>> +
>> +static int bitmask_from_clk_id(struct clk *clk)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
>> +
>> + switch (clk->id) {
>> + case STRATIX10_MPU_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
>> + break;
>> + case STRATIX10_L4_MAIN_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
>> + break;
>> + case STRATIX10_L4_MP_CLK:
>> + case STRATIX10_NAND_X_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
>> + break;
>> + case STRATIX10_L4_SP_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
>> + break;
>> + case STRATIX10_CS_AT_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
>> + break;
>> + case STRATIX10_CS_TRACE_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
>> + break;
>> + case STRATIX10_CS_PDBG_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
>> + break;
>> + case STRATIX10_CS_TIMER_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
>> + break;
>> + case STRATIX10_S2F_USER0_CLK:
>> + plat->pllgrp = CLKMGR_MAINPLL_EN;
>> + plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
>> + break;
>> + case STRATIX10_EMAC0_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
>> + break;
>> + case STRATIX10_EMAC1_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
>> + break;
>> + case STRATIX10_EMAC2_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
>> + break;
>> + case STRATIX10_EMAC_PTP_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
>> + break;
>> + case STRATIX10_GPIO_DB_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
>> + break;
>> + case STRATIX10_SDMMC_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
>> + break;
>> + case STRATIX10_S2F_USER1_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
>> + break;
>> + case STRATIX10_PSI_REF_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
>> + break;
>> + case STRATIX10_USB_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
>> + break;
>> + case STRATIX10_SPI_M_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
>> + break;
>> + case STRATIX10_NAND_CLK:
>> + plat->pllgrp = CLKMGR_PERPLL_EN;
>> + plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
>> + break;
>> + case STRATIX10_L4_SYS_FREE_CLK:
>> + return -EOPNOTSUPP;
>> + default:
>> + return -ENXIO;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int socfpga_clk_enable(struct clk *clk)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
>> + uintptr_t base_addr = (uintptr_t)plat->regs;
>> + int ret;
>> +
>> + ret = bitmask_from_clk_id(clk);
>> + if (ret == -EOPNOTSUPP)
>> + return 0;
>> +
>> + if (ret)
>> + return ret;
>> +
>> + setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
>> +
>> + return 0;
>> +}
>> +
>> +static int socfpga_clk_disable(struct clk *clk)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
>> + uintptr_t base_addr = (uintptr_t)plat->regs;
>> + int ret;
>> +
>> + ret = bitmask_from_clk_id(clk);
>> + if (ret == -EOPNOTSUPP)
>> + return 0;
>> +
>> + if (ret)
>> + return ret;
>> +
>> + clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
>> +
>> + return 0;
>> +}
>> +
>> +static int socfpga_clk_probe(struct udevice *dev)
>> +{
>> + const struct cm_config *cm_default_cfg = cm_get_default_config();
>> +
>> + clk_basic_init(dev, cm_default_cfg);
>> +
>> + return 0;
>> +}
>> +
>> +static int socfpga_clk_of_to_plat(struct udevice *dev)
>> +{
>> + struct socfpga_clk_plat *plat = dev_get_plat(dev);
>> + fdt_addr_t addr;
>> +
>> + addr = dev_read_addr(dev);
>> + if (addr == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> + plat->regs = (void __iomem *)addr;
>> +
>> + return 0;
>> +}
>> +
>> +static struct clk_ops socfpga_clk_ops = {
>> + .enable = socfpga_clk_enable,
>> + .disable = socfpga_clk_disable,
>> + .get_rate = socfpga_clk_get_rate,
>> +};
>> +
>> +static const struct udevice_id socfpga_clk_match[] = {
>> + { .compatible = "intel,stratix10-clkmgr" },
>> + {}
>> +};
>> +
>> +U_BOOT_DRIVER(socfpga_s10_clk) = {
>> + .name = "clk-s10",
>> + .id = UCLASS_CLK,
>> + .of_match = socfpga_clk_match,
>> + .ops = &socfpga_clk_ops,
>> + .probe = socfpga_clk_probe,
>> + .of_to_plat = socfpga_clk_of_to_plat,
>> + .plat_auto = sizeof(struct socfpga_clk_plat),
>> +};
>> diff --git a/drivers/clk/altera/clk-s10.h b/drivers/clk/altera/clk-s10.h
>> new file mode 100644
>> index 00000000000..f5be1e68500
>> --- /dev/null
>> +++ b/drivers/clk/altera/clk-s10.h
>> @@ -0,0 +1,202 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>
>
> NEW FILE, but derived from Intel code
>
> Copyright (C) 2016-2023 Intel Corporation <www.intel.com> ← must add
> (code origin)
>
>
I will add this in v3.
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> + *
>> + */
>> +
>> +#ifndef _CLK_S10_
>> +#define _CLK_S10_
>> +
>
>
> Best regards,
>
> Tien Fong
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 8/9] mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (6 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 7/9] clk: s10: Refactor S10 clock driver alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
2026-04-28 3:48 ` [PATCH v2 9/9] spl: s10: Enhance watchdog support in SPL for Stratix 10 alif.zakuan.yuslaimi
8 siblings, 0 replies; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Excluding Stratix10 from legacy implementation of retrieving clkmgr base
address as Stratix10's clock driver is already following clock driver model
and is supporting enable/disable APIs.
The legacy devices' clock driver will continue to be refactored to support
driver model which enables us to support enable/disable APIs for all these
devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
drivers/mmc/socfpga_dw_mmc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index c8da6ead0ea..b12212e02dd 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -59,7 +59,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
- !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
/* Disable SDMMC clock. */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
@@ -96,7 +97,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
#endif
if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
- !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
+ !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 9/9] spl: s10: Enhance watchdog support in SPL for Stratix 10
2026-04-28 3:48 [PATCH v2 0/9] SoCFPGA: Update Boot Support for Stratix10 in U-Boot alif.zakuan.yuslaimi
` (7 preceding siblings ...)
2026-04-28 3:48 ` [PATCH v2 8/9] mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval alif.zakuan.yuslaimi
@ 2026-04-28 3:48 ` alif.zakuan.yuslaimi
8 siblings, 0 replies; 19+ messages in thread
From: alif.zakuan.yuslaimi @ 2026-04-28 3:48 UTC (permalink / raw)
To: u-boot
Cc: Tom Rini, Marek Vasut, Simon Goldschmidt, Tien Fong Chee,
Lukasz Majewski, Peng Fan, Jaehoon Chung, Simon Glass,
Neil Armstrong, Kory Maincent, Yao Zi, Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Watchdog should be primed before longer, failure-prone steps such as
firewall, SDRAM or QSPI initialization so that if a hang occurs in one of
those steps, it is able to trigger a reset.
Switch from the legacy hw_watchdog_init() path to the driver-model WDT
(initr_watchdog()). This requires clocks and reset to be valid for
the L4 watchdog block, and so it must run after the clock manager
(uclass_get_device(UCLASS_CLK)) succeeds.
Enabling watchdog immediately after clock init keeps watchdog coverage as
early as possible.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
---
arch/arm/mach-socfpga/spl_s10.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index ace029557f3..588dca4fcd3 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -18,7 +18,7 @@
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-#include <watchdog.h>
+#include <wdt.h>
#include <dm/uclass.h>
u32 reset_flag(void)
@@ -54,13 +54,6 @@ void board_init_f(ulong dummy)
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
-#ifdef CONFIG_HW_WATCHDOG
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
-
/* ensure all processors are not released prior Linux boot */
writeq(0, CPU_RELEASE_ADDR);
@@ -80,6 +73,13 @@ void board_init_f(ulong dummy)
hang();
}
+ /*
+ * Enable watchdog as early as possible before initializing other
+ * component.
+ */
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
+
#ifdef CONFIG_DEBUG_UART
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
debug_uart_init();
--
2.43.7
^ permalink raw reply related [flat|nested] 19+ messages in thread