* [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-06-04 2:25 ` Alistair Francis
2024-05-23 12:40 ` [PATCH 2/6] target/riscv: Add AMO instructions for Zabha LIU Zhiwei
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 21 ---------------------
target/riscv/translate.c | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index eb080baddd..39bbf60f3c 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -96,27 +96,6 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
return true;
}
-static bool gen_amo(DisasContext *ctx, arg_atomic *a,
- void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
- MemOp mop)
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
- if (ctx->cfg_ptr->ext_zama16b) {
- mop |= MO_ATOM_WITHIN16;
- } else {
- mop |= MO_ALIGN;
- }
-
- decode_save_opc(ctx);
- src1 = get_address(ctx, a->rs1, 0);
- func(dest, src1, src2, ctx->mem_idx, mop);
-
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
-
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
REQUIRE_A_OR_ZALRSC(ctx);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 51dfb03685..b160bcbfe0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1075,6 +1075,27 @@ static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
return gen_unary(ctx, a, ext, f_tl);
}
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ if (ctx->cfg_ptr->ext_zama16b) {
+ mop |= MO_ATOM_WITHIN16;
+ } else {
+ mop |= MO_ALIGN;
+ }
+
+ decode_save_opc(ctx);
+ src1 = get_address(ctx, a->rs1, 0);
+ func(dest, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha
2024-05-23 12:40 ` [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha LIU Zhiwei
@ 2024-06-04 2:25 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2024-06-04 2:25 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis, dbarboza,
bmeng.cn, liwei1518
On Thu, May 23, 2024 at 10:43 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 21 ---------------------
> target/riscv/translate.c | 21 +++++++++++++++++++++
> 2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
> index eb080baddd..39bbf60f3c 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -96,27 +96,6 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
> return true;
> }
>
> -static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> - void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
> - MemOp mop)
> -{
> - TCGv dest = dest_gpr(ctx, a->rd);
> - TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> -
> - if (ctx->cfg_ptr->ext_zama16b) {
> - mop |= MO_ATOM_WITHIN16;
> - } else {
> - mop |= MO_ALIGN;
> - }
> -
> - decode_save_opc(ctx);
> - src1 = get_address(ctx, a->rs1, 0);
> - func(dest, src1, src2, ctx->mem_idx, mop);
> -
> - gen_set_gpr(ctx, a->rd, dest);
> - return true;
> -}
> -
> static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
> {
> REQUIRE_A_OR_ZALRSC(ctx);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 51dfb03685..b160bcbfe0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1075,6 +1075,27 @@ static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
> return gen_unary(ctx, a, ext, f_tl);
> }
>
> +static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
> + MemOp mop)
> +{
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +
> + if (ctx->cfg_ptr->ext_zama16b) {
> + mop |= MO_ATOM_WITHIN16;
> + } else {
> + mop |= MO_ALIGN;
> + }
> +
> + decode_save_opc(ctx);
> + src1 = get_address(ctx, a->rs1, 0);
> + func(dest, src1, src2, ctx->mem_idx, mop);
> +
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] target/riscv: Add AMO instructions for Zabha
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
2024-05-23 12:40 ` [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-06-04 3:09 ` Alistair Francis
2024-05-23 12:40 ` [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h] LIU Zhiwei
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131 ++++++++++++++++++++
target/riscv/translate.c | 4 +-
4 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index b327b144d7..f241b0b173 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_zaamo;
bool ext_zacas;
bool ext_zama16b;
+ bool ext_zabha;
bool ext_zalrsc;
bool ext_zawrs;
bool ext_zfa;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 972a1e8fd1..8a4801d442 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1021,3 +1021,23 @@ amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st
# *** Zimop may-be-operation extension ***
mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 0111011 @mop5
mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 0111011 @mop3
+
+# *** Zabhb Standard Extension ***
+amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st
+amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st
+amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st
+amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st
+amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st
+amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
+amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
new file mode 100644
index 0000000000..9093a1cfc1
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
@@ -0,0 +1,131 @@
+/*
+ * RISC-V translation routines for the Zabha Standard Extension.
+ *
+ * Copyright (c) 2024 Alibaba Group
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZABHA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zabha) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
+}
+
+static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
+}
+
+static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
+}
+
+static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
+}
+
+static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
+}
+
+static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
+}
+
+static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
+}
+
+static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
+}
+
+static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
+}
+
+static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW);
+}
+
+static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW);
+}
+
+static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW);
+}
+
+static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW);
+}
+
+static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW);
+}
+
+static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW);
+}
+
+static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW);
+}
+
+static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW);
+}
+
+static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
+{
+ REQUIRE_ZABHA(ctx);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b160bcbfe0..f597542f1c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1081,8 +1081,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ MemOp size = mop & MO_SIZE;
- if (ctx->cfg_ptr->ext_zama16b) {
+ if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
mop |= MO_ATOM_WITHIN16;
} else {
mop |= MO_ALIGN;
@@ -1116,6 +1117,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzicond.c.inc"
#include "insn_trans/trans_rvzacas.c.inc"
+#include "insn_trans/trans_rvzabha.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzicbo.c.inc"
#include "insn_trans/trans_rvzimop.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] target/riscv: Add AMO instructions for Zabha
2024-05-23 12:40 ` [PATCH 2/6] target/riscv: Add AMO instructions for Zabha LIU Zhiwei
@ 2024-06-04 3:09 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2024-06-04 3:09 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis, dbarboza,
bmeng.cn, liwei1518
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/insn32.decode | 20 +++
> target/riscv/insn_trans/trans_rvzabha.c.inc | 131 ++++++++++++++++++++
> target/riscv/translate.c | 4 +-
> 4 files changed, 155 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index b327b144d7..f241b0b173 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -84,6 +84,7 @@ struct RISCVCPUConfig {
> bool ext_zaamo;
> bool ext_zacas;
> bool ext_zama16b;
> + bool ext_zabha;
> bool ext_zalrsc;
> bool ext_zawrs;
> bool ext_zfa;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 972a1e8fd1..8a4801d442 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1021,3 +1021,23 @@ amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st
> # *** Zimop may-be-operation extension ***
> mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 0111011 @mop5
> mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 0111011 @mop3
> +
> +# *** Zabhb Standard Extension ***
> +amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
> new file mode 100644
> index 0000000000..9093a1cfc1
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
> @@ -0,0 +1,131 @@
> +/*
> + * RISC-V translation routines for the Zabha Standard Extension.
> + *
> + * Copyright (c) 2024 Alibaba Group
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZABHA(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zabha) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
> +}
> +
> +static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
> +}
> +
> +static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
> +}
> +
> +static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
> +}
> +
> +static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
> +}
> +
> +static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
> +}
> +
> +static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
> +}
> +
> +static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
> +}
> +
> +static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
> +}
> +
> +static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW);
> +}
> +
> +static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW);
> +}
> +
> +static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW);
> +}
> +
> +static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW);
> +}
> +
> +static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW);
> +}
> +
> +static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW);
> +}
> +
> +static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW);
> +}
> +
> +static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW);
> +}
> +
> +static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
> +{
> + REQUIRE_ZABHA(ctx);
> + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b160bcbfe0..f597542f1c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1081,8 +1081,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> {
> TCGv dest = dest_gpr(ctx, a->rd);
> TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> + MemOp size = mop & MO_SIZE;
>
> - if (ctx->cfg_ptr->ext_zama16b) {
> + if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
> mop |= MO_ATOM_WITHIN16;
> } else {
> mop |= MO_ALIGN;
> @@ -1116,6 +1117,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_rvzicond.c.inc"
> #include "insn_trans/trans_rvzacas.c.inc"
> +#include "insn_trans/trans_rvzabha.c.inc"
> #include "insn_trans/trans_rvzawrs.c.inc"
> #include "insn_trans/trans_rvzicbo.c.inc"
> #include "insn_trans/trans_rvzimop.c.inc"
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
2024-05-23 12:40 ` [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha LIU Zhiwei
2024-05-23 12:40 ` [PATCH 2/6] target/riscv: Add AMO instructions for Zabha LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-06-04 3:15 ` Alistair Francis
2024-05-23 12:40 ` [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha LIU Zhiwei
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -------------
target/riscv/translate.c | 13 +++++++++++++
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/insn_trans/trans_rvzacas.c.inc
index 5d274d4c08..fcced99fc7 100644
--- a/target/riscv/insn_trans/trans_rvzacas.c.inc
+++ b/target/riscv/insn_trans/trans_rvzacas.c.inc
@@ -22,19 +22,6 @@
} \
} while (0)
-static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
-{
- TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
- TCGv src1 = get_address(ctx, a->rs1, 0);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
- decode_save_opc(ctx);
- tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
-
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
-
static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a)
{
REQUIRE_ZACAS(ctx);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f597542f1c..0ce188bc91 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1097,6 +1097,19 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
return true;
}
+static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
+{
+ TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv src1 = get_address(ctx, a->rs1, 0);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ decode_save_opc(ctx);
+ tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
2024-05-23 12:40 ` [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h] LIU Zhiwei
@ 2024-06-04 3:15 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2024-06-04 3:15 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis, dbarboza,
bmeng.cn, liwei1518
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -------------
> target/riscv/translate.c | 13 +++++++++++++
> 2 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/insn_trans/trans_rvzacas.c.inc
> index 5d274d4c08..fcced99fc7 100644
> --- a/target/riscv/insn_trans/trans_rvzacas.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc
> @@ -22,19 +22,6 @@
> } \
> } while (0)
>
> -static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
> -{
> - TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
> - TCGv src1 = get_address(ctx, a->rs1, 0);
> - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> -
> - decode_save_opc(ctx);
> - tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
> -
> - gen_set_gpr(ctx, a->rd, dest);
> - return true;
> -}
> -
> static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a)
> {
> REQUIRE_ZACAS(ctx);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f597542f1c..0ce188bc91 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1097,6 +1097,19 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> return true;
> }
>
> +static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
> +{
> + TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
> + TCGv src1 = get_address(ctx, a->rs1, 0);
> + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +
> + decode_save_opc(ctx);
> + tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
> +
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
` (2 preceding siblings ...)
2024-05-23 12:40 ` [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h] LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-06-04 3:17 ` Alistair Francis
2024-05-23 12:40 ` [PATCH 5/6] target/riscv: Enable zabha for max cpu LIU Zhiwei
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8a4801d442..eee48f92d3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1041,3 +1041,5 @@ amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
+amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
+amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
index 9093a1cfc1..ce8edcba62 100644
--- a/target/riscv/insn_trans/trans_rvzabha.c.inc
+++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
@@ -129,3 +129,17 @@ static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
REQUIRE_ZABHA(ctx);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
}
+
+static bool trans_amocas_b(DisasContext *ctx, arg_amocas_b *a)
+{
+ REQUIRE_ZACAS(ctx);
+ REQUIRE_ZABHA(ctx);
+ return gen_cmpxchg(ctx, a, MO_SB);
+}
+
+static bool trans_amocas_h(DisasContext *ctx, arg_amocas_h *a)
+{
+ REQUIRE_ZACAS(ctx);
+ REQUIRE_ZABHA(ctx);
+ return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESW);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha
2024-05-23 12:40 ` [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha LIU Zhiwei
@ 2024-06-04 3:17 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2024-06-04 3:17 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis, dbarboza,
bmeng.cn, liwei1518
On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++++++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8a4801d442..eee48f92d3 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1041,3 +1041,5 @@ amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
> amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
> amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
> amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
> +amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
> index 9093a1cfc1..ce8edcba62 100644
> --- a/target/riscv/insn_trans/trans_rvzabha.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
> @@ -129,3 +129,17 @@ static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
> REQUIRE_ZABHA(ctx);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
> }
> +
> +static bool trans_amocas_b(DisasContext *ctx, arg_amocas_b *a)
> +{
> + REQUIRE_ZACAS(ctx);
> + REQUIRE_ZABHA(ctx);
> + return gen_cmpxchg(ctx, a, MO_SB);
> +}
> +
> +static bool trans_amocas_h(DisasContext *ctx, arg_amocas_h *a)
> +{
> + REQUIRE_ZACAS(ctx);
> + REQUIRE_ZABHA(ctx);
> + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESW);
> +}
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] target/riscv: Enable zabha for max cpu
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
` (3 preceding siblings ...)
2024-05-23 12:40 ` [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-05-24 11:38 ` Daniel Henrique Barboza
2024-05-23 12:40 ` [PATCH 6/6] disas/riscv: Support zabha disassemble LIU Zhiwei
2024-05-24 11:44 ` [PATCH 0/6] target/riscv: Support Zabha extension Daniel Henrique Barboza
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 21d4e36405..9ec03a1edc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -118,6 +118,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_12_0, ext_zama16b),
+ ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_12_0, ext_zabha),
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
@@ -1470,6 +1471,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zcmop", ext_zcmop, false),
MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false),
+ MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] target/riscv: Enable zabha for max cpu
2024-05-23 12:40 ` [PATCH 5/6] target/riscv: Enable zabha for max cpu LIU Zhiwei
@ 2024-05-24 11:38 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2024-05-24 11:38 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, bmeng.cn, liwei1518
On 5/23/24 09:40, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 21d4e36405..9ec03a1edc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -118,6 +118,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
> ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
> ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_12_0, ext_zama16b),
> + ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_12_0, ext_zabha),
I think this should be place right after zaamo. Thanks,
Daniel
> ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
> ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
> ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
> @@ -1470,6 +1471,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zcmop", ext_zcmop, false),
> MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
> MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false),
> + MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
> MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
> MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
> MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] disas/riscv: Support zabha disassemble
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
` (4 preceding siblings ...)
2024-05-23 12:40 ` [PATCH 5/6] target/riscv: Enable zabha for max cpu LIU Zhiwei
@ 2024-05-23 12:40 ` LIU Zhiwei
2024-06-04 3:18 ` Alistair Francis
2024-05-24 11:44 ` [PATCH 0/6] target/riscv: Support Zabha extension Daniel Henrique Barboza
6 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-23 12:40 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, dbarboza, bmeng.cn,
liwei1518, zhiwei_liu
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
disas/riscv.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 41050246f3..849af82ddf 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6 +954,26 @@ typedef enum {
rv_c_mop_11 = 923,
rv_c_mop_13 = 924,
rv_c_mop_15 = 925,
+ rv_op_amoswap_b = 926,
+ rv_op_amoadd_b = 927,
+ rv_op_amoxor_b = 928,
+ rv_op_amoor_b = 929,
+ rv_op_amoand_b = 930,
+ rv_op_amomin_b = 931,
+ rv_op_amomax_b = 932,
+ rv_op_amominu_b = 933,
+ rv_op_amomaxu_b = 934,
+ rv_op_amoswap_h = 935,
+ rv_op_amoadd_h = 936,
+ rv_op_amoxor_h = 937,
+ rv_op_amoor_h = 938,
+ rv_op_amoand_h = 939,
+ rv_op_amomin_h = 940,
+ rv_op_amomax_h = 941,
+ rv_op_amominu_h = 942,
+ rv_op_amomaxu_h = 943,
+ rv_op_amocas_b = 944,
+ rv_op_amocas_h = 945,
} rv_op;
/* register names */
@@ -2192,6 +2212,26 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2923,9 +2963,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 11:
switch (((inst >> 24) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
+ case 0: op = rv_op_amoadd_b; break;
+ case 1: op = rv_op_amoadd_h; break;
case 2: op = rv_op_amoadd_w; break;
case 3: op = rv_op_amoadd_d; break;
case 4: op = rv_op_amoadd_q; break;
+ case 8: op = rv_op_amoswap_b; break;
+ case 9: op = rv_op_amoswap_h; break;
case 10: op = rv_op_amoswap_w; break;
case 11: op = rv_op_amoswap_d; break;
case 12: op = rv_op_amoswap_q; break;
@@ -2947,27 +2991,43 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 26: op = rv_op_sc_w; break;
case 27: op = rv_op_sc_d; break;
case 28: op = rv_op_sc_q; break;
+ case 32: op = rv_op_amoxor_b; break;
+ case 33: op = rv_op_amoxor_h; break;
case 34: op = rv_op_amoxor_w; break;
case 35: op = rv_op_amoxor_d; break;
case 36: op = rv_op_amoxor_q; break;
+ case 40: op = rv_op_amocas_b; break;
+ case 41: op = rv_op_amocas_h; break;
case 42: op = rv_op_amocas_w; break;
case 43: op = rv_op_amocas_d; break;
case 44: op = rv_op_amocas_q; break;
+ case 64: op = rv_op_amoor_b; break;
+ case 65: op = rv_op_amoor_h; break;
case 66: op = rv_op_amoor_w; break;
case 67: op = rv_op_amoor_d; break;
case 68: op = rv_op_amoor_q; break;
+ case 96: op = rv_op_amoand_b; break;
+ case 97: op = rv_op_amoand_h; break;
case 98: op = rv_op_amoand_w; break;
case 99: op = rv_op_amoand_d; break;
case 100: op = rv_op_amoand_q; break;
+ case 128: op = rv_op_amomin_b; break;
+ case 129: op = rv_op_amomin_h; break;
case 130: op = rv_op_amomin_w; break;
case 131: op = rv_op_amomin_d; break;
case 132: op = rv_op_amomin_q; break;
+ case 160: op = rv_op_amomax_b; break;
+ case 161: op = rv_op_amomax_h; break;
case 162: op = rv_op_amomax_w; break;
case 163: op = rv_op_amomax_d; break;
case 164: op = rv_op_amomax_q; break;
+ case 192: op = rv_op_amominu_b; break;
+ case 193: op = rv_op_amominu_h; break;
case 194: op = rv_op_amominu_w; break;
case 195: op = rv_op_amominu_d; break;
case 196: op = rv_op_amominu_q; break;
+ case 224: op = rv_op_amomaxu_b; break;
+ case 225: op = rv_op_amomaxu_h; break;
case 226: op = rv_op_amomaxu_w; break;
case 227: op = rv_op_amomaxu_d; break;
case 228: op = rv_op_amomaxu_q; break;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] disas/riscv: Support zabha disassemble
2024-05-23 12:40 ` [PATCH 6/6] disas/riscv: Support zabha disassemble LIU Zhiwei
@ 2024-06-04 3:18 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2024-06-04 3:18 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis, dbarboza,
bmeng.cn, liwei1518
On Thu, May 23, 2024 at 10:46 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 41050246f3..849af82ddf 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -954,6 +954,26 @@ typedef enum {
> rv_c_mop_11 = 923,
> rv_c_mop_13 = 924,
> rv_c_mop_15 = 925,
> + rv_op_amoswap_b = 926,
> + rv_op_amoadd_b = 927,
> + rv_op_amoxor_b = 928,
> + rv_op_amoor_b = 929,
> + rv_op_amoand_b = 930,
> + rv_op_amomin_b = 931,
> + rv_op_amomax_b = 932,
> + rv_op_amominu_b = 933,
> + rv_op_amomaxu_b = 934,
> + rv_op_amoswap_h = 935,
> + rv_op_amoadd_h = 936,
> + rv_op_amoxor_h = 937,
> + rv_op_amoor_h = 938,
> + rv_op_amoand_h = 939,
> + rv_op_amomin_h = 940,
> + rv_op_amomax_h = 941,
> + rv_op_amominu_h = 942,
> + rv_op_amomaxu_h = 943,
> + rv_op_amocas_b = 944,
> + rv_op_amocas_h = 945,
> } rv_op;
>
> /* register names */
> @@ -2192,6 +2212,26 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> + { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> };
>
> /* CSR names */
> @@ -2923,9 +2963,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 11:
> switch (((inst >> 24) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> + case 0: op = rv_op_amoadd_b; break;
> + case 1: op = rv_op_amoadd_h; break;
> case 2: op = rv_op_amoadd_w; break;
> case 3: op = rv_op_amoadd_d; break;
> case 4: op = rv_op_amoadd_q; break;
> + case 8: op = rv_op_amoswap_b; break;
> + case 9: op = rv_op_amoswap_h; break;
> case 10: op = rv_op_amoswap_w; break;
> case 11: op = rv_op_amoswap_d; break;
> case 12: op = rv_op_amoswap_q; break;
> @@ -2947,27 +2991,43 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 26: op = rv_op_sc_w; break;
> case 27: op = rv_op_sc_d; break;
> case 28: op = rv_op_sc_q; break;
> + case 32: op = rv_op_amoxor_b; break;
> + case 33: op = rv_op_amoxor_h; break;
> case 34: op = rv_op_amoxor_w; break;
> case 35: op = rv_op_amoxor_d; break;
> case 36: op = rv_op_amoxor_q; break;
> + case 40: op = rv_op_amocas_b; break;
> + case 41: op = rv_op_amocas_h; break;
> case 42: op = rv_op_amocas_w; break;
> case 43: op = rv_op_amocas_d; break;
> case 44: op = rv_op_amocas_q; break;
> + case 64: op = rv_op_amoor_b; break;
> + case 65: op = rv_op_amoor_h; break;
> case 66: op = rv_op_amoor_w; break;
> case 67: op = rv_op_amoor_d; break;
> case 68: op = rv_op_amoor_q; break;
> + case 96: op = rv_op_amoand_b; break;
> + case 97: op = rv_op_amoand_h; break;
> case 98: op = rv_op_amoand_w; break;
> case 99: op = rv_op_amoand_d; break;
> case 100: op = rv_op_amoand_q; break;
> + case 128: op = rv_op_amomin_b; break;
> + case 129: op = rv_op_amomin_h; break;
> case 130: op = rv_op_amomin_w; break;
> case 131: op = rv_op_amomin_d; break;
> case 132: op = rv_op_amomin_q; break;
> + case 160: op = rv_op_amomax_b; break;
> + case 161: op = rv_op_amomax_h; break;
> case 162: op = rv_op_amomax_w; break;
> case 163: op = rv_op_amomax_d; break;
> case 164: op = rv_op_amomax_q; break;
> + case 192: op = rv_op_amominu_b; break;
> + case 193: op = rv_op_amominu_h; break;
> case 194: op = rv_op_amominu_w; break;
> case 195: op = rv_op_amominu_d; break;
> case 196: op = rv_op_amominu_q; break;
> + case 224: op = rv_op_amomaxu_b; break;
> + case 225: op = rv_op_amomaxu_h; break;
> case 226: op = rv_op_amomaxu_w; break;
> case 227: op = rv_op_amomaxu_d; break;
> case 228: op = rv_op_amomaxu_q; break;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] target/riscv: Support Zabha extension
2024-05-23 12:40 [PATCH 0/6] target/riscv: Support Zabha extension LIU Zhiwei
` (5 preceding siblings ...)
2024-05-23 12:40 ` [PATCH 6/6] disas/riscv: Support zabha disassemble LIU Zhiwei
@ 2024-05-24 11:44 ` Daniel Henrique Barboza
2024-05-26 0:37 ` LIU Zhiwei
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Henrique Barboza @ 2024-05-24 11:44 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, bmeng.cn, liwei1518
Hi Zhiwei!
On 5/23/24 09:40, LIU Zhiwei wrote:
> Zabha adds support AMO operations for byte and half word. If zacas has been implemented,
> zabha also adds support amocas.b and amocas.h.
>
> More details is on the specification here:
> https://github.com/riscv/riscv-zabha
>
> The implemenation of zabha follows the way of AMOs and zacas.
>
> This patch set is based on these two patch set:
> 1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
> 2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
These 2 series doesn't seem to apply on top of each other, doesn't matter which
order I try. Applying zimop/zcmop first, then zama16b:
$ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
Applying: target/riscv: Support Zama16b extension
error: patch failed: target/riscv/cpu.c:1464
error: target/riscv/cpu.c: patch does not apply
Patch failed at 0001 target/riscv: Support Zama16b extension
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Applying zama16b first, then zimop/zcmop:
$ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
Applying: target/riscv: Support Zama16b extension
$
$ git am \[PATCH\ 1_4\]\ target_riscv\:\ Add\ zimop\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml \[PATCH\ 2_4\]\ disas_riscv\:\ Support\ zimop\ disassemble\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml
Applying: target/riscv: Add zimop extension
error: patch failed: target/riscv/cpu.c:1463
error: target/riscv/cpu.c: patch does not apply
Patch failed at 0001 target/riscv: Add zimop extension
If the series are dependent on each other perhaps it's easier to send everything
in a single 11 patches series.
Thanks,
Daniel
>
>
> LIU Zhiwei (6):
> target/riscv: Move gen_amo before implement Zabha
> target/riscv: Add AMO instructions for Zabha
> target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
> target/riscv: Add amocas.[b|h] for Zabha
> target/riscv: Enable zabha for max cpu
> disas/riscv: Support zabha disassemble
>
> disas/riscv.c | 60 ++++++++
> target/riscv/cpu.c | 2 +
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/insn32.decode | 22 +++
> target/riscv/insn_trans/trans_rva.c.inc | 21 ---
> target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++++++
> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
> target/riscv/translate.c | 36 +++++
> 8 files changed, 266 insertions(+), 34 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] target/riscv: Support Zabha extension
2024-05-24 11:44 ` [PATCH 0/6] target/riscv: Support Zabha extension Daniel Henrique Barboza
@ 2024-05-26 0:37 ` LIU Zhiwei
2024-05-26 17:16 ` Daniel Henrique Barboza
0 siblings, 1 reply; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-26 0:37 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, bmeng.cn, liwei1518
On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
> Hi Zhiwei!
>
>
>
> On 5/23/24 09:40, LIU Zhiwei wrote:
>> Zabha adds support AMO operations for byte and half word. If zacas
>> has been implemented,
>> zabha also adds support amocas.b and amocas.h.
>>
>> More details is on the specification here:
>> https://github.com/riscv/riscv-zabha
>>
>> The implemenation of zabha follows the way of AMOs and zacas.
>>
>> This patch set is based on these two patch set:
>> 1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
>> 2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
>
> These 2 series doesn't seem to apply on top of each other, doesn't
> matter which
> order I try. Applying zimop/zcmop first, then zama16b:
>
> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\
> -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
> Applying: target/riscv: Support Zama16b extension
> error: patch failed: target/riscv/cpu.c:1464
> error: target/riscv/cpu.c: patch does not apply
> Patch failed at 0001 target/riscv: Support Zama16b extension
> hint: Use 'git am --show-current-patch=diff' to see the failed patch
>
>
> Applying zama16b first, then zimop/zcmop:
>
> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\
> -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
> Applying: target/riscv: Support Zama16b extension
> $
> $ git am \[PATCH\ 1_4\]\ target_riscv\:\ Add\ zimop\ extension\ -\
> LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml
> \[PATCH\ 2_4\]\ disas_riscv\:\ Support\ zimop\ disassemble\ -\ LIU\
> Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml
> Applying: target/riscv: Add zimop extension
> error: patch failed: target/riscv/cpu.c:1463
> error: target/riscv/cpu.c: patch does not apply
> Patch failed at 0001 target/riscv: Add zimop extension
>
>
> If the series are dependent on each other perhaps it's easier to send
> everything
> in a single 11 patches series.
They don't have dependency on each other. But if we both rebase them to
the master branch, they
couldn't be merged at the time, as them both modify cpu.h and cpu.c in
the same place.
I will send them as a whole patch set(RVA23 patch set) after I fix other
issues on implementing the RVA23 profile.
Thanks,
Zhiwei
>
>
> Thanks,
>
> Daniel
>
>>
>>
>> LIU Zhiwei (6):
>> target/riscv: Move gen_amo before implement Zabha
>> target/riscv: Add AMO instructions for Zabha
>> target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
>> target/riscv: Add amocas.[b|h] for Zabha
>> target/riscv: Enable zabha for max cpu
>> disas/riscv: Support zabha disassemble
>>
>> disas/riscv.c | 60 ++++++++
>> target/riscv/cpu.c | 2 +
>> target/riscv/cpu_cfg.h | 1 +
>> target/riscv/insn32.decode | 22 +++
>> target/riscv/insn_trans/trans_rva.c.inc | 21 ---
>> target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++++++
>> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
>> target/riscv/translate.c | 36 +++++
>> 8 files changed, 266 insertions(+), 34 deletions(-)
>> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] target/riscv: Support Zabha extension
2024-05-26 0:37 ` LIU Zhiwei
@ 2024-05-26 17:16 ` Daniel Henrique Barboza
2024-05-27 1:52 ` LIU Zhiwei
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Henrique Barboza @ 2024-05-26 17:16 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, bmeng.cn, liwei1518
On 5/25/24 21:37, LIU Zhiwei wrote:
>
> On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
>> Hi Zhiwei!
>>
>>
>>
>> On 5/23/24 09:40, LIU Zhiwei wrote:
>>> Zabha adds support AMO operations for byte and half word. If zacas has been implemented,
>>> zabha also adds support amocas.b and amocas.h.
>>>
>>> More details is on the specification here:
>>> https://github.com/riscv/riscv-zabha
>>>
>>> The implemenation of zabha follows the way of AMOs and zacas.
>>>
>>> This patch set is based on these two patch set:
>>> 1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
>>> 2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
>>
>> These 2 series doesn't seem to apply on top of each other, doesn't matter which
>> order I try. Applying zimop/zcmop first, then zama16b:
>>
>> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
>> Applying: target/riscv: Support Zama16b extension
>> error: patch failed: target/riscv/cpu.c:1464
>> error: target/riscv/cpu.c: patch does not apply
>> Patch failed at 0001 target/riscv: Support Zama16b extension
>> hint: Use 'git am --show-current-patch=diff' to see the failed patch
>>
>>
>> Applying zama16b first, then zimop/zcmop:
>>
>> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
>> Applying: target/riscv: Support Zama16b extension
>> $
>> $ git am \[PATCH\ 1_4\]\ target_riscv\:\ Add\ zimop\ extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml \[PATCH\ 2_4\]\ disas_riscv\:\ Support\ zimop\ disassemble\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml
>> Applying: target/riscv: Add zimop extension
>> error: patch failed: target/riscv/cpu.c:1463
>> error: target/riscv/cpu.c: patch does not apply
>> Patch failed at 0001 target/riscv: Add zimop extension
>>
>>
>> If the series are dependent on each other perhaps it's easier to send everything
>> in a single 11 patches series.
>
> They don't have dependency on each other. But if we both rebase them to the master branch, they
> couldn't be merged at the time, as them both modify cpu.h and cpu.c in the same place.
>
>
> I will send them as a whole patch set(RVA23 patch set) after I fix other issues on implementing the RVA23 profile.
Be aware that we have some RVA23 extensions that are implemented in the ML
but not merged no master yet. E.g. sstvala ended up being implemented after some
changes I did w.r.t tval and EBREAK. These patches are on riscv-to-apply.next.
Also, I took another look at RVA23 mandatory exts and what we have. I think we're
not that far off after these extensions you're adding. What we really seems to be
missing is supm and ssnpm.
Thanks,
Daniel
>
> Thanks,
>
> Zhiwei
>
>>
>>
>> Thanks,
>>
>> Daniel
>>
>>>
>>>
>>> LIU Zhiwei (6):
>>> target/riscv: Move gen_amo before implement Zabha
>>> target/riscv: Add AMO instructions for Zabha
>>> target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
>>> target/riscv: Add amocas.[b|h] for Zabha
>>> target/riscv: Enable zabha for max cpu
>>> disas/riscv: Support zabha disassemble
>>>
>>> disas/riscv.c | 60 ++++++++
>>> target/riscv/cpu.c | 2 +
>>> target/riscv/cpu_cfg.h | 1 +
>>> target/riscv/insn32.decode | 22 +++
>>> target/riscv/insn_trans/trans_rva.c.inc | 21 ---
>>> target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++++++
>>> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
>>> target/riscv/translate.c | 36 +++++
>>> 8 files changed, 266 insertions(+), 34 deletions(-)
>>> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] target/riscv: Support Zabha extension
2024-05-26 17:16 ` Daniel Henrique Barboza
@ 2024-05-27 1:52 ` LIU Zhiwei
0 siblings, 0 replies; 17+ messages in thread
From: LIU Zhiwei @ 2024-05-27 1:52 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, palmer, Alistair.Francis, bmeng.cn, liwei1518,
Alexey Baturo
On 2024/5/27 1:16, Daniel Henrique Barboza wrote:
>
>
> On 5/25/24 21:37, LIU Zhiwei wrote:
>>
>> On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
>>> Hi Zhiwei!
>>>
>>>
>>>
>>> On 5/23/24 09:40, LIU Zhiwei wrote:
>>>> Zabha adds support AMO operations for byte and half word. If zacas
>>>> has been implemented,
>>>> zabha also adds support amocas.b and amocas.h.
>>>>
>>>> More details is on the specification here:
>>>> https://github.com/riscv/riscv-zabha
>>>>
>>>> The implemenation of zabha follows the way of AMOs and zacas.
>>>>
>>>> This patch set is based on these two patch set:
>>>> 1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
>>>> 2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
>>>
>>> These 2 series doesn't seem to apply on top of each other, doesn't
>>> matter which
>>> order I try. Applying zimop/zcmop first, then zama16b:
>>>
>>> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\
>>> extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\
>>> 2024-05-22\ 0613.eml
>>> Applying: target/riscv: Support Zama16b extension
>>> error: patch failed: target/riscv/cpu.c:1464
>>> error: target/riscv/cpu.c: patch does not apply
>>> Patch failed at 0001 target/riscv: Support Zama16b extension
>>> hint: Use 'git am --show-current-patch=diff' to see the failed patch
>>>
>>>
>>> Applying zama16b first, then zimop/zcmop:
>>>
>>> $ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\
>>> extension\ -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\
>>> 2024-05-22\ 0613.eml
>>> Applying: target/riscv: Support Zama16b extension
>>> $
>>> $ git am \[PATCH\ 1_4\]\ target_riscv\:\ Add\ zimop\ extension\ -\
>>> LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\
>>> 0329.eml \[PATCH\ 2_4\]\ disas_riscv\:\ Support\ zimop\ disassemble\
>>> -\ LIU\ Zhiwei\ \<zhiwei_liu@linux.alibaba.com\>\ -\ 2024-05-22\
>>> 0329.eml
>>> Applying: target/riscv: Add zimop extension
>>> error: patch failed: target/riscv/cpu.c:1463
>>> error: target/riscv/cpu.c: patch does not apply
>>> Patch failed at 0001 target/riscv: Add zimop extension
>>>
>>>
>>> If the series are dependent on each other perhaps it's easier to
>>> send everything
>>> in a single 11 patches series.
>>
>> They don't have dependency on each other. But if we both rebase them
>> to the master branch, they
>> couldn't be merged at the time, as them both modify cpu.h and cpu.c
>> in the same place.
>>
>>
>> I will send them as a whole patch set(RVA23 patch set) after I fix
>> other issues on implementing the RVA23 profile.
>
>
> Be aware that we have some RVA23 extensions that are implemented in
> the ML
> but not merged no master yet. E.g. sstvala ended up being implemented
> after some
> changes I did w.r.t tval and EBREAK. These patches are on
> riscv-to-apply.next.
Yes. Besides these, there are some missing checks in Smstateen. And we
also need add named features for Sh* extensions.
>
> Also, I took another look at RVA23 mandatory exts and what we have. I
> think we're
> not that far off after these extensions you're adding. What we really
> seems to be
> missing is supm and ssnpm.
Alexey is working on this. I have some comments and let's wait for his
next patch set.
Thanks,
Zhiwei
>
>
> Thanks,
>
> Daniel
>
>>
>> Thanks,
>>
>> Zhiwei
>>
>>>
>>>
>>> Thanks,
>>>
>>> Daniel
>>>
>>>>
>>>>
>>>> LIU Zhiwei (6):
>>>> target/riscv: Move gen_amo before implement Zabha
>>>> target/riscv: Add AMO instructions for Zabha
>>>> target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
>>>> target/riscv: Add amocas.[b|h] for Zabha
>>>> target/riscv: Enable zabha for max cpu
>>>> disas/riscv: Support zabha disassemble
>>>>
>>>> disas/riscv.c | 60 ++++++++
>>>> target/riscv/cpu.c | 2 +
>>>> target/riscv/cpu_cfg.h | 1 +
>>>> target/riscv/insn32.decode | 22 +++
>>>> target/riscv/insn_trans/trans_rva.c.inc | 21 ---
>>>> target/riscv/insn_trans/trans_rvzabha.c.inc | 145
>>>> ++++++++++++++++++++
>>>> target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
>>>> target/riscv/translate.c | 36 +++++
>>>> 8 files changed, 266 insertions(+), 34 deletions(-)
>>>> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>>>>
^ permalink raw reply [flat|nested] 17+ messages in thread