All of lore.kernel.org
 help / color / mirror / Atom feed
From: Pratyush Yadav <pratyush@kernel.org>
To: Cheng Ming Lin <linchengming884@gmail.com>
Cc: tudor.ambarus@linaro.org,  pratyush@kernel.org,
	 mwalle@kernel.org, miquel.raynal@bootlin.com,  richard@nod.at,
	 vigneshr@ti.com, linux-mtd@lists.infradead.org,
	 linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw,
	 leoyu@mxic.com.tw,  Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: Re: [PATCH v2 3/3] mtd: spi-nor: macronix: Add fixups for MX25L3255E
Date: Tue, 08 Apr 2025 14:52:07 +0000	[thread overview]
Message-ID: <mafs0semipuy0.fsf@kernel.org> (raw)
In-Reply-To: <20250407075400.1113177-4-linchengming884@gmail.com>

On Mon, Apr 07 2025, Cheng Ming Lin wrote:

> From: Cheng Ming Lin <chengminglin@mxic.com.tw>
>
> SFDP of MX25L3255E is JESD216, which does not include the Quad
> Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> Therefore, it is necessary to correct this setting by late_init.
>
> In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> address mode. However, since the 3-byte address 1-4-4 page program
> is not defined in SFDP, it needs to be configured in late_init.
>
> Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw>
> ---
>  drivers/mtd/spi-nor/macronix.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 07e0bd0b70a0..4bbd3b651cec 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
>  	return 0;
>  }
>  
> +static int
> +mx25l3255e_late_init_fixups(struct spi_nor *nor)
> +{
> +	/*
> +	 * SFDP of MX25L3255E is JESD216, which does not include the Quad
> +	 * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> +	 * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> +	 * Therefore, it is necessary to correct this setting by late_init.
> +	 */
> +	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> +
> +	/*
> +	 * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> +	 * address mode. However, since the 3-byte address 1-4-4 page program
> +	 * is not defined in SFDP, it needs to be configured in late_init.
> +	 */
> +	struct spi_nor_flash_parameter *params = nor->params;

Please don't have variable declarations in the middle of the function.
It looks odd. Though neither checkpatch nor cc seem to complain about
this. I thought they did...

Anyway, no need for a new revision, this can be fixed when applying by
me or Tudor.

Acked-by: Pratyush Yadav <pratyush@kernel.org>

> +
> +	params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
> +	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_4_4],
> +				SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);
> +
> +	return 0;
> +}
> +
[...]

-- 
Regards,
Pratyush Yadav

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <pratyush@kernel.org>
To: Cheng Ming Lin <linchengming884@gmail.com>
Cc: tudor.ambarus@linaro.org,  pratyush@kernel.org,
	 mwalle@kernel.org, miquel.raynal@bootlin.com,  richard@nod.at,
	 vigneshr@ti.com, linux-mtd@lists.infradead.org,
	 linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw,
	 leoyu@mxic.com.tw,  Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: Re: [PATCH v2 3/3] mtd: spi-nor: macronix: Add fixups for MX25L3255E
Date: Tue, 08 Apr 2025 14:52:07 +0000	[thread overview]
Message-ID: <mafs0semipuy0.fsf@kernel.org> (raw)
In-Reply-To: <20250407075400.1113177-4-linchengming884@gmail.com>

On Mon, Apr 07 2025, Cheng Ming Lin wrote:

> From: Cheng Ming Lin <chengminglin@mxic.com.tw>
>
> SFDP of MX25L3255E is JESD216, which does not include the Quad
> Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> Therefore, it is necessary to correct this setting by late_init.
>
> In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> address mode. However, since the 3-byte address 1-4-4 page program
> is not defined in SFDP, it needs to be configured in late_init.
>
> Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw>
> ---
>  drivers/mtd/spi-nor/macronix.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 07e0bd0b70a0..4bbd3b651cec 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
>  	return 0;
>  }
>  
> +static int
> +mx25l3255e_late_init_fixups(struct spi_nor *nor)
> +{
> +	/*
> +	 * SFDP of MX25L3255E is JESD216, which does not include the Quad
> +	 * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> +	 * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> +	 * Therefore, it is necessary to correct this setting by late_init.
> +	 */
> +	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> +
> +	/*
> +	 * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> +	 * address mode. However, since the 3-byte address 1-4-4 page program
> +	 * is not defined in SFDP, it needs to be configured in late_init.
> +	 */
> +	struct spi_nor_flash_parameter *params = nor->params;

Please don't have variable declarations in the middle of the function.
It looks odd. Though neither checkpatch nor cc seem to complain about
this. I thought they did...

Anyway, no need for a new revision, this can be fixed when applying by
me or Tudor.

Acked-by: Pratyush Yadav <pratyush@kernel.org>

> +
> +	params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
> +	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_4_4],
> +				SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);
> +
> +	return 0;
> +}
> +
[...]

-- 
Regards,
Pratyush Yadav

  parent reply	other threads:[~2025-04-08 14:54 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-07  7:53 [PATCH v2 0/3] mtd: spi-nor: macronix: Cleanup macronix flash info Cheng Ming Lin
2025-04-07  7:53 ` Cheng Ming Lin
2025-04-07  7:53 ` [PATCH v2 1/3] mtd: spi-nor: macronix: Drop the redundant flash info fields Cheng Ming Lin
2025-04-07  7:53   ` Cheng Ming Lin
2025-06-08  1:04   ` Guenter Roeck
2025-06-08  1:04     ` Guenter Roeck
2025-06-08 12:53     ` Pratyush Yadav
2025-06-08 12:53       ` Pratyush Yadav
2025-06-09  1:13       ` Guenter Roeck
2025-06-09  1:13         ` Guenter Roeck
2025-06-10  0:14         ` Guenter Roeck
2025-06-10  0:14           ` Guenter Roeck
2025-06-10  6:46           ` Tudor Ambarus
2025-06-10  6:46             ` Tudor Ambarus
2025-06-10  7:29             ` Cheng Ming Lin
2025-06-10  7:29               ` Cheng Ming Lin
2025-06-10  7:43               ` Guenter Roeck
2025-06-10  7:43                 ` Guenter Roeck
2025-09-24 12:10               ` Michael Walle
2025-09-24 12:10                 ` Michael Walle
2025-09-30  7:36                 ` Cheng Ming Lin
2025-09-30  7:36                   ` Cheng Ming Lin
2025-09-30 12:19                   ` Pratyush Yadav
2025-09-30 12:19                     ` Pratyush Yadav
2025-09-30 13:15                     ` Maarten Zanders
2025-09-30 13:15                       ` Maarten Zanders
2025-10-01  6:59                       ` Michael Walle
2025-10-01  6:59                         ` Michael Walle
2025-09-30 14:39                     ` Guenter Roeck
2025-09-30 14:39                       ` Guenter Roeck
2025-06-10  7:41             ` Guenter Roeck
2025-06-10  7:41               ` Guenter Roeck
2025-06-22 19:09               ` Pratyush Yadav
2025-06-22 19:09                 ` Pratyush Yadav
2025-10-01  9:35                 ` Cédric Le Goater
2025-10-01  9:35                   ` Cédric Le Goater
2025-04-07  7:53 ` [PATCH v2 2/3] mtd: spi-nor: macronix: Remove duplicate flash info entries Cheng Ming Lin
2025-04-07  7:53   ` Cheng Ming Lin
2025-04-07  7:54 ` [PATCH v2 3/3] mtd: spi-nor: macronix: Add fixups for MX25L3255E Cheng Ming Lin
2025-04-07  7:54   ` Cheng Ming Lin
2025-04-07  8:25   ` Cheng Ming Lin
2025-04-07  8:25     ` Cheng Ming Lin
2025-04-08 14:52   ` Pratyush Yadav [this message]
2025-04-08 14:52     ` Pratyush Yadav
2025-05-06  9:36 ` [PATCH v2 0/3] mtd: spi-nor: macronix: Cleanup macronix flash info Pratyush Yadav
2025-05-06  9:36   ` Pratyush Yadav

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=mafs0semipuy0.fsf@kernel.org \
    --to=pratyush@kernel.org \
    --cc=alvinzhou@mxic.com.tw \
    --cc=chengminglin@mxic.com.tw \
    --cc=leoyu@mxic.com.tw \
    --cc=linchengming884@gmail.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=miquel.raynal@bootlin.com \
    --cc=mwalle@kernel.org \
    --cc=richard@nod.at \
    --cc=tudor.ambarus@linaro.org \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.