* [U-Boot] [PATCH v8 08/10] nds32: standalone support
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add standalone program related support for nds32 architecture.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
examples/standalone/nds32.lds | 64 +++++++++++++++++++++++++++++++++++++
examples/standalone/stubs.c | 17 +++++++++-
examples/standalone/x86-testapp.c | 12 +++++++
3 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 examples/standalone/nds32.lds
diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ _end = .;
+
+ . = 0x02000000;
+ .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 2d2e709..b711926 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
" jmp %%g1\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" lwi $r16, [$gp + (%0)]\n" \
+" lwi $r16, [$r16 + (%1)]\n" \
+" jr $r16\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
#else
+/*" addi $sp, $sp, -24\n" \
+" br $r16\n" \*/
+
#error stubs definition missing for this architecture
#endif
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile ( \
" lw $25, %1($25)\n" \
" jr $25\n" \
: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x) \
+asm volatile ( \
+" .globl mon_" #x "\n" \
+"mon_" #x ":\n" \
+" lwi $r16, [$gp + (%0)]\n" \
+" lwi $r16, [$r16 + (%1)]\n" \
+" jr $r16\n" \
+ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
#else
#error [No stub code for this arch]
#endif
@@ -72,6 +82,8 @@ int main(void)
register volatile xxx_t *pq asm("r8");
#elif defined(__mips__)
register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+ register volatile xxx_t *pq asm("$r16");
#endif
char buf[32];
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 07/10] nds32/lib: add generic funcs in NDS32 lib
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
- code clean up and formatting style.
Changes for v5-v6:
- board.c
- Do some clean up and add code
- Remove display banner which hasn't support.
- Add ftpmu010 related power management unit code.
- Remove useless LED related code.
- Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
- Remove CONFIG_SOFT_I2C which hasn't been support.
- Remove CONFIG_FSL_ESDHC which hasn't been support.
- clean up.
Changes for v7:
- clean up.
- move single file patch arch/nds32/config.mk to this commit.
- interrupts.c refine origin interrupt enable and disable.
Changes for v8:
- interrups.c: fix up for new ptraces.h.
arch/nds32/config.mk | 35 +++++
arch/nds32/lib/Makefile | 52 +++++++
arch/nds32/lib/board.c | 346 +++++++++++++++++++++++++++++++++++++++++++
arch/nds32/lib/bootm.c | 241 ++++++++++++++++++++++++++++++
arch/nds32/lib/interrupts.c | 131 ++++++++++++++++
5 files changed, 805 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/config.mk
create mode 100644 arch/nds32/lib/Makefile
create mode 100644 arch/nds32/lib/board.c
create mode 100644 arch/nds32/lib/bootm.c
create mode 100644 arch/nds32/lib/interrupts.c
diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..ac5d0cf
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common
+PLATFORM_RELFLAGS += -gdwarf-2
+PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..eca4324
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(ARCH).o
+
+OBJS := board.o bootm.o interrupts.o
+
+all: $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..6ed4194
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+ U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+ char tmp[64]; /* long enough for environment variables */
+ int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+ gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+ ? (int) simple_strtoul(tmp, NULL, 10)
+ : CONFIG_BAUDRATE;
+
+ return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+ int i;
+
+#ifdef DEBUG
+ puts("RAM Configuration:\n");
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size(gd->bd->bi_dram[i].size, "\n");
+ }
+#else
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ size += gd->bd->bi_dram[i].size;
+
+ puts("DRAM: ");
+ print_size(size, "\n");
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+ puts("Flash: ");
+ print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+ pci_init();
+ return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__ /* AG101: internal definition in toolchain */
+ ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+ ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+ ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif /* __NDS32_N1213_43U1H__ */
+#endif
+ return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+ arch_cpu_init, /* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+ pmu_init,
+#endif
+ board_init, /* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+ interrupt_init, /* set up exceptions */
+#endif
+ timer_init, /* initialize timer */
+ env_init, /* initialize environment */
+ init_baudrate, /* initialze baudrate settings */
+ serial_init, /* serial communications setup */
+ console_init_f, /* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+ checkboard, /* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ init_func_i2c,
+#endif
+ dram_init, /* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+ nds32_pci_init,
+#endif
+ display_dram_config,
+ NULL,
+};
+
+void start_andesboot(void)
+{
+ init_fnc_t **init_fnc_ptr;
+ char *s;
+#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
+ unsigned long addr;
+#endif
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)(_andesboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ memset((void *)gd, 0, sizeof(gd_t));
+ gd->bd = (bd_t *)((char *)gd - sizeof(bd_t));
+ memset(gd->bd, 0, sizeof(bd_t));
+
+ gd->flags |= GD_FLG_RELOC;
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
+
+ /* andesboot_start is defined in the board-specific linker script */
+ mem_malloc_init(_andesboot_start - CONFIG_SYS_MALLOC_LEN,
+ CONFIG_SYS_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* configure available FLASH banks */
+ gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+ gd->bd->bi_flashsize = flash_init();
+ gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+ if (gd->bd->bi_flashsize)
+ display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#ifdef CONFIG_VFD
+# ifndef PAGE_SIZE
+# define PAGE_SIZE 4096
+# endif
+ /*
+ * reserve memory for VFD display (always full pages)
+ */
+ /* bss_end is defined in the board-specific linker script */
+ addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ vfd_setmem(addr);
+ gd->fb_base = addr;
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_LCD
+ /* board init may have inited fb_base */
+ if (!gd->fb_base) {
+# ifndef PAGE_SIZE
+# define PAGE_SIZE 4096
+# endif
+ /*
+ * reserve memory for LCD display (always full pages)
+ */
+ /* bss_end is defined in the board-specific linker script */
+ addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ lcd_setmem(addr);
+ gd->fb_base = addr;
+ }
+#endif /* CONFIG_LCD */
+
+#if defined(CONFIG_CMD_NAND)
+ puts("NAND: ");
+ nand_init(); /* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+ onenand_init();
+#endif
+
+ /* initialize environment */
+ env_relocate();
+
+#ifdef CONFIG_VFD
+ /* must do this after the framebuffer is allocated */
+ drv_vfd_init();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
+ /* IP Address */
+ gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+ stdio_init(); /* get the devices list going. */
+
+ jumptable_init();
+
+#if defined(CONFIG_API)
+ /* Initialize API */
+ api_init();
+#endif
+
+ console_init_r(); /* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+ /* miscellaneous arch dependent initialisations */
+ arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+ /* miscellaneous platform dependent initialisations */
+ misc_init_r();
+#endif
+
+ /* enable exceptions */
+ enable_interrupts();
+
+ /* Perform network card initialisation if necessary */
+
+ /* Initialize from environment */
+ s = getenv("loadaddr");
+ if (s != NULL)
+ load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+ s = getenv("bootfile");
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+ board_late_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+ puts("MMC: ");
+ mmc_initialize(gd->bd);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+ puts("Net: ");
+#endif
+ eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+ debug("Reset Ethernet PHY\n");
+ reset_phy();
+#endif
+#endif
+ /* main_loop() can return to retry autoboot, if so just run it again. */
+ for (;;)
+ main_loop();
+
+ /* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv("bootargs");
+#endif
+
+ if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ return 1;
+
+ theKernel = (void (*)(int, int, uint))images->ep;
+
+ s = getenv("machid");
+ if (s) {
+ machid = simple_strtoul(s, NULL, 16);
+ printf("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress(15);
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+ setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag(¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag(¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+ setup_end_tag(bd);
+#endif
+
+ /* we assume that the kernel is in place */
+ printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+
+ cleanup_before_linux();
+
+ theKernel(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+ params = (struct tag *)bd->bi_boot_params;
+
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size(tag_core);
+
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 0;
+ params->u.core.rootdev = 0;
+
+ params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size(tag_mem32);
+
+ params->u.mem.start = bd->bi_dram[i].start;
+ params->u.mem.size = bd->bi_dram[i].size;
+
+ params = tag_next(params);
+ }
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+ char *p;
+
+ if (!commandline)
+ return;
+
+ /* eat leading white space */
+ for (p = commandline; *p == ' '; p++)
+ ;
+
+ /* skip non-existent command lines so the kernel will still
+ * use its default command line.
+ */
+ if (*p == '\0')
+ return;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+ strcpy(params->u.cmdline.cmdline, p)
+ ;
+
+ params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+ /* an ATAG_INITRD node tells the kernel where the compressed
+ * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+ */
+ params->hdr.tag = ATAG_INITRD2;
+ params->hdr.size = tag_size(tag_initrd);
+
+ params->u.initrd.start = initrd_start;
+ params->u.initrd.size = initrd_end - initrd_start;
+
+ params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+ struct tag *params = *tmp;
+ struct tag_serialnr serialnr;
+ void get_board_serial(struct tag_serialnr *serialnr);
+
+ get_board_serial(&serialnr);
+ params->hdr.tag = ATAG_SERIAL;
+ params->hdr.size = tag_size(tag_serialnr);
+ params->u.serialnr.low = serialnr.low;
+ params->u.serialnr.high = serialnr.high;
+ params = tag_next(params);
+ *tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+ u32 rev = 0;
+ u32 get_board_rev(void);
+
+ rev = get_board_rev();
+ params->hdr.tag = ATAG_REVISION;
+ params->hdr.size = tag_size(tag_revision);
+ params->u.revision.rev = rev;
+ params = tag_next(params);
+}
+#endif /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags; /* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $psw\n\t"
+ "andi %0, %0, 0x1\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+ return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+ local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+ int gie_ori_status;
+
+ gie_ori_status = GIE_STATUS();
+
+ local_irq_save(int_flag);
+
+ return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+ printf("\n");
+ printf("pc : [<%08lx>] sp: [<%08lx>]\n"
+ "lp : %08lx gp : %08lx fp : %08lx\n",
+ regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+ printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
+ regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+ printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
+ regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+ printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
+ regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+ printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
+ regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+ printf("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n",
+ regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+ printf("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+ printf(" Interrupts %s Mode %s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+ const char *interruption_type[] = {
+ "Reset",
+ "TLB Fill",
+ "TLB Not Present",
+ "TLB Misc",
+ "VLPT Miss",
+ "Cache Parity Error",
+ "Debug",
+ "General Exception",
+ "External Interrupt"
+ };
+
+ printf("%s\n", interruption_type[EVIC_num]);
+ show_regs(pt_regs);
+ bad_mode();
+}
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 06/10] nds32/ag101: cpu and init funcs of SoC ag101
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add main function of SoC ag101 based on NDS32 n1213 core.
cpu.c
According to the bootstrap procedure in n1213 Core,
to turn off watchdog timer is suggested after the
cpu is in superuser mdoe.
1. bootstrap
1.1 reset - start of Andesboot
1.2 to superuser mode - as is when reset
1.3 Turn off watchdog timer
If you take look into the start.S in n1213, you will find that
system will turn off watchdog after start.S has been retunred
from lowlevel_init.
Since the watchdog device is depends on the SoC is choosed.
It should be belonged to the SoC (ag101) folder.
watchdog.S:
If you've ran another bootloader before u-boot was started
the watchdog might have been enabled already.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v5-v6:
- Split watchdog.S from lowlevel_init.S.
- Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
- reset_cpu was remove inside do_reset().
Changes for v7:
- clean up.
arch/nds32/cpu/n1213/ag101/Makefile | 58 +++++++++
arch/nds32/cpu/n1213/ag101/cpu.c | 207 +++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/timer.c | 204 ++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/watchdog.S | 48 ++++++++
4 files changed, 517 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..e96b1e4
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..8e7eb0a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/* setup up stack if necessary */
+/* it makes no sense to use the caches if the MMU also isn't used */
+void cpu_init(void)
+{
+ _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE;
+}
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+ unsigned long i;
+#endif
+
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+ * reset to the base addr of andesboot.
+ * currently no ROM loader at addr 0.
+ * do not use reset_cpu(0);
+ */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+ /*
+ * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+ * automatic hardware reset when booting Linux.
+ * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+ */
+ ftwdt010_wdt_reset();
+ while (1)
+ ;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+ /*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+ if (cache == ICACHE)
+ return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+ >> ICM_CFG_OFF_ISZ) - 1);
+ else
+ return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+ >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ dcache_flush_range(addr , addr + size);
+ icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x01\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void icache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x01\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int icache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
+
+void dcache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x02\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void dcache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x02\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int dcache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..87275eb
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
+#endif
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+#endif
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ lastdec = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ ulong now = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+ long tmo = usec * (APB_CLK / 1000) / 1000;
+#endif
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ return CONFIG_SYS_HZ;
+#else
+ return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR 0xC
+#define WD_ENABLE 0x1
+
+ ! Turn off the watchdog, according to Faraday FTWDT010 spec
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ lwi $p1, [$p0] ! Get the config of WD
+ andi $p1, $p1, 0x1f ! Wipe out useless bits
+ li $r0, ~WD_ENABLE
+ and $p1, $p1, $r0 ! Set WD disable
+ sw $p1, [$p0] ! Write back to WD CR
+
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ret
+
+#endif
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 05/10] nds32/ag101: lowlevel_init.S of ag101
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.
This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
ChangeLog from v1-v4:
- Code clean up and formatting style.
ChangeLog from v5-v6
- Change hard code value into MARCO definitions.
- ftsmc010
- Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
- ftsdmc021
- Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
- Fix the default configuration value of FTSDMC and FTSMC controller.
- Remove some ftpmu010 and flash probe code to C functions.
arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 160 ++++++++++++++++++++++++++++
1 files changed, 160 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..96969ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ jal mem_init
+ jal remap
+
+ ret $r10
+
+mem_init:
+ move $r11, $lp
+
+ /*
+ * mem_init:
+ * There are 2 bank connected to FTSMC020 on AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ * we need to set onboard SDRAM before remap and relocation.
+ */
+ li $r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR)
+ li $r1, (FTSMC020_BANK1_CONFIG) ! 0x10000052
+ swi $r1, [$r0]
+ li $r1, (FTSMC020_BANK1_TIMING) ! 0x00151151
+ swi $r1, [$r0+FTSMC020_BANK0_TPR]
+
+ /*
+ * config AHB Controller
+ */
+ li $r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+ li $r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6)
+ swi $r1, [$r0]
+
+ /*
+ * config PMU
+ */
+ li $r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+ lwi $r1, [$r0]
+ ! ftpmu010_dlldis_disable, must do it in lowleve_init
+ li $r2, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
+ or $r1, $r1, $r2
+ swi $r1, [$r0]
+
+ /*
+ * config SDRAM controller
+ */
+ li $r0, (CONFIG_FTSDMC021_BASE)
+ li $r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312
+ swi $r1, [$r0]
+ li $r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180
+ swi $r1, [$r0+FTSDMC021_OFFSET_TP2]
+ li $r1, (CONFIG_SYS_FTSDMC021_CR1) ! 0x00002326
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR1]
+ li $r1, (FTSDMC021_CR2_IPREC) ! 0x00000010
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+1:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ andi $r1, $r1, (CONFIG_SYS_FTSDMC021_CR2) ! 0x1C
+ bnez $r1, 1b
+
+ li $r1, (FTSDMC021_CR2_ISMR) ! 0x00000004
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+2:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ bnez $r1, 2b
+
+ li $r1, (FTSDMC021_CR2_IREF) ! 0x00000008
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+3:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ bnez $r1, 3b
+
+ move $lp, $r11
+ ret
+
+remap:
+ move $r11, $lp
+#ifdef __NDS32_N1213_43U1H__ /* AG101 */
+ bal 2f
+relo_base:
+ move $r0, $lp
+#else
+relo_base:
+ mfusr $r0, $pc
+#endif
+
+ /*
+ * relocation, copy ROM code to SDRAM (current at 0x10000000)
+ */
+ li $r4, CONFIG_SYS_RELO_ADDR ! 0x10000000
+ li $r5, 0x0
+ la $r1, relo_base
+ sub $r2, $r0, $r1
+ sethi $r6, hi20(andesboot_end)
+ ori $r6, $r6, lo12(andesboot_end)
+ add $r6, $r6, $r2
+1:
+ lwi $r7, [$r5]
+ swi $r7, [$r4]
+ addi $r5, $r5, #4
+ addi $r4, $r4, #4
+ blt $r5, $r6, 1b
+
+ /*
+ * Remapping
+ */
+ li $r0, (CONFIG_FTSDMC021_BASE + FTSDMC021_OFFSET_TP1)
+ li $r1, (CONFIG_SYS_FTSDMC021_BANK0_BSR) ! 0x00001100
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+ li $r1, 0x0
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK1_BSR]
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK2_BSR]
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK3_BSR]
+ li $r1, (FTSDMC021_BANK_ENABLE) ! 0x00001000
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+
+ li $r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+ lwi $r1, [$r0]
+ ori $r1, $r1, FTAHBC020S_CR_REMAP ! 0x1
+ swi $r1, [$r0]
+
+ li $r0, (CONFIG_FTSMC020_BASE)
+
+ move $lp, $r11
+2:
+ ret
+
+.globl show_led
+show_led:
+ li $r8, (CONFIG_DEBUG_LED)
+ swi $r7, [$r8]
+ ret
+#endif
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add header file of device offset support for SoC ag101.
SoC ag101 is the first chip using NDS32 N1213 cpu core.
Note:
Ag101 is actually use ftsdmc021 instead of ftsdmc020
as dram controller, which is probably wrong in the datasheet.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
arch/nds32/include/asm/arch-ag101/ag101.h | 68 +++++++++++++++++++++++++++++
1 files changed, 68 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE 0x90100000 /* AHB Controller */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE 0x90300000 /* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE 0x90400000 /* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 /* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE 0x90600000 /* LCD Controller */
+#define CONFIG_RESERVED_01_BASE 0x90700000 /* Reserved */
+#define CONFIG_RESERVED_02_BASE 0x90800000 /* Reserved */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE 0x90A00000 /* External USB host */
+#define CONFIG_USB_DEV_BASE 0x90B00000 /* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE 0x90D00000 /* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 /* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 /* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED 0x902FFFFC /* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE 0x98300000 /* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Counter/Timers */
+#define CONFIG_FTWDT010_BASE 0x98500000 /* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE 0x98700000 /* GPIO */
+#define CONFIG_FTINTC010_BASE 0x98800000 /* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE 0x98A00000 /* I2C */
+#define CONFIG_RESERVED_04_BASE 0x98C00000 /* Reserved */
+#define CONFIG_FTCFC010_BASE 0x98D00000 /* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE 0x98E00000 /* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE 0x99400000 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE 0x99600000 /* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE 0x98200000 /* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE 0x98B00000 /* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE 0x98900000 /* IrDA */
+#define CONFIG_PMW_BASE 0x99100000 /* PWM - Pulse Width Modulator Controller */
+
+#endif /* __AG101_H */
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 03/10] nds32/core N1213: NDS32 N12 core family N1213
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.
NDS32 Core N1213 has the following hardware features.
Core:
- 16-/32-bit mixable instruction format
- 32 general-purpose 32-bit registers
- 8-stage pipeline
- Dynamic branch prediction
- 32/64/128/256 BTB
- Return address stack (RAS)
- Vector interrupts for internal/external
- 3 HW-level nested interruptions
- User and super-user mode support
- Memory-mapped I/O
- Address space up to 4GB
Memory Management Unit:
- TLB
- Optional hardware page table walker
- Two groups of page size support
Memory Subsystem:
- I & D cache
- I & D local memory (LM)
Bus Interface:
- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports
Start procedure:
start.S will start up the N1213 CPU core at first,
then jump to SoC dependent "lowlevel_init.S" and
"watchdog.S" to configure peripheral devices.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
arch/nds32/cpu/n1213/Makefile | 50 +++++
arch/nds32/cpu/n1213/start.S | 447 +++++++++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/u-boot.lds | 68 ++++++
3 files changed, 565 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/Makefile
create mode 100644 arch/nds32/cpu/n1213/start.S
create mode 100644 arch/nds32/cpu/n1213/u-boot.lds
diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..111d14f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..b04f3a5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,447 @@
+/*
+ * Andesboot - Startup Code for Whitiger core
+ *
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
+ * Copyright (C) 2011 Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC 2UL
+#define DIS_DCAC ~ENA_DCAC
+#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
+#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
+#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
+#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
+
+#define PSW $ir0
+#define EIT_INTR_PSW $ir1 ! interruption $PSW
+#define EIT_PREV_IPSW $ir2 ! previous $IPSW
+#define EIT_IVB $ir3 ! intr vector base address
+#define EIT_EVA $ir4 ! MMU related Exception Virtual Address register */
+#define EIT_PREV_EVA $ir5 ! previous $eva
+#define EIT_ITYPE $ir6 ! interruption type
+#define EIT_PREV_ITYPE $ir7 ! prev intr type
+#define EIT_MACH_ERR $ir8 ! machine error log
+#define EIT_INTR_PC $ir9 ! Interruption PC
+#define EIT_PREV_IPC $ir10 ! previous $IPC
+#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
+#define EIT_PREV_P0 $ir12 ! prev $P0
+#define EIT_PREV_P1 $ir13 ! prev $p1
+#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
+#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
+#define MR_CAC_CTL $mr8
+
+.globl _start
+
+_start: b reset
+ b tlb_fill
+ b tlb_not_present
+ b tlb_misc
+ b tlb_vlpt_miss
+ b cache_parity_error
+ b debug
+ b general_exception
+ b internal_interrupt ! H0I
+ b internal_interrupt ! H1I
+ b internal_interrupt ! H2I
+ b internal_interrupt ! H3I
+ b internal_interrupt ! H4I
+ b internal_interrupt ! H5I
+
+ .balign 16
+
+!========================================================================
+! Andesboot Startup Code (reset vector)
+!
+! 1. bootstrap
+! 1.1 reset - start of Andesboot
+! 1.2 to superuser mode - as is when reset
+! 1.4 Do lowlevel_init
+! - (this will jump out to lowlevel_init.S in SoC)
+! - (lowlevel_init)
+! 1.3 Turn off watchdog timer
+! - (this will jump out to watchdog.S in SoC)
+! - (turnoff_watchdog)
+! 2. Do critical init when reboot (not from mem)
+! 3. Relocate andesboot to ram
+! 4. Setup stack
+! 5. Jump to second stage (start_andesboot)
+!========================================================================
+
+! Note: TEXT_BASE is defined by the (board-dependent) linker script
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+.globl _andesboot_start
+_andesboot_start:
+ .word _start
+
+! Note: andesboot_end is defined by the (board-dependent) linker script
+.globl _andesboot_end
+_andesboot_end:
+ .word andesboot_end
+
+! _andesboot_real_end is the first usable RAM address behind Andesboot
+! and the various stacks
+.globl _andesboot_real_end
+_andesboot_real_end:
+ .word 0x0badc0de
+
+!=============================================
+! The bootstrap code of Andesboot
+!=============================================
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ jal load_lowlevel_init
+ jral $p0
+#endif
+
+! Set the Whitiger core to superuser mode
+! According to spec, it is already when reset
+
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ jal load_turnoff_watchdog
+ jral $p0
+#endif
+
+! Do CPU critical regs init only at reboot, not when booting from ram
+#ifdef CONFIG_INIT_CRITICAL
+ bal cpu_init_crit ! Do CPU critical regs init
+#endif
+
+ .align 2
+relocate:
+ ! relocate andesboot to RAM
+ jal 2f
+ !la $r0, _start ! $r0 = source start addr
+ !l.w $r2, _andesboot_start ! Andesboot start address
+ !l.w $r3, _andesboot_end ! Andesboot end address
+ !sub $r2, $r3, $r2 ! $r2 = size of Andesboot
+ !l.w $r1, _TEXT_BASE ! $r1 = destination start addr
+ move $r0, $lp
+ la $p0, _start
+ la $p1, relocate+4
+ sub $p0, $p1, $p0
+ sub $r0, $r0, $p0
+
+ la $p0, _andesboot_end
+ sub $p0, $p0, $p1
+ move $r3, $lp
+ lw $r3, [$r3+$p0] ! _andesboot_end
+ addi $p0, $p0, -4
+ move $r2, $lp
+ lw $r2, [$r2+$p0] ! _andesboot_start
+ sub $r2, $r3, $r2
+ addi $p0, $p0, -4
+ move $r1, $lp
+ lw $r1, [$r1+$p0] ! _TEXT_BASE
+
+ ! $r0 = source address
+ ! $r1 = destination address
+ ! $r2 = size to copy
+copy_loop:
+ lmw.bim $r3, [$r0], $r10
+ smw.bim $r3, [$r1], $r10
+ addi $r2, $r2, -32
+ bgez $r2, copy_loop
+
+ ! Set up the stack
+ l.w $p0, _andesboot_end ! Defined by board linker script
+ li $p1, CONFIG_STACKSIZE ! (128*1024) defined in config.h
+ add $sp, $p0, $p1
+
+ bal flib_init_bss_memory
+
+ ! Jump to start_andesboot (2nd phase)
+ l.w $p0, __start_andesboot
+ br $p0
+
+__start_andesboot: .word start_andesboot
+
+!=========================================================================
+! Initialize CPU critical registers
+!
+! 1. Setup control registers
+! 1.1 Mask all IRQs
+! 1.2 Flush cache and TLB
+! 1.3 Disable MMU and cache
+! 2. Setup memory timing
+!=========================================================================
+
+cpu_init_crit:
+ !push ra
+ move $r0, $lp
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ! Flush caches and TLB
+
+ ! Invalidate caches
+ bal invalidate_icac
+ bal invalidate_dcac
+
+ ! Flush TLB
+ mfsr $p0, $MMU_CFG
+ andi $p0, $p0, 0x3 ! MMPS
+ li $p1, 0x2 ! TLB MMU
+ bne $p0, $p1, 1f
+ tlbop FlushAll ! Flush TLB
+
+1:
+ ! Disable MMU, Dcache
+ ! Whitiger is MMU disabled when reset
+ ! Disable the D$
+ mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
+ li $p1, DIS_DCAC
+ and $p0, $p0, $p1 ! Set DC_EN bit
+ mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
+ isb
+
+ ! RAM is initialized in the dram_init()(board/nds32/cpe.c)
+ ! Remove the memsetup.S in the board directory.
+ !pop ra
+
+ move $lp, $r0
+2:
+ ret
+
+flib_init_bss_memory:
+ smw.adm $r4, [$sp], $r6, #0x1
+
+ la $r4, __bss_start
+ la $r5, __bss_end
+ move $r6, #0
+1:
+ swi.p $r6, [$r4], #4
+ blt $r4, $r5, 1b ! Check if done..
+
+ lmw.bim $r4, [$sp], $r6, #0x1
+ ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+ la $r6, lowlevel_init
+ la $r7, load_lli + 4
+ sub $p0, $r6, $r7
+ add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+ la $r6, turnoff_watchdog
+ la $r7, turnoff_wtdog + 4
+ sub $p0, $r6, $r7
+ add $p0, $p0, $lp
+ret
+#endif
+
+
+!=======================================================
+! Invalidate I$
+!=======================================================
+invalidate_icac:
+ mfsr $t0, CR_ICAC_MEM ! read $cr1(I CAC/MEM cfg. reg.) configuration
+ andi $p0, $t0, ICAC_MEM_KBF_ISZ ! Get the ISZ field
+ beqz $p0, end_flush_icache ! if $p0=0, then no I CAC existed
+ srli $p0, $p0, 6 ! get $p0 the index of I$ block
+ addi $t1, $p0, 2 ! $t1= bit width of I cache line size(ISZ)
+ li $t4, 1
+ sll $t5, $t4, $t1 ! get $t5 cache line size
+ andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
+ addi $t2, $p1, 6 ! $t2= bit width of ISET
+ andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
+ srli $p1, $p1, 3
+ addi $p1, $p1, 1 ! then $p1 is I way number
+ add $t3, $t2, $t1 ! SHIFT
+ sll $p1, $p1, $t3 ! GET the total cache size
+ICAC_LOOP:
+ sub $p1, $p1, $t5
+ cctl $p1, L1I_IX_INVAL
+ bnez $p1, ICAC_LOOP
+end_flush_icache:
+ ret
+
+!=======================================================
+! Invalidate D$
+!=======================================================
+invalidate_dcac:
+ mfsr $t0, CR_DCAC_MEM ! read $cr2(D CAC/MEM cfg. reg.) configuration
+ andi $p0, $t0, DCAC_MEM_KBF_DSZ ! Get the DSZ field
+ beqz $p0, end_flush_dcache ! if $p0=0, then no D CAC existed
+ srli $p0, $p0, 6 ! get $p0 the index of D$ block
+ addi $t1, $p0, 2 ! $t1= bit width of D cache line size(DSZ)
+ li $t4, 1
+ sll $t5, $t4, $t1 ! get $t5 cache line size
+ andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
+ addi $t2, $p1, 6 ! $t2= bit width of DSET
+ andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
+ srli $p1, $p1, 3
+ addi $p1, $p1, 1 ! then $p1 is D way number
+ add $t3, $t2, $t1 ! SHIFT
+ sll $p1, $p1, $t3 ! GET the total cache size
+DCAC_LOOP:
+ sub $p1, $p1, $t5
+ cctl $p1, L1D_IX_INVAL
+ bnez $p1, DCAC_LOOP
+end_flush_dcache:
+ ret
+
+!========================================================================
+! Interrupt handling
+!========================================================================
+
+/*
+ * exception handlers
+ */
+ .align 5
+
+ .macro SAVE_ALL
+ ! FIXME: Other way to get PC?
+ ! FIXME: Update according to the newest spec!!
+1: la $r28, 1
+ push $r28
+ mfsr $r28, PSW ! $PSW
+ push $r28
+ mfsr $r28, EIT_EVA ! $ir1 $EVA
+ push $r28
+ mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
+ push $r28
+ mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
+ push $r28
+ mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
+ push $r28
+ mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
+ push $r28
+ mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
+ push $r28
+ mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
+ push $r28
+ mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
+ push $r28
+ mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
+ push $r28
+ mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
+ push $r28
+ mfusr $r28, $d1.lo
+ push $r28
+ mfusr $r28, $d1.hi
+ push $r28
+ mfusr $r28, $d0.lo
+ push $r28
+ mfusr $r28, $d0.hi
+ push $r28
+ pushm $r0,$r30 /* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */
+ addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
+ .endm
+
+ .align 5
+tlb_fill:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 1 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_not_present:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 2 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_misc:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 3 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_vlpt_miss:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 4 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+cache_parity_error:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 5 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+debug:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 6 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+general_exception:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 7 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+internal_interrupt:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 8 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+
+!===========================================
+!void reset_cpu(ulong addr);
+! $r0: input address to jump to
+!===========================================
+.globl reset_cpu
+reset_cpu:
+! No need to disable MMU because we never enable it!
+
+ bal invalidate_icac
+ bal invalidate_dcac
+ mfsr $p0, $MMU_CFG
+ andi $p0, $p0, 0x3 ! MMPS
+ li $p1, 0x2 ! TLB MMU
+ bne $p0, $p1, 1f
+ tlbop FlushAll ! Flush TLB
+1:
+ mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
+ li $p1, DIS_DCAC
+ and $p0, $p0, $p1 ! Clear the DC_EN bit
+ mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
+ br $r0 ! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..824d05d
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ arch/nds32/cpu/n1213/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ andesboot_end = .;
+
+ . = 0x02000000;
+ .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 02/10] nds32: add NDS32 support into common header file
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1302490025-22060-1-git-send-email-macpaul@andestech.com>
Add NDS32 support into common header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
include/common.h | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/common.h b/include/common.h
index 54503ed..423bbd8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -273,6 +273,10 @@ int setenv (char *, char *);
#ifdef CONFIG_I386 /* x86 version to be fixed! */
# include <asm/u-boot-i386.h>
#endif /* CONFIG_I386 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h> /* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
#ifdef CONFIG_AUTO_COMPLETE
int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
--
1.7.3.5
^ permalink raw reply related
* [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
Add generic header files support for nds32 architecture.
Cache, ptrace, data type and other definitions are included.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
- Code cleanup and style formatting.
Changes for v5-v6:
- This patch also updated the following changes against the
change after master tree (v2010.12-rc1).
- fix upper case definitions in cache.h
- Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h.
- Add readsb, writesb functions into io.h.
Changes for v7:
- clean up
- volatile:
- types.h
- remove typedef volatile unsigned char vuchar;
- remove typedef volatile unsigned long vulong;
- remove typedef volatile unsigned short vushort;
- u-boot.h: remove bd_info_ext bi_ext
- bitops.h: add accessor function to bit operation with volatile var.
- system.h: add system.h for local_irq operation with flag.
Changes for v8:
- ptrace.h: rewrite the pt_reg structure, and merge ptregs.h.
- ptregs.h: removed
arch/nds32/include/asm/bitops.h | 186 +++++++++++++++
arch/nds32/include/asm/byteorder.h | 36 +++
arch/nds32/include/asm/cache.h | 54 +++++
arch/nds32/include/asm/config.h | 26 ++
arch/nds32/include/asm/global_data.h | 82 +++++++
arch/nds32/include/asm/io.h | 410 +++++++++++++++++++++++++++++++++
arch/nds32/include/asm/mach-types.h | 29 +++
arch/nds32/include/asm/memory.h | 19 ++
arch/nds32/include/asm/posix_types.h | 84 +++++++
arch/nds32/include/asm/processor.h | 25 ++
arch/nds32/include/asm/ptrace.h | 88 +++++++
arch/nds32/include/asm/string.h | 57 +++++
arch/nds32/include/asm/system.h | 88 +++++++
arch/nds32/include/asm/types.h | 63 +++++
arch/nds32/include/asm/u-boot-nds32.h | 50 ++++
arch/nds32/include/asm/u-boot.h | 63 +++++
arch/nds32/include/asm/unaligned.h | 31 +++
17 files changed, 1391 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/include/asm/bitops.h
create mode 100644 arch/nds32/include/asm/byteorder.h
create mode 100644 arch/nds32/include/asm/cache.h
create mode 100644 arch/nds32/include/asm/config.h
create mode 100644 arch/nds32/include/asm/global_data.h
create mode 100644 arch/nds32/include/asm/io.h
create mode 100644 arch/nds32/include/asm/mach-types.h
create mode 100644 arch/nds32/include/asm/memory.h
create mode 100644 arch/nds32/include/asm/posix_types.h
create mode 100644 arch/nds32/include/asm/processor.h
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/include/asm/string.h
create mode 100644 arch/nds32/include/asm/system.h
create mode 100644 arch/nds32/include/asm/types.h
create mode 100644 arch/nds32/include/asm/u-boot-nds32.h
create mode 100644 arch/nds32/include/asm/u-boot.h
create mode 100644 arch/nds32/include/asm/unaligned.h
diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..c56f04b
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ * Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space. Many of these are not implemented in assembler
+ * since they would be too costly. Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit() do { } while (0)
+#define smp_mb__after_clear_bit() do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void *addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a |= mask;
+}
+
+extern void clear_bit(int nr, volatile void *addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+ int *a = (int *)addr;
+ int mask;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ *a &= ~mask;
+ local_irq_restore(flags);
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+ int mask;
+ unsigned long *ADDR = (unsigned long *)addr;
+
+ ADDR += nr >> 5;
+ mask = 1 << (nr & 31);
+ *ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, volatile void *addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a |= mask;
+ return retval;
+}
+
+extern int test_and_clear_bit(int nr, volatile void *addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a &= ~mask;
+ return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+ return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+ return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+ int k;
+
+ word = ~word;
+ k = 31;
+ if (word & 0x0000ffff) {
+ k -= 16; word <<= 16;
+ }
+ if (word & 0x00ff0000) {
+ k -= 8; word <<= 8;
+ }
+ if (word & 0x0f000000) {
+ k -= 4; word <<= 4;
+ }
+ if (word & 0x30000000) {
+ k -= 2; word <<= 2;
+ }
+ if (word & 0x40000000)
+ k -= 1;
+
+ return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit test_and_set_bit
+#define ext2_clear_bit test_and_clear_bit
+#define ext2_test_bit test_bit
+#define ext2_find_first_zero_bit find_first_zero_bit
+#define ext2_find_next_zero_bit find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr) set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr) test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness. In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ * d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ * d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..d769196
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int icache_status(void);
+void icache_enable(void);
+void icache_disable(void);
+int dcache_status(void);
+void dcache_enable(void);
+void dcache_disable(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+ static inline unsigned long GET_##reg(void) \
+ { \
+ unsigned long val; \
+ __asm__ volatile ( \
+ "mfsr %0, $"#reg : "=&r" (val) : : "memory" \
+ ); \
+ return val; \
+ }
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */
+#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
+#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
+#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..23421b7
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..a3e5b4c
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**************************************************************
+ * CAUTION:
+ * - do not implement for NDS32 Arch yet.
+ * - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef __ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef struct global_data {
+ bd_t *bd;
+ unsigned long flags;
+ unsigned long baudrate;
+ unsigned long have_console; /* serial_init() was called */
+
+ unsigned long reloc_off; /* Relocation Offset */
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_valid; /* Checksum of Environment valid? */
+ unsigned long fb_base; /* base address of frame buffer */
+#ifdef CONFIG_VFD
+ unsigned char vfd_type; /* display type */
+#endif
+ void **jt; /* jump table */
+ char env_buf[32]; /* buffer for getenv() before reloc. */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
+#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG8
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r8")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..be097ec
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,410 @@
+/*
+ * linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
+ * constant addresses and variable addresses.
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
+ * specific IO header files.
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
+ * 04-Apr-1999 PJB Added check_signature.
+ * 12-Dec-1999 RMK More cleanups
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ * - do not implement for NDS32 Arch yet.
+ * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ * iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+ return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write. Note that we don't support half-word
+ * read/writes. We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a) __arch_putb(v, a)
+#define __raw_writew(v, a) __arch_putw(v, a)
+#define __raw_writel(v, a) __arch_putl(v, a)
+
+#define __raw_readb(a) __arch_getb(a)
+#define __raw_readw(a) __arch_getw(a)
+#define __raw_readl(a) __arch_getl(a)
+
+#define writeb(v, a) __arch_putb(v, a)
+#define writew(v, a) __arch_putw(v, a)
+#define writel(v, a) __arch_putl(v, a)
+
+#define readb(a) __arch_getb(a)
+#define readw(a) __arch_getw(a)
+#define readl(a) __arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly. Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off) __arch_base_getb(base, off)
+#define __raw_base_readw(base, off) __arch_base_getw(base, off)
+#define __raw_base_readl(base, off) __arch_base_getl(base, off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ * IO port access primitives
+ * -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only. Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ * PCI: D0-D7 D8-D15 D16-D23 D24-D31
+ * ARM: D24-D31 D16-D23 D8-D15 D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions. Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p) __raw_writeb(v, __io(p))
+#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l) writesb(__io(p), d, l)
+#define outsw(p, d, l) writesw(__io(p), d, l)
+#define outsl(p, d, l) writesl(__io(p), d, l)
+
+#define insb(p, d, l) readsb(__io(p), d, l)
+#define insw(p, d, l) readsw(__io(p), d, l)
+#define insl(p, d, l) readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+ unsigned char *ptr = (unsigned char *)addr;
+ unsigned char *ptr2 = (unsigned char *)data;
+ while (bytelen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ bytelen--;
+ }
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+ unsigned short *ptr = (unsigned short *)addr;
+ unsigned short *ptr2 = (unsigned short *)data;
+ while (wordlen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ wordlen--;
+ }
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+ unsigned int *ptr = (unsigned int *)addr;
+ unsigned int *ptr2 = (unsigned int *)data;
+ while (longlen) {
+ *ptr2 = *ptr;
+ ptr2++;
+ longlen--;
+ }
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+ unsigned char *ptr = (unsigned char *)addr;
+ unsigned char *ptr2 = (unsigned char *)data;
+ while (bytelen) {
+ *ptr = *ptr2;
+ ptr2++;
+ bytelen--;
+ }
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+ unsigned short *ptr = (unsigned short *)addr;
+ unsigned short *ptr2 = (unsigned short *)data;
+ while (wordlen) {
+ *ptr = *ptr2;
+ ptr2++;
+ wordlen--;
+ }
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+ unsigned int *ptr = (unsigned int *)addr;
+ unsigned int *ptr2 = (unsigned int *)data;
+ while (longlen) {
+ *ptr = *ptr2;
+ ptr2++;
+ longlen--;
+ }
+}
+#endif
+
+#define outb_p(val, port) outb((val), (port))
+#define outw_p(val, port) outw((val), (port))
+#define outl_p(val, port) outl((val), (port))
+#define inb_p(port) inb((port))
+#define inw_p(port) inw((port))
+#define inl_p(port) inl((port))
+
+#define outsb_p(port, from, len) outsb(port, from, len)
+#define outsw_p(port, from, len) outsw(port, from, len)
+#define outsl_p(port, from, len) outsl(port, from, len)
+#define insb_p(port, to, len) insb(port, to, len)
+#define insw_p(port, to, len) insw(port, to, len)
+#define insl_p(port, to, len) insl(port, to, len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt. If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ * iomem_valid_addr(off,size)
+ * iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off, sz, nocache) \
+({ \
+ unsigned long _off = (off), _size = (sz); \
+ void *_ret = (void *)0; \
+ if (iomem_valid_addr(_off, _size)) \
+ _ret = __ioremap(iomem_to_phys(_off), _size, 0); \
+ _ret; \
+})
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off, sz) __arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1)
+#define iounmap(_addr) __arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions. These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices. This is the "generic" version. The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros. These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
+#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+ eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+ int length)
+{
+ int retval = 0;
+ do {
+ if (readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+ return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr) (__readwrite_bug("readb"), 0)
+#define readw(addr) (__readwrite_bug("readw"), 0)
+#define readl(addr) (__readwrite_bug("readl"), 0)
+#define writeb(v, addr) __readwrite_bug("writeb")
+#define writew(v, addr) __readwrite_bug("writew")
+#define writel(v, addr) __readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a, b, c, d) __readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io, sig, len) (0)
+
+#endif /* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr) __raw_readb(__mem_isa(addr))
+#define isa_readw(addr) __raw_readw(__mem_isa(addr))
+#define isa_readl(addr) __raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+ eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+ int length)
+{
+ int retval = 0;
+ do {
+ if (isa_readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+ return retval;
+}
+
+#else /* __mem_isa */
+
+#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
+#define isa_writew(val, addr) __readwrite_bug("isa_writew")
+#define isa_writel(val, addr) __readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+ __readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len) (0)
+
+#endif /* __mem_isa */
+#endif /* __KERNEL__ */
+#endif /* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..a6f1c93
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,29 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101 0
+
+#ifdef CONFIG_ARCH_ADPAG101
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADPAG101
+# endif
+# define machine_is_adpag101() (machine_arch_type == MACH_TYPE_ADPAG101)
+#else
+# define machine_is_adpag101() (0)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 0000000..5bcc4e1
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm-arm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_NDS_MEMORY_H
+#define __ASM_NDS_MEMORY_H
+
+#endif /* __ASM_NDS_MEMORY_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..a928038
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ * 27-06-1996 RMK Created
+ * 05-03-2010 Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+#define __FD_SET(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef __FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef __FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+ ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef __FD_ZERO
+#define __FD_ZERO(fdsetp) \
+ (memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ * - do not implement for NDS32 Arch yet.
+ * - so far some files include /asm/processor.h, but
+ * no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..4336083
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE 0x00
+#define SU_MODE 0x01
+#define HV_MODE 0x10
+#define MODE_MASK (0x03<<3)
+#define GIE_BIT 0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+ NDS32_REG ir0;
+ NDS32_REG ipsw;
+ NDS32_REG ipc;
+ NDS32_REG sp;
+ NDS32_REG orig_r0;
+ NDS32_REG pipsw;
+ NDS32_REG pipc;
+ NDS32_REG pp0;
+ NDS32_REG pp1;
+ NDS32_REG d0hi;
+ NDS32_REG d0lo;
+ NDS32_REG d1hi;
+ NDS32_REG d1lo;
+ NDS32_REG r[26]; /* r0 - r25 */
+ NDS32_REG fp; /* r28 */
+ NDS32_REG gp; /* r29 */
+ NDS32_REG lp; /* r30 */
+ NDS32_REG fucop_ctl;
+ NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+ (((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+ ((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0 0
+#define PT_R1 1
+#define PT_R2 2
+#define PT_R3 3
+#define PT_R4 4
+#define PT_R5 5
+#define PT_R6 6
+#define PT_R7 7
+#define PT_R8 8
+#define PT_R9 9
+#define PT_R10 10
+#define PT_R11 11
+#define PT_R12 12
+#define PT_R13 13
+#define PT_R14 14
+#define PT_R15 15
+#define PT_R16 16
+#define PT_R17 17
+#define PT_R18 18
+#define PT_R19 19
+#define PT_R20 20
+#define PT_R21 21
+#define PT_R22 22
+#define PT_R23 23
+#define PT_R24 24
+#define PT_R25 25
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n) \
+ ({ \
+ if ((n) != 0) { \
+ if (__builtin_constant_p((v)) && (v) == 0) \
+ __memzero((p), (n)); \
+ else \
+ memset((p), (v), (n)); \
+ } \
+ (p); \
+ })
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..97f59e9
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+ __asm__ __volatile__ ( \
+ "mfsr %0, $psw\n\t" \
+ "andi %0, %0, 0x1\n\t" \
+ "setgie.e\n\t" \
+ : \
+ : "r" (irq_flags) \
+ )
+
+#define local_irq_disable() \
+ do { \
+ int __tmp_dummy; \
+ __asm__ __volatile__ ( \
+ "mfsr %0, $psw\n\t" \
+ "andi %0, %0, 0x1\n\t" \
+ "setgie.d\n\t" \
+ "dsb\n\t" \
+ : "=r" (__tmp_dummy) \
+ ); \
+ } while (0)
+
+#define local_irq_save(x) \
+ __asm__ __volatile__ ( \
+ "mfsr %0, $psw\n\t" \
+ "andi %0, %0, 0x1\n\t" \
+ "setgie.d\n\t" \
+ "dsb\n\t" \
+ : "=&r" (x) \
+ )
+
+#define local_save_flags(x) \
+ __asm__ __volatile__ ( \
+ "mfsr %0, $psw\n\t" \
+ "andi %0, %0, 0x1\n\t" \
+ "setgie.e\n\t" \
+ "setgie.d\n\t" \
+ : "=r" (x) \
+ )
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+ do { \
+ if (irqs_enabled_from_flags(x)) \
+ local_irq_enable(); \
+ } while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop() asm volatile ("nop;\n\t" : : )
+#define mb() asm volatile ("" : : : "memory")
+#define rmb() asm volatile ("" : : : "memory")
+#define wmb() asm volatile ("" : : : "memory")
+
+#endif /* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..2e8924f
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..2383e08
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_ 1
+
+/* for the following variables, see start.S */
+extern ulong _andesboot_start; /* code start */
+extern ulong _andesboot_end; /* code end */
+extern ulong _andesboot_real_end; /* first usable RAM address */
+
+/* cpu/.../cpu.c */
+int cleanup_before_linux(void);
+
+/* board/.../... */
+int board_init(void);
+int dram_init(void);
+
+/* cpu/.../interrupt.c */
+void reset_timer_masked(void);
+
+/* cpu/.../timer.c */
+int timer_init(void);
+
+#endif /* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..fafe4e4
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro at andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_ 1
+
+#include <environment.h>
+
+typedef struct bd_info {
+ int bi_baudrate; /* serial console baudrate */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+
+ env_t *bi_env;
+ unsigned long bi_arch_number; /* unique id for this board */
+ unsigned long bi_boot_params; /* where this board expects params */
+
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+
+ struct /* RAM configuration */
+ {
+ unsigned long start;
+ unsigned long size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#endif /* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..ffa7e30
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Copyright (C) 2011 Macpaul Lin (macpaul at andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_NDS_UNALIGNED_H
+#define _ASM_NDS_UNALIGNED_H
+
+#include <compiler.h>
+/*
+ * Select endianness
+ */
+#ifndef __NDSEB__
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
+#else
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+#endif /* __NDSEB__ */
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#endif /* _ASM_NDS_UNALIGNED_H */
--
1.7.3.5
^ permalink raw reply related
* [PATCH] fix build warnings on defconfigs
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-04-11 2:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com>
On 03:04 Sun 10 Apr , wanlong.gao at gmail.com wrote:
> From: Wanlong Gao <wanlong.gao@gmail.com>
>
> Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y',
> since BT_L2CAP and BT_SCO had changed to bool configs.
>
> Signed-off-by: Wanlong Gao <wanlong.gao@gmail.com>
> ---
for at91
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Best Regards,
J.
^ permalink raw reply
* Re: [PATCH] [v2] Nios2: Add Altera TSE MAC driver
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-04-11 2:37 UTC (permalink / raw)
To: Franck JULLIEN; +Cc: barebox
In-Reply-To: <BANLkTi=D=yLy3iZ2ZQuVAwb3Q=UPnk0ZaA@mail.gmail.com>
On 20:21 Sun 10 Apr , Franck JULLIEN wrote:
> 2011/4/10 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>
> > > index 0000000..2687377
> > > --- /dev/null
> > > +
> > > +static int tse_get_ethaddr(struct eth_device *edev, unsigned
> char *m)
> > > +{
> > > + /* There is no eeprom */
> > so return the content of the register no?
> >
> > Well, the register is reseted to 0 when the MAC starts so there is
> no
> > Ethernet address
> > to get.
> >
> except this function is supposed to return the mac address of the device
> at
> any time so after a set of it it will not be true any more
>
> If I implement the function I get a "eth@eth0: got MAC address from
> EEPROM: 00:00:00:00:00:00" at startup.
> That why I returned -1 as what I could find int at91_ether.c......
> Or, I could find something to return -1 as long as the MAC address hasn't
> been set.
>
I known this issue I re-write recently the at91_ether and the same on macb
will post the patch soon
It's fine the uperlayer will see that it's not a valid mac so this will
generate a random one
cf net/net.c IIRC
Best Regads,
J.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [PATCH 2/2] xfs:remove a warning in xfs_buf_readahead()
From: Weiping Pan(潘卫平) @ 2011-04-11 2:44 UTC (permalink / raw)
To: aelder, xfs-masters, dchinner, hch, jaxboe, tj, xfs
Cc: linux-kernel, Weiping Pan
/home/pwp/mysvn/linux/linux-2.6/fs/xfs/linux-2.6/xfs_buf.c: In function
‘xfs_buf_readahead’:
/home/pwp/mysvn/linux/linux-2.6/fs/xfs/linux-2.6/xfs_buf.c:660:27: warning:
unused variable ‘bdi’
Signed-off-by: Weiping Pan(潘卫平) <panweiping3@gmail.com>
---
fs/xfs/linux-2.6/xfs_buf.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/fs/xfs/linux-2.6/xfs_buf.c b/fs/xfs/linux-2.6/xfs_buf.c
index 5ea4020..a125b32 100644
--- a/fs/xfs/linux-2.6/xfs_buf.c
+++ b/fs/xfs/linux-2.6/xfs_buf.c
@@ -657,8 +657,6 @@ xfs_buf_readahead(
xfs_off_t ioff,
size_t isize)
{
- struct backing_dev_info *bdi;
-
if (bdi_read_congested(target->bt_bdi))
return;
--
1.7.4
^ permalink raw reply related
* [PATCH 1/2] gfs:remove a warning in gfs2_lookup_by_inum()
From: Weiping Pan(潘卫平) @ 2011-04-11 2:42 UTC (permalink / raw)
To: swhiteho; +Cc: cluster-devel, linux-kernel, Weiping Pan
/home/pwp/mysvn/linux/linux-2.6/fs/gfs2/inode.c: In function
‘gfs2_lookup_by_inum’: /home/pwp/mysvn/linux/linux-2.6/fs/gfs2/inode.c:188:16:
warning: ‘inode’ may be used uninitialized in this function
Signed-off-by: Weiping Pan(潘卫平) <panweiping3@gmail.com>
---
fs/gfs2/inode.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c
index 97d54a2..5b937c6 100644
--- a/fs/gfs2/inode.c
+++ b/fs/gfs2/inode.c
@@ -185,7 +185,7 @@ struct inode *gfs2_lookup_by_inum(struct gfs2_sbd *sdp, u64 no_addr,
{
struct super_block *sb = sdp->sd_vfs;
struct gfs2_holder i_gh;
- struct inode *inode;
+ struct inode *inode = NULL;
int error;
error = gfs2_glock_nq_num(sdp, no_addr, &gfs2_inode_glops,
--
1.7.4
^ permalink raw reply related
* (no subject)
From: TONY KINGS @ 2011-04-11 2:20 UTC (permalink / raw)
--
Are you in need of getting a loan today.Contact us via mail
at:tonykings_loans@yahoo.com
^ permalink raw reply
* [PATCH 2/2] xfs:remove a warning in xfs_buf_readahead()
From: Weiping Pan(潘卫平) @ 2011-04-11 2:44 UTC (permalink / raw)
To: aelder, xfs-masters, dchinner, hch, jaxboe, tj, xfs
Cc: linux-kernel, Weiping Pan (=E6=BD=98=E5=8D=AB=E5=B9=B3)
/home/pwp/mysvn/linux/linux-2.6/fs/xfs/linux-2.6/xfs_buf.c: In function
‘xfs_buf_readahead’:
/home/pwp/mysvn/linux/linux-2.6/fs/xfs/linux-2.6/xfs_buf.c:660:27: warning:
unused variable ‘bdi’
Signed-off-by: Weiping Pan(潘卫平) <panweiping3@gmail.com>
---
fs/xfs/linux-2.6/xfs_buf.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/fs/xfs/linux-2.6/xfs_buf.c b/fs/xfs/linux-2.6/xfs_buf.c
index 5ea4020..a125b32 100644
--- a/fs/xfs/linux-2.6/xfs_buf.c
+++ b/fs/xfs/linux-2.6/xfs_buf.c
@@ -657,8 +657,6 @@ xfs_buf_readahead(
xfs_off_t ioff,
size_t isize)
{
- struct backing_dev_info *bdi;
-
if (bdi_read_congested(target->bt_bdi))
return;
--
1.7.4
_______________________________________________
xfs mailing list
xfs@oss.sgi.com
http://oss.sgi.com/mailman/listinfo/xfs
^ permalink raw reply related
* (no subject)
From: TONY KINGS @ 2011-04-11 2:18 UTC (permalink / raw)
--
Are you in need of getting a loan today.Contact us via mail
at:tonykings_loans@yahoo.com
^ permalink raw reply
* Re: ipt_NETFLOW and xtables-addons
From: Jan Engelhardt @ 2011-04-11 2:37 UTC (permalink / raw)
To: Srinivasa T N; +Cc: netfilter-devel
In-Reply-To: <4D4661F3.4070507@linux.vnet.ibm.com>
On Monday 2011-01-31 08:17, Srinivasa T N wrote:
> Hi,
> Can I compile ipt_NETFLOW standalone (i.e., use pom and not change kernel)?
> Or should I integrate that with xtables-addons? If I have to integrate, how
> can I do so?
POM is defunct.
Integration into xtables-addons requires that the files be copied into
it and the Kbuild, Mbuild, mconfig files be modified appropriately.
Most important of all is that the copy in xtables-addons should be a
first-class citizen that is maintained, preferably by the person that
does the current standalone releases. Me picking code updates from
external projects would be time-consuming.
^ permalink raw reply
* Re: newer Qt in Yocto
From: Cui, Dexuan @ 2011-04-11 2:30 UTC (permalink / raw)
To: Li, Simon, yocto@yoctoproject.org
In-Reply-To: <23F1A04A50711046AF124F3D4D1EB2ECC0A3F6E1@pgsmsx507.gar.corp.intel.com>
[-- Attachment #1: Type: text/plain, Size: 698 bytes --]
We already have a recipe for the latest qt 4.7.2: http://git.pokylinux.org/cgit/cgit.cgi/poky/tree/meta/recipes-qt/qt4/qt4-x11-free_4.7.2.bb
Thanks,
-- Dexuan
________________________________
From: yocto-bounces@yoctoproject.org [mailto:yocto-bounces@yoctoproject.org] On Behalf Of Li, Simon
Sent: 2011年4月8日 16:11
To: yocto@yoctoproject.org
Subject: [yocto] newer Qt in Yocto
Hi, all,
Thanks for help to get Qt works on my Yocto.
I found that the Qt version is 4.6.3. This version does not support Qt Quick.
I guess maybe because of the QtEclipse plugin is for Qt 4.6.
Is there any plan to upgrade Qt to the latest version?
Thanks.
Best Regards,
Simon Li
[-- Attachment #2: Type: text/html, Size: 5767 bytes --]
^ permalink raw reply
* [PATCH] xfs: fix bmbt block allocation failures
From: Dave Chinner @ 2011-04-11 2:34 UTC (permalink / raw)
To: xfs
From: Dave Chinner <dchinner@redhat.com>
When a multilevel bmbt split occurs, we can be asked to allocate
blocks from an AG that has no space left available. In the case of
an extent just being allocated, the first bmbt block allocation sees
the firstblock parameter is set and does not set a minleft parameter
for the allocation. The allocation also does not set the total
number of blocks required by the allocation, either.
If the extent allocation used all the free space in the AG, the lack
of a total allocation size results in a block being reserved for the
AG freespace btree manipulations being used incorrectly.
Secondly, the allocation is only allowed to be allocated in the
current AG (NEAR_BNO) because the low space algorithm has not been
activated. As a result of this, the second block allocation in the
split fails to find sufficient space in the current AG and fails,
resulting in a dirty transaction cancellation and a filesytem
shutdown.
There are two problems here - both pointed out by Lachlan McIlroy
when we were first discussing a proposed fix for the problem (See
http://oss.sgi.com/archives/xfs/2010-09/msg00438.html). Firstly,
the missing args->total was causing the initial block to be
allocated from the freespace reserve. Secondly that the NEAR_BNO
allocation should probably be a START_BNO allocation to allow blocks
to be taken from a higher numbered AG.
With these changes, the allocation failure goes away, but we trigger
asserts in xfs_bmapi() that try to ensure that bmbt block
allocations only occur in the same AG as the extent allocated,
except if the low space algorithm is active. In this case, we don't
need to activate the low space algorithm - if a START_BNO allocation
fails with minleft = 0, then there is no space we can allocate at
all, and hence the low space algorithm is no help. Therefore the
asserts need modification reflect the new state of affairs.
This commit fixes the problem demonstrated by the test case in
xfstests 250.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
---
fs/xfs/xfs_bmap.c | 8 ++------
fs/xfs/xfs_bmap_btree.c | 7 ++-----
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/fs/xfs/xfs_bmap.c b/fs/xfs/xfs_bmap.c
index fa00788..50eed97 100644
--- a/fs/xfs/xfs_bmap.c
+++ b/fs/xfs/xfs_bmap.c
@@ -4917,13 +4917,9 @@ error0:
if (cur) {
if (!error) {
ASSERT(*firstblock == NULLFSBLOCK ||
- XFS_FSB_TO_AGNO(mp, *firstblock) ==
+ XFS_FSB_TO_AGNO(mp, *firstblock) <=
XFS_FSB_TO_AGNO(mp,
- cur->bc_private.b.firstblock) ||
- (flist->xbf_low &&
- XFS_FSB_TO_AGNO(mp, *firstblock) <
- XFS_FSB_TO_AGNO(mp,
- cur->bc_private.b.firstblock)));
+ cur->bc_private.b.firstblock));
*firstblock = cur->bc_private.b.firstblock;
}
xfs_btree_del_cursor(cur,
diff --git a/fs/xfs/xfs_bmap_btree.c b/fs/xfs/xfs_bmap_btree.c
index 87d3c10..b2cdbfe 100644
--- a/fs/xfs/xfs_bmap_btree.c
+++ b/fs/xfs/xfs_bmap_btree.c
@@ -518,10 +518,11 @@ xfs_bmbt_alloc_block(
args.mp = cur->bc_mp;
args.fsbno = cur->bc_private.b.firstblock;
args.firstblock = args.fsbno;
+ args.total = 1;
+ args.type = XFS_ALLOCTYPE_START_BNO;
if (args.fsbno == NULLFSBLOCK) {
args.fsbno = be64_to_cpu(start->l);
- args.type = XFS_ALLOCTYPE_START_BNO;
/*
* Make sure there is sufficient room left in the AG to
* complete a full tree split for an extent insert. If
@@ -534,10 +535,6 @@ xfs_bmbt_alloc_block(
* block allocation here and corrupt the filesystem.
*/
args.minleft = xfs_trans_get_block_res(args.tp);
- } else if (cur->bc_private.b.flist->xbf_low) {
- args.type = XFS_ALLOCTYPE_START_BNO;
- } else {
- args.type = XFS_ALLOCTYPE_NEAR_BNO;
}
args.minlen = args.maxlen = args.prod = 1;
--
1.7.2.3
_______________________________________________
xfs mailing list
xfs@oss.sgi.com
http://oss.sgi.com/mailman/listinfo/xfs
^ permalink raw reply related
* [Bug 32972] EXT4 causes corrupt BitTorrent downloads
From: bugzilla-daemon @ 2011-04-11 2:26 UTC (permalink / raw)
To: linux-ext4
In-Reply-To: <bug-32972-13602@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=32972
--- Comment #5 from Feng Tang <feng.tang@intel.com> 2011-04-11 02:26:43 ---
>
> Actually, I'm much more comfortable backing out commit 6de9843da
> entirely. The above is *not* equivalent to what we had before ---
> consider the case where ext4_map_blocks returns !EXT4_MAP_MAPPED &&
> !EXT4_MAP_UNWRITTEN.
>
> I don't *think* this should happen in the case where ext4_map_blocks
> returns a value > 0, but the fact that it's not obvious, means I'd
> much rather keep things the way that they are. It's not like dropping
> the set_buffer_mapped(bh) was saving anything measurable anyway....
>
> - Ted
Agree for the revert and sorry for the inconvenience brought by my patch. I
walked across the code when debugging a problem, and thought the patch can
clean the code a little :(
Thanks,
Feng
--
Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are watching the assignee of the bug.
^ permalink raw reply
* Re: [PATCH] Btrfs: fix memory leaks in btrfs_new_inode()
From: Li Zefan @ 2011-04-11 2:23 UTC (permalink / raw)
To: Yoshinori Sano; +Cc: linux-btrfs, chris.mason
In-Reply-To: <1302316207-30806-1-git-send-email-yoshinori.sano@gmail.com>
Yoshinori Sano wrote:
> This patch fixes memory leaks in btrfs_new_inode().
>
> Signed-off-by: Yoshinori Sano <yoshinori.sano@gmail.com>
> ---
> fs/btrfs/inode.c | 5 ++++-
> 1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
> index aa116dc..d8c93c1 100644
> --- a/fs/btrfs/inode.c
> +++ b/fs/btrfs/inode.c
> @@ -4536,14 +4536,17 @@ static struct inode *btrfs_new_inode(struct btrfs_trans_handle *trans,
> return ERR_PTR(-ENOMEM);
>
> inode = new_inode(root->fs_info->sb);
> - if (!inode)
> + if (!inode) {
> + btrfs_free_path(path);
> return ERR_PTR(-ENOMEM);
> + }
>
> if (dir) {
> trace_btrfs_inode_request(dir);
>
> ret = btrfs_set_inode_index(dir, index);
> if (ret) {
> + btrfs_free_path(path);
> iput(inode);
> return ERR_PTR(ret);
> }
It would be better to avoid multiple returns here:
fail_free_path:
btrfs_free_path(path);
fail_put_inode:
iput(inode);
fail:
...
^ permalink raw reply
* Re: [PATCH net-next-2.6 v3 0/3] sctp: Patch series
From: Wei Yongjun @ 2011-04-11 2:19 UTC (permalink / raw)
To: David Miller; +Cc: micchie, netdev, linux-sctp
In-Reply-To: <20110410.185236.59685173.davem@davemloft.net>
> From: Michio Honda <micchie@sfc.wide.ad.jp>
> Date: Fri, 8 Apr 2011 14:18:30 +0900
>
> [ Changed lksctp to linux-sctp@vger.kernel.org as that is the mailing
> list provided in linux/MAINTAINERS ]
>
>> Series of 5 patches to support auto_asconf and the other related
>> functionalities that auto_asconf relies on.
> ...
>> [1/3] Add Auto-ASCONF support
>> [2/3] Add ASCONF operation on the single-homed host
>> [3/3] Add a valid address list in association local
> Can an SCTP expert please review these patches?
I am review these patches now, I will check ASAP, but this will
spend some time since this patchset is too big. :-)
^ permalink raw reply
* Re: [PATCH net-next-2.6 v3 0/3] sctp: Patch series
From: Wei Yongjun @ 2011-04-11 2:19 UTC (permalink / raw)
To: David Miller; +Cc: micchie, netdev, linux-sctp
In-Reply-To: <20110410.185236.59685173.davem@davemloft.net>
> From: Michio Honda <micchie@sfc.wide.ad.jp>
> Date: Fri, 8 Apr 2011 14:18:30 +0900
>
> [ Changed lksctp to linux-sctp@vger.kernel.org as that is the mailing
> list provided in linux/MAINTAINERS ]
>
>> Series of 5 patches to support auto_asconf and the other related
>> functionalities that auto_asconf relies on.
> ...
>> [1/3] Add Auto-ASCONF support
>> [2/3] Add ASCONF operation on the single-homed host
>> [3/3] Add a valid address list in association local
> Can an SCTP expert please review these patches?
I am review these patches now, I will check ASAP, but this will
spend some time since this patchset is too big. :-)
^ permalink raw reply
* Re: Question about snd_mixer_selem_get_playback_dB_range()
From: Raymond Yau @ 2011-04-11 2:19 UTC (permalink / raw)
To: ALSA Development Mailing List
In-Reply-To: <4D884B8D.1000103@ladisch.de>
2011/3/22 Clemens Ladisch <clemens@ladisch.de>
> Peter Ujfalusi wrote:
> > Looking at the patch itself, it does going to return
> > min=SND_CTL_TLV_DB_GAIN_MUTE from snd_tlv_get_dB_range function.
> >
> > However I have my doubts, if this is the correct way...
> >
> > Take these two gain controls for example:
> > RAW value GAIN1 GAIN2
> > 0 mute mute
> > 1 -2dB 0dB
> > 2 0dB 1dB
> > 3 2dB 2dB
> >
> > If user space asks for the dB_range:
> > min max
> > GAIN1 mute 2dB
> > GAIN2 mute 2dB
> >
> > They are going to return with the same range, however if you ask for
> > -2dB on both:
> > GAIN1 will be -2dB
> > GAIN2 will be muted
>
> Or not, depending on which direction you instruct it to round.
>
> > So we are kind of hiding the dB range for the control.
>
> This is unavoidable if the only information returned is min/max.
> To get the entire curve and resolution, you'd have to get the dB value
> for each raw volume value.
>
>
Should the application include the dB range of "Virtual Master" ?
e.g. pulseaudio calculate the dB range (-168dB to 0dB ) on my ad1988 HDA
codec
which "front", "surround", "center/lfe" and "side" have (-58.0 to 0dB)
D: alsa-mixer.c: Activating path analog-output
D: alsa-mixer.c: Path analog-output (Analog Output), direction=1,
priority=99, probed=yes, supported=yes, has_mute=yes, has_volume=yes,
has_dB=yes, min_volume=0, max_volume=39, min_dB=-168, max_dB=0
D: alsa-mixer.c: Element Master, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x7ffffffffffff, n_channels=1, override_map=yes
D: alsa-mixer.c: Element Headphone, direction=1, switch=1, volume=0,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x0, n_channels=0, override_map=no
D: alsa-mixer.c: Element Front, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x6, n_channels=2, override_map=yes
D: alsa-mixer.c: Element Surround, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x60, n_channels=2, override_map=yes
D: alsa-mixer.c: Element Side, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0xc00, n_channels=2, override_map=yes
D: alsa-mixer.c: Element Center, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x4900000000018, n_channels=1, override_map=yes
D: alsa-mixer.c: Element LFE, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x80, n_channels=1, override_map=yes
D: alsa-mixer.c: Element PCM, direction=1, switch=0, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x3600000000f66, n_channels=2, override_map=yes
I: alsa-sink.c: Hardware volume ranges from -168.00 dB to 0.00 dB.
I: alsa-sink.c: Fixing base volume to 0.00 dB
I: alsa-sink.c: Successfully enabled synchronous volume.
I: alsa-sink.c: Using hardware volume control. Hardware dB scale supported.
I: alsa-sink.c: Using hardware mute control.
D: alsa-util.c: snd_pcm_dump():
D: alsa-util.c: Soft volume PCM
D: alsa-util.c: Control: PCM Playback Volume
D: alsa-util.c: min_dB: -51
D: alsa-util.c: max_dB: 0
D: alsa-util.c: resolution: 256
D: alsa-util.c: Its setup is:
D: alsa-util.c: stream : PLAYBACK
D: alsa-util.c: access : MMAP_INTERLEAVED
D: alsa-util.c: format : S16_LE
D: alsa-util.c: subformat : STD
D: alsa-util.c: channels : 2
D: alsa-util.c: rate : 44100
D: alsa-util.c: exact rate : 44100 (44100/1)
D: alsa-util.c: msbits : 16
D: alsa-util.c: buffer_size : 16384
D: alsa-util.c: period_size : 8192
D: alsa-util.c: period_time : 185759
D: alsa-util.c: tstamp_mode : ENABLE
D: alsa-util.c: period_step : 1
D: alsa-util.c: avail_min : 15502
D: alsa-util.c: period_event : 0
D: alsa-util.c: start_threshold : -1
D: alsa-util.c: stop_threshold : 1073741824
D: alsa-util.c: silence_threshold: 0
D: alsa-util.c: silence_size : 0
D: alsa-util.c: boundary : 1073741824
D: alsa-util.c: Slave: Hardware PCM card 1 'HDA Intel' device 0 subdevice 0
D: alsa-util.c: Its setup is:
D: alsa-util.c: stream : PLAYBACK
D: alsa-util.c: access : MMAP_INTERLEAVED
D: alsa-util.c: format : S16_LE
D: alsa-util.c: subformat : STD
D: alsa-util.c: channels : 2
D: alsa-util.c: rate : 44100
D: alsa-util.c: exact rate : 44100 (44100/1)
D: alsa-util.c: msbits : 16
D: alsa-util.c: buffer_size : 16384
D: alsa-util.c: period_size : 8192
D: alsa-util.c: period_time : 185759
D: alsa-util.c: tstamp_mode : ENABLE
D: alsa-util.c: period_step : 1
D: alsa-util.c: avail_min : 15502
D: alsa-util.c: period_event : 0
D: alsa-util.c: start_threshold : -1
D: alsa-util.c: stop_threshold : 1073741824
D: alsa-util.c: silence_threshold: 0
D: alsa-util.c: silence_size : 0
D: alsa-util.c: boundary : 1073741824
D: alsa-util.c: appl_ptr : 0
D: alsa-util.c: hw_ptr : 0
D: alsa-sink.c: Thread starting up
D: alsa-sink.c: Read hardware volume: 0: 100% 1: 100%
SB Live! platinum (CT4760P) which has "Surround Playback Volume" with
SND_CTL_TLV_DB_GAIN_MUTE , "Master and PCM Playback Volume" of stac9721
and PA report (-100081dB to +12 dB)
D: alsa-mixer.c: Activating path analog-output
D: alsa-mixer.c: Path analog-output (Analog Output), direction=1,
priority=99, probed=yes, supported=yes, has_mute=yes, has_volume=yes,
has_dB=yes, min_volume=0, max_volume=31, min_dB=-100081, max_dB=12
D: alsa-mixer.c: Element Master, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x3600000000f66, n_channels=2, override_map=yes
D: alsa-mixer.c: Element Surround, direction=1, switch=0, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x60, n_channels=2, override_map=yes
D: alsa-mixer.c: Element PCM, direction=1, switch=1, volume=1,
volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x3600000000f66, n_channels=2, override_map=yes
D: alsa-mixer.c: Element External Amplifier, direction=1, switch=4,
volume=0, volume_limit=-1, enumeration=0, required=0, required_any=0,
required_absent=0, mask=0x0, n_channels=0, override_map=no
D: alsa-mixer.c: Option on (output-amplifier-on/Amplifier) index=1,
priority=10
D: alsa-mixer.c: Option off (output-amplifier-off/No Amplifier) index=0,
priority=0
D: alsa-mixer.c: Setting output-amplifier-on (Amplifier) priority=10
D: alsa-mixer.c: Setting output-amplifier-off (No Amplifier) priority=0
I: alsa-sink.c: Hardware volume ranges from -100080.99 dB to 12.00 dB.
I: alsa-sink.c: Fixing base volume to -12.00 dB
^ permalink raw reply
* [ath9k-devel] Sparklan WPEA-121N AR9382 168c:abcd
From: Adrian Chadd @ 2011-04-11 2:19 UTC (permalink / raw)
To: ath9k-devel
In-Reply-To: <A814A73D6E73AA4994667CA0CF22B6F45EF2B8@svr-w2000.mail.miniqar.com>
Is there an easy way to get an EEPROM/OTP contents dump in ath9k?
Adrian
2011/4/11 Hasan Rashid <hrashad@avionica.com>
> That's exactly what I did, also, I had to add the vendor ID in the
> hw_init function for the driver to fully load. I got it to work after making
> these changes in the ath9k driver.
>
> Now I have a different problem. In AP mode using hostapd, the driver
> doesn't transmit at a higher rate than 54Mbit. The iw tool reports only
> non-HT data rates. Does the vendor id need to be added somewhere else as
> well for the rate control algorithm to load 802.11n HT rates? Using iperf I
> can only get a transmit rate up to 29Mbps. However, when I transmit from an
> 802.11n station, it works like you would expect, a throughput of 70-80 Mbps.
>
>
> Thank you!
>
> Regards, Hasan R.
> ------------------------------
> *From:* Mohammed Shafi [mailto:shafi.ath9k at gmail.com]
> *Sent:* ????? 10/04/2011 8:14 AM
> *To:* Hasan Rashid
> *Cc:* ath9k-devel at lists.ath9k.org
> *Subject:* Re: [ath9k-devel] Sparklan WPEA-121N AR9382 168c:abcd
>
> On Sun, Apr 10, 2011 at 5:39 PM, Mohammed Shafi <shafi.ath9k@gmail.com>
> wrote:
> > On Sat, Apr 9, 2011 at 2:00 AM, Hasan Rashid <hrashad@avionica.com>
> wrote:
> >> Hello All,
> >>
> >> I recently purchased a Sparklan WPEA-121N, it uses the AR9382
> chipset. It is
> >> mentioned as supported on the device list, however, when I load that
> ath9k
> >> modules nothing comes up.
> >>
> >> Does ath9k support this chipset? I compiled compat-wirless on Ubuntu
> 10.10
> >> on an x86 Core2Duo machine.
> >>
> >> lspci -vvvnn returns the following:
> >>
> >> 02:00.0 Ethernet controller [0200]: Atheros Communications Inc. Device
> >> [168c:abcd] (rev 01)
> >
> > Yes AR9382 is supported in ath9k, your device id 'abcd' ?
> > Did you check with the latest compat wireless?
>
> I doubt the vendor id, if you get you vendor id some thing like this might
> help
> diff --git a/drivers/net/wireless/ath/ath9k/pci.c
> b/drivers/net/wireless/ath/ath9k/pci.c
> index e83128c..594336a 100644
> --- a/drivers/net/wireless/ath/ath9k/pci.c
> +++ b/drivers/net/wireless/ath/ath9k/pci.c
> @@ -30,6 +30,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
> { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
> { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
> { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
> + { PCI_VDEVICE(ATHEROS, 0xabcd) }, /* PCI-E AR9300 */
> { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
> { 0 }
> };
>
>
> >
> >
> >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr-
> >> Stepping- SERR- FastB2B- DisINTx-
> >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> >> <TAbort- <MAbort- >SERR- <PERR- INTx-
> >> Latency: 0, Cache Line Size: 32 bytes
> >> Interrupt: pin A routed to IRQ 15
> >> Region 0: Memory at fc8e0000 (64-bit, non-prefetchable)
> [size=128K]
> >> Expansion ROM at fc8d0000 [disabled] [size=64K]
> >> Capabilities: [40] Power Management version 3
> >> Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA
> >> PME(D0+,D1+,D2-,D3hot+,D3cold-)
> >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
> >> Capabilities: [50] MSI: Enable- Count=1/4 Maskable+ 64bit+
> >> Address: 0000000000000000 Data: 0000
> >> Masking: 00000000 Pending: 00000000
> >> Capabilities: [70] Express (v2) Endpoint, MSI 00
> >> DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s
> <1us,
> >> L1 <8us
> >> ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
> >> DevCtl: Report errors: Correctable- Non-Fatal- Fatal-
> >> Unsupported-
> >> RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
> >> MaxPayload 128 bytes, MaxReadReq 512 bytes
> >> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
> >> TransPend-
> >> LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1,
> >> Latency L0 <2us, L1 <64us
> >> ClockPM- Surprise- LLActRep- BwNot-
> >> LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain-
> >> CommClk+
> >> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> >> LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+
> >> DLActive- BWMgmt- ABWMgmt-
> >> DevCap2: Completion Timeout: Not Supported, TimeoutDis+
> >> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
> >> LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance-
> >> SpeedDis-, Selectable De-emphasis: -6dB
> >> Transmit Margin: Normal Operating Range,
> >> EnterModifiedCompliance- ComplianceSOS-
> >> Compliance De-emphasis: -6dB
> >> LnkSta2: Current De-emphasis Level: -6dB
> >> Capabilities: [100 v1] Advanced Error Reporting
> >> UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
> UnxCmplt-
> >> RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
> >> UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
> UnxCmplt-
> >> RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
> >> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt-
> UnxCmplt-
> >> RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
> >> CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> >> NonFatalErr+
> >> CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> >> NonFatalErr+
> >> AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap-
> >> ChkEn-
> >> Capabilities: [140 v1] Virtual Channel
> >> Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
> >> Arb: Fixed- WRR32- WRR64- WRR128-
> >> Ctrl: ArbSelect=Fixed
> >> Status: InProgress-
> >> VC0: Caps: PATOffset=00 MaxTimeSlots=1
> RejSnoopTrans-
> >> Arb: Fixed- WRR32- WRR64- WRR128- TWRR128-
> >> WRR256-
> >> Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
> >> Status: NegoPending- InProgress-
> >> Capabilities: [300 v1] Device Serial Number
> 00-00-00-00-00-00-00-00
> >>
> >> Hasan R.
> >> _______________________________________________
> >> ath9k-devel mailing list
> >> ath9k-devel at lists.ath9k.org
> >> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
> >>
> >>
> >
> This communication contains information that may be confidential or
> privileged. The information is solely intended for the use of the addressee.
> If you are not the intended recipient, be advised that any disclosure, copy,
> distribution, or use of the contents of this communication is prohibited. If
> you have received this communication in
> error, please immediately notify the sender by telephone or by electronic
> mail.
>
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
>
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^ permalink raw reply
* quota lockdep while running ext4 xfstests #219
From: Theodore Ts'o @ 2011-04-11 2:16 UTC (permalink / raw)
To: Jan Kara; +Cc: linux-ext4
Hi Jan,
FYI, I manage to trigger the following lockdep warning while running
v2.6.39-rc1 plus the ext4 patch queue. None of the patches except for
your "ext4: remove unnecessary [cm]time update of quota file" patch
should affect the quota operations, and I don't think this patch should
have caused this, either.
I'm going to ignore this now, since it was triggered by repquota, and
I'm guessing it should occur rarely, but I thought I should let you know
in case I'm misjudging things.
Regards,
- Ted
219 7s ...[ 3314.895274] EXT4-fs (vdc1): warning: maximal mount count reached, running e2fsck is recommended
[ 3315.676490]
[ 3315.676493] =======================================================
[ 3315.679704] [ INFO: possible circular locking dependency detected ]
[ 3315.679704] 2.6.39-rc1-00009-g19e2b53 #1508
[ 3315.679704] -------------------------------------------------------
[ 3315.679704] repquota/10186 is trying to acquire lock:
[ 3315.679704] (&mm->mmap_sem){++++++}, at: [<c01e3cce>] might_fault+0x4c/0x8a
[ 3315.679704]
[ 3315.679704] but task is already holding lock:
[ 3315.679704] (&type->s_umount_key#21){+++++.}, at: [<c01fd7b2>] get_super+0x55/0x98
[ 3315.679704]
[ 3315.679704] which lock already depends on the new lock.
[ 3315.679704]
[ 3315.679704]
[ 3315.679704] the existing dependency chain (in reverse order) is:
[ 3315.679704]
[ 3315.679704] -> #2 (&type->s_umount_key#21){+++++.}:
[ 3315.679704] [<c0189957>] lock_acquire+0x99/0xbd
[ 3315.679704] [<c0688727>] down_read+0x39/0x76
[ 3315.679704] [<c0216db5>] writeback_inodes_sb_if_idle+0x26/0x3d
[ 3315.679704] [<c026392b>] ext4_da_write_begin+0xfe/0x27d
[ 3315.679704] [<c025e04c>] ext4_page_mkwrite+0x14b/0x198
[ 3315.679704] [<c01e6220>] __do_fault+0xfd/0x346
[ 3315.679704] [<c01e70a5>] handle_pte_fault+0x318/0x73c
[ 3315.679704] [<c01e7589>] handle_mm_fault+0xc0/0xd2
[ 3315.679704] [<c068c3c8>] do_page_fault+0x362/0x37e
[ 3315.679704] [<c0689fab>] error_code+0x5f/0x64
[ 3315.679704]
[ 3315.679704] -> #1 (&sb->s_type->i_alloc_sem_key#3){++++..}:
[ 3315.679704] [<c0189957>] lock_acquire+0x99/0xbd
[ 3315.679704] [<c0688727>] down_read+0x39/0x76
[ 3315.679704] [<c025df32>] ext4_page_mkwrite+0x31/0x198
[ 3315.679704] [<c01e6220>] __do_fault+0xfd/0x346
[ 3315.679704] [<c01e70a5>] handle_pte_fault+0x318/0x73c
[ 3315.679704] [<c01e7589>] handle_mm_fault+0xc0/0xd2
[ 3315.679704] [<c068c3c8>] do_page_fault+0x362/0x37e
[ 3315.679704] [<c0689fab>] error_code+0x5f/0x64
[ 3315.679704]
[ 3315.679704] -> #0 (&mm->mmap_sem){++++++}:
[ 3315.679704] [<c018964d>] __lock_acquire+0x926/0xb97
[ 3315.679704] [<c0189957>] lock_acquire+0x99/0xbd
[ 3315.679704] [<c01e3ced>] might_fault+0x6b/0x8a
[ 3315.679704] [<c036e6f0>] copy_to_user+0x34/0x10c
[ 3315.679704] [<c02365d1>] do_quotactl+0x247/0x39c
[ 3315.679704] [<c0236830>] sys_quotactl+0x10a/0x136
[ 3315.679704] [<c06898dd>] syscall_call+0x7/0xb
[ 3315.679704]
[ 3315.679704] other info that might help us debug this:
[ 3315.679704]
[ 3315.679704] 1 lock held by repquota/10186:
[ 3315.679704] #0: (&type->s_umount_key#21){+++++.}, at: [<c01fd7b2>] get_super+0x55/0x98
[ 3315.679704]
[ 3315.679704] stack backtrace:
[ 3315.679704] Pid: 10186, comm: repquota Not tainted 2.6.39-rc1-00009-g19e2b53 #1508
[ 3315.679704] Call Trace:
[ 3315.679704] [<c0188099>] print_circular_bug+0x90/0x9c
[ 3315.679704] [<c018964d>] __lock_acquire+0x926/0xb97
[ 3315.679704] [<c01876d3>] ? mark_lock+0x1e/0x1df
[ 3315.679704] [<c0189957>] lock_acquire+0x99/0xbd
[ 3315.679704] [<c01e3cce>] ? might_fault+0x4c/0x8a
[ 3315.679704] [<c01e3ced>] might_fault+0x6b/0x8a
[ 3315.679704] [<c01e3cce>] ? might_fault+0x4c/0x8a
[ 3315.679704] [<c036e6f0>] copy_to_user+0x34/0x10c
[ 3315.679704] [<c02365d1>] do_quotactl+0x247/0x39c
[ 3315.679704] [<c01fd7b2>] ? get_super+0x55/0x98
[ 3315.679704] [<c01fd7b2>] ? get_super+0x55/0x98
[ 3315.679704] [<c0236830>] sys_quotactl+0x10a/0x136
[ 3315.679704] [<c06898dd>] syscall_call+0x7/0xb
^ permalink raw reply
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