* Re: [Xen-users] Re: Xen document day (Oct 12 or 26)
From: Florian Heigl @ 2011-10-30 20:58 UTC (permalink / raw)
To: Lars Kurth
Cc: xen-devel@lists.xensource.com, Ian Campbell,
Konrad Rzeszutek Wilk, Andrew Bobulsky, Joseph Glanville,
xen-users@lists.xensource.com
In-Reply-To: <4EAAA467.2030503@xen.org>
Hi Lars,
2011/10/28 Lars Kurth <lars.kurth@xen.org>:
> There may be a few more. Will need to work on these a little more. It may
> also mean that the MediWiki instance is set up that pages must have a
> category and that only a subset of users can create new ones. Otherwise we
> get into the same mess again.
I think the main issues (mess) with the old wiki were:
- not being able to contact someone if information is incorrect / outdated
- noone looking into pages that had become outdated
- not looking for pages that might be outdated
- most of the pages being immutable so you couldn't even fix stuff.
So if we limit edit rights to certain user groups that is not a
problem, as long as the groups are big enough to maintain the
categories.
Also it might be helpful to use a release mechanism - if any
registered user can create pages, but they stay invisible until
approval then this would save a lot of time for the regular authors
and still keep up quality. (Thats working really well in my
experience)
Greetings
Florian
^ permalink raw reply
* Re: [B.A.T.M.A.N.] [PATCH 1/2] batman-adv: Fix style changes reported by cppcheck
From: Simon Wunderlich @ 2011-10-30 20:58 UTC (permalink / raw)
To: The list for a Better Approach To Mobile Ad-hoc Networking
In-Reply-To: <201110302124.31362.lindner_marek@yahoo.de>
[-- Attachment #1: Type: text/plain, Size: 1094 bytes --]
Hey,
Patch 2/2 was created accidently due to my lack of git skills, please
assume [PATCH]. :)
The output of cppcheck (before the applying the patch):
$ cppcheck -q --enable=all .
[bat_iv_ogm.c:993]: (style) The scope of the variable 'offset' can be reduced
[routing.c:980]: (style) The scope of the variable 'ret' can be reduced
[soft-interface.c:695]: (style) The scope of the variable 'ret' can be reduced
Note that reduced scope may be a matter of taste, I could not really find
anything about that in the CodingStyle.
Cheers
Simon
On Sun, Oct 30, 2011 at 09:24:31PM +0100, Marek Lindner wrote:
> On Sunday, October 30, 2011 16:36:20 Simon Wunderlich wrote:
> > cppcheck reported some style issues this patch fixes.
> >
> > Signed-off-by: Simon Wunderlich <siwu@hrz.tu-chemnitz.de>
> > ---
> > bat_iv_ogm.c | 2 +-
> > routing.c | 2 +-
> > soft-interface.c | 2 +-
> > 3 files changed, 3 insertions(+), 3 deletions(-)
>
> Do you mind saying what cppcheck reported ?
> What happened to patch 2/2 ?
>
> Regards,
> Marek
>
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^ permalink raw reply
* Re: [B.A.T.M.A.N.] [PATCH] batman-adv: Fix range check for expected packets
From: Marek Lindner @ 2011-10-30 20:58 UTC (permalink / raw)
To: b.a.t.m.a.n; +Cc: netdev, Simon Wunderlich
In-Reply-To: <1319988163-3249-1-git-send-email-siwu@hrz.tu-chemnitz.de>
On Sunday, October 30, 2011 16:22:43 Simon Wunderlich wrote:
> The check for new packets in the future used a wrong binary operator,
> which makes the check expression always true and accepting too many
> packets.
Applied in revision 00ca20e.
Thanks,
Marek
^ permalink raw reply
* Re: [PATCH] batman-adv: Fix range check for expected packets
From: Marek Lindner @ 2011-10-30 20:58 UTC (permalink / raw)
To: b.a.t.m.a.n-ZwoEplunGu2X36UT3dwllkB+6BGkLq7r
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, Simon Wunderlich
In-Reply-To: <1319988163-3249-1-git-send-email-siwu-MaAgPAbsBIVS8oHt8HbXEIQuADTiUCJX@public.gmane.org>
On Sunday, October 30, 2011 16:22:43 Simon Wunderlich wrote:
> The check for new packets in the future used a wrong binary operator,
> which makes the check expression always true and accepting too many
> packets.
Applied in revision 00ca20e.
Thanks,
Marek
^ permalink raw reply
* Re: [PATCH v2 3/3] staging: nvec: add device tree support
From: Marc Dietrich @ 2011-10-30 20:58 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Olof Johansson, Colin Cross,
devel-tBiZLqfeLfOHmIFyCCdPziST3g8Odh+X@public.gmane.org,
Julian Andres Klode
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF173EDAB4D1-C7FfzLzN0UxDw2glCA4ptUEOCMrvLtNR@public.gmane.org>
On Friday 28 October 2011 09:56:41 you wrote:
> Marc Dietrich wrote at Friday, October 28, 2011 5:02 AM:
> > Am Donnerstag, 27. Oktober 2011, 12:17:25 schrieb Stephen Warren:
> > > Marc Dietrich wrote at Wednesday, October 26, 2011 1:59 PM:
> > > > This adds device tree support to the nvec driver. By using this
> > > > method it is no longer necessary to specify platform data
> > > > through a board file.
>
> ...
>
> > > > +/* Match table for of_platform binding */
> > > > +static const struct of_device_id nvidia_nvec_of_match[]
> > > > __devinitconst = { + { .compatible = "nvidia,nvec", },
> > >
> > > I'm not sure that nvidia,nvec is the right value, but need a little
> > > more background.
> > >
> > > It's my understanding that how this works is a little
> > > micro-controller
> > > exists on the board, handles various devices like the keyboard, and
> > > sends data to Tegra by making I2C master transactions. Isn't it the
> > > case that the micro-controller (or at least the SW running on it)
> > > is board-specific, and the same for the I2C protocol? If so,
> > > nvidia,nvec is a little generic; we probably need to name it
> > > compal,paz00-ec or something like that?>
> > The firmware (for the 8051 mc inside the keyboard controller) is likely
> > made by Compal, but as Julian already said, the EC protocol definition
> > is very likely from NVIDIA itself. Compal just implemented it for the
> > master. You may refer to <http://nv-
> > tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=commitdiff;h=12114faf442a8c6a
> > ac81a9702712077364db0e82> Also this protocol is not board specific as
> > many first generation boards/device use it, so "nvidia,nvec" should be
> > correct here.
> >
> > > Either way, we should probably include some kind of version number
> > > in
> > > the compatible property so we can support upgrades to the protocol
> > > if
> > > needed.
> >
> > You may ask your colleagues on that topic, but it seems that the
> > protocol is dead already, e.g. it wasn't implemented for the new-world
> > kernels (>= .36) anymore.
> OK, I asked internally and it sounds like this is /probably/ standardized.
>
> That said, there are apparently some OEMs who did change the protocol
> and do something slightly different. I'm trying to confirm whether PAZ00
> was one of them. I guess not if PAZ00 works with the standard driver that
> you linked to.
There are so called OEM commands which we will move to a board specific nvec
file (e.g. nvec_paz00.c). We haven't got the chance to test it on other boards
using it yet (e.g. toshiba folio, advent vega, ...). The tablets are mostly
using it for power control and maybe also leds/switches. I don't think any
other board uses keyboard / mouse functions.
> So the good news is that there's an internal specification for this
> protocol, and we might be able to release it. I'll let you know if/when
> there are updates on this.
The original source is well documentated already, but additional info is
always welcome ;-)
> I'd like to call this "nvidia,nvec-1.0" to version this compatible
> property; that's the specification version in the latest document that
> I saw. While we do seemed to have abandoned this approach, I want to
> make sure this is extensible if someone suddenly decides to go back to
> it and creates a 2.0 in the future. Does that seem reasonable?
mmh, I can't see why we should add it now. There is no V2 I can see in my
limited view. If your company plans to expand the protocol you can either
enhance our driver or create a new one (nvec2), which can add a nvidia,nvec-2
compatibility property (we can also change ours to nvidia,nvec-1 at the same
time, but that's not required).
Marc
^ permalink raw reply
* [Bug 41592] [Radeon] The display often freezes with gnome-shell 3.2
From: bugzilla-daemon @ 2011-10-30 20:58 UTC (permalink / raw)
To: dri-devel
In-Reply-To: <bug-41592-502@http.bugs.freedesktop.org/>
https://bugs.freedesktop.org/show_bug.cgi?id=41592
--- Comment #10 from peterle@hottemptation.org 2011-10-30 13:58:51 PDT ---
Bugzilla Gnome 661898
Posted some days ago.
Because it can be just a bug around the radeon driver in kernel I opened a new
bug here.
https://bugs.freedesktop.org/show_bug.cgi?id=41838
Would be intersting to see if it freezes your system in the same way, if you
visit the website I mentioned in my bug. So we can be sure, that is the same
issue.
--
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are the assignee for the bug.
^ permalink raw reply
* Re: [RESEND PATCH 1/14] staging/media/as102: initial import from Abilis
From: Piotr Chmura @ 2011-10-30 21:03 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Devin Heitmueller, Stefan Richter, Greg KH, Patrick Dickey, LMML,
devel, Sylwester Nawrocki
In-Reply-To: <20111018214634.544344cc@darkstar>
W dniu 18.10.2011 21:46, Piotr Chmura pisze:
> Patch taken from http://kernellabs.com/hg/~dheitmueller/v4l-dvb-as102-2/
>
> Changes made by me:
> 1. Driver moved from media/dvb to staging/media
> 2. Removed Makefile/Kconfig - it doesn't compile in current tree
(...)
> +
> +/*
> + * Note:
> + * - in AS102 SNR=MER
> + * - the SNR will be returned in linear terms, i.e. not in dB
> + * - the accuracy equals ±2dB for a SNR range from 4dB to 30dB
> + * - the accuracy is>2dB for SNR values outside this range
> + */
I found another issue here.
In this comment "±" is from upper ASCII (0xF1). Should I change it into
sth. like "+/-" in this patch (1/14) or leave it and just resend without
"Â" (wasn't there in original patch, don't know where it came from) ?
Peter
P.S. Thanks to Sylwester Nawrocki for pointing me out, that there is
something wrong with patch 6/14, which was caused by this comment in 1/14.
^ permalink raw reply
* [PATCH 01/51] ARM: reset: introduce arm_arch_reset function pointer
From: Will Deacon @ 2011-10-30 21:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111029200548.GC19187@n2100.arm.linux.org.uk>
On Sat, Oct 29, 2011 at 09:05:48PM +0100, Russell King - ARM Linux wrote:
> On Sat, Oct 29, 2011 at 02:56:53PM +0100, Will Deacon wrote:
> > I initially observed this in the idle code, where it looks to me like all
> > the pm_idle overrides could actually be done in the arch_idle hook (the only
> > slightly fiddly one is OMAP). Maybe Nicolas could use the same sort of
> > approach for that?
>
> Beware about changing the semantics of pm_idle - it's a cross-arch thing,
> and we really shouldn't change those semantics without changing the other
> architectures as well.
Indeed. I'm not suggesting making any changes to pm_idle, I'm just pointing
out that all of the pm_idle overrides for ARM can be written as:
if (!need_resched())
do_magic_soc_specific_idle();
local_irq_enable();
so the platform magic may as well just be implemented using arch_idle and we
can remove the ability to reassign pm_idle, therefore consolidating the
platform idle code into one function pointer.
Will
^ permalink raw reply
* Re: Problems cloning the git repostories
From: Marek Vasut @ 2011-10-30 21:09 UTC (permalink / raw)
To: Devin Heitmueller; +Cc: Patrick Dickey, LMML
In-Reply-To: <CAGoCfixneQG=S5wy2qZZ50+PB-QNTFx=GLM7RYPuxfXtUy6Ecg@mail.gmail.com>
> On Sun, Sep 25, 2011 at 8:33 AM, Patrick Dickey <pdickeybeta@gmail.com> wrote:
> > Hello there,
> >
> > I tried to follow the steps for cloning both the "media_tree.git" and
> > "media_build.git" repositories, and received errors for both. The
> > media_tree repository failed on the first line
> >
> >> git clone
> >> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> >> v4l-dvb
> >
> > which I'm assuming is because kernel.org is down.
> >
> > The media_build.git repository fails on the first line also
> >
> >> git clone git://linuxtv.org/media_build.git
> >
> > with a fatal: read error: Connection reset by peer.
> >
> > Is it possible to clone either (or both) repositories at this time, or
> > are they down? And in the absence of cloning the kernel for the
> > media_tree.git repository, is it possible to simply clone the
> > git://linuxtv.org/media_tree.git repository and work from that?
> >
> > My interest in this is to install some patches created by Devin
> > Heitmueller for the Pinnacle PCTV 80e USB tuner (at least the ATSC
> > portion of the tuner). Once I'm able to determine exactly what changes
> > are made, I would like to either submit the patches to the repository,
> > or send them to someone who has more experience in patching the files
> > for submission.
> >
> > One other question (totally unrelated to this post though): When I send
> > emails, normally they are GPG signed. Should I disable that for this
> > list, or is it acceptable?
> >
> > Thank you for any information, and have a great day:)
> > Patrick.
>
> Hi Patrick,
>
> As I said on the blog, the issue isn't getting the driver to work
> against current kernels. Merging the driver against the current tree
> is a trivial exercise (the patch series should apply trivially against
> the current code, with only a few minor conflicts related to board
> numbers, etc).
>
> The bigger issue though is once you do that and have the driver
> running, you now have a body of code > 10,000 lines which doesn't meet
> the "coding standards". Doing such a refactoring is a relatively
> straightforward exercise but very time consuming (you already have a
> working driver, so you just have to make sure you don't break
> anything).
>
> The more I think about this, the more it annoys me. I did all the hard
> parts:
>
> * I worked with the product vendor to get the details for the design
> * I got Hauppauge/PCTV to compel the chipset vendor to release the
> reference code under a GPL compatible license
> * I worked out redistribution terms on the firmware
> * I ported the driver to Linux
> * I integrated the driver and debugged it to achieve signal lock
>
> And why is it not in the mainline? Because none of the above matters
> if I didn't waste a bunch of my time removing a bunch of "#ifdef
> WINDOWS" lines and converting whitespace from tabs to spaces.
>
> It's crap like this that's the reason why some of the best LinuxTV
> driver authors still have a bunch of stuff that isn't merged upstream.
> We just don't have time for this sort of bullshit that any monkey
> could do if he/she was willing to invest the effort. We're just too
> busy doing *actual* driver work.
>
> Five years ago the hard part was finding competent developers, getting
> access to datasheets, getting access to reference driver code, and
> getting access to the details for a hardware design. Now most of
> those problems are not the issue - we have access to all the data but
> we want to waste the time of the few competent developers out there
> making them do "coding style cleanup" before perfectly good code gets
> merged upstream. There has been more than one case where I've
> considered doing a driver for a new board and decided against it
> because the barrier to getting it upstream is not worth my time.
>
> Want to see more device support upstream? Optimize the process to
> make it easy for the people who know the hardware and how to write the
> drivers to get code upstream, and leave it to the "janitors" to work
> out the codingstyle issues.
Mate, I feel sorry for you :-(
^ permalink raw reply
* Re: JMicron Technology JMB362 JMB363 SError: { DevExch } ExpressCard, sometimes fails to boot
From: Tejun Heo @ 2011-10-30 21:12 UTC (permalink / raw)
To: Orson; +Cc: linux-ide, arieslee
In-Reply-To: <4E930916.6050503@gmail.com>
Hello,
(cc'ing Aries of jmicron)
On Mon, Oct 10, 2011 at 06:02:46PM +0300, Orson wrote:
> I tried my xpress54 card JMB362/363 on Debian Wheezy testing, with
> kernel 3.0.0-1-amd64 (Debian 3.0.0.-3).
>
> The card was inserted into the express slot without any external
> disk attached and I experienced the same problems I had been having
> with debian squeeze, perhaps even more consistently.
>
> I am now only using single port JMB 360 cards which operate flawlessly.
>
> I am attaching a kernel log with the said card inserted.
Hmmm.... it looks like the controller is continuously raising
connection status changed state and libata is faithfully trying to
probe whether new device appeared on the port. Does it work if you
plug an actual hard drive into the port? Looks more like wrong wiring
than anything else. Aries, any ideas?
ahci 0000:10:00.0: AHCI 0001.0000 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
ahci 0000:10:00.0: flags: 64bit ncq pm led clo pmp pio slum part
ahci 0000:10:00.0: setting latency timer to 64
scsi1 : ahci
ata1: SATA max UDMA/133 abar m8192@0xd0000000 port 0xd0000100 irq 16
ata2: SATA max UDMA/133 abar m8192@0xd0000000 port 0xd0000180 irq 16
ata1: SATA link down (SStatus 0 SControOct 9 23:45:46 hp-laptop kernel: [ 1.414084] ata1: exception Emask 0x10 SAct 0x0 SErr 0x4060000 action 0xe frozen
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { PHYInt CommWake DevExch }
ata1: hard resetting link
ata1: COMRESET failed (errno=-32)
ata1: reset failed (errno=-32), retrying in 8 secs
ata1: limiting SATA link speed to 1.5 Gbps
ata1: hard resetting link
ata1: SATA link down (SStatus 0 SControl 310)
ata1: EH complete
ata1: exception Emask 0x10 SAct 0x0 SErr 0x4060000 action 0xe frozen
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { PHYInt CommWake DevExch }
ata1: hard resetting link
ata1: COMRESET failed (errno=-32)
ata1: reset failed (errno=-32), retrying in 8 secs
ata1: hard resetting link
ata1: SATA link down (SStatus 0 SControl 310)
ata1: EH complete
ata1: exception Emask 0x10 SAct 0x0 SErr 0x4060000 action 0xe frozen
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { PHYInt CommWake DevExch }
ata1: limiting SATA link speed to 1.5 Gbps
ata1: hard resetting link
ata1: SATA link down (SStatus 0 SControl 310)
ata1: EH complete
ata1: exception Emask 0x10 SAct 0x0 SErr 0x4060000 action 0xe frozen
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { PHYInt CommWake DevExch }
ata1: limiting SATA link speed to 1.5 Gbps
ata1: hard resetting link
ata1: SATA link down (SStatus 0 SControl 310)
ata1: EH complete
ata1: exception Emask 0x10 SAct 0x0 SErr 0x4060000 action 0xe frozen
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { PHYInt CommWake DevExch }
ata1: limiting SATA link speed to 1.5 Gbps
ata1: hard resetting link
ata1: SATA link down (SStatus 0 SControl 310)
ata1: EH complete
(repeat...)
--
tejun
^ permalink raw reply
* Re: [RESEND PATCH 11/14] staging/media/as102: fix compile warning about unused function
From: Stefan Richter @ 2011-10-30 21:15 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Mauro Carvalho Chehab, Piotr Chmura, devel, Devin Heitmueller,
Patrick Dickey, Greg KH, LMML
In-Reply-To: <4EADADE1.4080606@gmail.com>
On Oct 30 Sylwester Nawrocki wrote:
> On 10/18/2011 10:03 PM, Piotr Chmura wrote:
> > Patch taken from http://kernellabs.com/hg/~dheitmueller/v4l-dvb-as102-2/
[...]
> > +#if (LINUX_VERSION_CODE< KERNEL_VERSION(2, 6, 19))
>
> I was wondering, could such a conditional compilation be simply skipped when
> we are merging the driver into exactly known kernel version ?
> For backports there are separate patches at media_build.git and I can't see
> such an approach used in any driver upstream.
Compatibility code is in fact not allowed anymore upstream. But AFAIU,
this patch here does not have such a cleanup in its scope. If the compat
removal isn't already included later on in Piotr's series, it will be done
later before this driver can be moved out of staging.
--
Stefan Richter
-=====-==-== =-=- ====-
http://arcgraph.de/sr/
^ permalink raw reply
* Module Error
From: Artur Baruchi @ 2011-10-30 21:16 UTC (permalink / raw)
To: Xen-devel, xen-users
Hi.
Im writing a kernel module to extract some information from kernel,
the module is working really fine in an AMD (AMD Athlon(tm) 64 X2 Dual
Core Processor 3800+), but, when trying to run the module in a i7
(Intel(R) Core(TM) i7 CPU 930 @ 2.80GHz) Im facing some strange errors
(see below). The kernel versions are just the same on both machines
(2.6.34.10-0.2-xen #1 SMP x86_64 x86_64 x86_64 GNU/Linux). The
difference are the amount of memory AND processor vendor. I noted that
the line of code that hangs my machine is this one:
if(end->host==NULL) {
The end->host points to an Inode type (end is an address_space type).
If I remove this line, the module works (but, obviously, do not return
what I want). I tried the same code in a kernel without xen
(2.6.34.10-0.2-desktop #1 SMP x86_64 x86_64 x86_64 GNU/Linux) and
worked fine, so I suppose that this error is due to something in Xen
running in a intel processor (I tried the module in an intel quad, and
got the same error). Follow some outputs:
The error stack:
Oct 28 23:40:35 goku kernel: [ 4472.129718] BUG: unable to handle
kernel paging request at 000003d600000004
Oct 28 23:40:35 goku kernel: [ 4472.129933] IP: [<ffffffffa08d118c>]
get_files+0x6c/0x220 [pagecache]
Oct 28 23:40:35 goku kernel: [ 4472.130098] PGD 0
Oct 28 23:40:35 goku kernel: [ 4472.130250] Oops: 0000 [#4] SMP
Oct 28 23:40:35 goku kernel: [ 4472.130452] last sysfs file:
/sys/devices/system/cpu/cpu7/online
Oct 28 23:40:35 goku kernel: [ 4472.130562] CPU 0
Oct 28 23:40:35 goku kernel: [ 4472.130615] Modules linked in:
pagecache ocfs2_dlmfs ocfs2_stack_o2cb ocfs2_dlm ocfs2_nodemanager
ocfs2_stackglue configfs drbd crc32c libcrc32c bridge stp llc nfsd
lockd nfs_acl snd_pcm_oss auth_rpcgss snd_mixer_oss usbbk gntdev netbk
blkbk blkback_pagemap blktap domctl xenbus_be snd_seq evtchn
snd_seq_device sunrpc exportfs edd fuse loop snd_hda_codec_realtek
firewire_ohci snd_hda_intel firewire_core snd_hda_codec crc_itu_t
snd_hwdep snd_pcm snd_timer ohci1394 iTCO_wdt snd soundcore sr_mod
xhci_hcd ieee1394 i2c_i801 iTCO_vendor_support pcspkr snd_page_alloc
sg r8169 wmi serio_raw ext4 jbd2 crc16 linear uhci_hcd sd_mod nouveau
ehci_hcd ttm drm_kms_helper usbcore drm agpgart i2c_algo_bit i2c_core
button dm_snapshot dm_mod xenblk cdrom xennet fan processor ata_piix
ahci pata_jmicron ata_generic libata scsi_mod thermal thermal_sys
hwmon
Oct 28 23:40:35 goku kernel: [ 4472.132037]
Oct 28 23:40:35 goku kernel: [ 4472.132037] Pid: 4641, comm: cat
Tainted: G D 2.6.34.10-0.2-xen #1 X58A-UD3R/X58A-UD3R
Oct 28 23:40:35 goku kernel: [ 4472.132037] RIP:
e030:[<ffffffffa08d118c>] [<ffffffffa08d118c>] get_files+0x6c/0x220
[pagecache]
Oct 28 23:40:35 goku kernel: [ 4472.132037] RSP: e02b:ffff8801ded93c88
EFLAGS: 00010246
Oct 28 23:40:35 goku kernel: [ 4472.132037] RAX: 8000000004000400 RBX:
ffff8801e8ea5bd0 RCX: 0000000000000001
Oct 28 23:40:35 goku kernel: [ 4472.132037] RDX: ffff8801efc8c7e8 RSI:
ffffffffa08d15c0 RDI: ffff8801e8ea4c28
Oct 28 23:40:35 goku kernel: [ 4472.132037] RBP: 0000000000000001 R08:
ffff8801eed81e00 R09: 0000000000000000
Oct 28 23:40:35 goku kernel: [ 4472.132037] R10: ffff8801e8ea5c00 R11:
0000000000000000 R12: 00000000001e6000
Oct 28 23:40:35 goku kernel: [ 4472.132037] R13: 0000000006a50000 R14:
ffff8801e8ea5b88 R15: 000003d600000004
Oct 28 23:40:35 goku kernel: [ 4472.132037] FS:
00007fcb81c3b700(0000) GS:ffff88000200b000(0000)
knlGS:0000000000000000
Oct 28 23:40:35 goku kernel: [ 4472.132037] CS: e033 DS: 0000 ES:
0000 CR0: 0000000080050033
Oct 28 23:40:35 goku kernel: [ 4472.132037] CR2: 000003d600000004 CR3:
00000001edecf000 CR4: 0000000000002660
Oct 28 23:40:35 goku kernel: [ 4472.132037] DR0: 0000000000000000 DR1:
0000000000000000 DR2: 0000000000000000
Oct 28 23:40:35 goku kernel: [ 4472.132037] DR3: 0000000000000000 DR6:
00000000ffff0ff0 DR7: 0000000000000400
Oct 28 23:40:35 goku kernel: [ 4472.132037] Process cat (pid: 4641,
threadinfo ffff8801ded92000, task ffff8801eedfa780)
Oct 28 23:40:35 goku kernel: [ 4472.132037] Stack:
Oct 28 23:40:35 goku kernel: [ 4472.132037] 0000000101baa5b4
0000000200000002 0000000000000000 ffff8801f16ffae8
Oct 28 23:40:35 goku kernel: [ 4472.132037] <0> 0000000000000000
ffff8801ee7c6500 ffff8801efd32bc0 ffff8801e45de2d0
Oct 28 23:40:35 goku kernel: [ 4472.132037] <0> ffff8801ee7c6500
ffff8801f05d80f8 ffffffff801314f0 ffffffffa08d1349
Oct 28 23:40:35 goku kernel: [ 4472.132037] Call Trace:
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffffa08d1349>]
cache_open+0x9/0x20 [pagecache]
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff8016c529>]
proc_reg_open+0xb9/0x240
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff8011060b>]
__dentry_open+0xeb/0x340
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff801206a8>]
finish_open+0xe8/0x1c0
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff80120f40>]
do_filp_open+0x1a0/0x630
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff8011214a>]
do_sys_open+0x6a/0x140
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<ffffffff80007438>]
system_call_fastpath+0x16/0x1b
Oct 28 23:40:35 goku kernel: [ 4472.132037] [<00007fcb817a7130>] 0x7fcb817a7130
Oct 28 23:40:35 goku kernel: [ 4472.132037] Code: 03 05 69 9d f9 df 4c
8b 78 18 4d 85 ff 0f 84 9c 00 00 00 41 f6 c7 01 0f 85 92 00 00 00 48
8b 00 a9 00 00 02 00 0f 85 84 00 00 00 <49> 8b 1f 48 85 db 0f 84 78 00
00 00 48 83 7b 40 00 74 71 4c 8b
Oct 28 23:40:35 goku kernel: [ 4472.132037] RIP [<ffffffffa08d118c>]
get_files+0x6c/0x220 [pagecache]
Oct 28 23:40:35 goku kernel: [ 4472.132037] RSP <ffff8801ded93c88>
Oct 28 23:40:35 goku kernel: [ 4472.132037] CR2: 000003d600000004
Oct 28 23:40:35 goku kernel: [ 4472.143966] ---[ end trace a998217447e12d1d ]---
Peace of code (simplified):
int init_module () {
unsigned long pfn;
struct inode *ino;
unsigned char * c;
struct address_space *end;
struct dentry *dentry;
int fl;
struct filepage * temp;
struct filepage *pos;
for (pfn = 0; pfn < num_physpages; pfn++) {
struct page *page;
if (!pfn_valid(pfn))
continue;
page = pfn_to_page(pfn);
if((page->mapping!=NULL) && (!PageAnon(page)) && (!PageSwapCache(page))) {
end = page->mapping;
if(end->host==NULL) { <- without this line, no hangs, but the
module returns wrong data to me...
printk(KERN_INFO "Cool... found an valid inode \n");
}
}
}
return 0;
}
Thanks in advance.
Att.
Artur Baruchi
^ permalink raw reply
* [U-Boot] HELLO!!
From: MARTINS ROMMEL @ 2011-10-30 21:17 UTC (permalink / raw)
To: u-boot
Hello friend,
Good fortune has blessed you with a name that has planted you into the center
of relevance in my life. I would respectfully request that you keep the
content of this mail confidential because of its nature and respect the
integrity of this information. First of all I'll like to introduce myself and
status, I am Mr. Martins Rommel, Cheif Operations Officer of HSBC Bank
London. I am contacting you concerning a deceased customer and a financial
portfolio of $8.5m United state dollars, which she placed under HSBC Bank
managements two years ago for turn over on her behalf.
As the Chief Operations Officer of the private banking sector, I encouraged
the deceased on her arrival to our bank on various growth of fund with prime
ratings.The favoured route in my advice to her was accessing datas on 6000
traditional stocks and bond managements. Based on my advise, attractive
margins acquired profit and interest stood at over $10m United state dollars,
this margin was not the full potential of the fund but she desired low risk
guaranteed returns on investment. Early 2009 my client asked that the money
be liquidated because of an urgent investment requiring cash payments here in
United Kingdom, and that the liquidated fund be deposited in CORPORATE
SECURITIES CO, a security consulting firm based in London who are specialist
private firm that accepts deposits from high net worth individuals and blue
chip corporations that handle valuable products and undertake transactions
that need immediate access to cash. This order was given to me in
anticipation of her arrival from United States later that week, this was the
last communication we had. Sometime that year I got a call from CORPORATE
SECURITIES CO,informing me of the in-activity of the portfolio, since I was
the only one who knew about the deposit. I immediately passed the task of
locating my client to the Internal Investigation Department of HSBC, which
now revealed that the person who suited her description was declared dead of
a Heart attack in Christian Health Care, Nevada, Dec. 30, 2009. And in line
with banking internal processes for account holders who have passed away, an
investigation was meant to be launched to contact a possible surviving NEXT
OF KIN to come forward as beneficiary of the fund but unfortunately when my
client came patronizing our services, in her bio-data form no next of kin was
listed neither was there a TESTATE. My client only used numbers and codes to
make the account she opened with us anonymous. At this juncture, I'll like to
unravel the true position of this transaction, CORPORATE SECURITIES CO. has
requested for statements of claim from me and I alone know of the existence
of the deposit, for as far as HSBC Bank is concerned the transaction with our
late client concluded when I sent the fund to the security firm, all
outstanding interactions in relation to the file are just customer service
and due process. The security firm has no single idea of what the history or
nature of the deposit is, they await instructions to release the deposit to
any party that I nominate as the beneficiary of the fund. I am prepared to
place you in a position to instruct Corporate Securities Co. to release the
deposit to you as the NEXT OF KIN.
Kindly let me know your true interest in this pending transaction so as to
ascertain the proceeds, and I assure you that I could have the deposit
released to you within few days. I implore you to discard this mail if you
find no interest in this transaction and if my offer is of no appeal to you,
please don't be vindictive and destructive just delete this message and
forget I ever contacted you.
Finally, I am sending you this mail without a measure of fear as to what the
consequences are, but I know within me that nothing ventured is nothing
gained and that success and riches never comes in a platter of gold. This is
the one truth I have learnt from my private banking clients. Do not betray my
confidence, if we can be of one accord, we should plan a meeting soon.
I await your response.
Martins A. Rommel
^ permalink raw reply
* Re: [RESEND PATCH 1/14] staging/media/as102: initial import from Abilis
From: Stefan Richter @ 2011-10-30 21:25 UTC (permalink / raw)
To: Piotr Chmura
Cc: Mauro Carvalho Chehab, Devin Heitmueller, Greg KH, Patrick Dickey,
LMML, devel, Sylwester Nawrocki
In-Reply-To: <4EADBBB7.7070802@poczta.onet.pl>
On Oct 30 Piotr Chmura wrote:
> > + * Note:
> > + * - in AS102 SNR=MER
> > + * - the SNR will be returned in linear terms, i.e. not in dB
> > + * - the accuracy equals ±2dB for a SNR range from 4dB to 30dB
> > + * - the accuracy is>2dB for SNR values outside this range
> > + */
>
> I found another issue here.
> In this comment "±" is from upper ASCII (0xF1). Should I change it into
> sth. like "+/-" in this patch (1/14) or leave it and just resend without
> "Â" (wasn't there in original patch, don't know where it came from) ?
Special characters can be used in comments, provided that they are UTF-8
encoded. In case of names of persons or companies, it is very much
desirable to preserve special characters. In case like this one on the
other hand, sticking with ASCII (the 7 bit character table) might not be
such a bad idea to keep things simple. But since you are passing on a
patch from somebody else, the right thing to do is IMO to keep the special
characters that the author chose and only make sure that the file (and
the patch mailing) are UTF-8 encoded.
--
Stefan Richter
-=====-==-== =-=- ====-
http://arcgraph.de/sr/
^ permalink raw reply
* Re: HT (Hyper Threading) aware process scheduling doesn't work as it should
From: Henrique de Moraes Holschuh @ 2011-10-30 21:26 UTC (permalink / raw)
To: Artem S. Tashkinov; +Cc: linux-kernel
In-Reply-To: <269467866.49093.1320004632156.JavaMail.mail@webmail17>
On Sun, 30 Oct 2011, Artem S. Tashkinov wrote:
> I've found out that even on Linux 3.0.8 the process scheduler doesn't correctly distributes
> the load amongst virtual CPUs. E.g. on a 4-core system (8 total virtual CPUs) the process
> scheduler often run some instances of four different tasks on the same physical CPU.
Please check how your sched_mc_power_savings and sched_smt_power_savings
tunables. Here's the doc from lesswats.org:
'sched_mc_power_savings' tunable under /sys/devices/system/cpu/ controls
the Multi-core related tunable. By default, this is set to '0' (for
optimal performance). By setting this to '1', under light load
scenarios, the process load is distributed such that all the cores in a
processor package are busy before distributing the process load to other
processor packages.
[...]
'sched_smt_power_savings' tunable under /sys/devices/system/cpu/
controls the multi-threading related tunable. By default, this is set to
'0' (for optimal performance). By setting this to '1', under light load
scenarios, the process load is distributed such that all the threads in
a core and all the cores in a processor package are busy before
distributing the process load to threads and cores, in other processor
packages.
Please make sure both are set to 0. If they were not 0 at the time you
ran your tests, please retest and report back.
You also want to make sure you _do_ have the SMT scheduler compiled in
whatever kernel you're using, just in case.
It is certainly possible that there is a bug in the scheduler, but it is
best to make sure it is not something else, first.
You may also want to refer to: http://oss.intel.com/pdfs/mclinux.pdf and
to the irqbalance and hwloc[1] utilities, since you're apparently
interested in SMP/SMT/NUMA scheduler performance.
[1] http://www.open-mpi.org/projects/hwloc/
--
"One disk to rule them all, One disk to find them. One disk to bring
them all and in the darkness grind them. In the Land of Redmond
where the shadows lie." -- The Silicon Valley Tarot
Henrique Holschuh
^ permalink raw reply
* [B.A.T.M.A.N.] [PATCH] batman-adv: report compat_version in version field in case of version mismatch
From: Marek Lindner @ 2011-10-30 21:27 UTC (permalink / raw)
To: b.a.t.m.a.n; +Cc: Marek Lindner
Reported-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Marek Lindner <lindner_marek@yahoo.de>
---
icmp_socket.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/icmp_socket.c b/icmp_socket.c
index ac3520e..defd692 100644
--- a/icmp_socket.c
+++ b/icmp_socket.c
@@ -217,7 +217,7 @@ static ssize_t bat_socket_write(struct file *file, const char __user *buff,
if (icmp_packet->version != COMPAT_VERSION) {
icmp_packet->msg_type = PARAMETER_PROBLEM;
- icmp_packet->ttl = COMPAT_VERSION;
+ icmp_packet->version = COMPAT_VERSION;
bat_socket_add_packet(socket_client, icmp_packet, packet_len);
goto free_skb;
}
--
1.7.5.4
^ permalink raw reply related
* [B.A.T.M.A.N.] [PATCH] batctl: retrieve compat version from version field in case of parameter problem
From: Marek Lindner @ 2011-10-30 21:27 UTC (permalink / raw)
To: b.a.t.m.a.n; +Cc: Marek Lindner
Reported-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Marek Lindner <lindner_marek@yahoo.de>
---
ping.c | 4 ++--
traceroute.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/ping.c b/ping.c
index 1003ab1..91b733a 100644
--- a/ping.c
+++ b/ping.c
@@ -283,8 +283,8 @@ int ping(char *mesh_iface, int argc, char **argv)
break;
case PARAMETER_PROBLEM:
printf("Error - the batman adv kernel module version (%d) differs from ours (%d)\n",
- icmp_packet_in.ttl, COMPAT_VERSION);
- printf("Please make sure to compatible versions!\n");
+ icmp_packet_in.version, COMPAT_VERSION);
+ printf("Please make sure to use compatible versions!\n");
goto out;
default:
printf("Unknown message type %d len %zd received\n", icmp_packet_in.msg_type, read_len);
diff --git a/traceroute.c b/traceroute.c
index ea43331..d120311 100644
--- a/traceroute.c
+++ b/traceroute.c
@@ -188,8 +188,8 @@ int traceroute(char *mesh_iface, int argc, char **argv)
goto out;
case PARAMETER_PROBLEM:
printf("Error - the batman adv kernel module version (%d) differs from ours (%d)\n",
- icmp_packet_in.ttl, COMPAT_VERSION);
- printf("Please make sure to compatible versions!\n");
+ icmp_packet_in.version, COMPAT_VERSION);
+ printf("Please make sure to use compatible versions!\n");
goto out;
default:
printf("Unknown message type %d len %zd received\n", icmp_packet_in.msg_type, read_len);
--
1.7.5.4
^ permalink raw reply related
* [U-Boot] [PATCH 1/2] Create a single cmd_call() function to handle command execution
From: Mike Frysinger @ 2011-10-30 21:28 UTC (permalink / raw)
To: u-boot
In-Reply-To: <CAPnjgZ2Gw8Oa6_fbFwGamgq-5iuCv=jLp-af7QG_nrAzGHZtOA@mail.gmail.com>
On Tuesday 25 October 2011 19:05:02 Simon Glass wrote:
> On Tue, Oct 25, 2011 at 6:57 AM, Mike Frysinger wrote:
> > On Mon, Oct 24, 2011 at 23:52, Simon Glass wrote:
> >> +int cmd_call(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> >> +{
> >> + int result;
> >> +
> >> + result = (cmdtp->cmd)(cmdtp, flag, argc, argv);
> >> + if (result)
> >> + debug("Command failed, result=%d", result);
> >> + return result;
> >> +}
> >
> > i don't think this goes for enough. it should integrate the "if (argc
> >
> >> cmdtp->maxargs) return cmd_usage(cmdtp);".
>
> Yes, that might turn this into a patch worth accepting on its merits.
>
> > and perhaps even the find_cmd(argv[0]) lookup ...
> > -mike
>
> How about if the commands return error codes, one of which means
> 'print usage'? Then we might remove 265 calls to cmd_usage and even
> reduce code size :-O
i'm not sure hardcoding a specific value across all commands is possible. for
most commands, we do just return -1/0/1, which probably should be normalized
into 0/1 ...
but the overhead with these calls is probably not that bad since we return via
it. so the asm isn't a matter of setting up the args, making the call, moving
the return into the right place, and then returning ... we set up the args and
jump to cmd_usage. for some arches (depending on the calling convention), we
might not even have to touch the args since the one arg is already in the
right place.
you could prototype the overhead:
- return cmd_usage(cmdtp);
+ return -500;
but i wouldn't be surprised if there was no difference, or even if this was
actually more overhead ...
-mike
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^ permalink raw reply
* [PATCH v2] net: add calxeda xgmac ethernet driver
From: Rob Herring @ 2011-10-30 21:30 UTC (permalink / raw)
To: netdev, devicetree-discuss; +Cc: joe, saeed.bishara, Rob Herring
From: Rob Herring <rob.herring@calxeda.com>
Add support for the XGMAC 10Gb ethernet device in the Calxeda Highbank
SOC.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
v2:
- use __le32 for descriptor fields and cpu_to_le32/le32_to_cpu to access
- use u32 instead of dma_addr_t for descriptor phys addresses
- improve allocation error handling for descriptor ring allocations
- converted all prints to netdev_XXX
- rebase to current Linus master
- move into drivers/net/ethernet
.../devicetree/bindings/net/calxeda-xgmac.txt | 16 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/calxeda/Kconfig | 7 +
drivers/net/ethernet/calxeda/Makefile | 2 +
drivers/net/ethernet/calxeda/xgmac.c | 1928 ++++++++++++++++++++
6 files changed, 1955 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.txt
create mode 100644 drivers/net/ethernet/calxeda/Kconfig
create mode 100644 drivers/net/ethernet/calxeda/Makefile
create mode 100644 drivers/net/ethernet/calxeda/xgmac.c
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
new file mode 100644
index 0000000..c03a7bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
@@ -0,0 +1,16 @@
+* Calxeda Highbank 10Gb XGMAC Ethernet
+
+Required properties:
+- compatible : Should be "calxeda,hb-xgmac"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
+ The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
+
+Example:
+
+ethernet@fff50000 {
+ compatible = "calxeda,hb-xgmac";
+ reg = <0xfff50000 0x1000>;
+ interrupts = <0 77 4 0 78 4 0 79 4>;
+};
+
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 6dff5a0..57e3fda 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -28,6 +28,7 @@ source "drivers/net/ethernet/cadence/Kconfig"
source "drivers/net/ethernet/adi/Kconfig"
source "drivers/net/ethernet/broadcom/Kconfig"
source "drivers/net/ethernet/brocade/Kconfig"
+source "drivers/net/ethernet/calxeda/Kconfig"
source "drivers/net/ethernet/chelsio/Kconfig"
source "drivers/net/ethernet/cirrus/Kconfig"
source "drivers/net/ethernet/cisco/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index c53ad3a..683aeb6 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_NET_ATMEL) += cadence/
obj-$(CONFIG_NET_BFIN) += adi/
obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
+obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
diff --git a/drivers/net/ethernet/calxeda/Kconfig b/drivers/net/ethernet/calxeda/Kconfig
new file mode 100644
index 0000000..a52e725
--- /dev/null
+++ b/drivers/net/ethernet/calxeda/Kconfig
@@ -0,0 +1,7 @@
+config NET_CALXEDA_XGMAC
+ tristate "Calxeda 1G/10G XGMAC Ethernet driver"
+
+ select CRC32
+ help
+ This is the driver for the XGMAC Ethernet IP block found on Calxeda
+ Highbank platforms.
diff --git a/drivers/net/ethernet/calxeda/Makefile b/drivers/net/ethernet/calxeda/Makefile
new file mode 100644
index 0000000..5057cd2
--- /dev/null
+++ b/drivers/net/ethernet/calxeda/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_NET_CALXEDA_XGMAC) += xgmac.o
+
diff --git a/drivers/net/ethernet/calxeda/xgmac.c b/drivers/net/ethernet/calxeda/xgmac.c
new file mode 100644
index 0000000..5e93c8b
--- /dev/null
+++ b/drivers/net/ethernet/calxeda/xgmac.c
@@ -0,0 +1,1928 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/circ_buf.h>
+#include <linux/interrupt.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <linux/ethtool.h>
+#include <linux/if.h>
+#include <linux/crc32.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+
+/* XGMAC Register definitions */
+#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
+#define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
+#define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
+#define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
+#define XGMAC_VERSION 0x00000020 /* Version */
+#define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
+#define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
+#define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
+#define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
+#define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
+#define XGMAC_DEBUG 0x00000038 /* Debug */
+#define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
+#define XGMAC_ADDR_HIGH(reg) (0x00000040+((reg) * 8))
+#define XGMAC_ADDR_LOW(reg) (0x00000044+((reg) * 8))
+#define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
+#define XGMAC_NUM_HASH 16
+#define XGMAC_OMR 0x00000400
+#define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
+#define XGMAC_PMT 0x00000704 /* PMT Control and Status */
+#define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
+#define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
+#define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
+#define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
+#define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
+
+/* Hardware TX Statistics Counters */
+#define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
+#define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
+#define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
+#define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
+#define XGMAC_MMC_TXBCFRAME_G 0x00000824
+#define XGMAC_MMC_TXMCFRAME_G 0x0000082C
+#define XGMAC_MMC_TXUCFRAME_GB 0x00000864
+#define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
+#define XGMAC_MMC_TXBCFRAME_GB 0x00000874
+#define XGMAC_MMC_TXUNDERFLOW 0x0000087C
+#define XGMAC_MMC_TXOCTET_G_LO 0x00000884
+#define XGMAC_MMC_TXOCTET_G_HI 0x00000888
+#define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
+#define XGMAC_MMC_TXFRAME_G_HI 0x00000890
+#define XGMAC_MMC_TXPAUSEFRAME 0x00000894
+#define XGMAC_MMC_TXVLANFRAME 0x0000089C
+
+/* Hardware RX Statistics Counters */
+#define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
+#define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
+#define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
+#define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
+#define XGMAC_MMC_RXOCTET_G_LO 0x00000910
+#define XGMAC_MMC_RXOCTET_G_HI 0x00000914
+#define XGMAC_MMC_RXBCFRAME_G 0x00000918
+#define XGMAC_MMC_RXMCFRAME_G 0x00000920
+#define XGMAC_MMC_RXCRCERR 0x00000928
+#define XGMAC_MMC_RXRUNT 0x00000930
+#define XGMAC_MMC_RXJABBER 0x00000934
+#define XGMAC_MMC_RXUCFRAME_G 0x00000970
+#define XGMAC_MMC_RXLENGTHERR 0x00000978
+#define XGMAC_MMC_RXOVERFLOW 0x00000990
+#define XGMAC_MMC_RXPAUSEFRAME 0x00000988
+#define XGMAC_MMC_RXVLANFRAME 0x00000998
+
+/* DMA Control and Status Registers */
+#define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
+#define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
+#define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
+#define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
+#define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
+#define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
+#define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
+#define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
+#define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
+#define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
+#define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
+#define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
+#define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
+
+#define XGMAC_ADDR_AE 0x80000000
+#define XGMAC_MAX_FILTER_ADDR 31
+
+/* PMT Control and Status */
+#define XGMAC_PMT_POINTER_RESET 0x80000000
+#define XGMAC_PMT_GLBL_UNICAST 0x00000200
+#define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
+#define XGMAC_PMT_MAGIC_PKT 0x00000020
+#define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
+#define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
+#define XGMAC_PMT_POWERDOWN 0x00000001
+
+#define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
+#define XGMAC_CONTROL_SPD_MASK 0x60000000
+#define XGMAC_CONTROL_SPD_1G 0x60000000
+#define XGMAC_CONTROL_SPD_2_5G 0x40000000
+#define XGMAC_CONTROL_SPD_10G 0x00000000
+#define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
+#define XGMAC_CONTROL_SARK_MASK 0x18000000
+#define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
+#define XGMAC_CONTROL_CAR_MASK 0x06000000
+#define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
+#define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
+#define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
+#define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
+#define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
+#define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
+#define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
+#define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
+#define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
+#define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
+
+/* XGMAC Frame Filter defines */
+#define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
+#define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
+#define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
+#define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
+#define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
+#define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
+#define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
+#define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
+#define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
+#define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
+#define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
+#define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
+
+/* XGMAC FLOW CTRL defines */
+#define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
+#define XGMAC_FLOW_CTRL_PT_SHIFT 16
+#define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
+#define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
+#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
+#define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
+#define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
+#define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
+#define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
+
+/* XGMAC_INT_STAT reg */
+#define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
+#define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
+
+/* DMA Bus Mode register defines */
+#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
+#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
+#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
+#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
+
+/* Programmable burst length */
+#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
+#define DMA_BUS_MODE_PBL_SHIFT 8
+#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
+#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
+#define DMA_BUS_MODE_RPBL_SHIFT 17
+#define DMA_BUS_MODE_USP 0x00800000
+#define DMA_BUS_MODE_8PBL 0x01000000
+#define DMA_BUS_MODE_AAL 0x02000000
+
+/* DMA Bus Mode register defines */
+#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
+#define DMA_BUS_PR_RATIO_SHIFT 14
+#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
+
+/* DMA Control register defines */
+#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
+#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
+#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
+
+/* DMA Normal interrupt */
+#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
+#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
+#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
+#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
+#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
+#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
+#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
+#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
+#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
+#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
+#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
+#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
+#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */
+#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
+#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
+
+#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
+ DMA_INTR_ENA_TUE)
+
+#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
+ DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
+ DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
+ DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
+ DMA_INTR_ENA_TSE)
+
+/* DMA default interrupt mask */
+#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
+
+/* DMA Status register defines */
+#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
+#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
+#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
+#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
+#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
+#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
+#define DMA_STATUS_TS_SHIFT 20
+#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
+#define DMA_STATUS_RS_SHIFT 17
+#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
+#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
+#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
+#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
+#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
+#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
+#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
+#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
+#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
+#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
+#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
+#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
+#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */
+#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
+#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
+
+/* Common MAC defines */
+#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
+#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
+
+/* XGMAC Operation Mode Register */
+#define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
+#define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
+#define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
+#define XGMAC_OMR_TTC_MASK 0x00030000
+#define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
+#define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
+#define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
+#define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
+#define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
+#define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
+#define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
+#define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
+#define XGMAC_OMR_RTC 0x00000010 /* RX Threshhold Ctrl */
+#define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
+
+/* XGMAC HW Features Register */
+#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
+
+/* XGMAC Descriptor Defines */
+#define MAX_DESC_BUF_SZ (SZ_8K - 8)
+
+#define RXDESC_EXT_STATUS 0x00000001
+#define RXDESC_CRC_ERR 0x00000002
+#define RXDESC_RX_ERR 0x00000008
+#define RXDESC_RX_WDOG 0x00000010
+#define RXDESC_FRAME_TYPE 0x00000020
+#define RXDESC_GIANT_FRAME 0x00000080
+#define RXDESC_LAST_SEG 0x00000100
+#define RXDESC_FIRST_SEG 0x00000200
+#define RXDESC_VLAN_FRAME 0x00000400
+#define RXDESC_OVERFLOW_ERR 0x00000800
+#define RXDESC_LENGTH_ERR 0x00001000
+#define RXDESC_SA_FILTER_FAIL 0x00002000
+#define RXDESC_DESCRIPTOR_ERR 0x00004000
+#define RXDESC_ERROR_SUMMARY 0x00008000
+#define RXDESC_FRAME_LEN_OFFSET 16
+#define RXDESC_FRAME_LEN_MASK 0x3fff0000
+#define RXDESC_DA_FILTER_FAIL 0x40000000
+
+#define RXDESC1_END_RING 0x00008000
+
+#define RXDESC_IP_PAYLOAD_MASK 0x00000003
+#define RXDESC_IP_PAYLOAD_UDP 0x00000001
+#define RXDESC_IP_PAYLOAD_TCP 0x00000002
+#define RXDESC_IP_PAYLOAD_ICMP 0x00000003
+#define RXDESC_IP_HEADER_ERR 0x00000008
+#define RXDESC_IP_PAYLOAD_ERR 0x00000010
+#define RXDESC_IPV4_PACKET 0x00000040
+#define RXDESC_IPV6_PACKET 0x00000080
+#define TXDESC_UNDERFLOW_ERR 0x00000001
+#define TXDESC_JABBER_TIMEOUT 0x00000002
+#define TXDESC_LOCAL_FAULT 0x00000004
+#define TXDESC_REMOTE_FAULT 0x00000008
+#define TXDESC_VLAN_FRAME 0x00000010
+#define TXDESC_FRAME_FLUSHED 0x00000020
+#define TXDESC_IP_HEADER_ERR 0x00000040
+#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
+#define TXDESC_ERROR_SUMMARY 0x00008000
+#define TXDESC_SA_CTRL_INSERT 0x00040000
+#define TXDESC_SA_CTRL_REPLACE 0x00080000
+#define TXDESC_2ND_ADDR_CHAINED 0x00100000
+#define TXDESC_END_RING 0x00200000
+#define TXDESC_CSUM_IP 0x00400000
+#define TXDESC_CSUM_IP_PAYLD 0x00800000
+#define TXDESC_CSUM_ALL 0x00C00000
+#define TXDESC_CRC_EN_REPLACE 0x01000000
+#define TXDESC_CRC_EN_APPEND 0x02000000
+#define TXDESC_DISABLE_PAD 0x04000000
+#define TXDESC_FIRST_SEG 0x10000000
+#define TXDESC_LAST_SEG 0x20000000
+#define TXDESC_INTERRUPT 0x40000000
+
+#define DESC_OWN 0x80000000
+#define DESC_BUFFER1_SZ_MASK 0x00001fff
+#define DESC_BUFFER2_SZ_MASK 0x1fff0000
+#define DESC_BUFFER2_SZ_OFFSET 16
+
+struct xgmac_dma_desc {
+ __le32 flags;
+ __le32 buf_size;
+ __le32 buf1_addr; /* Buffer 1 Address Pointer */
+ __le32 buf2_addr; /* Buffer 2 Address Pointer */
+ __le32 ext_status;
+ __le32 res[3];
+};
+
+struct xgmac_extra_stats {
+ /* Transmit errors */
+ unsigned long tx_jabber;
+ unsigned long tx_frame_flushed;
+ unsigned long tx_payload_error;
+ unsigned long tx_ip_header_error;
+ unsigned long tx_local_fault;
+ unsigned long tx_remote_fault;
+ /* Receive errors */
+ unsigned long rx_watchdog;
+ unsigned long da_rx_filter_fail;
+ unsigned long sa_rx_filter_fail;
+ unsigned long rx_missed_cntr;
+ unsigned long rx_overflow_cntr;
+ unsigned long rx_payload_error;
+ unsigned long rx_ip_header_error;
+ /* Tx/Rx IRQ errors */
+ unsigned long tx_undeflow_irq;
+ unsigned long tx_process_stopped_irq;
+ unsigned long tx_jabber_irq;
+ unsigned long rx_overflow_irq;
+ unsigned long rx_buf_unav_irq;
+ unsigned long rx_process_stopped_irq;
+ unsigned long rx_watchdog_irq;
+ unsigned long tx_early_irq;
+ unsigned long fatal_bus_error_irq;
+};
+
+struct xgmac_priv {
+ struct xgmac_dma_desc *dma_rx;
+ struct sk_buff **rx_skbuff;
+ unsigned int rx_tail;
+ unsigned int rx_head;
+
+ struct xgmac_dma_desc *dma_tx;
+ struct sk_buff **tx_skbuff;
+ unsigned int tx_head;
+ unsigned int tx_tail;
+
+ void __iomem *base;
+ struct sk_buff_head rx_recycle;
+ unsigned int dma_buf_sz;
+ dma_addr_t dma_rx_phy;
+ dma_addr_t dma_tx_phy;
+
+ struct net_device *dev;
+ struct device *device;
+ struct napi_struct napi;
+
+ struct xgmac_extra_stats xstats;
+
+ int pmt_irq;
+ char rx_pause;
+ char tx_pause;
+ int wolopts;
+};
+
+/* XGMAC Configuration Settings */
+#define MAX_MTU 9000
+#define PAUSE_TIME 0x400
+
+#define DMA_RX_RING_SZ 256
+#define DMA_TX_RING_SZ 128
+/* minimum number of free TX descriptors required to wake up TX process */
+#define TX_THRESH (DMA_TX_RING_SZ/4)
+
+/* DMA descriptor ring helpers */
+#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
+#define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s)
+#define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s)
+
+/* XGMAC Descriptor Access Helpers */
+static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
+{
+ if (buf_sz > MAX_DESC_BUF_SZ)
+ p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
+ (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
+ else
+ p->buf_size = cpu_to_le32(buf_sz);
+}
+
+static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
+{
+ u32 len = cpu_to_le32(p->flags);
+ return (len & DESC_BUFFER1_SZ_MASK) +
+ ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
+}
+
+static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
+ int buf_sz)
+{
+ struct xgmac_dma_desc *end = p + ring_size - 1;
+
+ memset(p, 0, sizeof(*p) * ring_size);
+
+ for (; p <= end; p++)
+ desc_set_buf_len(p, buf_sz);
+
+ end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
+}
+
+static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
+{
+ memset(p, 0, sizeof(*p) * ring_size);
+ p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
+}
+
+static inline int desc_get_owner(struct xgmac_dma_desc *p)
+{
+ return le32_to_cpu(p->flags) & DESC_OWN;
+}
+
+static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
+{
+ /* Clear all fields and set the owner */
+ p->flags = cpu_to_le32(DESC_OWN);
+}
+
+static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
+{
+ u32 tmpflags = le32_to_cpu(p->flags);
+ tmpflags &= TXDESC_END_RING;
+ tmpflags |= flags | DESC_OWN;
+ p->flags = cpu_to_le32(tmpflags);
+}
+
+static inline int desc_get_tx_ls(struct xgmac_dma_desc *p)
+{
+ return le32_to_cpu(p->flags) & TXDESC_LAST_SEG;
+}
+
+static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p)
+{
+ return le32_to_cpu(p->buf1_addr);
+}
+
+static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
+ u32 paddr, int len)
+{
+ p->buf1_addr = cpu_to_le32(paddr);
+ if (len > MAX_DESC_BUF_SZ)
+ p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
+}
+
+static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
+ u32 paddr, int len)
+{
+ desc_set_buf_len(p, len);
+ desc_set_buf_addr(p, paddr, len);
+}
+
+static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
+{
+ u32 data = le32_to_cpu(p->flags);
+ u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
+ if (data & RXDESC_FRAME_TYPE)
+ len -= ETH_FCS_LEN;
+
+ return len;
+}
+
+static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr)
+{
+ int timeout = 1000;
+ u32 reg = readl(ioaddr + XGMAC_OMR);
+ writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR);
+
+ while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF)
+ udelay(1);
+}
+
+static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
+{
+ struct xgmac_extra_stats *x = &priv->xstats;
+ u32 status = le32_to_cpu(p->flags);
+
+ if (!(status & TXDESC_ERROR_SUMMARY))
+ return 0;
+
+ netdev_dbg(priv->dev, "tx desc error = 0x%08x\n", status);
+ if (status & TXDESC_JABBER_TIMEOUT)
+ x->tx_jabber++;
+ if (status & TXDESC_FRAME_FLUSHED)
+ x->tx_frame_flushed++;
+ if (status & TXDESC_UNDERFLOW_ERR)
+ xgmac_dma_flush_tx_fifo(priv->base);
+ if (status & TXDESC_IP_HEADER_ERR)
+ x->tx_ip_header_error++;
+ if (status & TXDESC_LOCAL_FAULT)
+ x->tx_local_fault++;
+ if (status & TXDESC_REMOTE_FAULT)
+ x->tx_remote_fault++;
+ if (status & TXDESC_PAYLOAD_CSUM_ERR)
+ x->tx_payload_error++;
+
+ return -1;
+}
+
+static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
+{
+ struct xgmac_extra_stats *x = &priv->xstats;
+ int ret = CHECKSUM_UNNECESSARY;
+ u32 status = le32_to_cpu(p->flags);
+ u32 ext_status = le32_to_cpu(p->ext_status);
+
+ if (status & RXDESC_DA_FILTER_FAIL) {
+ netdev_dbg(priv->dev, "XGMAC RX : Dest Address filter fail\n");
+ x->da_rx_filter_fail++;
+ return -1;
+ }
+
+ /* Check if packet has checksum already */
+ if ((status & RXDESC_FRAME_TYPE) && (status & RXDESC_EXT_STATUS) &&
+ !(ext_status & RXDESC_IP_PAYLOAD_MASK))
+ ret = CHECKSUM_NONE;
+
+ netdev_dbg(priv->dev, "rx status - frame type=%d, csum = %d, ext stat %08x\n",
+ (status & RXDESC_FRAME_TYPE) ? 1 : 0, ret, ext_status);
+
+ if (!(status & RXDESC_ERROR_SUMMARY))
+ return ret;
+
+ /* Handle any errors */
+ if (status & (RXDESC_DESCRIPTOR_ERR | RXDESC_OVERFLOW_ERR |
+ RXDESC_GIANT_FRAME | RXDESC_LENGTH_ERR | RXDESC_CRC_ERR))
+ return -1;
+
+ if (status & RXDESC_EXT_STATUS) {
+ if (ext_status & RXDESC_IP_HEADER_ERR)
+ x->rx_ip_header_error++;
+ if (ext_status & RXDESC_IP_PAYLOAD_ERR)
+ x->rx_payload_error++;
+ netdev_dbg(priv->dev, "IP checksum error - stat %08x\n",
+ ext_status);
+ return -1;
+ }
+
+ return ret;
+}
+
+static inline void xgmac_mac_enable(void __iomem *ioaddr)
+{
+ u32 value = readl(ioaddr + XGMAC_CONTROL);
+ value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
+ writel(value, ioaddr + XGMAC_CONTROL);
+
+ value = readl(ioaddr + XGMAC_DMA_CONTROL);
+ value |= DMA_CONTROL_ST | DMA_CONTROL_SR;
+ writel(value, ioaddr + XGMAC_DMA_CONTROL);
+}
+
+static inline void xgmac_mac_disable(void __iomem *ioaddr)
+{
+ u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
+ value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
+ writel(value, ioaddr + XGMAC_DMA_CONTROL);
+
+ value = readl(ioaddr + XGMAC_CONTROL);
+ value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
+ writel(value, ioaddr + XGMAC_CONTROL);
+}
+
+static void xgmac_set_mac_addr(void __iomem *ioaddr, unsigned char *addr,
+ int num)
+{
+ u32 data;
+
+ data = (addr[5] << 8) | addr[4] | (num ? XGMAC_ADDR_AE : 0);
+ writel(data, ioaddr + XGMAC_ADDR_HIGH(num));
+ data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
+ writel(data, ioaddr + XGMAC_ADDR_LOW(num));
+}
+
+static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
+ int num)
+{
+ u32 hi_addr, lo_addr;
+
+ /* Read the MAC address from the hardware */
+ hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num));
+ lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num));
+
+ /* Extract the MAC address from the high and low words */
+ addr[0] = lo_addr & 0xff;
+ addr[1] = (lo_addr >> 8) & 0xff;
+ addr[2] = (lo_addr >> 16) & 0xff;
+ addr[3] = (lo_addr >> 24) & 0xff;
+ addr[4] = hi_addr & 0xff;
+ addr[5] = (hi_addr >> 8) & 0xff;
+}
+
+static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx)
+{
+ u32 reg;
+ unsigned int flow = 0;
+
+ priv->rx_pause = rx;
+ priv->tx_pause = tx;
+
+ if (rx || tx) {
+ if (rx)
+ flow |= XGMAC_FLOW_CTRL_RFE;
+ if (tx)
+ flow |= XGMAC_FLOW_CTRL_TFE;
+
+ flow |= XGMAC_FLOW_CTRL_PLT | XGMAC_FLOW_CTRL_UP;
+ flow |= (PAUSE_TIME << XGMAC_FLOW_CTRL_PT_SHIFT);
+
+ writel(flow, priv->base + XGMAC_FLOW_CTRL);
+
+ reg = readl(priv->base + XGMAC_OMR);
+ reg |= XGMAC_OMR_EFC;
+ writel(reg, priv->base + XGMAC_OMR);
+ } else {
+ writel(0, priv->base + XGMAC_FLOW_CTRL);
+
+ reg = readl(priv->base + XGMAC_OMR);
+ reg &= ~XGMAC_OMR_EFC;
+ writel(reg, priv->base + XGMAC_OMR);
+ }
+
+ return 0;
+}
+
+static void xgmac_rx_refill(struct xgmac_priv *priv)
+{
+ struct xgmac_dma_desc *p;
+ dma_addr_t paddr;
+
+ while (dma_ring_space(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ) > 1) {
+ int entry = priv->rx_head;
+ struct sk_buff *skb;
+
+ p = priv->dma_rx + entry;
+
+ if (priv->rx_skbuff[entry] != NULL)
+ continue;
+
+ skb = __skb_dequeue(&priv->rx_recycle);
+ if (skb == NULL)
+ skb = netdev_alloc_skb(priv->dev, priv->dma_buf_sz);
+ if (unlikely(skb == NULL))
+ break;
+
+ priv->rx_skbuff[entry] = skb;
+ paddr = dma_map_single(priv->device, skb->data,
+ priv->dma_buf_sz, DMA_FROM_DEVICE);
+ desc_set_buf_addr(p, paddr, priv->dma_buf_sz);
+
+ netdev_dbg(priv->dev, "rx ring: head %d, tail %d\n",
+ priv->rx_head, priv->rx_tail);
+
+ priv->rx_head = dma_ring_incr(priv->rx_head, DMA_RX_RING_SZ);
+ /* Ensure descriptor is in memory before handing to h/w */
+ wmb();
+ desc_set_rx_owner(p);
+ }
+}
+
+/**
+ * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings
+ * @dev: net device structure
+ * Description: this function initializes the DMA RX/TX descriptors
+ * and allocates the socket buffers.
+ */
+static int xgmac_dma_desc_rings_init(struct net_device *dev)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ unsigned int bfsize;
+
+ /* Set the Buffer size according to the MTU;
+ * indeed, in case of jumbo we need to bump-up the buffer sizes.
+ */
+ bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN + 64,
+ 64);
+
+ netdev_dbg(priv->dev, "mtu [%d] bfsize [%d]\n", dev->mtu, bfsize);
+
+ priv->rx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_RX_RING_SZ,
+ GFP_KERNEL);
+ if (!priv->rx_skbuff)
+ return -ENOMEM;
+
+ priv->dma_rx = dma_alloc_coherent(priv->device,
+ DMA_RX_RING_SZ *
+ sizeof(struct xgmac_dma_desc),
+ &priv->dma_rx_phy,
+ GFP_KERNEL);
+ if (!priv->dma_rx)
+ goto err_dma_rx;
+
+ priv->tx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_TX_RING_SZ,
+ GFP_KERNEL);
+ if (!priv->tx_skbuff)
+ goto err_tx_skb;
+
+ priv->dma_tx = dma_alloc_coherent(priv->device,
+ DMA_TX_RING_SZ *
+ sizeof(struct xgmac_dma_desc),
+ &priv->dma_tx_phy,
+ GFP_KERNEL);
+ if (!priv->dma_tx)
+ goto err_dma_tx;
+
+ netdev_dbg(priv->dev, "DMA desc rings: virt addr (Rx %p, "
+ "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
+ priv->dma_rx, priv->dma_tx,
+ (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
+
+ priv->rx_tail = 0;
+ priv->rx_head = 0;
+ priv->dma_buf_sz = bfsize;
+ desc_init_rx_desc(priv->dma_rx, DMA_RX_RING_SZ, priv->dma_buf_sz);
+ xgmac_rx_refill(priv);
+
+ priv->tx_tail = 0;
+ priv->tx_head = 0;
+ desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
+
+ /* The base address of the RX/TX descriptor lists must be written into
+ * DMA CSR3 and CSR4, respectively. */
+ writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
+ writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);
+
+ return 0;
+
+err_dma_tx:
+ kfree(priv->tx_skbuff);
+err_tx_skb:
+ dma_free_coherent(priv->device,
+ DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
+ priv->dma_rx, priv->dma_rx_phy);
+err_dma_rx:
+ kfree(priv->rx_skbuff);
+ return -ENOMEM;
+}
+
+static void xgmac_free_rx_skbufs(struct xgmac_priv *priv)
+{
+ int i;
+ struct xgmac_dma_desc *p;
+
+ for (i = 0; i < DMA_RX_RING_SZ; i++) {
+ if (priv->rx_skbuff[i] == NULL)
+ continue;
+
+ p = priv->dma_rx + i;
+ dma_unmap_single(priv->device, desc_get_buf_addr(p),
+ priv->dma_buf_sz, DMA_FROM_DEVICE);
+ dev_kfree_skb_any(priv->rx_skbuff[i]);
+ priv->rx_skbuff[i] = NULL;
+ }
+}
+
+static void xgmac_free_tx_skbufs(struct xgmac_priv *priv)
+{
+ int i;
+ struct xgmac_dma_desc *p;
+
+ for (i = 0; i < DMA_TX_RING_SZ; i++) {
+ if (priv->tx_skbuff[i] == NULL)
+ continue;
+
+ p = priv->dma_tx + i;
+ dma_unmap_single(priv->device, desc_get_buf_addr(p),
+ desc_get_buf_len(p), DMA_TO_DEVICE);
+ dev_kfree_skb_any(priv->tx_skbuff[i]);
+ priv->tx_skbuff[i] = NULL;
+ }
+}
+
+static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv)
+{
+ /* Release the DMA TX/RX socket buffers */
+ xgmac_free_rx_skbufs(priv);
+ xgmac_free_tx_skbufs(priv);
+
+ /* Free the consistent memory allocated for descriptor rings */
+ dma_free_coherent(priv->device,
+ DMA_TX_RING_SZ * sizeof(struct xgmac_dma_desc),
+ priv->dma_tx, priv->dma_tx_phy);
+ priv->dma_tx = NULL;
+ dma_free_coherent(priv->device,
+ DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
+ priv->dma_rx, priv->dma_rx_phy);
+ priv->dma_rx = NULL;
+
+ kfree(priv->rx_skbuff);
+ priv->rx_skbuff = NULL;
+ kfree(priv->tx_skbuff);
+ priv->tx_skbuff = NULL;
+}
+
+/**
+ * xgmac_tx:
+ * @priv: private driver structure
+ * Description: it reclaims resources after transmission completes.
+ */
+static void xgmac_tx_complete(struct xgmac_priv *priv)
+{
+ void __iomem *ioaddr = priv->base;
+
+
+ writel(DMA_STATUS_TU | DMA_STATUS_NIS, ioaddr + XGMAC_DMA_STATUS);
+
+ while (dma_ring_cnt(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ)) {
+ unsigned int entry = priv->tx_tail;
+ struct sk_buff *skb = priv->tx_skbuff[entry];
+ struct xgmac_dma_desc *p = priv->dma_tx + entry;
+
+ /* Check if the descriptor is owned by the DMA. */
+ if (desc_get_owner(p))
+ break;
+
+ /* Verify tx error by looking at the last segment */
+ if (desc_get_tx_ls(p))
+ desc_get_tx_status(priv, p);
+
+ netdev_dbg(priv->dev, "tx ring: curr %d, dirty %d\n",
+ priv->tx_head, priv->tx_tail);
+
+ dma_unmap_single(priv->device, desc_get_buf_addr(p),
+ desc_get_buf_len(p), DMA_TO_DEVICE);
+
+ if (skb) {
+ /*
+ * If there's room in the queue (limit it to size)
+ * we add this skb back into the pool,
+ * if it's the right size.
+ */
+ if ((skb_queue_len(&priv->rx_recycle) <
+ DMA_RX_RING_SZ) &&
+ skb_recycle_check(skb, priv->dma_buf_sz))
+ __skb_queue_head(&priv->rx_recycle, skb);
+ else
+ dev_kfree_skb(skb);
+
+ priv->tx_skbuff[entry] = NULL;
+ }
+
+ priv->tx_tail = dma_ring_incr(priv->tx_tail, DMA_TX_RING_SZ);
+ }
+
+ if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) >
+ TX_THRESH)
+ netif_wake_queue(priv->dev);
+}
+
+/**
+ * xgmac_tx_err:
+ * @priv: pointer to the private device structure
+ * Description: it cleans the descriptors and restarts the transmission
+ * in case of errors.
+ */
+static void xgmac_tx_err(struct xgmac_priv *priv)
+{
+ u32 reg, value, inten;
+
+ netif_stop_queue(priv->dev);
+
+ inten = readl(priv->base + XGMAC_DMA_INTR_ENA);
+ writel(0, priv->base + XGMAC_DMA_INTR_ENA);
+
+ reg = readl(priv->base + XGMAC_DMA_CONTROL);
+ writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
+ do {
+ value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000;
+ } while (value && (value != 0x600000));
+
+ xgmac_free_tx_skbufs(priv);
+ desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
+ priv->tx_tail = 0;
+ priv->tx_head = 0;
+ writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
+
+ writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS,
+ priv->base + XGMAC_DMA_STATUS);
+ writel(inten, priv->base + XGMAC_DMA_INTR_ENA);
+
+ netif_wake_queue(priv->dev);
+}
+
+static int xgmac_hw_init(struct net_device *dev)
+{
+ u32 value, ctrl;
+ int limit;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+
+ /* Save the ctrl register value */
+ ctrl = readl(ioaddr + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
+
+ /* SW reset */
+ value = DMA_BUS_MODE_SFT_RESET;
+ writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
+ limit = 15000;
+ while (limit-- &&
+ (readl(ioaddr + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
+ cpu_relax();
+ if (limit < 0)
+ return -EBUSY;
+
+ value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) |
+ (0x10 << DMA_BUS_MODE_RPBL_SHIFT) |
+ DMA_BUS_MODE_FB | DMA_BUS_MODE_ATDS | DMA_BUS_MODE_AAL;
+ writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
+
+ /* Enable interrupts */
+ writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
+ writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
+
+ /* XGMAC requires AXI bus init. This is a 'magic number' for now */
+ writel(0x000100E, ioaddr + XGMAC_DMA_AXI_BUS);
+
+ ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS |
+ XGMAC_CONTROL_CAR;
+ if (dev->features & NETIF_F_RXCSUM)
+ ctrl |= XGMAC_CONTROL_IPC;
+ writel(ctrl, ioaddr + XGMAC_CONTROL);
+
+ value = DMA_CONTROL_DFF;
+ writel(value, ioaddr + XGMAC_DMA_CONTROL);
+
+ /* Set the HW DMA mode and the COE */
+ writel(XGMAC_OMR_TSF | XGMAC_OMR_RSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA,
+ ioaddr + XGMAC_OMR);
+
+ /* Reset the MMC counters */
+ writel(1, ioaddr + XGMAC_MMC_CTRL);
+ return 0;
+}
+
+/**
+ * xgmac_open - open entry point of the driver
+ * @dev : pointer to the device structure.
+ * Description:
+ * This function is the open entry point of the driver.
+ * Return value:
+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ */
+static int xgmac_open(struct net_device *dev)
+{
+ int ret;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+
+ /* Check that the MAC address is valid. If its not, refuse
+ * to bring the device up. The user must specify an
+ * address using the following linux command:
+ * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
+ if (!is_valid_ether_addr(dev->dev_addr)) {
+ random_ether_addr(dev->dev_addr);
+ netdev_dbg(priv->dev, "generated random MAC address %pM\n",
+ dev->dev_addr);
+ }
+
+ skb_queue_head_init(&priv->rx_recycle);
+ memset(&priv->xstats, 0, sizeof(struct xgmac_extra_stats));
+
+ /* Initialize the XGMAC and descriptors */
+ xgmac_hw_init(dev);
+ xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
+ xgmac_set_flow_ctrl(priv, priv->rx_pause, priv->tx_pause);
+
+ ret = xgmac_dma_desc_rings_init(dev);
+ if (ret < 0)
+ return ret;
+
+ /* Enable the MAC Rx/Tx */
+ xgmac_mac_enable(ioaddr);
+
+ napi_enable(&priv->napi);
+ netif_start_queue(dev);
+
+ enable_irq(dev->irq);
+
+ return 0;
+}
+
+/**
+ * xgmac_release - close entry point of the driver
+ * @dev : device pointer.
+ * Description:
+ * This is the stop entry point of the driver.
+ */
+static int xgmac_release(struct net_device *dev)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+
+ netif_stop_queue(dev);
+
+ disable_irq(dev->irq);
+ napi_disable(&priv->napi);
+ skb_queue_purge(&priv->rx_recycle);
+
+ /* Disable the MAC core */
+ xgmac_mac_disable(priv->base);
+
+ /* Release and free the Rx/Tx resources */
+ xgmac_free_dma_desc_rings(priv);
+
+ return 0;
+}
+
+/**
+ * xgmac_xmit:
+ * @skb : the socket buffer
+ * @dev : device pointer
+ * Description : Tx entry point of the driver.
+ */
+static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ unsigned int entry;
+ int i;
+ int nfrags = skb_shinfo(skb)->nr_frags;
+ struct xgmac_dma_desc *desc, *first;
+ unsigned int desc_flags;
+ unsigned int len;
+ dma_addr_t paddr;
+
+ if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) <
+ (nfrags + 1)) {
+ writel(DMA_INTR_DEFAULT_MASK | DMA_INTR_ENA_TIE,
+ priv->base + XGMAC_DMA_INTR_ENA);
+ netif_stop_queue(dev);
+ return NETDEV_TX_BUSY;
+ }
+
+ desc_flags = (skb->ip_summed == CHECKSUM_PARTIAL) ?
+ TXDESC_CSUM_ALL : 0;
+ entry = priv->tx_head;
+ desc = priv->dma_tx + entry;
+ first = desc;
+
+ priv->tx_skbuff[entry] = skb;
+ len = skb_headlen(skb);
+ paddr = dma_map_single(priv->device, skb->data, len, DMA_TO_DEVICE);
+ desc_set_buf_addr_and_size(desc, paddr, len);
+
+ for (i = 0; i < nfrags; i++) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+ len = frag->size;
+ entry = dma_ring_incr(entry, DMA_TX_RING_SZ);
+ desc = priv->dma_tx + entry;
+
+ paddr = dma_map_page(priv->device, frag->page.p,
+ frag->page_offset, len, DMA_TO_DEVICE);
+ priv->tx_skbuff[entry] = NULL;
+
+ desc_set_buf_addr_and_size(desc, paddr, len);
+ if (i < (nfrags - 1))
+ desc_set_tx_owner(desc, desc_flags);
+ }
+
+ /* Interrupt on completition only for the latest segment */
+ if (desc != first)
+ desc_set_tx_owner(desc, desc_flags |
+ TXDESC_LAST_SEG | TXDESC_INTERRUPT);
+ else
+ desc_flags |= TXDESC_LAST_SEG | TXDESC_INTERRUPT;
+
+ /* Set owner on first desc last to avoid race condition */
+ wmb();
+ desc_set_tx_owner(first, desc_flags | TXDESC_FIRST_SEG);
+
+ priv->tx_head = dma_ring_incr(entry, DMA_TX_RING_SZ);
+
+ writel(1, priv->base + XGMAC_DMA_TX_POLL);
+
+ return NETDEV_TX_OK;
+}
+
+static int xgmac_rx(struct xgmac_priv *priv, int limit)
+{
+ unsigned int entry;
+ unsigned int count = 0;
+ struct xgmac_dma_desc *p;
+
+ while (count < limit) {
+ int ip_checksum;
+ struct sk_buff *skb;
+ int frame_len;
+
+ writel(DMA_STATUS_RI | DMA_STATUS_NIS,
+ priv->base + XGMAC_DMA_STATUS);
+
+ entry = priv->rx_tail;
+ p = priv->dma_rx + entry;
+ if (desc_get_owner(p))
+ break;
+
+ count++;
+ priv->rx_tail = dma_ring_incr(priv->rx_tail, DMA_RX_RING_SZ);
+
+ /* read the status of the incoming frame */
+ ip_checksum = desc_get_rx_status(priv, p);
+ if (ip_checksum < 0)
+ continue;
+
+ skb = priv->rx_skbuff[entry];
+ if (unlikely(!skb)) {
+ netdev_err(priv->dev, "Inconsistent Rx descriptor chain\n");
+ break;
+ }
+ priv->rx_skbuff[entry] = NULL;
+
+ frame_len = desc_get_rx_frame_len(p);
+ netdev_dbg(priv->dev, "RX frame size %d, COE status: %d\n",
+ frame_len, ip_checksum);
+
+ skb_put(skb, frame_len);
+ dma_unmap_single(priv->device, desc_get_buf_addr(p),
+ frame_len, DMA_FROM_DEVICE);
+
+ skb->protocol = eth_type_trans(skb, priv->dev);
+ skb->ip_summed = ip_checksum;
+ if (ip_checksum == CHECKSUM_NONE)
+ netif_receive_skb(skb);
+ else
+ napi_gro_receive(&priv->napi, skb);
+ }
+
+ xgmac_rx_refill(priv);
+
+ writel(1, priv->base + XGMAC_DMA_RX_POLL);
+
+ return count;
+}
+
+/**
+ * xgmac_poll - xgmac poll method (NAPI)
+ * @napi : pointer to the napi structure.
+ * @budget : maximum number of packets that the current CPU can receive from
+ * all interfaces.
+ * Description :
+ * This function implements the the reception process.
+ * Also it runs the TX completion thread
+ */
+static int xgmac_poll(struct napi_struct *napi, int budget)
+{
+ struct xgmac_priv *priv = container_of(napi,
+ struct xgmac_priv, napi);
+ int work_done = 0;
+
+ xgmac_tx_complete(priv);
+ work_done = xgmac_rx(priv, budget);
+
+ if (work_done < budget) {
+ napi_complete(napi);
+ writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
+ }
+ return work_done;
+}
+
+/**
+ * xgmac_tx_timeout
+ * @dev : Pointer to net device structure
+ * Description: this function is called when a packet transmission fails to
+ * complete within a reasonable tmrate. The driver will mark the error in the
+ * netdev structure and arrange for the device to be reset to a sane state
+ * in order to transmit a new packet.
+ */
+static void xgmac_tx_timeout(struct net_device *dev)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+
+ /* Clear Tx resources and restart transmitting again */
+ xgmac_tx_err(priv);
+}
+
+/**
+ * xgmac_set_rx_mode - entry point for multicast addressing
+ * @dev : pointer to the device structure
+ * Description:
+ * This function is a driver entry point which gets called by the kernel
+ * whenever multicast addresses must be enabled/disabled.
+ * Return value:
+ * void.
+ */
+static void xgmac_set_rx_mode(struct net_device *dev)
+{
+ int i;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+ unsigned int value = 0;
+ u32 mc_filter[XGMAC_NUM_HASH];
+ int reg = 1;
+ struct netdev_hw_addr *ha;
+ bool use_hash = false;
+
+ netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n",
+ netdev_mc_count(dev), netdev_uc_count(dev));
+
+ if (dev->flags & IFF_PROMISC) {
+ writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER);
+ return;
+ }
+
+ memset(mc_filter, 0, sizeof(mc_filter));
+
+ if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) {
+ use_hash = true;
+ value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF;
+ }
+ netdev_for_each_uc_addr(ha, dev) {
+ if (use_hash) {
+ u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
+
+ /* The most significant 4 bits determine the register to
+ * use (H/L) while the other 5 bits determine the bit
+ * within the register. */
+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
+ } else {
+ xgmac_set_mac_addr(ioaddr, ha->addr, reg);
+ reg++;
+ }
+ }
+
+ if (dev->flags & IFF_ALLMULTI) {
+ value |= XGMAC_FRAME_FILTER_PM;
+ goto out;
+ }
+
+ if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) {
+ use_hash = true;
+ value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF;
+ }
+ netdev_for_each_mc_addr(ha, dev) {
+ if (use_hash) {
+ u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
+
+ /* The most significant 4 bits determine the register to
+ * use (H/L) while the other 5 bits determine the bit
+ * within the register. */
+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
+ } else {
+ xgmac_set_mac_addr(ioaddr, ha->addr, reg);
+ reg++;
+ }
+ }
+
+out:
+ for (i = 0; i < XGMAC_NUM_HASH; i++)
+ writel(mc_filter[i], ioaddr + XGMAC_HASH(i));
+
+ writel(value, ioaddr + XGMAC_FRAME_FILTER);
+}
+
+/**
+ * xgmac_change_mtu - entry point to change MTU size for the device.
+ * @dev : device pointer.
+ * @new_mtu : the new MTU size for the device.
+ * Description: the Maximum Transfer Unit (MTU) is used by the network layer
+ * to drive packet transmission. Ethernet has an MTU of 1500 octets
+ * (ETH_DATA_LEN). This value can be changed with ifconfig.
+ * Return value:
+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ */
+static int xgmac_change_mtu(struct net_device *dev, int new_mtu)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ int old_mtu;
+
+ if ((new_mtu < 46) || (new_mtu > MAX_MTU)) {
+ netdev_err(priv->dev, "invalid MTU, max MTU is: %d\n", MAX_MTU);
+ return -EINVAL;
+ }
+
+ old_mtu = dev->mtu;
+ dev->mtu = new_mtu;
+
+ /* return early if the buffer sizes will not change */
+ if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
+ return 0;
+ if (old_mtu == new_mtu)
+ return 0;
+
+ /* Stop everything, get ready to change the MTU */
+ if (!netif_running(dev))
+ return 0;
+
+ /* Bring the interface down and then back up */
+ xgmac_release(dev);
+ xgmac_open(dev);
+
+ return 0;
+}
+
+static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id)
+{
+ u32 intr_status;
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+
+ intr_status = readl(ioaddr + XGMAC_INT_STAT);
+ if (intr_status & XGMAC_INT_STAT_PMT) {
+ netdev_dbg(priv->dev, "received Magic frame\n");
+ /* clear the PMT bits 5 and 6 by reading the PMT */
+ readl(ioaddr + XGMAC_PMT);
+ }
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t xgmac_interrupt(int irq, void *dev_id)
+{
+ u32 intr_status;
+ bool tx_err = false;
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ struct xgmac_extra_stats *x = &priv->xstats;
+
+ /* read the status register (CSR5) */
+ intr_status = readl(priv->base + XGMAC_DMA_STATUS);
+ intr_status &= readl(priv->base + XGMAC_DMA_INTR_ENA);
+ writel(intr_status, priv->base + XGMAC_DMA_STATUS);
+
+ /* It displays the DMA process states (CSR5 register) */
+ /* ABNORMAL interrupts */
+ if (unlikely(intr_status & DMA_STATUS_AIS)) {
+ if (intr_status & DMA_STATUS_UNF) {
+ netdev_err(priv->dev, "transmit underflow\n");
+ tx_err = true;
+ x->tx_undeflow_irq++;
+ }
+ if (intr_status & DMA_STATUS_TJT) {
+ netdev_err(priv->dev, "transmit jabber\n");
+ x->tx_jabber_irq++;
+ }
+ if (intr_status & DMA_STATUS_OVF) {
+ netdev_err(priv->dev, "recv overflow\n");
+ x->rx_overflow_irq++;
+ }
+ if (intr_status & DMA_STATUS_RU)
+ x->rx_buf_unav_irq++;
+ if (intr_status & DMA_STATUS_RPS) {
+ netdev_err(priv->dev, "receive process stopped\n");
+ x->rx_process_stopped_irq++;
+ }
+ if (intr_status & DMA_STATUS_RWT) {
+ netdev_err(priv->dev, "receive watchdog\n");
+ x->rx_watchdog_irq++;
+ }
+ if (intr_status & DMA_STATUS_ETI) {
+ netdev_err(priv->dev, "transmit early interrupt\n");
+ x->tx_early_irq++;
+ }
+ if (intr_status & DMA_STATUS_TPS) {
+ netdev_err(priv->dev, "transmit process stopped\n");
+ x->tx_process_stopped_irq++;
+ tx_err = true;
+ }
+ if (intr_status & DMA_STATUS_FBI) {
+ netdev_err(priv->dev, "fatal bus error\n");
+ x->fatal_bus_error_irq++;
+ tx_err = true;
+ }
+
+ if (tx_err)
+ xgmac_tx_err(priv);
+ }
+
+ /* TX/RX NORMAL interrupts */
+ if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU)) {
+ writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
+ napi_schedule(&priv->napi);
+ }
+
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/* Polling receive - used by NETCONSOLE and other diagnostic tools
+ * to allow network I/O with interrupts disabled. */
+static void xgmac_poll_controller(struct net_device *dev)
+{
+ disable_irq(dev->irq);
+ xgmac_interrupt(dev->irq, dev);
+ enable_irq(dev->irq);
+}
+#endif
+
+struct rtnl_link_stats64 *
+xgmac_get_stats64(struct net_device *dev,
+ struct rtnl_link_stats64 *storage)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *base = priv->base;
+ u64 count;
+
+ storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO);
+ storage->rx_packets |=
+ (u64)(readl(base + XGMAC_MMC_RXFRAME_GB_HI)) << 32;
+ storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO);
+ storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32;
+
+ storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G);
+ storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR);
+ storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR);
+ storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW);
+
+ storage->tx_packets = readl(base + XGMAC_MMC_TXFRAME_GB_LO);
+ storage->tx_packets |=
+ (u64)(readl(base + XGMAC_MMC_TXFRAME_GB_HI)) << 32;
+ storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO);
+ storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32;
+
+ count = readl(base + XGMAC_MMC_TXFRAME_G_LO);
+ count |= (__u64)(readl(base + XGMAC_MMC_TXFRAME_G_HI)) << 32;
+ storage->tx_errors = storage->tx_packets - count;
+
+ storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW);
+
+ return storage;
+}
+
+static int xgmac_set_mac_address(struct net_device *dev, void *p)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+ struct sockaddr *addr = p;
+
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EADDRNOTAVAIL;
+
+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+ xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
+
+ return 0;
+}
+
+static int xgmac_set_features(struct net_device *dev, u32 features)
+{
+ u32 ctrl;
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void __iomem *ioaddr = priv->base;
+ u32 changed = dev->features ^ features;
+
+ if (!(changed & NETIF_F_RXCSUM))
+ return 0;
+
+ ctrl = readl(ioaddr + XGMAC_CONTROL);
+ if (features & NETIF_F_RXCSUM)
+ ctrl |= XGMAC_CONTROL_IPC;
+ else
+ ctrl &= ~XGMAC_CONTROL_IPC;
+ writel(ctrl, ioaddr + XGMAC_CONTROL);
+
+ return 0;
+}
+
+static const struct net_device_ops xgmac_netdev_ops = {
+ .ndo_open = xgmac_open,
+ .ndo_start_xmit = xgmac_xmit,
+ .ndo_stop = xgmac_release,
+ .ndo_change_mtu = xgmac_change_mtu,
+ .ndo_set_rx_mode = xgmac_set_rx_mode,
+ .ndo_tx_timeout = xgmac_tx_timeout,
+ .ndo_get_stats64 = xgmac_get_stats64,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = xgmac_poll_controller,
+#endif
+ .ndo_set_mac_address = xgmac_set_mac_address,
+ .ndo_set_features = xgmac_set_features,
+};
+
+static int xgmac_ethtool_getsettings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+{
+ cmd->autoneg = 0;
+ cmd->duplex = DUPLEX_FULL;
+ ethtool_cmd_speed_set(cmd, 10000);
+ cmd->supported = SUPPORTED_10000baseT_Full;
+ cmd->advertising = 0;
+ cmd->transceiver = XCVR_INTERNAL;
+ return 0;
+}
+
+static void xgmac_get_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pause)
+{
+ struct xgmac_priv *priv = netdev_priv(netdev);
+
+ pause->rx_pause = priv->rx_pause;
+ pause->tx_pause = priv->tx_pause;
+}
+
+static int xgmac_set_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pause)
+{
+ struct xgmac_priv *priv = netdev_priv(netdev);
+ return xgmac_set_flow_ctrl(priv, pause->rx_pause, pause->tx_pause);
+}
+
+struct xgmac_stats {
+ char stat_string[ETH_GSTRING_LEN];
+ int stat_offset;
+ bool is_reg;
+};
+
+#define XGMAC_STAT(m) \
+ { #m, offsetof(struct xgmac_priv, xstats.m), false }
+#define XGMAC_HW_STAT(m, reg_offset) \
+ { #m, reg_offset, true }
+
+static const struct xgmac_stats xgmac_gstrings_stats[] = {
+ XGMAC_STAT(tx_frame_flushed),
+ XGMAC_STAT(tx_payload_error),
+ XGMAC_STAT(tx_ip_header_error),
+ XGMAC_STAT(tx_local_fault),
+ XGMAC_STAT(tx_remote_fault),
+ XGMAC_STAT(rx_watchdog),
+ XGMAC_STAT(da_rx_filter_fail),
+ XGMAC_STAT(sa_rx_filter_fail),
+ XGMAC_STAT(rx_missed_cntr),
+ XGMAC_STAT(rx_overflow_cntr),
+ XGMAC_STAT(tx_undeflow_irq),
+ XGMAC_STAT(tx_process_stopped_irq),
+ XGMAC_STAT(tx_jabber_irq),
+ XGMAC_STAT(rx_overflow_irq),
+ XGMAC_STAT(rx_buf_unav_irq),
+ XGMAC_STAT(rx_process_stopped_irq),
+ XGMAC_STAT(rx_watchdog_irq),
+ XGMAC_STAT(rx_payload_error),
+ XGMAC_STAT(rx_ip_header_error),
+ XGMAC_STAT(tx_early_irq),
+ XGMAC_STAT(fatal_bus_error_irq),
+ XGMAC_HW_STAT(tx_vlan, XGMAC_MMC_TXVLANFRAME),
+ XGMAC_HW_STAT(rx_vlan, XGMAC_MMC_RXVLANFRAME),
+ XGMAC_HW_STAT(tx_pause, XGMAC_MMC_TXPAUSEFRAME),
+ XGMAC_HW_STAT(rx_pause, XGMAC_MMC_RXPAUSEFRAME),
+};
+#define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats)
+
+static void xgmac_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *dummy,
+ u64 *data)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ void *p = priv;
+ int i;
+
+ for (i = 0; i < XGMAC_STATS_LEN; i++) {
+ if (xgmac_gstrings_stats[i].is_reg)
+ *data++ = readl(priv->base +
+ xgmac_gstrings_stats[i].stat_offset);
+ else
+ *data++ = *(u32 *)(p +
+ xgmac_gstrings_stats[i].stat_offset);
+ }
+}
+
+static int xgmac_get_sset_count(struct net_device *netdev, int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return XGMAC_STATS_LEN;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void xgmac_get_strings(struct net_device *dev, u32 stringset,
+ u8 *data)
+{
+ int i;
+ u8 *p = data;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < XGMAC_STATS_LEN; i++) {
+ memcpy(p, xgmac_gstrings_stats[i].stat_string,
+ ETH_GSTRING_LEN);
+ p += ETH_GSTRING_LEN;
+ }
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
+static void xgmac_get_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wol)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+
+ if (device_can_wakeup(priv->device)) {
+ wol->supported = WAKE_MAGIC | WAKE_UCAST;
+ wol->wolopts = priv->wolopts;
+ }
+}
+
+static int xgmac_set_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wol)
+{
+ struct xgmac_priv *priv = netdev_priv(dev);
+ u32 support = WAKE_MAGIC | WAKE_UCAST;
+
+ if (!device_can_wakeup(priv->device))
+ return -EINVAL;
+
+ if (wol->wolopts & ~support)
+ return -EINVAL;
+
+ priv->wolopts = wol->wolopts;
+
+ if (wol->wolopts) {
+ device_set_wakeup_enable(priv->device, 1);
+ enable_irq_wake(dev->irq);
+ } else {
+ device_set_wakeup_enable(priv->device, 0);
+ disable_irq_wake(dev->irq);
+ }
+
+ return 0;
+}
+
+static struct ethtool_ops xgmac_ethtool_ops = {
+ .get_settings = xgmac_ethtool_getsettings,
+ .get_link = ethtool_op_get_link,
+ .get_pauseparam = xgmac_get_pauseparam,
+ .set_pauseparam = xgmac_set_pauseparam,
+ .get_ethtool_stats = xgmac_get_ethtool_stats,
+ .get_strings = xgmac_get_strings,
+ .get_wol = xgmac_get_wol,
+ .set_wol = xgmac_set_wol,
+ .get_sset_count = xgmac_get_sset_count,
+};
+
+/**
+ * xgmac_probe
+ * @pdev: platform device pointer
+ * Description: the driver is initialized through platform_device.
+ */
+static int xgmac_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct resource *res;
+ struct net_device *ndev = NULL;
+ struct xgmac_priv *priv = NULL;
+ u32 uid;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ if (!request_mem_region(res->start, resource_size(res), pdev->name))
+ return -EBUSY;
+
+ ndev = alloc_etherdev(sizeof(struct xgmac_priv));
+ if (!ndev) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ priv = netdev_priv(ndev);
+ platform_set_drvdata(pdev, ndev);
+ ether_setup(ndev);
+ ndev->netdev_ops = &xgmac_netdev_ops;
+ SET_ETHTOOL_OPS(ndev, &xgmac_ethtool_ops);
+
+ priv->device = &pdev->dev;
+ priv->dev = ndev;
+ priv->rx_pause = 1;
+ priv->tx_pause = 1;
+
+ priv->base = ioremap(res->start, resource_size(res));
+ if (!priv->base) {
+ netdev_err(ndev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto err_io;
+ }
+
+ uid = readl(priv->base + XGMAC_VERSION);
+ netdev_info(ndev, "h/w version is 0x%x\n", uid);
+
+ ndev->irq = platform_get_irq(pdev, 0);
+ if (ndev->irq == -ENXIO) {
+ netdev_err(ndev, "No irq resource\n");
+ ret = ndev->irq;
+ goto err_irq;
+ }
+
+ ret = request_irq(ndev->irq, xgmac_interrupt, 0,
+ dev_name(&pdev->dev), ndev);
+ if (ret < 0) {
+ netdev_err(ndev, "Could not request irq %d - ret %d)\n",
+ ndev->irq, ret);
+ goto err_irq;
+ }
+ disable_irq(ndev->irq);
+
+ priv->pmt_irq = platform_get_irq(pdev, 1);
+ if (priv->pmt_irq == -ENXIO) {
+ netdev_err(ndev, "No pmt irq resource\n");
+ ret = priv->pmt_irq;
+ goto err_pmt_irq;
+ }
+
+ ret = request_irq(priv->pmt_irq, xgmac_pmt_interrupt, 0,
+ dev_name(&pdev->dev), ndev);
+ if (ret < 0) {
+ netdev_err(ndev, "Could not request irq %d - ret %d)\n",
+ priv->pmt_irq, ret);
+ goto err_pmt_irq;
+ }
+
+ device_set_wakeup_capable(&pdev->dev, 1);
+ if (device_can_wakeup(priv->device))
+ priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
+
+ ndev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA;
+ if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL)
+ ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
+ NETIF_F_RXCSUM;
+ ndev->features |= ndev->hw_features;
+ ndev->priv_flags |= IFF_UNICAST_FLT;
+
+ /* Get the MAC address */
+ xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0);
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ netdev_warn(ndev, "MAC address %pM not valid",
+ ndev->dev_addr);
+
+ netif_napi_add(ndev, &priv->napi, xgmac_poll, 64);
+ ret = register_netdev(ndev);
+ if (ret)
+ goto err_reg;
+
+ return 0;
+
+err_reg:
+ free_irq(priv->pmt_irq, ndev);
+err_pmt_irq:
+ free_irq(ndev->irq, ndev);
+err_irq:
+ iounmap(priv->base);
+err_io:
+ free_netdev(ndev);
+err_alloc:
+ release_mem_region(res->start, resource_size(res));
+ platform_set_drvdata(pdev, NULL);
+ return ret;
+}
+
+/**
+ * xgmac_dvr_remove
+ * @pdev: platform device pointer
+ * Description: this function resets the TX/RX processes, disables the MAC RX/TX
+ * changes the link status, releases the DMA descriptor rings,
+ * unregisters the MDIO bus and unmaps the allocated memory.
+ */
+static int xgmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct xgmac_priv *priv = netdev_priv(ndev);
+ struct resource *res;
+
+ xgmac_mac_disable(priv->base);
+
+ /* Free the IRQ lines */
+ free_irq(ndev->irq, ndev);
+ free_irq(priv->pmt_irq, ndev);
+
+ platform_set_drvdata(pdev, NULL);
+ unregister_netdev(ndev);
+
+ iounmap(priv->base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, resource_size(res));
+
+ free_netdev(ndev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode)
+{
+ unsigned int pmt = 0;
+
+ if (mode & WAKE_MAGIC)
+ pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT;
+ if (mode & WAKE_UCAST)
+ pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST;
+
+ writel(pmt, ioaddr + XGMAC_PMT);
+}
+
+static int xgmac_suspend(struct device *dev)
+{
+ struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
+ struct xgmac_priv *priv = netdev_priv(ndev);
+ u32 value;
+
+ if (!ndev || !netif_running(ndev))
+ return 0;
+
+ netif_device_detach(ndev);
+ napi_disable(&priv->napi);
+ writel(0, priv->base + XGMAC_DMA_INTR_ENA);
+
+ if (device_may_wakeup(priv->device)) {
+ /* Stop TX/RX DMA Only */
+ value = readl(priv->base + XGMAC_DMA_CONTROL);
+ value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
+ writel(value, priv->base + XGMAC_DMA_CONTROL);
+
+ xgmac_pmt(priv->base, priv->wolopts);
+ } else
+ xgmac_mac_disable(priv->base);
+
+ return 0;
+}
+
+static int xgmac_resume(struct device *dev)
+{
+ struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
+ struct xgmac_priv *priv = netdev_priv(ndev);
+ void __iomem *ioaddr = priv->base;
+
+ if (!netif_running(ndev))
+ return 0;
+
+ xgmac_pmt(ioaddr, 0);
+
+ /* Enable the MAC and DMA */
+ xgmac_mac_enable(ioaddr);
+ writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
+ writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
+
+ netif_device_attach(ndev);
+ napi_enable(&priv->napi);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume);
+#define XGMAC_PM_OPS (&xgmac_pm_ops)
+#else
+#define XGMAC_PM_OPS NULL
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct of_device_id xgmac_of_match[] = {
+ { .compatible = "calxeda,hb-xgmac", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xgmac_of_match);
+
+static struct platform_driver xgmac_driver = {
+ .driver = {
+ .name = "calxedaxgmac",
+ .of_match_table = xgmac_of_match,
+ },
+ .probe = xgmac_probe,
+ .remove = xgmac_remove,
+ .driver.pm = XGMAC_PM_OPS,
+};
+
+/**
+ * xgmac_init - Entry point for the driver
+ * Description: This function is the entry point for the driver.
+ */
+static int __init xgmac_init(void)
+{
+ return platform_driver_register(&xgmac_driver);
+}
+module_init(xgmac_init);
+
+/**
+ * xgmac_cleanup_module - Cleanup routine for the driver
+ * Description: This function is the cleanup routine for the driver.
+ */
+static void __exit xgmac_exit(void)
+{
+ platform_driver_unregister(&xgmac_driver);
+}
+module_exit(xgmac_exit);
+
+MODULE_AUTHOR("Calxeda, Inc.");
+MODULE_DESCRIPTION("Calxeda 10G XGMAC driver");
+MODULE_LICENSE("GPL v2");
--
1.7.5.4
^ permalink raw reply related
* [U-Boot] [PATCH 2/2] RFC: Add XON/XOFF support
From: Mike Frysinger @ 2011-10-30 21:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319514744-18697-2-git-send-email-sjg@chromium.org>
On Monday 24 October 2011 23:52:24 Simon Glass wrote:
> This is just for testing - please try it out and report back with results.
> For me it works on Minicom but not ser2net.
>
> This needs to be controlled by an environment variable, CONFIG option or
> both. We may need a way of specifying flow control on a per-device basis.
> We may need to do something special for X-modem transfers, etc. This might
> turn out to be a can of worms.
we have CONFIG_HWFLOW already, so CONFIG_SWFLOW would probably be the natural
choice. and then have the funcs be named swflow_xxx (although the hwflow code
does it via one and uses its arg to figure out what to do).
-mike
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^ permalink raw reply
* Re: [B.A.T.M.A.N.] openwrt lib/batman-adv/config.sh
From: Marek Lindner @ 2011-10-30 21:36 UTC (permalink / raw)
To: The list for a Better Approach To Mobile Ad-hoc Networking
In-Reply-To: <CAFevQmP7Qu5iMi6nHG3WJdbXFAEQej9Ro7W9aEkLxg4YhSX-wQ@mail.gmail.com>
Filippo,
> I've writed a hotplug.d script that readd interfaces that are present
> in every bat definition of batman-adv uci file when network restart or
> an interface come up.
> This script must be placed in /etc/hotplug.d/net/
>
> P.S. for Marek you don't need to split /etc/init.d/batman-adv function
> in a separate file such the previous emails.
I am little bit late with your script but finally got around looking at it.
Why don't we use the functions from /lib/batman-adv/config.sh as we previously
discussed ? Any unexpected side effects ?
Regards,
Marek
^ permalink raw reply
* Re: [msysGit] Re: What's cooking in git.git (Oct 2011, #11; Fri, 28)
From: Johannes Sixt @ 2011-10-30 21:43 UTC (permalink / raw)
To: kusmabite; +Cc: Junio C Hamano, git, msysGit
In-Reply-To: <CABPQNSYi7gJKbUb7y2hNvF9KXXyt8ShgJD8AoBhryGwAxp6ejw@mail.gmail.com>
Am 29.10.2011 17:42, schrieb Erik Faye-Lund:
> On Fri, Oct 28, 2011 at 8:12 PM, Junio C Hamano <gitster@pobox.com> wrote:
>> * ef/mingw-upload-archive (2011-10-26) 3 commits
>> - upload-archive: use start_command instead of fork
>> - compat/win32/poll.c: upgrade from upstream
>> - mingw: move poll out of sys-folder
>>
>> Are msysgit folks OK with this series (I didn't see msysgit list Cc'ed on
>> these patches)? If so let's move this forward, as the changes to the core
>> part seem solid.
>
> The msysgit list not being Cc'ed on the patches was a slip-up on my
> behalf. I believe the changes are relatively uncontroversial from an
> msysgit point of view, though. However, an ack/nack would be
> appreciated ;)
The patch series looks good and passes my tests. Therefore:
Acked-by: Johannes Sixt <j6t@kdbg.org>
-- Hannes
^ permalink raw reply
* Re: [PATCH 00/13] DocG3 fixes and write support
From: Mike Dunn @ 2011-10-30 21:43 UTC (permalink / raw)
To: Robert Jarzmik; +Cc: Marek Vasut, linux-mtd, dwmw2, linux-kernel, dedekind1
In-Reply-To: <87bosy6eab.fsf@free.fr>
Hi guys,
On 10/30/2011 02:04 AM, Robert Jarzmik wrote:
> Marek Vasut <marek.vasut@gmail.com> writes:
>
>> Hi,
>>
>> can you sum up the situation about the another (docg4) driver for us not
>> watching this too tightly? Was there any improvement/progress/... ?
> The review is underway, my comments should be dealt with, and a V2 of the patch
> should be sent. It's not in my hands.
I've been busy working on this, and should post a patch within the next few
days. Progress has been very good. I still want to run the mtd tests in the
kernel before posting the patch (except the torture test - I'm not ready to
sacrifice my development Treo), but it continues to pass the nandtest userspace
utility (part of mtd-utils) flawlessly, and a ubifs still appears to be working
well. The code is now in a much cleaner state.
> The global view we have with Mike is that chips are different, and each one
> deserves its own driver. Several registers are common, and the docg3.h could
> become common.
>
Actually, I'm open on this. My opinion is that they should share a header file
for sure, because the register set largely overlaps. To that end, my upcoming
patch will adopt Robert's register #defines, with just a few additional ones
that are G4 specific.
On the broader question of combined or separate drivers... a combined driver is
certainly doable. Each device would have to use its own set of low-level
functions, but I think there's merit in combining them because it would provide
a consistent interface with the mtd nand infrastructure code, which is rather
messy. But before that discussion can take place, the more fundamental question
of whether or not the drivers should use the nand interface needs to be
resolved. I used the nand interface when I started on the G4 driver, because it
*is* a nand device, and the legacy diskonchip.c driver was updated not long ago
from a stand-alone driver to the nand interface. I'm not knowledgeable enough
of the mtd subsystem to argue for or against the nand interface, but the end
result (once I invested the time slogging through nand_base.c) is fairly clean,
with just a couple minor hacks to get around the fact that it doesnt have a
"standard" nand controller.
Hopefully some mtd experts can share an opinion on this.
Thanks,
Mike
^ permalink raw reply
* [RFC] [PROGS] Regression tests
From: Hugo Mills @ 2011-10-30 21:44 UTC (permalink / raw)
To: linux-btrfs
Add a shell-script based test harness for performing regression tests
on btrfs tools. This is not intended as a test system for kernel
issues, but instead to put the userspace tools through their paces.
Currently implemented tests are compilation of all tools, and checking
argument counting on "btrfs sub snap". Other tests will follow.
Signed-off-by: Hugo Mills <hugo@carfax.org.uk>
---
If nobody has any major comments or objections, I'll feed this up
to Chris from the integration branch when I next send him a stack of
patches.
Hugo.
Makefile | 8 +++
test/001u.sh | 23 ++++++++++
test/002s.sh | 42 +++++++++++++++++
test/functions.sh | 128 +++++++++++++++++++++++++++++++++++++++++++++++++++++
test/run-tests | 13 +++++
5 files changed, 214 insertions(+), 0 deletions(-)
create mode 100755 test/001u.sh
create mode 100755 test/002s.sh
create mode 100644 test/functions.sh
create mode 100755 test/run-tests
diff --git a/Makefile b/Makefile
index edee1a0..24e1ce1 100644
--- a/Makefile
+++ b/Makefile
@@ -100,4 +100,12 @@ install: $(progs) install-man
$(INSTALL) $(progs) $(DESTDIR)$(bindir)
if [ -e btrfs-convert ]; then $(INSTALL) btrfs-convert $(DESTDIR)$(bindir); fi
+test: test-userspace test-root
+
+test-userspace:
+ ./test/run-tests
+
+test-root:
+ sudo ./test/run-tests
+
-include .*.d
diff --git a/test/001u.sh b/test/001u.sh
new file mode 100755
index 0000000..d2cadff
--- /dev/null
+++ b/test/001u.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+. test/functions.sh
+
+unset BTRFS_TESTS_VOLUMES
+
+announce compilation
+
+export CC=gcc-4.6
+catchclean
+make clean >/dev/null 2>&1
+
+catch make || fail Plain make failed
+#catch make dir-test || fail Failed to make dir-test
+catch make btrfs-zero-log || fail Failed to make btrfs-zero-log
+catch make btrfs-select-super || fail Failed to make btrfs-select-super
+catch make btrfstune || fail Failed to make btrfstune
+catch make btrfs-image || fail Failed to make btrfsimage
+catch make quick-test || fail Failed to make quick-test
+catch make convert || fail Failed to make btrfs-convert
+catch make ioctl-test || fail Failed to make ioctl-test
+
+summarise
diff --git a/test/002s.sh b/test/002s.sh
new file mode 100755
index 0000000..2c715b7
--- /dev/null
+++ b/test/002s.sh
@@ -0,0 +1,42 @@
+#!/bin/bash
+
+. test/functions.sh
+
+MNT=./test-mountpoint
+
+function setup() {
+ setup_mkfs btrfs-tests $MNT
+
+ ./btrfs subvolume create $MNT/source >/dev/null || return 1
+ dd if=/dev/urandom of=$MNT/source/file1 \
+ bs=1M count=1 >/dev/null 2>&1 || return 1
+}
+
+function teardown() {
+ teardown_rmfs $MNT
+}
+
+announce snapshot
+catchclean
+
+function test_ro() {
+ ./btrfs subvolume snapshot -r $MNT/source $MNT/destination
+ echo foo >$MNT/destination/foo.txt
+}
+
+# Success modes
+catch ./btrfs subvolume snapshot $MNT/source $MNT/destination \
+ || fail Failed to create rw snapshot
+catch ./btrfs subvolume snapshot -r $MNT/source $MNT/destination \
+ || fail Failed to create ro snapshot
+catch test_ro && fail Failed to use read-only flag
+
+# Failure modes
+catch ./btrfs subvolume snapshot \
+ && fail Accepted incorrect parameters \(0 params\)
+catch ./btrfs subvolume snapshot $MNT/source \
+ && fail Accepted incorrect parameters \(1 param\)
+catch ./btrfs subvolume snapshot -r $MNT/source \
+ && fail Accepted incorrect parameters \(1 param, ro\)
+
+summarise
diff --git a/test/functions.sh b/test/functions.sh
new file mode 100644
index 0000000..ca89c67
--- /dev/null
+++ b/test/functions.sh
@@ -0,0 +1,128 @@
+BTRFS_TESTS_VOLUMES="test1.img test2.img test3.img test4.img"
+TESTS_RUN=0
+TESTS_SUCCEEDED=0
+
+if [ -f .tests.conf ]; then
+ . .tests.conf
+fi
+
+function announce()
+{
+ echo --- $(basename $0) --- Testing "$@"
+}
+
+function summarise()
+{
+ echo === ${TESTS_RUN} tests run
+ echo === ${TESTS_SUCCEEDED} successes
+ echo === $((${TESTS_RUN}-${TESTS_SUCCEEDED})) failures
+}
+
+function catchclean()
+{
+ export SUITE=$(basename "$0" .sh)
+ rm -f ${SUITE}.out ${SUITE}.err
+ touch ${SUITE}.out ${SUITE}.err
+}
+
+# Internal function: set up/check the test volumes as requested
+function local_setup()
+{
+ # Set up for this test
+ VOLUMES=
+ for vol in $BTRFS_TESTS_VOLUMES; do
+ if [ ! -e $vol ]; then
+ dd if=/dev/zero of=$vol count=0 seek=4G bs=1 >/dev/null 2>&1 || return 1
+ fi
+ if [ -f $vol ]; then
+ vol=$(losetup -f --show $vol) || return 1
+ VOLUMES="$VOLUMES $vol"
+ elif [ -b $vol ]; then
+ VOLUMES="$VOLUMES $vol"
+ else
+ echo Don\'t know what to do with $vol
+ fi
+ done
+}
+
+# Internal function: destroy test volumes if we created them
+function local_teardown()
+{
+ for vol in $VOLUMES; do
+ if [ -b $vol ]; then
+ if losetup $vol >/dev/null 2>&1; then
+ file=$(losetup $vol | sed -e 's/^.* (\(.*\)).*$/\1/')
+ losetup -d $vol
+ rm $file
+ fi
+ fi
+ done
+ return 0
+}
+
+trap local_teardown EXIT
+
+function catch()
+{
+ TESTS_RUN=$((${TESTS_RUN}+1))
+
+ local_setup
+ if ! setup; then
+ teardown
+ local_teardown
+ return 1
+ fi
+
+ # Preemptively increase the success count: if we call fail, we'll
+ # decrease it again
+ TESTS_SUCCEEDED=$((${TESTS_SUCCEEDED}+1))
+
+ "$@" >>${SUITE}.out 2>>${SUITE}.err
+ rv=$?
+
+ # Undo any setup we did earlier
+ teardown
+ local_teardown
+
+ return ${rv}
+}
+
+function fail()
+{
+ echo "$@"
+ TESTS_SUCCEEDED=$((${TESTS_SUCCEEDED}-1))
+ summarise
+ exit 1
+}
+
+function setup()
+{
+ echo -n
+}
+
+function teardown()
+{
+ echo -n
+}
+
+function setup_mkfs()
+{
+ LABEL=$1
+ MNT=$2
+
+ mkdir -p $MNT
+ ./mkfs.btrfs -L $LABEL $VOLUMES >/dev/null || return 1
+ mount LABEL=$LABEL $MNT || return 1
+}
+
+function teardown_rmfs()
+{
+ MNT=$1
+
+ sleeptime=1
+ while ! umount $MNT 2>/dev/null; do
+ sleep ${sleeptime}
+ sleeptime=$((${sleeptime}+2))
+ done
+ rmdir $MNT
+}
diff --git a/test/run-tests b/test/run-tests
new file mode 100755
index 0000000..981fc22
--- /dev/null
+++ b/test/run-tests
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+testdir=$(dirname $0)
+
+if [ $UID -eq 0 ]; then
+ type=s
+else
+ type=u
+fi
+
+for test in ${testdir}/[0-9][0-9][0-9]${type}.sh; do
+ ${test}
+done
--
1.7.6.3
^ permalink raw reply related
* Re: [GIT PULL] mm: frontswap (for 3.2 window)
From: Johannes Weiner @ 2011-10-30 21:47 UTC (permalink / raw)
To: Dan Magenheimer
Cc: Pekka Enberg, Cyclonus J, Sasha Levin, Christoph Hellwig,
David Rientjes, Linus Torvalds, linux-mm, LKML, Andrew Morton,
Konrad Wilk, Jeremy Fitzhardinge, Seth Jennings, ngupta,
Chris Mason, JBeulich, Dave Hansen, Jonathan Corbet
In-Reply-To: <b86860d2-3aac-4edd-b460-bd95cb1103e6@default>
On Fri, Oct 28, 2011 at 10:07:12AM -0700, Dan Magenheimer wrote:
>
> > From: Johannes Weiner [mailto:jweiner@redhat.com]
> > Subject: Re: [GIT PULL] mm: frontswap (for 3.2 window)
> >
> > On Fri, Oct 28, 2011 at 06:36:03PM +0300, Pekka Enberg wrote:
> > > On Fri, Oct 28, 2011 at 6:21 PM, Dan Magenheimer
> > > <dan.magenheimer@oracle.com> wrote:
> > > Looking at your patches, there's no trace that anyone outside your own
> > > development team even looked at the patches. Why do you feel that it's
> > > OK to ask Linus to pull them?
> >
> > People did look at it.
> >
> > In my case, the handwavy benefits did not convince me. The handwavy
> > 'this is useful' from just more people of the same company does not
> > help, either.
> >
> > I want to see a usecase that tangibly gains from this, not just more
> > marketing material. Then we can talk about boring infrastructure and
> > adding hooks to the VM.
> >
> > Convincing the development community of the problem you are trying to
> > solve is the undocumented part of the process you fail to follow.
>
> Hi Johannes --
>
> First, there are several companies and several unaffiliated kernel
> developers contributing here, building on top of frontswap. I happen
> to be spearheading it, and my company is backing me up. (It
> might be more appropriate to note that much of the resistance comes
> from people of your company... but please let's keep our open-source
> developer hats on and have a technical discussion rather than one
> which pleases our respective corporate overlords.)
I didn't mean to start a mud fight about this, I only mentioned the
part about your company because I already assume it sees value in tmem
- it probably wouldn't fund its development otherwise. I just tend to
not care too much about Acks from the same company as the patch itself
and I believe other people do the same.
> Second, have you read http://lwn.net/Articles/454795/ ?
> If not, please do. If yes, please explain what you don't
> see as convincing or tangible or documented. All of this
> exists today as working publicly available code... it's
> not marketing material.
I remember answering this to you in private already some time ago when
discussing frontswap.
You keep proposing a bridge and I keep asking for proof that this is
not a bridge to nowhere. Unless that question is answered, I am not
interested in discussing the bridge's design.
According to the LWN article, there are the following backends:
1. Zcache: allow swapping into compressed memory
This sets aside a portion of memory which the kernel will swap
compressed pages into upon pressure. Now, obviously, reserving memory
from the system for this increases the pressure in the first place,
eating away on what space we have for anonymous memory and page cache.
Do you auto-size that region depending on workload?
If so, how? If not, is it documented how to size it manually?
Where are the performance numbers for various workloads, including
both those that benefit from every bit of page cache and those that
would fit into memory without zcache occupying space?
However, looking at the zcache code, it seems it wants to allocate
storage pages only when already trying to swap out. Are you sure this
works in reality?
2. RAMster: allow swapping between machines in a cluster
Are there people using it? It, too, sounds like a good idea but I
don't see any proof it actually works as intended.
3. Xen: allow guests to swap into the host.
The article mentions that there is code to put the guests under
pressure and let them swap to host memory when the pressure is too
high. This sounds useful.
Where is the code that controls the amount of pressure put on the
guests?
Where are the performance numbers? Surely you can construct a case
where the initial machine sizes are not quite right and then collect
data that demonstrates the machines are rebalancing as expected?
4. kvm: same as Xen
Apart from the questions that already apply to Xen, I remember KVM
people in particular complaining about the synchroneous single-page
interface that results in a hypercall per swapped page. What happened
to this concern?
---
I would really appreciate if you could pick one of those backends and
present them as a real and practical solution to real and practical
problems. With documentation on configuration and performance data of
real workloads. We can discuss implementation details like how memory
is exchanged between source and destination when we come to it.
I am not asking for just more code that uses your interface, I want to
know the real value for real people of the combination of all that
stuff. With proof, not just explanations of how it's supposed to
work.
Until you can accept that, please include
Nacked-by: Johannes Weiner <hannes@cmpxchg.org>
on all further stand-alone submissions of tmem core code and/or hooks
in the VM. Thanks.
--
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