* Re: [PATCH libdrm] xf86drm: Parse the separate files to retrieve the vendor/device info
From: Mauro Santos @ 2016-11-08 18:08 UTC (permalink / raw)
To: Emil Velikov; +Cc: Michel Dänzer, ML dri-devel
In-Reply-To: <CACvgo51Q=xGYtuKPY0crhqiMPj_dH_ZOXAJ-u+A95SQvhhN9HA@mail.gmail.com>
On 08-11-2016 17:13, Emil Velikov wrote:
> On 8 November 2016 at 16:57, Mauro Santos <registo.mailling@gmail.com> wrote:
>> On 08-11-2016 15:57, Emil Velikov wrote:
>>> On 8 November 2016 at 15:27, Mauro Santos <registo.mailling@gmail.com> wrote:
>>>> On 08-11-2016 15:00, Emil Velikov wrote:
>>>>> On 8 November 2016 at 13:38, Mauro Santos <registo.mailling@gmail.com> wrote:
>>>>>> On 08-11-2016 11:06, Emil Velikov wrote:
>>>>>>> On 1 November 2016 at 18:47, Mauro Santos <registo.mailling@gmail.com> wrote:
>>>>>>>> On 01-11-2016 18:13, Emil Velikov wrote:
>>>>>>>>> From: Emil Velikov <emil.velikov@collabora.com>
>>>>>>>>>
>>>>>>>>> Parsing config sysfs file wakes up the device. The latter of which may
>>>>>>>>> be slow and isn't required to begin with.
>>>>>>>>>
>>>>>>>>> Reading through config is/was required since the revision is not
>>>>>>>>> available by other means, although with a kernel patch in the way we can
>>>>>>>>> 'cheat' temporarily.
>>>>>>>>>
>>>>>>>>> That should be fine, since no open-source project has ever used the
>>>>>>>>> value.
>>>>>>>>>
>>>>>>>>> Cc: Michel Dänzer <michel.daenzer@amd.com>
>>>>>>>>> Cc: Mauro Santos <registo.mailling@gmail.com>
>>>>>>>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98502
>>>>>>>>> Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
>>>>>>>>> ---
>>>>>>>>> Mauro can you apply this against libdrm and rebuild it. You do _not_
>>>>>>>>> need to rebuild mesa afterwords.
>>>>>>>>>
>>>>>>>>> Thanks
>>>>>>>>> ---
>>>>>>>>> xf86drm.c | 50 +++++++++++++++++++++++++++++++++++---------------
>>>>>>>>> 1 file changed, 35 insertions(+), 15 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/xf86drm.c b/xf86drm.c
>>>>>>>>> index 52add5e..5a5100c 100644
>>>>>>>>> --- a/xf86drm.c
>>>>>>>>> +++ b/xf86drm.c
>>>>>>>>> @@ -2950,25 +2950,45 @@ static int drmParsePciDeviceInfo(const char *d_name,
>>>>>>>>> drmPciDeviceInfoPtr device)
>>>>>>>>> {
>>>>>>>>> #ifdef __linux__
>>>>>>>>> +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
>>>>>>>>> + static const char *attrs[] = {
>>>>>>>>> + "revision", /* XXX: make sure it's always first, see note below */
>>>>>>>>> + "vendor",
>>>>>>>>> + "device",
>>>>>>>>> + "subsystem_vendor",
>>>>>>>>> + "subsystem_device",
>>>>>>>>> + };
>>>>>>>>> char path[PATH_MAX + 1];
>>>>>>>>> - unsigned char config[64];
>>>>>>>>> - int fd, ret;
>>>>>>>>> + unsigned int data[ARRAY_SIZE(attrs)];
>>>>>>>>> + FILE *fp;
>>>>>>>>> + int ret;
>>>>>>>>>
>>>>>>>>> - snprintf(path, PATH_MAX, "/sys/class/drm/%s/device/config", d_name);
>>>>>>>>> - fd = open(path, O_RDONLY);
>>>>>>>>> - if (fd < 0)
>>>>>>>>> - return -errno;
>>>>>>>>> + for (unsigned i = 0; i < ARRAY_SIZE(attrs); i++) {
>>>>>>>>> + snprintf(path, PATH_MAX, "/sys/class/drm/%s/device/%s",
>>>>>>>>> + d_name, attrs[i]);
>>>>>>>>> + fp = fopen(path, "r");
>>>>>>>>> + if (!fp) {
>>>>>>>>> + /* Note: First we check the revision, since older kernels
>>>>>>>>> + * may not have it. Default to zero in such cases. */
>>>>>>>>> + if (i == 0) {
>>>>>>>>> + data[i] = 0;
>>>>>>>>> + continue;
>>>>>>>>> + }
>>>>>>>>> + return -errno;
>>>>>>>>> + }
>>>>>>>>>
>>>>>>>>> - ret = read(fd, config, sizeof(config));
>>>>>>>>> - close(fd);
>>>>>>>>> - if (ret < 0)
>>>>>>>>> - return -errno;
>>>>>>>>> + ret = fscanf(fp, "%x", &data[i]);
>>>>>>>>> + fclose(fp);
>>>>>>>>> + if (ret != 1)
>>>>>>>>> + return -errno;
>>>>>>>>> +
>>>>>>>>> + }
>>>>>>>>>
>>>>>>>>> - device->vendor_id = config[0] | (config[1] << 8);
>>>>>>>>> - device->device_id = config[2] | (config[3] << 8);
>>>>>>>>> - device->revision_id = config[8];
>>>>>>>>> - device->subvendor_id = config[44] | (config[45] << 8);
>>>>>>>>> - device->subdevice_id = config[46] | (config[47] << 8);
>>>>>>>>> + device->revision_id = data[0] & 0xff;
>>>>>>>>> + device->vendor_id = data[1] & 0xffff;
>>>>>>>>> + device->device_id = data[2] & 0xffff;
>>>>>>>>> + device->subvendor_id = data[3] & 0xffff;
>>>>>>>>> + device->subdevice_id = data[4] & 0xffff;
>>>>>>>>>
>>>>>>>>> return 0;
>>>>>>>>> #else
>>>>>>>>>
>>>>>>>>
>>>>>>>> I have applied this against libdrm 2.4.71 and I don't see any delays
>>>>>>>> when starting firefox/chromium/thunderbird/glxgears.
>>>>>>>>
>>>>>>>> There is also no indication in dmesg that the dGPU is being
>>>>>>>> reinitialized when starting the programs where I've detected the problem.
>>>>>>>>
>>>>>>> Thanks Mauro. Can you give this a try alongside the kernel fix [1] ?
>>>>>>> I'd love to get the latter merged soon(ish).
>>>>>>> Independent of the kernel side, I might need to go another way for
>>>>>>> libdrm/mesa so I'll CC you on future patches.
>>>>>>>
>>>>>>> Your help is greatly appreciated !
>>>>>>>
>>>>>>> Thanks
>>>>>>> Emil
>>>>>>>
>>>>>>> [1] http://patchwork.ozlabs.org/patch/689975/
>>>>>>>
>>>>>>
>>>>>> I have applied the patch on top of kernel 4.8.6 and I'm using the libdrm
>>>>>> with the patch you sent me previously.
>>>>>>
>>>>>> With this patch things still seem work fine, I don't see any of the
>>>>>> problems I've seen before, but I don't know how to confirm that the
>>>>>> value from sysfs is now being used by libdrm instead of defaulting to zero.
>>>>>>
>>>>> Grr my bad. $libdrm_builddir/tests/drmdevice should do it. You might
>>>>> need to explicitly build it (cd tests && make drmdevice)
>>>>>
>>>>
>>>> When running drmdevice as my user it still wakes up the dGPU. The
>>>> correct device revisions are being reported by I suppose that is not
>>>> being read from sysfs.
>>>>
>>> Based on the output you're spot on - doesn't seem like the revision
>>> sysfs gets used. Most likely drmdevice is linked/using the pre-patch
>>> (system/local?) libdrm.so ?
>>>
>>
>> I've been using the patched libdrm.so ever since you sent me the patch
>> for libdrm and I've recompiled libdrm today to get drmdevice so both the
>> system's and in-tree libdrm.so should have the patch. Arch's PKGBUILD
>> does have a non default --enable-udev configure parameter, could that
>> make any difference?
>>
> The --enable-udev does not make any difference.
>
> The rest does not make sense - the exact same functions are used by
> drmdevice and mesa, yet it two different results are produced :-\
> Or something very funny is happening and reading the device/vendor
> file does _not_ wake the device, while the revision one does.
>
If I do 'cat revision' for the dGPU it does not wake up the device so I
guess we can scratch that.
> Can you pull out the kernel patch and check drmdevice/dmesg with
> patched libdrm ?
>
Same behavior as before, both versions of drmdevice wake up the dGPU.
Could it be that some other lib called by drmdevice and not called by
other programs is doing something to wake up the dGPU?
> Thanks
> Emil
>
--
Mauro Santos
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [U-Boot] [PATCH v2] armv8: fsl-layerscape: Add Readme for deploy QSPI image
From: york sun @ 2016-11-08 18:09 UTC (permalink / raw)
To: u-boot
In-Reply-To: <DB6PR0401MB2407D7B0F43151234AD59EE889A60@DB6PR0401MB2407.eurprd04.prod.outlook.com>
On 11/07/2016 09:44 PM, Yao Yuan wrote:
> On 11/08/2016 12:46 PM, York Sun wrote:
>> On 11/07/2016 07:52 PM, Yuan Yao wrote:
>>> From: Yuan Yao <yao.yuan@nxp.com>
>>>
>>> Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
>>> ---
>>> Changed in v2:
>>> Move the readme for QSPI deploy out of only for ls2080aqds.
>>> ---
>>> .../arm/cpu/armv8/fsl-layerscape/doc/README.deploy | 44
>>> ++++++++++++++++++++++
>>> 1 file changed, 44 insertions(+)
>>> create mode 100644
>>> arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
>>>
>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
>>> b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
>>> new file mode 100644
>>> index 0000000..25813b3
>>> --- /dev/null
>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
>>> @@ -0,0 +1,44 @@
>>> +Boot source support Overview
>>> +-------------------
>>> + 1. LS1043A
>>> + LS1043AQDS:QSPI, SD, NOR, NAND
>>> + LS1043ARDB:SD, NOR, NAND
>>> + 2. LS2080A
>>> + LS2080AQDS:QSPI, SD, NOR, NAND
>>> + LS2080ARDB:NOR, NAND
>>> + 3. LS1012A
>>> + LS1012AQDS:QSPI
>>> + LS1012ARDB:QSPI
>>> + 4. LS1046A
>>> + LS1046AQDS:QSPI, SD, NOR, NAND
>>> + LS1046ARDB:QSPI, SD
>>> +
>>
>> If you plan to add all SD/NAND/QSPI into this document, it is OK to call it
>> README.deploy. Otherwise it may be better to name as README.qspi.
>>
> I'm not be familiar with SD/NAND boot. So should I rename as README.qspi?
> Or just keep it but waiting for some others to add SD/NAND boot in another patch?
>
We already have NAND boot explained in other document. Stick with the
procedure you are trying to explain. Keep it simple and we can expand it
when necessary.
York
^ permalink raw reply
* Re: [PATCH] x86/MCE: Remove MCP_TIMESTAMP
From: Borislav Petkov @ 2016-11-08 18:09 UTC (permalink / raw)
To: Luck, Tony; +Cc: linux-edac, X86 ML, LKML
In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F3A22728C@ORSMSX114.amr.corp.intel.com>
On Mon, Nov 07, 2016 at 06:37:50PM +0000, Luck, Tony wrote:
> Also to me ... and I think that's what used to happen (or at least was the
> intent).
How's that?
This still preserves the precise TSC timestamp in intel_threshold_interrupt().
---
From: Borislav Petkov <bp@suse.de>
Date: Tue, 8 Nov 2016 16:20:05 +0100
Subject: [PATCH] x86/MCE: Correct TSC timestamping of error records
We did have logic in the MCE code which would TSC-timestamp an error
record only when it is exact - i.e., it wasn't detected by polling. This
isn't the case anymore. So let's fix that:
We have a TSC timestamp in the error record only when it has been a
precise detection, i.e., either in the #MC handler or in one of the
interrupt handlers (thresholding, deferred, ...).
All other error records still have mce.time which contains the wall time
in order to be able to place the error record in time approximately.
Also, this fixes another bug where machine_check_poll() would clear
mce.tsc unconditionally even if we requested precise MCP_TIMESTAMP
logging.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Tony Luck <tony.luck@intel.com>
---
arch/x86/kernel/cpu/mcheck/mce.c | 3 +--
arch/x86/kernel/cpu/mcheck/mce_intel.c | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 4ca00474804b..b7a976d657f3 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -713,7 +713,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
m.misc = 0;
m.addr = 0;
m.bank = i;
- m.tsc = 0;
barrier();
m.status = mce_rdmsrl(msr_ops.status(i));
@@ -1394,7 +1393,7 @@ static void mce_timer_fn(unsigned long data)
iv = __this_cpu_read(mce_next_interval);
if (mce_available(this_cpu_ptr(&cpu_info))) {
- machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks));
+ machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
if (mce_intel_cmci_poll()) {
iv = mce_adjust_timer(iv);
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 1defb8ea882c..be0b2fad47c5 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -130,7 +130,7 @@ bool mce_intel_cmci_poll(void)
* Reset the counter if we've logged an error in the last poll
* during the storm.
*/
- if (machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned)))
+ if (machine_check_poll(0, this_cpu_ptr(&mce_banks_owned)))
this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
else
this_cpu_dec(cmci_backoff_cnt);
@@ -342,7 +342,7 @@ void cmci_recheck(void)
return;
local_irq_save(flags);
- machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
+ machine_check_poll(0, this_cpu_ptr(&mce_banks_owned));
local_irq_restore(flags);
}
--
2.10.0
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply related
* Re: auto stop of scrubbing and deep scrubbing while backfilling or recovering
From: Wido den Hollander @ 2016-11-08 18:09 UTC (permalink / raw)
To: Sage Weil; +Cc: Stefan Priebe - Profihost AG, ceph-devel
In-Reply-To: <alpine.DEB.2.11.1611081415550.32512@piezo.us.to>
> Op 8 november 2016 om 15:19 schreef Sage Weil <sage@newdream.net>:
>
>
> On Tue, 8 Nov 2016, Wido den Hollander wrote:
> > > Op 8 november 2016 om 9:35 schreef Stefan Priebe - Profihost AG <s.priebe@profihost.ag>:
> > >
> > >
> > > Hello,
> > >
> > > i'm wondering if anybody has already thought about automatically
> > > stopping srub and deep-scrub in case of backfilling or recovering. I've
> > > seen several situations where scrubbing massivly raises the latency
> > > while doing backfilling or recovering.
> > >
> >
> > Seems like a sane change to me, but maybe a dev has a better option. I
> > don't think a stop is easy, but a 'noscrub' flag could be set inside the
> > OSD.
> >
> > Maybe a config option: osd_scrub_during_recovery
> >
> > Defaults to true, but can be set to false by the admin.
> >
> > Before a scrub starts the OSD will check if there is recovery /
> > backfilling active on the OSD and if so it will not initiate the scrub.
>
> Yeah, it seems reasonable. I think there are two basic options:
>
> - Disable scrubbing locally on each OSD if it has scrubbing PGs. Two
> unrelated OSDs would be free to scrub and backfill at the same time.
>
> - Disable scrubbing globally if any pgs are backfilling. The reasoning
> here is that if backfilling is increasing the latency on some PGs, we
> don't want to increase the latency on others (by scrubbing) too.
>
> The other consideration is that if backfil is happening it probably
> doesn't mean we want to prevent scrubbing indefinitely. Instead, I'd
> suggest increasing the scrub intervals by some factor (e.g., 2x).
>
> The first option would probably be a change in the scrub scheduling in
> the OSD.
>
I would go for the first one. Imagine a large cluster where one backfill is busy, that would otherwise halt all scrubs while only a few OSDs are involved.
Option one isn't that hard to implement either I think.
Wido
> The latter could be accomplished by having the mon publish a scrub
> interval scaling factor in the OSDMap...
>
> sage
> --
> To unsubscribe from this list: send the line "unsubscribe ceph-devel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 1/2] arm64: Add hypervisor safe helper for checking constant capabilities
From: Will Deacon @ 2016-11-08 18:11 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: Robert Ritcher, ard.biesheuvel, marc.zyngier, catalin.marinas,
linux-kernel, Tirumalesh Chalamarla, kvmarm, linux-arm-kernel
In-Reply-To: <1478613381-5718-2-git-send-email-suzuki.poulose@arm.com>
On Tue, Nov 08, 2016 at 01:56:20PM +0000, Suzuki K Poulose wrote:
> The hypervisor may not have full access to the kernel data structures
> and hence cannot safely use cpus_have_cap() helper for checking the
> system capability. Add a safe helper for hypervisors to check a constant
> system capability, which *doesn't* fall back to checking the bitmap
> maintained by the kernel. With this, make the cpus_have_cap() only
> check the bitmask and force constant cap checks to use the new API
> for quicker checks.
>
> Cc: Robert Ritcher <rritcher@cavium.com>
> Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 19 ++++++++++++-------
> arch/arm64/kernel/cpufeature.c | 2 +-
> arch/arm64/kernel/process.c | 2 +-
> drivers/irqchip/irq-gic-v3.c | 13 +------------
It might be worth having the GIC changes as a separate patch, but either
way:
Reviewed-by: Will Deacon <will.deacon@arm.com>
Will
^ permalink raw reply
* [PATCH v3 1/2] arm64: Add hypervisor safe helper for checking constant capabilities
From: Will Deacon @ 2016-11-08 18:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478613381-5718-2-git-send-email-suzuki.poulose@arm.com>
On Tue, Nov 08, 2016 at 01:56:20PM +0000, Suzuki K Poulose wrote:
> The hypervisor may not have full access to the kernel data structures
> and hence cannot safely use cpus_have_cap() helper for checking the
> system capability. Add a safe helper for hypervisors to check a constant
> system capability, which *doesn't* fall back to checking the bitmap
> maintained by the kernel. With this, make the cpus_have_cap() only
> check the bitmask and force constant cap checks to use the new API
> for quicker checks.
>
> Cc: Robert Ritcher <rritcher@cavium.com>
> Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/include/asm/cpufeature.h | 19 ++++++++++++-------
> arch/arm64/kernel/cpufeature.c | 2 +-
> arch/arm64/kernel/process.c | 2 +-
> drivers/irqchip/irq-gic-v3.c | 13 +------------
It might be worth having the GIC changes as a separate patch, but either
way:
Reviewed-by: Will Deacon <will.deacon@arm.com>
Will
^ permalink raw reply
* [U-Boot] [PATCH] armv8: QSPI: Add AHB bus 16MB+ size support
From: york sun @ 2016-11-08 18:11 UTC (permalink / raw)
To: u-boot
In-Reply-To: <DB6PR0401MB2407DAE42C7A0D03C582431989A60@DB6PR0401MB2407.eurprd04.prod.outlook.com>
On 11/07/2016 10:03 PM, Yao Yuan wrote:
> On 11/08/2016 02:27 AM, York Sun wrote:
>> On 10/25/2016 07:10 PM, Yuan Yao wrote:
>>> From: Yuan Yao <yao.yuan@nxp.com>
>>>
>>> The default configuration for QSPI AHB bus can't support 16MB+.
>>> But some flash on NXP layerscape board are more than 16MB.
>>
>> So what do you do?
>>
>> Is this an erratum workaround? If yes, please refer the erratum number.
>
> Hi York,
>
> I think It's not an erratum maybe it's better to call it new feature.
>
> As a default configuration for QSPI AHB, the address size is 3-bytes.
> It has a good compatibility for QSPI boot for different SPI-NOR flash.
>
> But if the address size is only 3-bytes, the QSPI can't access to the data that more than 16M+.
>
> So we can update the default configuration for QSPI AHB in uboot to use 4-bytes address.
> So that QSPI can access to 16M+ size by AHB bus.
>
I cannot figure this out from the change you proposed, or from the
commit message. Maybe adding some comments next to the code? Those magic
numbers are better explained.
York
^ permalink raw reply
* [Qemu-devel] [PULL 0/3] Block patches
From: Stefan Hajnoczi @ 2016-11-08 18:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Stefan Hajnoczi
The following changes since commit 207faf24c58859f5240f66bf6decc33b87a1776e:
Merge remote-tracking branch 'pm215/tags/pull-target-arm-20161107' into staging (2016-11-07 14:02:15 +0000)
are available in the git repository at:
git://github.com/stefanha/qemu.git tags/block-pull-request
for you to fetch changes up to 35dd66e23ce96283723de58e10d2877ae2be4a1b:
aio-posix: simplify aio_epoll_update (2016-11-08 17:09:14 +0000)
----------------------------------------------------------------
----------------------------------------------------------------
Kevin Wolf (1):
block: Don't mark node clean after failed flush
Paolo Bonzini (2):
aio-posix: avoid NULL pointer dereference in aio_epoll_update
aio-posix: simplify aio_epoll_update
aio-posix.c | 53 +++++++++++++++++---------------------
block/io.c | 4 ++-
tests/qemu-iotests/026.out | 22 ++++++++++++++++
tests/qemu-iotests/026.out.nocache | 22 ++++++++++++++++
tests/qemu-iotests/071.out | 2 ++
5 files changed, 73 insertions(+), 30 deletions(-)
--
2.7.4
^ permalink raw reply
* [Qemu-devel] [PULL 2/3] aio-posix: avoid NULL pointer dereference in aio_epoll_update
From: Stefan Hajnoczi @ 2016-11-08 18:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Paolo Bonzini, Stefan Hajnoczi
In-Reply-To: <1478628762-31050-1-git-send-email-stefanha@redhat.com>
From: Paolo Bonzini <pbonzini@redhat.com>
aio_epoll_update dereferences parameter "node", but it could have been NULL
if deleting an fd handler that was not registered in the first place.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Fam Zheng <famz@redhat.com>
Message-id: 20161108135524.25927-2-pbonzini@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
---
aio-posix.c | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/aio-posix.c b/aio-posix.c
index 4ef34dd..304b016 100644
--- a/aio-posix.c
+++ b/aio-posix.c
@@ -217,21 +217,23 @@ void aio_set_fd_handler(AioContext *ctx,
/* Are we deleting the fd handler? */
if (!io_read && !io_write) {
- if (node) {
- g_source_remove_poll(&ctx->source, &node->pfd);
+ if (node == NULL) {
+ return;
+ }
- /* If the lock is held, just mark the node as deleted */
- if (ctx->walking_handlers) {
- node->deleted = 1;
- node->pfd.revents = 0;
- } else {
- /* Otherwise, delete it for real. We can't just mark it as
- * deleted because deleted nodes are only cleaned up after
- * releasing the walking_handlers lock.
- */
- QLIST_REMOVE(node, node);
- deleted = true;
- }
+ g_source_remove_poll(&ctx->source, &node->pfd);
+
+ /* If the lock is held, just mark the node as deleted */
+ if (ctx->walking_handlers) {
+ node->deleted = 1;
+ node->pfd.revents = 0;
+ } else {
+ /* Otherwise, delete it for real. We can't just mark it as
+ * deleted because deleted nodes are only cleaned up after
+ * releasing the walking_handlers lock.
+ */
+ QLIST_REMOVE(node, node);
+ deleted = true;
}
} else {
if (node == NULL) {
--
2.7.4
^ permalink raw reply related
* [Qemu-devel] [PULL 1/3] block: Don't mark node clean after failed flush
From: Stefan Hajnoczi @ 2016-11-08 18:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Kevin Wolf, qemu-stable, Stefan Hajnoczi
In-Reply-To: <1478628762-31050-1-git-send-email-stefanha@redhat.com>
From: Kevin Wolf <kwolf@redhat.com>
Commit 3ff2f67a changed bdrv_co_flush() so that no flush is issues if
the image hasn't been dirtied since the last flush. This is not quite
correct: The condition should be that the image hasn't been dirtied
since the last _successful_ flush. This patch changes the logic
accordingly.
Without this fix, subsequent bdrv_co_flush() calls would return success
without actually doing anything even though the image is still dirty.
The difference is visible in some blkdebug test cases where error
messages incorrectly disappeared after commit 3ff2f67a.
Cc: qemu-stable@nongnu.org
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Denis V. Lunev <den@openvz.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1478300595-10090-1-git-send-email-kwolf@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
---
block/io.c | 4 +++-
tests/qemu-iotests/026.out | 22 ++++++++++++++++++++++
tests/qemu-iotests/026.out.nocache | 22 ++++++++++++++++++++++
tests/qemu-iotests/071.out | 2 ++
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/block/io.c b/block/io.c
index 37749b6..aa532a5 100644
--- a/block/io.c
+++ b/block/io.c
@@ -2372,7 +2372,9 @@ flush_parent:
ret = bs->file ? bdrv_co_flush(bs->file->bs) : 0;
out:
/* Notify any pending flushes that we have completed */
- bs->flushed_gen = current_gen;
+ if (ret == 0) {
+ bs->flushed_gen = current_gen;
+ }
bs->active_flush_req = false;
/* Return value is ignored - it's ok if wait queue is empty */
qemu_co_queue_next(&bs->flush_queue);
diff --git a/tests/qemu-iotests/026.out b/tests/qemu-iotests/026.out
index 8531735..59b8f74 100644
--- a/tests/qemu-iotests/026.out
+++ b/tests/qemu-iotests/026.out
@@ -14,6 +14,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
@@ -22,6 +23,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
@@ -40,6 +42,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -48,6 +51,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -286,12 +290,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -308,12 +314,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -330,12 +338,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -352,12 +362,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -374,12 +386,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -396,12 +410,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -513,6 +529,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -521,6 +538,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -539,6 +557,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -547,6 +566,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -611,6 +631,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_grow_write_table; errno: 5; imm: off; once: off
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -622,6 +643,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_grow_write_table; errno: 28; imm: off; once: off
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
diff --git a/tests/qemu-iotests/026.out.nocache b/tests/qemu-iotests/026.out.nocache
index 672d77c..b4aeebc 100644
--- a/tests/qemu-iotests/026.out.nocache
+++ b/tests/qemu-iotests/026.out.nocache
@@ -14,6 +14,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
@@ -22,6 +23,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
@@ -40,6 +42,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -48,6 +51,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_update; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -294,12 +298,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -316,12 +322,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_load; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -338,12 +346,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -360,12 +370,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_update_part; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -382,12 +394,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 5; imm: off; once: off; write
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 5; imm: off; once: off; write -b
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -404,12 +418,14 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
@@ -521,6 +537,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -529,6 +546,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -547,6 +565,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -555,6 +574,7 @@ This means waste of disk space, but no harm to data.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write -b
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
@@ -619,6 +639,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_grow_write_table; errno: 5; imm: off; once: off
+Failed to flush the L2 table cache: Input/output error
Failed to flush the refcount block cache: Input/output error
write failed: Input/output error
No errors were found on the image.
@@ -630,6 +651,7 @@ No errors were found on the image.
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
Event: l1_grow_write_table; errno: 28; imm: off; once: off
+Failed to flush the L2 table cache: No space left on device
Failed to flush the refcount block cache: No space left on device
write failed: No space left on device
No errors were found on the image.
diff --git a/tests/qemu-iotests/071.out b/tests/qemu-iotests/071.out
index 8c6851e..8ff423f 100644
--- a/tests/qemu-iotests/071.out
+++ b/tests/qemu-iotests/071.out
@@ -86,5 +86,7 @@ read failed: Input/output error
{"return": ""}
{"return": {}}
{"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "SHUTDOWN"}
+QEMU_PROG: Failed to flush the L2 table cache: Input/output error
+QEMU_PROG: Failed to flush the refcount block cache: Input/output error
*** done
--
2.7.4
^ permalink raw reply related
* [Qemu-devel] [PULL 3/3] aio-posix: simplify aio_epoll_update
From: Stefan Hajnoczi @ 2016-11-08 18:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Paolo Bonzini, Stefan Hajnoczi
In-Reply-To: <1478628762-31050-1-git-send-email-stefanha@redhat.com>
From: Paolo Bonzini <pbonzini@redhat.com>
Extract common code out of the "if".
Reviewed-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20161108135524.25927-3-pbonzini@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
---
aio-posix.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/aio-posix.c b/aio-posix.c
index 304b016..e13b9ab 100644
--- a/aio-posix.c
+++ b/aio-posix.c
@@ -81,29 +81,22 @@ static void aio_epoll_update(AioContext *ctx, AioHandler *node, bool is_new)
{
struct epoll_event event;
int r;
+ int ctl;
if (!ctx->epoll_enabled) {
return;
}
if (!node->pfd.events) {
- r = epoll_ctl(ctx->epollfd, EPOLL_CTL_DEL, node->pfd.fd, &event);
- if (r) {
- aio_epoll_disable(ctx);
- }
+ ctl = EPOLL_CTL_DEL;
} else {
event.data.ptr = node;
event.events = epoll_events_from_pfd(node->pfd.events);
- if (is_new) {
- r = epoll_ctl(ctx->epollfd, EPOLL_CTL_ADD, node->pfd.fd, &event);
- if (r) {
- aio_epoll_disable(ctx);
- }
- } else {
- r = epoll_ctl(ctx->epollfd, EPOLL_CTL_MOD, node->pfd.fd, &event);
- if (r) {
- aio_epoll_disable(ctx);
- }
- }
+ ctl = is_new ? EPOLL_CTL_ADD : EPOLL_CTL_MOD;
+ }
+
+ r = epoll_ctl(ctx->epollfd, ctl, node->pfd.fd, &event);
+ if (r) {
+ aio_epoll_disable(ctx);
}
}
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM: davinci: enable PM for DT boot
From: Kevin Hilman @ 2016-11-08 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c3a69359-bcec-40fe-e25c-048b97bab726@ti.com>
Hi Sekhar,
Sekhar Nori <nsekhar@ti.com> writes:
> On Wednesday 26 October 2016 03:17 AM, Kevin Hilman wrote:
>> Currently system PM is only enabled for legacy (non-DT) boot. Enable
>> for DT boot also.
>>
>> Tested on da850-lcdk using "rtcwake -m mem -s5 -d rtc0".
>>
>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>> ---
>> arch/arm/mach-davinci/da8xx-dt.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
>> index c9f7e9274aa8..a8089fa40d86 100644
>> --- a/arch/arm/mach-davinci/da8xx-dt.c
>> +++ b/arch/arm/mach-davinci/da8xx-dt.c
>> @@ -43,8 +43,26 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
>>
>> #ifdef CONFIG_ARCH_DAVINCI_DA850
>>
>> +static struct davinci_pm_config da850_pm_pdata = {
>> + .sleepcount = 128,
>> +};
>> +
>> +static struct platform_device da850_pm_device = {
>> + .name = "pm-davinci",
>> + .dev = {
>> + .platform_data = &da850_pm_pdata,
>> + },
>> + .id = -1,
>> +};
>> +
>> static void __init da850_init_machine(void)
>> {
>> + int ret;
>> +
>> + ret = da850_register_pm(&da850_pm_device);
>
> I am not sure if it makes sense to keep the "pm device" around anymore.
> I think for both DT and non-DT boot, we can get rid of the fake PM
> device and combine da850_register_pm() and davinci_pm_probe() into a
> single davinci_init_suspend() function which can then be called both for
> DT and non-DT boot.
Looking closer at this, where do you propose the pdata comes from for
the non-DT boot?
It seems to me that we can't currently remove the pdata dependency
without breaking the non-DT platforms, so the approach proposed here is
the least invasive.
Once other platforms are DT converted, we could clean this up a bit
more.
Kevin
^ permalink raw reply
* ✓ Fi.CI.BAT: success for drm/i915: remove duplicated memsets in skl_allocate_pipe_ddb()
From: Patchwork @ 2016-11-08 18:15 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
In-Reply-To: <1478625682-8955-1-git-send-email-paulo.r.zanoni@intel.com>
== Series Details ==
Series: drm/i915: remove duplicated memsets in skl_allocate_pipe_ddb()
URL : https://patchwork.freedesktop.org/series/14984/
State : success
== Summary ==
Series 14984v1 drm/i915: remove duplicated memsets in skl_allocate_pipe_ddb()
https://patchwork.freedesktop.org/api/1.0/series/14984/revisions/1/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (fi-skl-6770hq)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
9435ffb9ffbfecfa5a429a46af96b1b3fda41d6c drm-intel-nightly: 2016y-11m-08d-13h-53m-48s UTC integration manifest
af272ef drm/i915: remove duplicated memsets in skl_allocate_pipe_ddb()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2936/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH 1/3] ipmi/bt-bmc: change compatible node to 'aspeed,ast2400-ibt-bmc'
From: Corey Minyard @ 2016-11-08 18:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a886778e-a85e-758e-3a61-c4909652e39d@kaod.org>
On 11/08/2016 09:52 AM, C?dric Le Goater wrote:
> O
snip
>>>> While we're modifying the binding, should we add a compat string for
>>>> the ast2500?
>>> Well, if the change in this patch is fine for all, may be we can add
>>> the ast2500 compat string in a followup patch ?
>> Sounds good to me.
> OK. So, how do we proceed with this patch ? Who would include it in its
> tree ?
I don't have anything for 4.9 at the moment. Arnd, if you have
something, can
you take this? Otherwise I will.
And I guess I should add:
Acked-by: Corey Minyard <cminyard@mvista.com>
-corey
> Thanks,
>
> C.
>
^ permalink raw reply
* Re: [PATCH 1/3] ipmi/bt-bmc: change compatible node to 'aspeed,ast2400-ibt-bmc'
From: Corey Minyard @ 2016-11-08 18:15 UTC (permalink / raw)
To: Cédric Le Goater, Arnd Bergmann
Cc: Joel Stanley, openipmi-developer-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Benjamin Herrenschmidt
In-Reply-To: <a886778e-a85e-758e-3a61-c4909652e39d-Bxea+6Xhats@public.gmane.org>
On 11/08/2016 09:52 AM, Cédric Le Goater wrote:
> O
snip
>>>> While we're modifying the binding, should we add a compat string for
>>>> the ast2500?
>>> Well, if the change in this patch is fine for all, may be we can add
>>> the ast2500 compat string in a followup patch ?
>> Sounds good to me.
> OK. So, how do we proceed with this patch ? Who would include it in its
> tree ?
I don't have anything for 4.9 at the moment. Arnd, if you have
something, can
you take this? Otherwise I will.
And I guess I should add:
Acked-by: Corey Minyard <cminyard-Igf4POYTYCDQT0dZR+AlfA@public.gmane.org>
-corey
> Thanks,
>
> C.
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] gpio: davinci: Use unique labels for each gpio chip
From: Kevin Hilman @ 2016-11-08 18:16 UTC (permalink / raw)
To: Axel Haslam
Cc: linus.walleij, gnurou, nsekhar, david, grygorii.strashko, keerthy,
linux-gpio, linux-kernel
In-Reply-To: <20161103113410.2163-1-ahaslam@baylibre.com>
Axel Haslam <ahaslam@baylibre.com> writes:
> The gpiod framework uses the chip label to match a specific chip.
> The davinci gpio driver, creates several chips using always the same
> label, which is not compatible with gpiod.
>
> To allow platform data to declare gpio lookup tables, and for drivers
> to use the gpiod framework, allocate unique label per registered chip.
>
> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
* BUG: Hung task timeouts in for-4.10/dio
From: Logan Gunthorpe @ 2016-11-08 18:16 UTC (permalink / raw)
To: Jens Axboe, Christoph Hellwig; +Cc: linux-block, Stephen Bates
[-- Attachment #1: Type: text/plain, Size: 856 bytes --]
Hi guys,
We were looking at testing the new IO polling improvements and we built
a kernel from the 'for-4.10/dio' (64ead7d) branch in linux-block.
However this branch seems to cause hung tasks when booted. Most
noticeably, dhclient seems to always hang as it tries to read from it's
leases file, and that means networking does not work on the computers we
tested on. Other tasks seemed to hang occasionally and randomly.
We tested on two machines with radically different hardware but both
running Debian Jessie. (One is a dual-socket server system with the
root FS on an HDD and the other is an off the shelf commodity
motherboard with root on an SSD.)
We performed a bisect to find the culprit commit to be:
[b685d3d65ac791406e0dfd8779cc9b3707fea5a3] block: treat REQ_FUA and
REQ_PREFLUSH as synchronous
I've attached a bisect log.
Thanks,
Logan
[-- Attachment #2: block-bisect.log --]
[-- Type: text/x-log, Size: 1346 bytes --]
git bisect start
# good: [1001354ca34179f3db924eb66672442a173147dc] Linux 4.9-rc1
git bisect good 1001354ca34179f3db924eb66672442a173147dc
# bad: [64ead7d24b34ed40e85577e9be8bd203835e57c4] blk-mq: make the polling code adaptive
git bisect bad 64ead7d24b34ed40e85577e9be8bd203835e57c4
# bad: [70fd76140a6cb63262bd47b68d57b42e889c10ee] block,fs: use REQ_* flags directly
git bisect bad 70fd76140a6cb63262bd47b68d57b42e889c10ee
# good: [2552e3f878c2b43b41d7728a328821d8220c28da] blk-mq: get rid of confusing blk_map_ctx structure
git bisect good 2552e3f878c2b43b41d7728a328821d8220c28da
# good: [aa39ebd404423e62f74cfd3e27e9ffe7e38b2a25] cfq-iosched: use op_is_sync instead of opencoding it
git bisect good aa39ebd404423e62f74cfd3e27e9ffe7e38b2a25
# good: [67f055c798c72c49ee0c844eae0cd6e9c83b1b16] btrfs: use op_is_sync to check for synchronous requests
git bisect good 67f055c798c72c49ee0c844eae0cd6e9c83b1b16
# bad: [b685d3d65ac791406e0dfd8779cc9b3707fea5a3] block: treat REQ_FUA and REQ_PREFLUSH as synchronous
git bisect bad b685d3d65ac791406e0dfd8779cc9b3707fea5a3
# good: [6f6b29171a192e84b666c816e49d2175afbbb09f] block: don't use REQ_SYNC in the READ_SYNC definition
git bisect good 6f6b29171a192e84b666c816e49d2175afbbb09f
# first bad commit: [b685d3d65ac791406e0dfd8779cc9b3707fea5a3] block: treat REQ_FUA and REQ_PREFLUSH as synchronous
^ permalink raw reply
* [kvm-unit-tests PATCH v8 1/3] arm: Add PMU test
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: alindsay, kvm, croberts, qemu-devel, alistair.francis,
shannon.zhao, kvmarm
In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/Makefile.common | 3 ++-
arm/pmu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 5 ++++
3 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
diff --git a/arm/Makefile.common b/arm/Makefile.common
index ccb554d..f98f422 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -11,7 +11,8 @@ endif
tests-common = \
$(TEST_DIR)/selftest.flat \
- $(TEST_DIR)/spinlock-test.flat
+ $(TEST_DIR)/spinlock-test.flat \
+ $(TEST_DIR)/pmu.flat
all: test_cases
diff --git a/arm/pmu.c b/arm/pmu.c
new file mode 100644
index 0000000..0b29088
--- /dev/null
+++ b/arm/pmu.c
@@ -0,0 +1,73 @@
+/*
+ * Test the ARM Performance Monitors Unit (PMU).
+ *
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License version 2.1 and
+ * only version 2.1 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+ * for more details.
+ */
+#include "libcflat.h"
+
+#define PMU_PMCR_N_SHIFT 11
+#define PMU_PMCR_N_MASK 0x1f
+#define PMU_PMCR_ID_SHIFT 16
+#define PMU_PMCR_ID_MASK 0xff
+#define PMU_PMCR_IMP_SHIFT 24
+#define PMU_PMCR_IMP_MASK 0xff
+
+#if defined(__arm__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
+ return ret;
+}
+#elif defined(__aarch64__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
+ return ret;
+}
+#endif
+
+/*
+ * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't
+ * null. Also print out a couple other interesting fields for diagnostic
+ * purposes. For example, as of fall 2016, QEMU TCG mode doesn't implement
+ * event counters and therefore reports zero event counters, but hopefully
+ * support for at least the instructions event will be added in the future and
+ * the reported number of event counters will become nonzero.
+ */
+static bool check_pmcr(void)
+{
+ uint32_t pmcr;
+
+ pmcr = pmcr_read();
+
+ printf("PMU implementer: %c\n",
+ (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK);
+ printf("Identification code: 0x%x\n",
+ (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK);
+ printf("Event counters: %d\n",
+ (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK);
+
+ return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
+}
+
+int main(void)
+{
+ report_prefix_push("pmu");
+
+ report("Control register", check_pmcr());
+
+ return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 3f6fa45..7645180 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -54,3 +54,8 @@ file = selftest.flat
smp = $MAX_SMP
extra_params = -append 'smp'
groups = selftest
+
+# Test PMU support
+[pmu]
+file = pmu.flat
+groups = pmu
--
1.8.3.1
^ permalink raw reply related
* slcand multiple interfaces on single serial interface
From: Paul Bongaerts @ 2016-11-08 18:17 UTC (permalink / raw)
To: linux-can
Hi my name is Paul, 37, dutch mechanical engineer new to mailing lists
and no programmer.
After looking into linux-can i would like setup 2 mcp2515 controllers
on one serial interface.
I'm using an ATMEGA 328 based arduino with 2 mcp2515 controllers on
isobus (2 250kbbs can interfaces)
For this i found :
The latest mcp_library:
https://github.com/coryjfowler/MCP_CAN_lib
Also i found two ways to use this with the slcand driver
The arduino-canbus-monitor
https://github.com/latonita/arduino-canbus-monitor
And https://github.com/kahiroka/slcanuino/blob/master/slcan.ino
The commands used in the driver
http://www.can232.com/can232/can232_v3.pdf
What i cant figure out is how to do use enumeration to specify which
can controller is used on the serial bus.
There is a serial option
N[CR] which will return the serial. maybe this could be set to ie CAN0 and CAN1
So
Tiiiiiiiildd...[CR]
Could maybe changed into
Tiiiiiiiildd...Nx[CR] to send on CANx
this way it might be possible bind linux CAN0 and CAN1 interfaces to
CAN0 and CAN1 on the arduino.
Who can help me out or point in the correct direction?
Br Paul
^ permalink raw reply
* [kvm-unit-tests PATCH v8 0/3] ARM PMU tests
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
Changes from v7:
* Standardize PMU register accessor names and remove unused ones
* Use bit defines instead of bit fields
* Change the testing configure for pmu.flat
* Commit comments were updated
Note:
1) Current KVM code has bugs in handling PMCCFILTR write. A fix (see
below) is required for this unit testing code to work correctly under
KVM mode.
https://lists.cs.columbia.edu/pipermail/kvmarm/2016-November/022134.html.
2) Because the code was changed, Drew's original reviewed-by needs to
be acknowledged by him again.
-Wei
Wei Huang (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
arm/Makefile.common | 3 +-
arm/pmu.c | 270 ++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 19 ++++
3 files changed, 291 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
--
1.8.3.1
^ permalink raw reply
* [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/pmu.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arm/pmu.c b/arm/pmu.c
index 0b29088..d5e3ac3 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -14,6 +14,7 @@
*/
#include "libcflat.h"
+#define PMU_PMCR_E (1 << 0)
#define PMU_PMCR_N_SHIFT 11
#define PMU_PMCR_N_MASK 0x1f
#define PMU_PMCR_ID_SHIFT 16
@@ -21,6 +22,10 @@
#define PMU_PMCR_IMP_SHIFT 24
#define PMU_PMCR_IMP_MASK 0xff
+#define PMU_CYCLE_IDX 31
+
+#define NR_SAMPLES 10
+
#if defined(__arm__)
static inline uint32_t pmcr_read(void)
{
@@ -29,6 +34,47 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (value));
+}
+
+static inline void pmselr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (value));
+}
+
+static inline void pmxevtyper_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (value));
+}
+
+/*
+ * While PMCCNTR can be accessed as a 64 bit coprocessor register, returning 64
+ * bits doesn't seem worth the trouble when differential usage of the result is
+ * expected (with differences that can easily fit in 32 bits). So just return
+ * the lower 32 bits of the cycle count in AArch32.
+ */
+static inline uint32_t pmccntr_read(void)
+{
+ uint32_t cycles;
+
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles));
+ return cycles;
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (value));
+}
+
+/* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */
+static inline void pmccfiltr_write(uint32_t value)
+{
+ pmselr_write(PMU_CYCLE_IDX);
+ pmxevtyper_write(value);
+}
#elif defined(__aarch64__)
static inline uint32_t pmcr_read(void)
{
@@ -37,6 +83,29 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("msr pmcr_el0, %0" : : "r" (value));
+}
+
+static inline uint32_t pmccntr_read(void)
+{
+ uint32_t cycles;
+
+ asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles));
+ return cycles;
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("msr pmcntenset_el0, %0" : : "r" (value));
+}
+
+static inline void pmccfiltr_write(uint32_t value)
+{
+ asm volatile("msr pmccfiltr_el0, %0" : : "r" (value));
+}
#endif
/*
@@ -63,11 +132,40 @@ static bool check_pmcr(void)
return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
}
+/*
+ * Ensure that the cycle counter progresses between back-to-back reads.
+ */
+static bool check_cycles_increase(void)
+{
+ pmcr_write(pmcr_read() | PMU_PMCR_E);
+
+ for (int i = 0; i < NR_SAMPLES; i++) {
+ unsigned long a, b;
+
+ a = pmccntr_read();
+ b = pmccntr_read();
+
+ if (a >= b) {
+ printf("Read %ld then %ld.\n", a, b);
+ return false;
+ }
+ }
+
+ pmcr_write(pmcr_read() & ~PMU_PMCR_E);
+
+ return true;
+}
+
int main(void)
{
report_prefix_push("pmu");
+ /* init for PMU event access, right now only care about cycle count */
+ pmcntenset_write(1 << PMU_CYCLE_IDX);
+ pmccfiltr_write(0); /* count cycles in EL0, EL1, but not EL2 */
+
report("Control register", check_pmcr());
+ report("Monotonically increasing cycle count", check_cycles_increase());
return report_summary();
}
--
1.8.3.1
^ permalink raw reply related
* [kvm-unit-tests PATCH v8 3/3] arm: pmu: Add CPI checking
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/pmu.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
arm/unittests.cfg | 14 ++++++++
2 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index d5e3ac3..09aff89 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -15,6 +15,7 @@
#include "libcflat.h"
#define PMU_PMCR_E (1 << 0)
+#define PMU_PMCR_C (1 << 2)
#define PMU_PMCR_N_SHIFT 11
#define PMU_PMCR_N_MASK 0x1f
#define PMU_PMCR_ID_SHIFT 16
@@ -75,6 +76,23 @@ static inline void pmccfiltr_write(uint32_t value)
pmselr_write(PMU_CYCLE_IDX);
pmxevtyper_write(value);
}
+
+/*
+ * Extra instructions inserted by the compiler would be difficult to compensate
+ * for, so hand assemble everything between, and including, the PMCR accesses
+ * to start and stop counting.
+ */
+static inline void loop(int i, uint32_t pmcr)
+{
+ asm volatile(
+ " mcr p15, 0, %[pmcr], c9, c12, 0\n"
+ "1: subs %[i], %[i], #1\n"
+ " bgt 1b\n"
+ " mcr p15, 0, %[z], c9, c12, 0\n"
+ : [i] "+r" (i)
+ : [pmcr] "r" (pmcr), [z] "r" (0)
+ : "cc");
+}
#elif defined(__aarch64__)
static inline uint32_t pmcr_read(void)
{
@@ -106,6 +124,23 @@ static inline void pmccfiltr_write(uint32_t value)
{
asm volatile("msr pmccfiltr_el0, %0" : : "r" (value));
}
+
+/*
+ * Extra instructions inserted by the compiler would be difficult to compensate
+ * for, so hand assemble everything between, and including, the PMCR accesses
+ * to start and stop counting.
+ */
+static inline void loop(int i, uint32_t pmcr)
+{
+ asm volatile(
+ " msr pmcr_el0, %[pmcr]\n"
+ "1: subs %[i], %[i], #1\n"
+ " b.gt 1b\n"
+ " msr pmcr_el0, xzr\n"
+ : [i] "+r" (i)
+ : [pmcr] "r" (pmcr)
+ : "cc");
+}
#endif
/*
@@ -156,8 +191,71 @@ static bool check_cycles_increase(void)
return true;
}
-int main(void)
+/*
+ * Execute a known number of guest instructions. Only odd instruction counts
+ * greater than or equal to 3 are supported by the in-line assembly code. The
+ * control register (PMCR_EL0) is initialized with the provided value (allowing
+ * for example for the cycle counter or event counters to be reset). At the end
+ * of the exact instruction loop, zero is written to PMCR_EL0 to disable
+ * counting, allowing the cycle counter or event counters to be read at the
+ * leisure of the calling code.
+ */
+static void measure_instrs(int num, uint32_t pmcr)
+{
+ int i = (num - 1) / 2;
+
+ assert(num >= 3 && ((num - 1) % 2 == 0));
+ loop(i, pmcr);
+}
+
+/*
+ * Measure cycle counts for various known instruction counts. Ensure that the
+ * cycle counter progresses (similar to check_cycles_increase() but with more
+ * instructions and using reset and stop controls). If supplied a positive,
+ * nonzero CPI parameter, also strictly check that every measurement matches
+ * it. Strict CPI checking is used to test -icount mode.
+ */
+static bool check_cpi(int cpi)
+{
+ uint32_t pmcr = pmcr_read() | PMU_PMCR_C | PMU_PMCR_E;
+
+ if (cpi > 0)
+ printf("Checking for CPI=%d.\n", cpi);
+ printf("instrs : cycles0 cycles1 ...\n");
+
+ for (int i = 3; i < 300; i += 32) {
+ int avg, sum = 0;
+
+ printf("%d :", i);
+ for (int j = 0; j < NR_SAMPLES; j++) {
+ int cycles;
+
+ measure_instrs(i, pmcr);
+ cycles =pmccntr_read();
+ printf(" %d", cycles);
+
+ if (!cycles || (cpi > 0 && cycles != i * cpi)) {
+ printf("\n");
+ return false;
+ }
+
+ sum += cycles;
+ }
+ avg = sum / NR_SAMPLES;
+ printf(" sum=%d avg=%d avg_ipc=%d avg_cpi=%d\n",
+ sum, avg, i / avg, avg / i);
+ }
+
+ return true;
+}
+
+int main(int argc, char *argv[])
{
+ int cpi = 0;
+
+ if (argc >= 1)
+ cpi = atol(argv[0]);
+
report_prefix_push("pmu");
/* init for PMU event access, right now only care about cycle count */
@@ -166,6 +264,7 @@ int main(void)
report("Control register", check_pmcr());
report("Monotonically increasing cycle count", check_cycles_increase());
+ report("Cycle/instruction ratio", check_cpi(cpi));
return report_summary();
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 7645180..2050dc8 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -59,3 +59,17 @@ groups = selftest
[pmu]
file = pmu.flat
groups = pmu
+
+# Test PMU support (TCG) with -icount IPC=1
+[pmu-tcg-icount-1]
+file = pmu.flat
+extra_params = -icount 0 -append '1'
+groups = pmu
+accel = tcg
+
+# Test PMU support (TCG) with -icount IPC=256
+[pmu-tcg-icount-256]
+file = pmu.flat
+extra_params = -icount 8 -append '256'
+groups = pmu
+accel = tcg
--
1.8.3.1
^ permalink raw reply related
* [Qemu-devel] [kvm-unit-tests PATCH v8 0/3] ARM PMU tests
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
Changes from v7:
* Standardize PMU register accessor names and remove unused ones
* Use bit defines instead of bit fields
* Change the testing configure for pmu.flat
* Commit comments were updated
Note:
1) Current KVM code has bugs in handling PMCCFILTR write. A fix (see
below) is required for this unit testing code to work correctly under
KVM mode.
https://lists.cs.columbia.edu/pipermail/kvmarm/2016-November/022134.html.
2) Because the code was changed, Drew's original reviewed-by needs to
be acknowledged by him again.
-Wei
Wei Huang (3):
arm: Add PMU test
arm: pmu: Check cycle count increases
arm: pmu: Add CPI checking
arm/Makefile.common | 3 +-
arm/pmu.c | 270 ++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 19 ++++
3 files changed, 291 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
--
1.8.3.1
^ permalink raw reply
* [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/pmu.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arm/pmu.c b/arm/pmu.c
index 0b29088..d5e3ac3 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -14,6 +14,7 @@
*/
#include "libcflat.h"
+#define PMU_PMCR_E (1 << 0)
#define PMU_PMCR_N_SHIFT 11
#define PMU_PMCR_N_MASK 0x1f
#define PMU_PMCR_ID_SHIFT 16
@@ -21,6 +22,10 @@
#define PMU_PMCR_IMP_SHIFT 24
#define PMU_PMCR_IMP_MASK 0xff
+#define PMU_CYCLE_IDX 31
+
+#define NR_SAMPLES 10
+
#if defined(__arm__)
static inline uint32_t pmcr_read(void)
{
@@ -29,6 +34,47 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (value));
+}
+
+static inline void pmselr_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (value));
+}
+
+static inline void pmxevtyper_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (value));
+}
+
+/*
+ * While PMCCNTR can be accessed as a 64 bit coprocessor register, returning 64
+ * bits doesn't seem worth the trouble when differential usage of the result is
+ * expected (with differences that can easily fit in 32 bits). So just return
+ * the lower 32 bits of the cycle count in AArch32.
+ */
+static inline uint32_t pmccntr_read(void)
+{
+ uint32_t cycles;
+
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles));
+ return cycles;
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (value));
+}
+
+/* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */
+static inline void pmccfiltr_write(uint32_t value)
+{
+ pmselr_write(PMU_CYCLE_IDX);
+ pmxevtyper_write(value);
+}
#elif defined(__aarch64__)
static inline uint32_t pmcr_read(void)
{
@@ -37,6 +83,29 @@ static inline uint32_t pmcr_read(void)
asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
return ret;
}
+
+static inline void pmcr_write(uint32_t value)
+{
+ asm volatile("msr pmcr_el0, %0" : : "r" (value));
+}
+
+static inline uint32_t pmccntr_read(void)
+{
+ uint32_t cycles;
+
+ asm volatile("mrs %0, pmccntr_el0" : "=r" (cycles));
+ return cycles;
+}
+
+static inline void pmcntenset_write(uint32_t value)
+{
+ asm volatile("msr pmcntenset_el0, %0" : : "r" (value));
+}
+
+static inline void pmccfiltr_write(uint32_t value)
+{
+ asm volatile("msr pmccfiltr_el0, %0" : : "r" (value));
+}
#endif
/*
@@ -63,11 +132,40 @@ static bool check_pmcr(void)
return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
}
+/*
+ * Ensure that the cycle counter progresses between back-to-back reads.
+ */
+static bool check_cycles_increase(void)
+{
+ pmcr_write(pmcr_read() | PMU_PMCR_E);
+
+ for (int i = 0; i < NR_SAMPLES; i++) {
+ unsigned long a, b;
+
+ a = pmccntr_read();
+ b = pmccntr_read();
+
+ if (a >= b) {
+ printf("Read %ld then %ld.\n", a, b);
+ return false;
+ }
+ }
+
+ pmcr_write(pmcr_read() & ~PMU_PMCR_E);
+
+ return true;
+}
+
int main(void)
{
report_prefix_push("pmu");
+ /* init for PMU event access, right now only care about cycle count */
+ pmcntenset_write(1 << PMU_CYCLE_IDX);
+ pmccfiltr_write(0); /* count cycles in EL0, EL1, but not EL2 */
+
report("Control register", check_pmcr());
+ report("Monotonically increasing cycle count", check_cycles_increase());
return report_summary();
}
--
1.8.3.1
^ permalink raw reply related
* [Qemu-devel] [kvm-unit-tests PATCH v8 1/3] arm: Add PMU test
From: Wei Huang @ 2016-11-08 18:17 UTC (permalink / raw)
To: cov
Cc: qemu-devel, kvm, kvmarm, shannon.zhao, alistair.francis, croberts,
alindsay, drjones
In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com>
From: Christopher Covington <cov@codeaurora.org>
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Wei Huang <wei@redhat.com>
---
arm/Makefile.common | 3 ++-
arm/pmu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 5 ++++
3 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 arm/pmu.c
diff --git a/arm/Makefile.common b/arm/Makefile.common
index ccb554d..f98f422 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -11,7 +11,8 @@ endif
tests-common = \
$(TEST_DIR)/selftest.flat \
- $(TEST_DIR)/spinlock-test.flat
+ $(TEST_DIR)/spinlock-test.flat \
+ $(TEST_DIR)/pmu.flat
all: test_cases
diff --git a/arm/pmu.c b/arm/pmu.c
new file mode 100644
index 0000000..0b29088
--- /dev/null
+++ b/arm/pmu.c
@@ -0,0 +1,73 @@
+/*
+ * Test the ARM Performance Monitors Unit (PMU).
+ *
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License version 2.1 and
+ * only version 2.1 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+ * for more details.
+ */
+#include "libcflat.h"
+
+#define PMU_PMCR_N_SHIFT 11
+#define PMU_PMCR_N_MASK 0x1f
+#define PMU_PMCR_ID_SHIFT 16
+#define PMU_PMCR_ID_MASK 0xff
+#define PMU_PMCR_IMP_SHIFT 24
+#define PMU_PMCR_IMP_MASK 0xff
+
+#if defined(__arm__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret));
+ return ret;
+}
+#elif defined(__aarch64__)
+static inline uint32_t pmcr_read(void)
+{
+ uint32_t ret;
+
+ asm volatile("mrs %0, pmcr_el0" : "=r" (ret));
+ return ret;
+}
+#endif
+
+/*
+ * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't
+ * null. Also print out a couple other interesting fields for diagnostic
+ * purposes. For example, as of fall 2016, QEMU TCG mode doesn't implement
+ * event counters and therefore reports zero event counters, but hopefully
+ * support for at least the instructions event will be added in the future and
+ * the reported number of event counters will become nonzero.
+ */
+static bool check_pmcr(void)
+{
+ uint32_t pmcr;
+
+ pmcr = pmcr_read();
+
+ printf("PMU implementer: %c\n",
+ (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK);
+ printf("Identification code: 0x%x\n",
+ (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK);
+ printf("Event counters: %d\n",
+ (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK);
+
+ return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
+}
+
+int main(void)
+{
+ report_prefix_push("pmu");
+
+ report("Control register", check_pmcr());
+
+ return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 3f6fa45..7645180 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -54,3 +54,8 @@ file = selftest.flat
smp = $MAX_SMP
extra_params = -append 'smp'
groups = selftest
+
+# Test PMU support
+[pmu]
+file = pmu.flat
+groups = pmu
--
1.8.3.1
^ permalink raw reply related
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