* [PATCH v4 2/3] arm64: dts: marvell: Add I2C definitions for the Armada 3700
From: Romain Perier @ 2016-11-09 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109115715.2557-1-romain.perier@free-electrons.com>
The Armada 3700 has two i2c bus interface units, this commit adds the
definitions of the corresponding device nodes. It also enables the node
on the development board for this SoC.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6..16d84af 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -62,6 +62,10 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
/* CON3 */
&sata {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c476253..bf2d73d 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -98,6 +98,24 @@
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
+ i2c0: i2c at 11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x24>;
+ clocks = <&nb_perih_clk 10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 11080 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11080 0x24>;
+ clocks = <&nb_perih_clk 9>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
uart0: serial at 12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
--
2.9.3
^ permalink raw reply related
* [PATCH v4 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Romain Perier @ 2016-11-09 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109115715.2557-1-romain.perier@free-electrons.com>
The Armada 3700 has two I2C controllers that is compliant with the I2C
Bus Specificiation 2.1, supports multi-master and different bus speed:
Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
High speed mode (up to 3.4 Mhz).
This IP block has a lot of similarity with the PXA, except some register
offsets and bitfield. This commits adds a basic support for this I2C
unit.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
Changes in v4:
- Replaced the type of hs_mask and fm_mask by u32, instead of
unsigned int, As writel() take an u32 as first argument...
Changes in v3:
- Replaced the type of hs_mask and fm_mask by unsigned int,
instead of unsigned long.
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d252276..2f56a26 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -763,7 +763,7 @@ config I2C_PUV3
config I2C_PXA
tristate "Intel PXA2XX I2C adapter"
- depends on ARCH_PXA || ARCH_MMP || (X86_32 && PCI && OF)
+ depends on ARCH_PXA || ARCH_MMP || ARCH_MVEBU || (X86_32 && PCI && OF)
help
If you have devices in the PXA I2C bus, say yes to this option.
This driver can also be built as a module. If so, the module
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index e28b825..09b4705 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -55,6 +55,7 @@ enum pxa_i2c_types {
REGS_PXA3XX,
REGS_CE4100,
REGS_PXA910,
+ REGS_A3700,
};
/*
@@ -91,6 +92,13 @@ static struct pxa_reg_layout pxa_reg_layout[] = {
.ilcr = 0x28,
.iwcr = 0x30,
},
+ [REGS_A3700] = {
+ .ibmr = 0x00,
+ .idbr = 0x04,
+ .icr = 0x08,
+ .isr = 0x0c,
+ .isar = 0x10,
+ },
};
static const struct platform_device_id i2c_pxa_id_table[] = {
@@ -98,6 +106,7 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
{ "pxa3xx-pwri2c", REGS_PXA3XX },
{ "ce4100-i2c", REGS_CE4100 },
{ "pxa910-i2c", REGS_PXA910 },
+ { "armada-3700-i2c", REGS_A3700 },
{ },
};
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
@@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ICR_FM (1 << 15) /* fast mode */
+#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
#define ICR_HS (1 << 16) /* High Speed mode */
+#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
#define ISR_RWM (1 << 0) /* read/write mode */
@@ -193,6 +204,8 @@ struct pxa_i2c {
unsigned char master_code;
unsigned long rate;
bool highmode_enter;
+ u32 fm_mask;
+ u32 hs_mask;
};
#define _IBMR(i2c) ((i2c)->reg_ibmr)
@@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
- writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
- writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
+ writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
+ writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
@@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
+ { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
{}
};
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
@@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
i2c->fast_mode = 1;
+ if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
+ i2c->fm_mask = ICR_BUSMODE_FM;
+ i2c->hs_mask = ICR_BUSMODE_HS;
+ } else {
+ i2c->fm_mask = ICR_FM;
+ i2c->hs_mask = ICR_HS;
+ }
*i2c_types = (enum pxa_i2c_types)(of_id->data);
--
2.9.3
^ permalink raw reply related
* [PATCH v4 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Romain Perier @ 2016-11-09 11:57 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
In-Reply-To: <20161109115715.2557-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The Armada 3700 has two I2C controllers that is compliant with the I2C
Bus Specificiation 2.1, supports multi-master and different bus speed:
Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
High speed mode (up to 3.4 Mhz).
This IP block has a lot of similarity with the PXA, except some register
offsets and bitfield. This commits adds a basic support for this I2C
unit.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Tested-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Changes in v4:
- Replaced the type of hs_mask and fm_mask by u32, instead of
unsigned int, As writel() take an u32 as first argument...
Changes in v3:
- Replaced the type of hs_mask and fm_mask by unsigned int,
instead of unsigned long.
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d252276..2f56a26 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -763,7 +763,7 @@ config I2C_PUV3
config I2C_PXA
tristate "Intel PXA2XX I2C adapter"
- depends on ARCH_PXA || ARCH_MMP || (X86_32 && PCI && OF)
+ depends on ARCH_PXA || ARCH_MMP || ARCH_MVEBU || (X86_32 && PCI && OF)
help
If you have devices in the PXA I2C bus, say yes to this option.
This driver can also be built as a module. If so, the module
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index e28b825..09b4705 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -55,6 +55,7 @@ enum pxa_i2c_types {
REGS_PXA3XX,
REGS_CE4100,
REGS_PXA910,
+ REGS_A3700,
};
/*
@@ -91,6 +92,13 @@ static struct pxa_reg_layout pxa_reg_layout[] = {
.ilcr = 0x28,
.iwcr = 0x30,
},
+ [REGS_A3700] = {
+ .ibmr = 0x00,
+ .idbr = 0x04,
+ .icr = 0x08,
+ .isr = 0x0c,
+ .isar = 0x10,
+ },
};
static const struct platform_device_id i2c_pxa_id_table[] = {
@@ -98,6 +106,7 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
{ "pxa3xx-pwri2c", REGS_PXA3XX },
{ "ce4100-i2c", REGS_CE4100 },
{ "pxa910-i2c", REGS_PXA910 },
+ { "armada-3700-i2c", REGS_A3700 },
{ },
};
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
@@ -122,7 +131,9 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ICR_FM (1 << 15) /* fast mode */
+#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
#define ICR_HS (1 << 16) /* High Speed mode */
+#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
#define ISR_RWM (1 << 0) /* read/write mode */
@@ -193,6 +204,8 @@ struct pxa_i2c {
unsigned char master_code;
unsigned long rate;
bool highmode_enter;
+ u32 fm_mask;
+ u32 hs_mask;
};
#define _IBMR(i2c) ((i2c)->reg_ibmr)
@@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
- writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
- writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
+ writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
+ writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
@@ -1137,6 +1150,7 @@ static const struct of_device_id i2c_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
+ { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
{}
};
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
@@ -1158,6 +1172,13 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
i2c->fast_mode = 1;
+ if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
+ i2c->fm_mask = ICR_BUSMODE_FM;
+ i2c->hs_mask = ICR_BUSMODE_HS;
+ } else {
+ i2c->fm_mask = ICR_FM;
+ i2c->hs_mask = ICR_HS;
+ }
*i2c_types = (enum pxa_i2c_types)(of_id->data);
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v4 0/3] Add basic support for the I2C units of the Armada 3700
From: Romain Perier @ 2016-11-09 11:57 UTC (permalink / raw)
To: linux-arm-kernel
This series add basic support for the I2C bus interface units present
in the Armada 3700 to the pxa-i2c driver. It also add the definitions of
the device nodes to the devicetree at the SoC level and for its official
development board: the Armada 3720 DB.
Romain Perier (3):
i2c: pxa: Add support for the I2C units found in Armada 3700
arm64: dts: marvell: Add I2C definitions for the Armada 3700
dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++--
5 files changed, 47 insertions(+), 3 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH v4 0/3] Add basic support for the I2C units of the Armada 3700
From: Romain Perier @ 2016-11-09 11:57 UTC (permalink / raw)
To: Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Omri Itach, Shadi Ammouri,
Yahuda Yitschak, Hanna Hawa, Neta Zur Hershkovits, Igal Liberman,
Marcin Wojtas <mw>
This series add basic support for the I2C bus interface units present
in the Armada 3700 to the pxa-i2c driver. It also add the definitions of
the device nodes to the devicetree at the SoC level and for its official
development board: the Armada 3720 DB.
Romain Perier (3):
i2c: pxa: Add support for the I2C units found in Armada 3700
arm64: dts: marvell: Add I2C definitions for the Armada 3700
dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
Documentation/devicetree/bindings/i2c/i2c-pxa.txt | 1 +
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 ++++++++++++++++
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-pxa.c | 25 +++++++++++++++++++++--
5 files changed, 47 insertions(+), 3 deletions(-)
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: Question about nfsdcltrack --storagedir
From: Jeff Layton @ 2016-11-09 11:57 UTC (permalink / raw)
To: NeilBrown; +Cc: Linux NFS Mailing List
In-Reply-To: <87k2cdmi26.fsf@notabene.neil.brown.name>
On Wed, 2016-11-09 at 14:46 +1100, NeilBrown wrote:
> Hi,
> I notice that nfsdcltrack has a "--storagedir" option.
> I wonder how this can be used, given the nfsdcltrack is only(?) called
> from the kernel and there is no(?) mechanism to pass extra options.
>
> In a clustered-server context it would make sense(?) to share the
> database between cluster nodes and it is easiest to do this if the
> file in a separate filesystem (mounted as part of fail-over) rather
> than in /var.
> This can(?) be achieved using a symlink, but rpm likes to remove
> symlinks to non-existent locations.
>
> With NFSv3 the equivalent is the state files maintained by statd, and
> these can be relocated by passing the -P option to rpc.statd.
> How does one do a similar thing for NFSv4???
>
>
Ahh, I added that option mostly for when I was testing it. I did a lot
of the earlier testing running it by hand, and --storagedir let me use a
different directory for the db. I did have a vague idea that we might
use it in the situation you describe, but I never wired that up as I
didn't have a real need for it.
We could add a new module parm that would set that option when the
kernel does its callout, or allow passing the storagedir by environment
variable.
What would make the most sense from a usability standpoint?
--
Jeff Layton <jlayton@redhat.com>
^ permalink raw reply
* Re: [PATCH v6 04/14] mmc: sdhci-msm: Change poor style writel/readl of registers
From: Ritesh Harjani @ 2016-11-09 11:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: ulf.hansson, linux-mmc, adrian.hunter, shawn.lin, devicetree,
linux-clk, david.brown, andy.gross, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd, kdorfman,
david.griego, stummala, venkatg, rnayak, pramod.gurav
In-Reply-To: <20161108230724.GO16026@codeaurora.org>
Hi Stephen,
On 11/9/2016 4:37 AM, Stephen Boyd wrote:
> On 11/07, Ritesh Harjani wrote:
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index 8ef44a2a..42f42aa 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -137,8 +137,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
>> writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
>>
>> /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
>> - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
>> - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
>> + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
>> + config |= CORE_CK_OUT_EN;
>> + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
>>
>> /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
>> rc = msm_dll_poll_ck_out_en(host, 1);
>> @@ -305,6 +306,7 @@ static int msm_init_cm_dll(struct sdhci_host *host)
>> struct mmc_host *mmc = host->mmc;
>> int wait_cnt = 50;
>> unsigned long flags;
>> + u32 config = 0;
>
> It needs to be initialized?
No, will make it uninitialized.
>
>>
>> spin_lock_irqsave(&host->lock, flags);
>>
>> @@ -313,33 +315,40 @@ static int msm_init_cm_dll(struct sdhci_host *host)
>> * tuning is in progress. Keeping PWRSAVE ON may
>> * turn off the clock.
>> */
>> - writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
>> - & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
>> + config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
>
> It's written here unconditionally though?
>
>> + config &= ~CORE_CLK_PWRSAVE;
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v6 04/14] mmc: sdhci-msm: Change poor style writel/readl of registers
From: Ritesh Harjani @ 2016-11-09 11:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ, kdorfman-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <20161108230724.GO16026-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Hi Stephen,
On 11/9/2016 4:37 AM, Stephen Boyd wrote:
> On 11/07, Ritesh Harjani wrote:
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index 8ef44a2a..42f42aa 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -137,8 +137,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
>> writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
>>
>> /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
>> - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
>> - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
>> + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
>> + config |= CORE_CK_OUT_EN;
>> + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
>>
>> /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
>> rc = msm_dll_poll_ck_out_en(host, 1);
>> @@ -305,6 +306,7 @@ static int msm_init_cm_dll(struct sdhci_host *host)
>> struct mmc_host *mmc = host->mmc;
>> int wait_cnt = 50;
>> unsigned long flags;
>> + u32 config = 0;
>
> It needs to be initialized?
No, will make it uninitialized.
>
>>
>> spin_lock_irqsave(&host->lock, flags);
>>
>> @@ -313,33 +315,40 @@ static int msm_init_cm_dll(struct sdhci_host *host)
>> * tuning is in progress. Keeping PWRSAVE ON may
>> * turn off the clock.
>> */
>> - writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
>> - & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
>> + config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
>
> It's written here unconditionally though?
>
>> + config &= ~CORE_CLK_PWRSAVE;
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [kvm-unit-tests PATCH v4 06/11] arm/arm64: add initial gicv2 support
From: Andre Przywara @ 2016-11-09 11:53 UTC (permalink / raw)
To: Andrew Jones, kvm, kvmarm, qemu-devel, qemu-arm
Cc: pbonzini, peter.maydell, alex.bennee, marc.zyngier, eric.auger,
christoffer.dall
In-Reply-To: <1478636499-14339-7-git-send-email-drjones@redhat.com>
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> Add some gicv2 support. This just adds init and enable
> functions, allowing unit tests to start messing with it.
>
> Signed-off-by: Andrew Jones <drjones@redhat.com>
>
> ---
> v4:
> - only take defines from kernel we need now [Andre]
> - moved defines to asm/gic.h so they'll be shared with v3 [drew]
> - simplify enable by not caring if we reinit the distributor [drew]
> - init all GICD_INT_DEF_PRI_X4 registers [Eric]
> ---
> arm/Makefile.common | 1 +
> lib/arm/asm/gic-v2.h | 28 +++++++++++++++++++
> lib/arm/asm/gic.h | 44 +++++++++++++++++++++++++++++
> lib/arm/gic.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++
> lib/arm64/asm/gic-v2.h | 1 +
> lib/arm64/asm/gic.h | 1 +
> 6 files changed, 150 insertions(+)
> create mode 100644 lib/arm/asm/gic-v2.h
> create mode 100644 lib/arm/asm/gic.h
> create mode 100644 lib/arm/gic.c
> create mode 100644 lib/arm64/asm/gic-v2.h
> create mode 100644 lib/arm64/asm/gic.h
>
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index ccb554d9251a..41239c37e092 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -42,6 +42,7 @@ cflatobjs += lib/arm/mmu.o
> cflatobjs += lib/arm/bitops.o
> cflatobjs += lib/arm/psci.o
> cflatobjs += lib/arm/smp.o
> +cflatobjs += lib/arm/gic.o
>
> libeabi = lib/arm/libeabi.a
> eabiobjs = lib/arm/eabi_compat.o
> diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h
> new file mode 100644
> index 000000000000..f91530f88355
> --- /dev/null
> +++ b/lib/arm/asm/gic-v2.h
> @@ -0,0 +1,28 @@
> +/*
> + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h
> + *
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM_GIC_V2_H_
> +#define _ASMARM_GIC_V2_H_
> +
> +#ifndef _ASMARM_GIC_H_
> +#error Do not directly include <asm/gic-v2.h>. Include <asm/gic.h>
> +#endif
> +
> +struct gicv2_data {
> + void *dist_base;
> + void *cpu_base;
> + unsigned int irq_nr;
> +};
> +extern struct gicv2_data gicv2_data;
> +
> +#define gicv2_dist_base() (gicv2_data.dist_base)
> +#define gicv2_cpu_base() (gicv2_data.cpu_base)
> +
> +extern int gicv2_init(void);
> +extern void gicv2_enable_defaults(void);
> +
> +#endif /* _ASMARM_GIC_V2_H_ */
> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
> new file mode 100644
> index 000000000000..ec92f1064dc0
> --- /dev/null
> +++ b/lib/arm/asm/gic.h
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM_GIC_H_
> +#define _ASMARM_GIC_H_
> +
> +#include <asm/gic-v2.h>
> +
> +#define GIC_CPU_CTRL 0x00
> +#define GIC_CPU_PRIMASK 0x04
> +
> +#define GICC_ENABLE 0x1
> +#define GICC_INT_PRI_THRESHOLD 0xf0
> +
> +#define GIC_DIST_CTRL 0x000
> +#define GIC_DIST_CTR 0x004
I think we shouldn't copy this old name here, which stems from pre-GICv2
times (PL390?), IIUC. Both GIC specs talk of TYPER here.
Also if we now use the same defines for both the GICv2 and GICv3
distributor, we should really stick with the (modern) spec naming, which
is GICD_CTRL, GICD_TYPER and so on. Same for the CPU interface (GICC_CTRL).
In the kernel these names are used for GICv3, but we didn't bother to
adjust the existing GICv2 names to avoid pointless churn.
Also that would line up with the bit field defines below.
Cheers,
Andre.
> +#define GIC_DIST_ENABLE_SET 0x100
> +#define GIC_DIST_PRI 0x400
> +
> +#define GICD_ENABLE 0x1
> +#define GICD_INT_EN_SET_SGI 0x0000ffff
> +#define GICD_INT_DEF_PRI 0xa0
> +#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
> + (GICD_INT_DEF_PRI << 16) |\
> + (GICD_INT_DEF_PRI << 8) |\
> + GICD_INT_DEF_PRI)
> +
> +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
> +
> +#ifndef __ASSEMBLY__
> +
> +/*
> + * gic_init will try to find all known gics, and then
> + * initialize the gic data for the one found.
> + * returns
> + * 0 : no gic was found
> + * > 0 : the gic version of the gic found
> + */
> +extern int gic_init(void);
> +
> +#endif /* !__ASSEMBLY__ */
> +#endif /* _ASMARM_GIC_H_ */
> diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> new file mode 100644
> index 000000000000..91d78c9a0cc2
> --- /dev/null
> +++ b/lib/arm/gic.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include <devicetree.h>
> +#include <asm/gic.h>
> +#include <asm/io.h>
> +
> +struct gicv2_data gicv2_data;
> +
> +/*
> + * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> + */
> +static bool
> +gic_get_dt_bases(const char *compatible, void **base1, void **base2)
> +{
> + struct dt_pbus_reg reg;
> + struct dt_device gic;
> + struct dt_bus bus;
> + int node, ret;
> +
> + dt_bus_init_defaults(&bus);
> + dt_device_init(&gic, &bus, NULL);
> +
> + node = dt_device_find_compatible(&gic, compatible);
> + assert(node >= 0 || node == -FDT_ERR_NOTFOUND);
> +
> + if (node == -FDT_ERR_NOTFOUND)
> + return false;
> +
> + dt_device_bind_node(&gic, node);
> +
> + ret = dt_pbus_translate(&gic, 0, ®);
> + assert(ret == 0);
> + *base1 = ioremap(reg.addr, reg.size);
> +
> + ret = dt_pbus_translate(&gic, 1, ®);
> + assert(ret == 0);
> + *base2 = ioremap(reg.addr, reg.size);
> +
> + return true;
> +}
> +
> +int gicv2_init(void)
> +{
> + return gic_get_dt_bases("arm,cortex-a15-gic",
> + &gicv2_data.dist_base, &gicv2_data.cpu_base);
> +}
> +
> +int gic_init(void)
> +{
> + if (gicv2_init())
> + return 2;
> + return 0;
> +}
> +
> +void gicv2_enable_defaults(void)
> +{
> + void *dist = gicv2_dist_base();
> + void *cpu_base = gicv2_cpu_base();
> + unsigned int i;
> +
> + gicv2_data.irq_nr = GICD_TYPER_IRQS(readl(dist + GIC_DIST_CTR));
> + if (gicv2_data.irq_nr > 1020)
> + gicv2_data.irq_nr = 1020;
> +
> + for (i = 0; i < gicv2_data.irq_nr; i += 4)
> + writel(GICD_INT_DEF_PRI_X4, dist + i + GIC_DIST_PRI);
> +
> + writel(GICD_INT_EN_SET_SGI, dist + GIC_DIST_ENABLE_SET);
> + writel(GICD_ENABLE, dist + GIC_DIST_CTRL);
> + writel(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
> + writel(GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
> +}
> diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h
> new file mode 100644
> index 000000000000..52226624a209
> --- /dev/null
> +++ b/lib/arm64/asm/gic-v2.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic-v2.h"
> diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h
> new file mode 100644
> index 000000000000..e5eb302a31b4
> --- /dev/null
> +++ b/lib/arm64/asm/gic.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic.h"
>
^ permalink raw reply
* [3rdparty][PATCH] linux-boundary: Enable TRACER support
From: Fabio Berton @ 2016-11-09 11:52 UTC (permalink / raw)
To: meta-freescale
Fix warning:
/
| WARNING: lttng-modules-2.8.0+gitAUTOINC+6e4fc6f36d-r0 do_package:
| lttng-modules: no modules were created; this may be due to
| CONFIG_TRACEPOINTS not being enabled in your kernel.
\
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
---
recipes-kernel/linux/linux-boundary-4.1.15/defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/recipes-kernel/linux/linux-boundary-4.1.15/defconfig b/recipes-kernel/linux/linux-boundary-4.1.15/defconfig
index f1564db..94f6821 100644
--- a/recipes-kernel/linux/linux-boundary-4.1.15/defconfig
+++ b/recipes-kernel/linux/linux-boundary-4.1.15/defconfig
@@ -401,7 +401,7 @@ CONFIG_FRAME_WARN=2048
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
+CONFIG_FUNCTION_TRACER=y
CONFIG_STRICT_DEVMEM=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_SET_MODULE_RONX=y
--
2.1.4
^ permalink raw reply related
* Re: [PATCH v2 1/3] hwmon: (mcp3021) rework for DT support
From: Guenter Roeck @ 2016-11-09 11:53 UTC (permalink / raw)
To: Clemens Gruber, linux-hwmon
Cc: Rob Herring, Jean Delvare, devicetree, linux-doc, linux-kernel
In-Reply-To: <20161027223345.16733-1-clemens.gruber@pqgruber.com>
On 10/27/2016 03:33 PM, Clemens Gruber wrote:
> Support setting the reference voltage from the device tree.
> Rework of driver structure, put chip specific data in a separate
> structure and assign it depending on device id from platform data or
> DT match.
>
> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
> ---
> Documentation/hwmon/mcp3021 | 6 ++
> drivers/hwmon/mcp3021.c | 145 ++++++++++++++++++++++++++++++++------------
> 2 files changed, 111 insertions(+), 40 deletions(-)
>
> diff --git a/Documentation/hwmon/mcp3021 b/Documentation/hwmon/mcp3021
> index 74a6b72..be252b7 100644
> --- a/Documentation/hwmon/mcp3021
> +++ b/Documentation/hwmon/mcp3021
> @@ -12,6 +12,7 @@ Supported chips:
> Authors:
> Mingkai Hu
> Sven Schuchmann <schuchmann@schleissheimer.de>
> + Clemens Gruber <clemens.gruber@pqgruber.com>
>
> Description
> -----------
> @@ -27,3 +28,8 @@ Communication to the MCP3021/MCP3221 is performed using a 2-wire I2C
> compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
> available. The default I2C device address is 0x4d (contact the Microchip
> factory for additional address options).
> +
> +The reference voltage used in the conversion can be set through platform data
> +in millivolt (for backwards compatibility) or via device tree in microvolt.
> +Please refer to Documentation/devicetree/bindings/i2c/mcp3021.txt for details
> +about the device tree bindings.
> diff --git a/drivers/hwmon/mcp3021.c b/drivers/hwmon/mcp3021.c
> index 972444a..a8cf97f 100644
> --- a/drivers/hwmon/mcp3021.c
> +++ b/drivers/hwmon/mcp3021.c
> @@ -4,6 +4,7 @@
> * Copyright (C) 2008-2009, 2012 Freescale Semiconductor, Inc.
> * Author: Mingkai Hu <Mingkai.hu@freescale.com>
> * Reworked by Sven Schuchmann <schuchmann@schleissheimer.de>
> + * Copyright (C) 2016 Clemens Gruber <clemens.gruber@pqgruber.com>
> *
> * This driver export the value of analog input voltage to sysfs, the
> * voltage unit is mV. Through the sysfs interface, lm-sensors tool
> @@ -22,37 +23,56 @@
> #include <linux/i2c.h>
> #include <linux/err.h>
> #include <linux/device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>
> -/* Vdd info */
> +/* Vdd / reference voltage in millivolt */
> #define MCP3021_VDD_MAX 5500
> #define MCP3021_VDD_MIN 2700
> -#define MCP3021_VDD_REF 3300
> -
> -/* output format */
> -#define MCP3021_SAR_SHIFT 2
> -#define MCP3021_SAR_MASK 0x3ff
> -#define MCP3021_OUTPUT_RES 10 /* 10-bit resolution */
> -
> -#define MCP3221_SAR_SHIFT 0
> -#define MCP3221_SAR_MASK 0xfff
> -#define MCP3221_OUTPUT_RES 12 /* 12-bit resolution */
> +#define MCP3021_VDD_DEFAULT 3300
>
There is no technical reason to drop / change those defines and use literals
in the code instead. Please don't.
> enum chips {
> mcp3021,
> mcp3221
> };
>
> +struct mcp3021_chip_info {
> + u16 sar_shift;
> + u16 sar_mask;
> + u8 output_res;
> +};
> +
> /*
> * Client data (each client gets its own)
> */
> struct mcp3021_data {
> struct device *hwmon_dev;
> - u32 vdd; /* device power supply */
> - u16 sar_shift;
> - u16 sar_mask;
> - u8 output_res;
> + const struct mcp3021_chip_info *chip_info;
> + u32 vdd; /* device power supply and reference voltage in millivolt */
> };
>
> +static const struct mcp3021_chip_info mcp3021_chip_info_tbl[] = {
> + [mcp3021] = {
> + .sar_shift = 2,
> + .sar_mask = 0x3ff,
> + .output_res = 10, /* 10-bit resolution */
> + },
> + [mcp3221] = {
> + .sar_shift = 0,
> + .sar_mask = 0xfff,
> + .output_res = 12, /* 12-bit resolution */
> + },
> +};
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id of_mcp3021_match[] = {
> + { .compatible = "microchip,mcp3021", .data = (void *)mcp3021 },
> + { .compatible = "microchip,mcp3221", .data = (void *)mcp3221 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, of_mcp3021_match);
> +#endif
> +
> static int mcp3021_read16(struct i2c_client *client)
> {
> struct mcp3021_data *data = i2c_get_clientdata(client);
> @@ -73,14 +93,15 @@ static int mcp3021_read16(struct i2c_client *client)
> * The ten-bit output code is composed of the lower 4-bit of the
> * first byte and the upper 6-bit of the second byte.
> */
> - reg = (reg >> data->sar_shift) & data->sar_mask;
> + reg = (reg >> data->chip_info->sar_shift) & data->chip_info->sar_mask;
>
> return reg;
> }
>
> static inline u16 volts_from_reg(struct mcp3021_data *data, u16 val)
> {
> - return DIV_ROUND_CLOSEST(data->vdd * val, 1 << data->output_res);
> + return DIV_ROUND_CLOSEST(data->vdd * val,
> + 1 << data->chip_info->output_res);
> }
>
> static ssize_t show_in_input(struct device *dev, struct device_attribute *attr,
> @@ -101,44 +122,85 @@ static ssize_t show_in_input(struct device *dev, struct device_attribute *attr,
>
> static DEVICE_ATTR(in0_input, S_IRUGO, show_in_input, NULL);
>
> -static int mcp3021_probe(struct i2c_client *client,
> +#ifdef CONFIG_OF
> +static int mcp3021_probe_dt(struct i2c_client *client,
> const struct i2c_device_id *id)
> {
> - int err;
> - struct mcp3021_data *data = NULL;
> + struct mcp3021_data *data = i2c_get_clientdata(client);
> + struct device_node *np = client->dev.of_node;
> + const struct of_device_id *match;
> + int devid, ret;
>
> - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
> + match = of_match_device(of_mcp3021_match, &client->dev);
> + if (!match)
> return -ENODEV;
>
> - data = devm_kzalloc(&client->dev, sizeof(struct mcp3021_data),
> - GFP_KERNEL);
> - if (!data)
> - return -ENOMEM;
> -
> - i2c_set_clientdata(client, data);
> + devid = (int)(uintptr_t)match->data;
> + data->chip_info = &mcp3021_chip_info_tbl[devid];
>
> - switch (id->driver_data) {
> - case mcp3021:
> - data->sar_shift = MCP3021_SAR_SHIFT;
> - data->sar_mask = MCP3021_SAR_MASK;
> - data->output_res = MCP3021_OUTPUT_RES;
> - break;
> -
> - case mcp3221:
> - data->sar_shift = MCP3221_SAR_SHIFT;
> - data->sar_mask = MCP3221_SAR_MASK;
> - data->output_res = MCP3221_OUTPUT_RES;
> - break;
> + ret = of_property_read_u32(np, "reference-voltage-microvolt",
> + &data->vdd);
> + if (ret) {
> + /* fallback */
> + data->vdd = MCP3021_VDD_DEFAULT;
> + return 0;
> }
>
> + /* Convert microvolt from DT to millivolt used in the formula */
> + data->vdd /= 1000;
> +
> + if (data->vdd > MCP3021_VDD_MAX || data->vdd < MCP3021_VDD_MIN)
> + return -EINVAL;
> +
> + return 0;
> +}
> +#else
> +static int mcp3021_probe_dt(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + return 1;
> +}
> +#endif
> +
> +static int mcp3021_probe_pdata(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct mcp3021_data *data = i2c_get_clientdata(client);
> +
> + data->chip_info = &mcp3021_chip_info_tbl[id->driver_data];
> +
> if (dev_get_platdata(&client->dev)) {
> data->vdd = *(u32 *)dev_get_platdata(&client->dev);
> if (data->vdd > MCP3021_VDD_MAX || data->vdd < MCP3021_VDD_MIN)
> return -EINVAL;
> } else {
> - data->vdd = MCP3021_VDD_REF;
> + data->vdd = MCP3021_VDD_DEFAULT;
> }
>
> + return 0;
> +}
> +
> +static int mcp3021_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct mcp3021_data *data = NULL;
> + int err;
> +
> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
> + return -ENODEV;
> +
> + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + i2c_set_clientdata(client, data);
> +
> + err = mcp3021_probe_dt(client, id);
> + if (err > 0)
> + mcp3021_probe_pdata(client, id);
> + else if (err < 0)
> + return err;
> +
Most other drivers generate the platform data from devicetree data.
if (of_match_device())
pdata = probe_dt();
else
pdata = dev_get_platdata();
In this case, this is even simpler, since the only devicetree property is the reference
voltage.
if (np) {
if (of_property_read_u32(np, "reference-voltage-microvolt", &vdd))
vdd = MCP3021_VDD_REF * 1000;
vdd /= 1000;
devid = (int)(uintptr_t)match->data;
} else {
u32 *pdata = dev_get_platdata(&client->dev);
if (pdata)
vdd = *pdata;
else
vdd = MCP3021_VDD_REF;
devid = id->driver_data;
}
You should actually be able to use id->driver_data directly in both cases since it is
always passed as parameter from the i2c core.
This would be much simpler than your suggested changes.
> err = sysfs_create_file(&client->dev.kobj, &dev_attr_in0_input.attr);
> if (err)
> return err;
> @@ -176,6 +238,9 @@ MODULE_DEVICE_TABLE(i2c, mcp3021_id);
> static struct i2c_driver mcp3021_driver = {
> .driver = {
> .name = "mcp3021",
> +#ifdef CONFIG_OF
> + .of_match_table = of_match_ptr(of_mcp3021_match),
> +#endif
of_match_ptr() is already protected with #ifdef CONFIG_OF and otherwise
returns NULL, so this ifdef is unnecessary.
> },
> .probe = mcp3021_probe,
> .remove = mcp3021_remove,
>
^ permalink raw reply
* Re: [PATCH v2 1/3] hwmon: (mcp3021) rework for DT support
From: Guenter Roeck @ 2016-11-09 11:53 UTC (permalink / raw)
To: Clemens Gruber, linux-hwmon-u79uwXL29TY76Z2rM5mHXA
Cc: Rob Herring, Jean Delvare, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161027223345.16733-1-clemens.gruber-lZxf/j91sTNWk0Htik3J/w@public.gmane.org>
On 10/27/2016 03:33 PM, Clemens Gruber wrote:
> Support setting the reference voltage from the device tree.
> Rework of driver structure, put chip specific data in a separate
> structure and assign it depending on device id from platform data or
> DT match.
>
> Signed-off-by: Clemens Gruber <clemens.gruber-lZxf/j91sTNWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/hwmon/mcp3021 | 6 ++
> drivers/hwmon/mcp3021.c | 145 ++++++++++++++++++++++++++++++++------------
> 2 files changed, 111 insertions(+), 40 deletions(-)
>
> diff --git a/Documentation/hwmon/mcp3021 b/Documentation/hwmon/mcp3021
> index 74a6b72..be252b7 100644
> --- a/Documentation/hwmon/mcp3021
> +++ b/Documentation/hwmon/mcp3021
> @@ -12,6 +12,7 @@ Supported chips:
> Authors:
> Mingkai Hu
> Sven Schuchmann <schuchmann-ogs+x9k7xBHcX9AoAvVr1bNAH6kLmebB@public.gmane.org>
> + Clemens Gruber <clemens.gruber-lZxf/j91sTNWk0Htik3J/w@public.gmane.org>
>
> Description
> -----------
> @@ -27,3 +28,8 @@ Communication to the MCP3021/MCP3221 is performed using a 2-wire I2C
> compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
> available. The default I2C device address is 0x4d (contact the Microchip
> factory for additional address options).
> +
> +The reference voltage used in the conversion can be set through platform data
> +in millivolt (for backwards compatibility) or via device tree in microvolt.
> +Please refer to Documentation/devicetree/bindings/i2c/mcp3021.txt for details
> +about the device tree bindings.
> diff --git a/drivers/hwmon/mcp3021.c b/drivers/hwmon/mcp3021.c
> index 972444a..a8cf97f 100644
> --- a/drivers/hwmon/mcp3021.c
> +++ b/drivers/hwmon/mcp3021.c
> @@ -4,6 +4,7 @@
> * Copyright (C) 2008-2009, 2012 Freescale Semiconductor, Inc.
> * Author: Mingkai Hu <Mingkai.hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> * Reworked by Sven Schuchmann <schuchmann-ogs+x9k7xBHcX9AoAvVr1bNAH6kLmebB@public.gmane.org>
> + * Copyright (C) 2016 Clemens Gruber <clemens.gruber-lZxf/j91sTNWk0Htik3J/w@public.gmane.org>
> *
> * This driver export the value of analog input voltage to sysfs, the
> * voltage unit is mV. Through the sysfs interface, lm-sensors tool
> @@ -22,37 +23,56 @@
> #include <linux/i2c.h>
> #include <linux/err.h>
> #include <linux/device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>
> -/* Vdd info */
> +/* Vdd / reference voltage in millivolt */
> #define MCP3021_VDD_MAX 5500
> #define MCP3021_VDD_MIN 2700
> -#define MCP3021_VDD_REF 3300
> -
> -/* output format */
> -#define MCP3021_SAR_SHIFT 2
> -#define MCP3021_SAR_MASK 0x3ff
> -#define MCP3021_OUTPUT_RES 10 /* 10-bit resolution */
> -
> -#define MCP3221_SAR_SHIFT 0
> -#define MCP3221_SAR_MASK 0xfff
> -#define MCP3221_OUTPUT_RES 12 /* 12-bit resolution */
> +#define MCP3021_VDD_DEFAULT 3300
>
There is no technical reason to drop / change those defines and use literals
in the code instead. Please don't.
> enum chips {
> mcp3021,
> mcp3221
> };
>
> +struct mcp3021_chip_info {
> + u16 sar_shift;
> + u16 sar_mask;
> + u8 output_res;
> +};
> +
> /*
> * Client data (each client gets its own)
> */
> struct mcp3021_data {
> struct device *hwmon_dev;
> - u32 vdd; /* device power supply */
> - u16 sar_shift;
> - u16 sar_mask;
> - u8 output_res;
> + const struct mcp3021_chip_info *chip_info;
> + u32 vdd; /* device power supply and reference voltage in millivolt */
> };
>
> +static const struct mcp3021_chip_info mcp3021_chip_info_tbl[] = {
> + [mcp3021] = {
> + .sar_shift = 2,
> + .sar_mask = 0x3ff,
> + .output_res = 10, /* 10-bit resolution */
> + },
> + [mcp3221] = {
> + .sar_shift = 0,
> + .sar_mask = 0xfff,
> + .output_res = 12, /* 12-bit resolution */
> + },
> +};
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id of_mcp3021_match[] = {
> + { .compatible = "microchip,mcp3021", .data = (void *)mcp3021 },
> + { .compatible = "microchip,mcp3221", .data = (void *)mcp3221 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, of_mcp3021_match);
> +#endif
> +
> static int mcp3021_read16(struct i2c_client *client)
> {
> struct mcp3021_data *data = i2c_get_clientdata(client);
> @@ -73,14 +93,15 @@ static int mcp3021_read16(struct i2c_client *client)
> * The ten-bit output code is composed of the lower 4-bit of the
> * first byte and the upper 6-bit of the second byte.
> */
> - reg = (reg >> data->sar_shift) & data->sar_mask;
> + reg = (reg >> data->chip_info->sar_shift) & data->chip_info->sar_mask;
>
> return reg;
> }
>
> static inline u16 volts_from_reg(struct mcp3021_data *data, u16 val)
> {
> - return DIV_ROUND_CLOSEST(data->vdd * val, 1 << data->output_res);
> + return DIV_ROUND_CLOSEST(data->vdd * val,
> + 1 << data->chip_info->output_res);
> }
>
> static ssize_t show_in_input(struct device *dev, struct device_attribute *attr,
> @@ -101,44 +122,85 @@ static ssize_t show_in_input(struct device *dev, struct device_attribute *attr,
>
> static DEVICE_ATTR(in0_input, S_IRUGO, show_in_input, NULL);
>
> -static int mcp3021_probe(struct i2c_client *client,
> +#ifdef CONFIG_OF
> +static int mcp3021_probe_dt(struct i2c_client *client,
> const struct i2c_device_id *id)
> {
> - int err;
> - struct mcp3021_data *data = NULL;
> + struct mcp3021_data *data = i2c_get_clientdata(client);
> + struct device_node *np = client->dev.of_node;
> + const struct of_device_id *match;
> + int devid, ret;
>
> - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
> + match = of_match_device(of_mcp3021_match, &client->dev);
> + if (!match)
> return -ENODEV;
>
> - data = devm_kzalloc(&client->dev, sizeof(struct mcp3021_data),
> - GFP_KERNEL);
> - if (!data)
> - return -ENOMEM;
> -
> - i2c_set_clientdata(client, data);
> + devid = (int)(uintptr_t)match->data;
> + data->chip_info = &mcp3021_chip_info_tbl[devid];
>
> - switch (id->driver_data) {
> - case mcp3021:
> - data->sar_shift = MCP3021_SAR_SHIFT;
> - data->sar_mask = MCP3021_SAR_MASK;
> - data->output_res = MCP3021_OUTPUT_RES;
> - break;
> -
> - case mcp3221:
> - data->sar_shift = MCP3221_SAR_SHIFT;
> - data->sar_mask = MCP3221_SAR_MASK;
> - data->output_res = MCP3221_OUTPUT_RES;
> - break;
> + ret = of_property_read_u32(np, "reference-voltage-microvolt",
> + &data->vdd);
> + if (ret) {
> + /* fallback */
> + data->vdd = MCP3021_VDD_DEFAULT;
> + return 0;
> }
>
> + /* Convert microvolt from DT to millivolt used in the formula */
> + data->vdd /= 1000;
> +
> + if (data->vdd > MCP3021_VDD_MAX || data->vdd < MCP3021_VDD_MIN)
> + return -EINVAL;
> +
> + return 0;
> +}
> +#else
> +static int mcp3021_probe_dt(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + return 1;
> +}
> +#endif
> +
> +static int mcp3021_probe_pdata(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct mcp3021_data *data = i2c_get_clientdata(client);
> +
> + data->chip_info = &mcp3021_chip_info_tbl[id->driver_data];
> +
> if (dev_get_platdata(&client->dev)) {
> data->vdd = *(u32 *)dev_get_platdata(&client->dev);
> if (data->vdd > MCP3021_VDD_MAX || data->vdd < MCP3021_VDD_MIN)
> return -EINVAL;
> } else {
> - data->vdd = MCP3021_VDD_REF;
> + data->vdd = MCP3021_VDD_DEFAULT;
> }
>
> + return 0;
> +}
> +
> +static int mcp3021_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct mcp3021_data *data = NULL;
> + int err;
> +
> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
> + return -ENODEV;
> +
> + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + i2c_set_clientdata(client, data);
> +
> + err = mcp3021_probe_dt(client, id);
> + if (err > 0)
> + mcp3021_probe_pdata(client, id);
> + else if (err < 0)
> + return err;
> +
Most other drivers generate the platform data from devicetree data.
if (of_match_device())
pdata = probe_dt();
else
pdata = dev_get_platdata();
In this case, this is even simpler, since the only devicetree property is the reference
voltage.
if (np) {
if (of_property_read_u32(np, "reference-voltage-microvolt", &vdd))
vdd = MCP3021_VDD_REF * 1000;
vdd /= 1000;
devid = (int)(uintptr_t)match->data;
} else {
u32 *pdata = dev_get_platdata(&client->dev);
if (pdata)
vdd = *pdata;
else
vdd = MCP3021_VDD_REF;
devid = id->driver_data;
}
You should actually be able to use id->driver_data directly in both cases since it is
always passed as parameter from the i2c core.
This would be much simpler than your suggested changes.
> err = sysfs_create_file(&client->dev.kobj, &dev_attr_in0_input.attr);
> if (err)
> return err;
> @@ -176,6 +238,9 @@ MODULE_DEVICE_TABLE(i2c, mcp3021_id);
> static struct i2c_driver mcp3021_driver = {
> .driver = {
> .name = "mcp3021",
> +#ifdef CONFIG_OF
> + .of_match_table = of_match_ptr(of_mcp3021_match),
> +#endif
of_match_ptr() is already protected with #ifdef CONFIG_OF and otherwise
returns NULL, so this ifdef is unnecessary.
> },
> .probe = mcp3021_probe,
> .remove = mcp3021_remove,
>
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [Qemu-devel] [kvm-unit-tests PATCH v4 06/11] arm/arm64: add initial gicv2 support
From: Andre Przywara @ 2016-11-09 11:53 UTC (permalink / raw)
To: Andrew Jones, kvm, kvmarm, qemu-devel, qemu-arm
Cc: pbonzini, peter.maydell, alex.bennee, marc.zyngier, eric.auger,
christoffer.dall
In-Reply-To: <1478636499-14339-7-git-send-email-drjones@redhat.com>
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> Add some gicv2 support. This just adds init and enable
> functions, allowing unit tests to start messing with it.
>
> Signed-off-by: Andrew Jones <drjones@redhat.com>
>
> ---
> v4:
> - only take defines from kernel we need now [Andre]
> - moved defines to asm/gic.h so they'll be shared with v3 [drew]
> - simplify enable by not caring if we reinit the distributor [drew]
> - init all GICD_INT_DEF_PRI_X4 registers [Eric]
> ---
> arm/Makefile.common | 1 +
> lib/arm/asm/gic-v2.h | 28 +++++++++++++++++++
> lib/arm/asm/gic.h | 44 +++++++++++++++++++++++++++++
> lib/arm/gic.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++
> lib/arm64/asm/gic-v2.h | 1 +
> lib/arm64/asm/gic.h | 1 +
> 6 files changed, 150 insertions(+)
> create mode 100644 lib/arm/asm/gic-v2.h
> create mode 100644 lib/arm/asm/gic.h
> create mode 100644 lib/arm/gic.c
> create mode 100644 lib/arm64/asm/gic-v2.h
> create mode 100644 lib/arm64/asm/gic.h
>
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index ccb554d9251a..41239c37e092 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -42,6 +42,7 @@ cflatobjs += lib/arm/mmu.o
> cflatobjs += lib/arm/bitops.o
> cflatobjs += lib/arm/psci.o
> cflatobjs += lib/arm/smp.o
> +cflatobjs += lib/arm/gic.o
>
> libeabi = lib/arm/libeabi.a
> eabiobjs = lib/arm/eabi_compat.o
> diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h
> new file mode 100644
> index 000000000000..f91530f88355
> --- /dev/null
> +++ b/lib/arm/asm/gic-v2.h
> @@ -0,0 +1,28 @@
> +/*
> + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h
> + *
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM_GIC_V2_H_
> +#define _ASMARM_GIC_V2_H_
> +
> +#ifndef _ASMARM_GIC_H_
> +#error Do not directly include <asm/gic-v2.h>. Include <asm/gic.h>
> +#endif
> +
> +struct gicv2_data {
> + void *dist_base;
> + void *cpu_base;
> + unsigned int irq_nr;
> +};
> +extern struct gicv2_data gicv2_data;
> +
> +#define gicv2_dist_base() (gicv2_data.dist_base)
> +#define gicv2_cpu_base() (gicv2_data.cpu_base)
> +
> +extern int gicv2_init(void);
> +extern void gicv2_enable_defaults(void);
> +
> +#endif /* _ASMARM_GIC_V2_H_ */
> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
> new file mode 100644
> index 000000000000..ec92f1064dc0
> --- /dev/null
> +++ b/lib/arm/asm/gic.h
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM_GIC_H_
> +#define _ASMARM_GIC_H_
> +
> +#include <asm/gic-v2.h>
> +
> +#define GIC_CPU_CTRL 0x00
> +#define GIC_CPU_PRIMASK 0x04
> +
> +#define GICC_ENABLE 0x1
> +#define GICC_INT_PRI_THRESHOLD 0xf0
> +
> +#define GIC_DIST_CTRL 0x000
> +#define GIC_DIST_CTR 0x004
I think we shouldn't copy this old name here, which stems from pre-GICv2
times (PL390?), IIUC. Both GIC specs talk of TYPER here.
Also if we now use the same defines for both the GICv2 and GICv3
distributor, we should really stick with the (modern) spec naming, which
is GICD_CTRL, GICD_TYPER and so on. Same for the CPU interface (GICC_CTRL).
In the kernel these names are used for GICv3, but we didn't bother to
adjust the existing GICv2 names to avoid pointless churn.
Also that would line up with the bit field defines below.
Cheers,
Andre.
> +#define GIC_DIST_ENABLE_SET 0x100
> +#define GIC_DIST_PRI 0x400
> +
> +#define GICD_ENABLE 0x1
> +#define GICD_INT_EN_SET_SGI 0x0000ffff
> +#define GICD_INT_DEF_PRI 0xa0
> +#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
> + (GICD_INT_DEF_PRI << 16) |\
> + (GICD_INT_DEF_PRI << 8) |\
> + GICD_INT_DEF_PRI)
> +
> +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
> +
> +#ifndef __ASSEMBLY__
> +
> +/*
> + * gic_init will try to find all known gics, and then
> + * initialize the gic data for the one found.
> + * returns
> + * 0 : no gic was found
> + * > 0 : the gic version of the gic found
> + */
> +extern int gic_init(void);
> +
> +#endif /* !__ASSEMBLY__ */
> +#endif /* _ASMARM_GIC_H_ */
> diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> new file mode 100644
> index 000000000000..91d78c9a0cc2
> --- /dev/null
> +++ b/lib/arm/gic.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include <devicetree.h>
> +#include <asm/gic.h>
> +#include <asm/io.h>
> +
> +struct gicv2_data gicv2_data;
> +
> +/*
> + * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> + */
> +static bool
> +gic_get_dt_bases(const char *compatible, void **base1, void **base2)
> +{
> + struct dt_pbus_reg reg;
> + struct dt_device gic;
> + struct dt_bus bus;
> + int node, ret;
> +
> + dt_bus_init_defaults(&bus);
> + dt_device_init(&gic, &bus, NULL);
> +
> + node = dt_device_find_compatible(&gic, compatible);
> + assert(node >= 0 || node == -FDT_ERR_NOTFOUND);
> +
> + if (node == -FDT_ERR_NOTFOUND)
> + return false;
> +
> + dt_device_bind_node(&gic, node);
> +
> + ret = dt_pbus_translate(&gic, 0, ®);
> + assert(ret == 0);
> + *base1 = ioremap(reg.addr, reg.size);
> +
> + ret = dt_pbus_translate(&gic, 1, ®);
> + assert(ret == 0);
> + *base2 = ioremap(reg.addr, reg.size);
> +
> + return true;
> +}
> +
> +int gicv2_init(void)
> +{
> + return gic_get_dt_bases("arm,cortex-a15-gic",
> + &gicv2_data.dist_base, &gicv2_data.cpu_base);
> +}
> +
> +int gic_init(void)
> +{
> + if (gicv2_init())
> + return 2;
> + return 0;
> +}
> +
> +void gicv2_enable_defaults(void)
> +{
> + void *dist = gicv2_dist_base();
> + void *cpu_base = gicv2_cpu_base();
> + unsigned int i;
> +
> + gicv2_data.irq_nr = GICD_TYPER_IRQS(readl(dist + GIC_DIST_CTR));
> + if (gicv2_data.irq_nr > 1020)
> + gicv2_data.irq_nr = 1020;
> +
> + for (i = 0; i < gicv2_data.irq_nr; i += 4)
> + writel(GICD_INT_DEF_PRI_X4, dist + i + GIC_DIST_PRI);
> +
> + writel(GICD_INT_EN_SET_SGI, dist + GIC_DIST_ENABLE_SET);
> + writel(GICD_ENABLE, dist + GIC_DIST_CTRL);
> + writel(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
> + writel(GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
> +}
> diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h
> new file mode 100644
> index 000000000000..52226624a209
> --- /dev/null
> +++ b/lib/arm64/asm/gic-v2.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic-v2.h"
> diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h
> new file mode 100644
> index 000000000000..e5eb302a31b4
> --- /dev/null
> +++ b/lib/arm64/asm/gic.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic.h"
>
^ permalink raw reply
* Re: [PATCH v6 02/14] clk: qcom: Add rcg ops to return floor value closest to the requested rate
From: Ritesh Harjani @ 2016-11-09 11:53 UTC (permalink / raw)
To: Stephen Boyd
Cc: ulf.hansson, linux-mmc, adrian.hunter, shawn.lin, devicetree,
linux-clk, david.brown, andy.gross, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd, kdorfman,
david.griego, stummala, venkatg, rnayak, pramod.gurav
In-Reply-To: <20161108230217.GM16026@codeaurora.org>
Hi Stephen,
Thanks for the review.
On 11/9/2016 4:32 AM, Stephen Boyd wrote:
> On 11/07, Ritesh Harjani wrote:
>> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
>> index b904c33..1b3e8d2 100644
>> --- a/drivers/clk/qcom/clk-rcg.h
>> +++ b/drivers/clk/qcom/clk-rcg.h
>> @@ -173,6 +173,7 @@ struct clk_rcg2 {
>> #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
>>
>> extern const struct clk_ops clk_rcg2_ops;
>> +extern const struct clk_ops clk_rcg2_floor_ops;
>> extern const struct clk_ops clk_rcg2_shared_ops;
>> extern const struct clk_ops clk_edp_pixel_ops;
>> extern const struct clk_ops clk_byte_ops;
>> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
>> index a071bba..04433a6 100644
>> --- a/drivers/clk/qcom/clk-rcg2.c
>> +++ b/drivers/clk/qcom/clk-rcg2.c
>> @@ -47,6 +47,11 @@
>> #define N_REG 0xc
>> #define D_REG 0x10
>>
>> +enum {
>> + FLOOR,
>> + CEIL,
>> +};
>
> Give it a name.
Yes, sure. I will keep it as freq_policy.
>
>> +
>> static int clk_rcg2_is_enabled(struct clk_hw *hw)
>> {
>> struct clk_rcg2 *rcg = to_clk_rcg2(hw);
>> @@ -176,15 +181,25 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
>> return calc_rate(parent_rate, m, n, mode, hid_div);
>> }
>>
>> -static int _freq_tbl_determine_rate(struct clk_hw *hw,
>> - const struct freq_tbl *f, struct clk_rate_request *req)
>> +static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
>> + struct clk_rate_request *req, bool match)
>
> Use the enum please. Also name it something besides match.
> policy?
Sure. (freq_policy)
>
>> {
>> unsigned long clk_flags, rate = req->rate;
>> struct clk_hw *p;
>> struct clk_rcg2 *rcg = to_clk_rcg2(hw);
>> int index;
>>
>> - f = qcom_find_freq(f, rate);
>> + switch (match) {
>> + case FLOOR:
>> + f = qcom_find_freq_floor(f, rate);
>> + break;
>> + case CEIL:
>> + f = qcom_find_freq(f, rate);
>> + break;
>> + default:
>> + return -EINVAL;
>> + };
>> +
>> if (!f)
>> return -EINVAL;
>>
>> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
>> index fffcbaf..cf6b87f 100644
>> --- a/drivers/clk/qcom/common.c
>> +++ b/drivers/clk/qcom/common.c
>> @@ -46,6 +46,32 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
>> }
>> EXPORT_SYMBOL_GPL(qcom_find_freq);
>>
>> +const
>> +struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
>
> We can't put const and struct on the same line?
Ok sure.
>
>> + unsigned long rate)
>> +{
>> + int size = 0;
>> +
>> + if (!f)
>> + return NULL;
>> +
>> + /*
>> + * The freq table has entries in the ascending order of frequencies
>> + * To find the floor for a given frequency, we need to do a reverse
>> + * lookup of the table
>> + */
>> + for (; f->freq; f++, size++)
>> + ;
>> +
>> + for (f--; size; f--, size--)
>> + if (rate >= f->freq)
>> + return f;
>
> I don't understand why we can't do this while iterating through
> the table. We shouldn't need to size up the frequency table first.
>
> const struct freq_tbl *best = NULL;
>
> for ( ; f->freq; f++) {
> if (rate >= f->freq)
> best = f->freq;
> else
> break;
> }
>
> return best;
>
Yes, will do above change.
>> +
>> + /* could not find any rates lower than *rate* */
>
>> + return NULL;
>> +}
>> +EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v2] leds: ledtrig-heartbeat: Make top brightness adjustable
From: Hans de Goede @ 2016-11-09 11:51 UTC (permalink / raw)
To: Jacek Anaszewski, linux-leds; +Cc: linux-kernel, Pavel Machek
In-Reply-To: <1478688226-4158-1-git-send-email-j.anaszewski@samsung.com>
Hi,
On 09-11-16 11:43, Jacek Anaszewski wrote:
> LED class heartbeat trigger allowed only for blinking with max_brightness
> value. This patch adds more flexibility by exploiting part of LED core
> software blink infrastructure.
>
> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
> Cc: Pavel Machek <pavel@ucw.cz>
> Cc: Hans de Goede <hdegoede@redhat.com>
> ---
> Changes since v1:
> - after introduction of work_flags and new_blink_brightness properties
> this patch needs to be updated
Patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
>
> drivers/leds/trigger/ledtrig-heartbeat.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/leds/trigger/ledtrig-heartbeat.c b/drivers/leds/trigger/ledtrig-heartbeat.c
> index c9f3862..e6f2f8b 100644
> --- a/drivers/leds/trigger/ledtrig-heartbeat.c
> +++ b/drivers/leds/trigger/ledtrig-heartbeat.c
> @@ -43,6 +43,9 @@ static void led_heartbeat_function(unsigned long data)
> return;
> }
>
> + if (test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE, &led_cdev->work_flags))
> + led_cdev->blink_brightness = led_cdev->new_blink_brightness;
> +
> /* acts like an actual heart beat -- ie thump-thump-pause... */
> switch (heartbeat_data->phase) {
> case 0:
> @@ -59,26 +62,26 @@ static void led_heartbeat_function(unsigned long data)
> delay = msecs_to_jiffies(70);
> heartbeat_data->phase++;
> if (!heartbeat_data->invert)
> - brightness = led_cdev->max_brightness;
> + brightness = led_cdev->blink_brightness;
> break;
> case 1:
> delay = heartbeat_data->period / 4 - msecs_to_jiffies(70);
> heartbeat_data->phase++;
> if (heartbeat_data->invert)
> - brightness = led_cdev->max_brightness;
> + brightness = led_cdev->blink_brightness;
> break;
> case 2:
> delay = msecs_to_jiffies(70);
> heartbeat_data->phase++;
> if (!heartbeat_data->invert)
> - brightness = led_cdev->max_brightness;
> + brightness = led_cdev->blink_brightness;
> break;
> default:
> delay = heartbeat_data->period - heartbeat_data->period / 4 -
> msecs_to_jiffies(70);
> heartbeat_data->phase = 0;
> if (heartbeat_data->invert)
> - brightness = led_cdev->max_brightness;
> + brightness = led_cdev->blink_brightness;
> break;
> }
>
> @@ -133,7 +136,10 @@ static void heartbeat_trig_activate(struct led_classdev *led_cdev)
> setup_timer(&heartbeat_data->timer,
> led_heartbeat_function, (unsigned long) led_cdev);
> heartbeat_data->phase = 0;
> + if (!led_cdev->blink_brightness)
> + led_cdev->blink_brightness = led_cdev->max_brightness;
> led_heartbeat_function(heartbeat_data->timer.data);
> + set_bit(LED_BLINK_SW, &led_cdev->work_flags);
> led_cdev->activated = true;
> }
>
> @@ -145,6 +151,7 @@ static void heartbeat_trig_deactivate(struct led_classdev *led_cdev)
> del_timer_sync(&heartbeat_data->timer);
> device_remove_file(led_cdev->dev, &dev_attr_invert);
> kfree(heartbeat_data);
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> led_cdev->activated = false;
> }
> }
>
^ permalink raw reply
* Re: [PATCH v2] led: core: Use atomic bit-field for the blink-flags
From: Hans de Goede @ 2016-11-09 11:51 UTC (permalink / raw)
To: Jacek Anaszewski, linux-leds; +Cc: linux-kernel
In-Reply-To: <1478613535-32564-1-git-send-email-j.anaszewski@samsung.com>
Hi,
On 08-11-16 14:58, Jacek Anaszewski wrote:
> From: Hans de Goede <hdegoede@redhat.com>
>
> All the LED_BLINK* flags are accessed read-modify-write from e.g.
> led_set_brightness and led_blink_set_oneshot while both
> set_brightness_work and the blink_timer may be running.
>
> If these race then the modify step done by one of them may be lost,
> switch the LED_BLINK* flags to a new atomic work_flags bit-field
> to avoid this race.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
> ---
> Changes since v1:
> - keep set_brightness_work in linux/leds.h
Thank you.
Patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
>
> drivers/leds/led-class.c | 1 +
> drivers/leds/led-core.c | 52 +++++++++++++++++++++++++-----------------------
> include/linux/leds.h | 24 ++++++++++++----------
> 3 files changed, 42 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index c8d2d67..b12f861 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -212,6 +212,7 @@ int led_classdev_register(struct device *parent, struct led_classdev *led_cdev)
> return -ENODEV;
> }
>
> + led_cdev->work_flags = 0;
> #ifdef CONFIG_LEDS_TRIGGERS
> init_rwsem(&led_cdev->trigger_lock);
> #endif
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index e2e5cc7..620257a 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -61,12 +61,13 @@ static void led_timer_function(unsigned long data)
>
> if (!led_cdev->blink_delay_on || !led_cdev->blink_delay_off) {
> led_set_brightness_nosleep(led_cdev, LED_OFF);
> - led_cdev->flags &= ~LED_BLINK_SW;
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> return;
> }
>
> - if (led_cdev->flags & LED_BLINK_ONESHOT_STOP) {
> - led_cdev->flags &= ~(LED_BLINK_ONESHOT_STOP | LED_BLINK_SW);
> + if (test_and_clear_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags)) {
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> return;
> }
>
> @@ -81,10 +82,9 @@ static void led_timer_function(unsigned long data)
> * Do it only if there is no pending blink brightness
> * change, to avoid overwriting the new value.
> */
> - if (!(led_cdev->flags & LED_BLINK_BRIGHTNESS_CHANGE))
> + if (!test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> + &led_cdev->work_flags))
> led_cdev->blink_brightness = brightness;
> - else
> - led_cdev->flags &= ~LED_BLINK_BRIGHTNESS_CHANGE;
> brightness = LED_OFF;
> delay = led_cdev->blink_delay_off;
> }
> @@ -95,13 +95,15 @@ static void led_timer_function(unsigned long data)
> * the final blink state so that the led is toggled each delay_on +
> * delay_off milliseconds in worst case.
> */
> - if (led_cdev->flags & LED_BLINK_ONESHOT) {
> - if (led_cdev->flags & LED_BLINK_INVERT) {
> + if (test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags)) {
> + if (test_bit(LED_BLINK_INVERT, &led_cdev->work_flags)) {
> if (brightness)
> - led_cdev->flags |= LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags);
> } else {
> if (!brightness)
> - led_cdev->flags |= LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags);
> }
> }
>
> @@ -114,10 +116,9 @@ static void set_brightness_delayed(struct work_struct *ws)
> container_of(ws, struct led_classdev, set_brightness_work);
> int ret = 0;
>
> - if (led_cdev->flags & LED_BLINK_DISABLE) {
> + if (test_and_clear_bit(LED_BLINK_DISABLE, &led_cdev->work_flags)) {
> led_cdev->delayed_set_value = LED_OFF;
> led_stop_software_blink(led_cdev);
> - led_cdev->flags &= ~LED_BLINK_DISABLE;
> }
>
> ret = __led_set_brightness(led_cdev, led_cdev->delayed_set_value);
> @@ -160,7 +161,7 @@ static void led_set_software_blink(struct led_classdev *led_cdev,
> return;
> }
>
> - led_cdev->flags |= LED_BLINK_SW;
> + set_bit(LED_BLINK_SW, &led_cdev->work_flags);
> mod_timer(&led_cdev->blink_timer, jiffies + 1);
> }
>
> @@ -169,7 +170,7 @@ static void led_blink_setup(struct led_classdev *led_cdev,
> unsigned long *delay_on,
> unsigned long *delay_off)
> {
> - if (!(led_cdev->flags & LED_BLINK_ONESHOT) &&
> + if (!test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) &&
> led_cdev->blink_set &&
> !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> return;
> @@ -196,8 +197,8 @@ void led_blink_set(struct led_classdev *led_cdev,
> {
> del_timer_sync(&led_cdev->blink_timer);
>
> - led_cdev->flags &= ~LED_BLINK_ONESHOT;
> - led_cdev->flags &= ~LED_BLINK_ONESHOT_STOP;
> + clear_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags);
> + clear_bit(LED_BLINK_ONESHOT_STOP, &led_cdev->work_flags);
>
> led_blink_setup(led_cdev, delay_on, delay_off);
> }
> @@ -208,17 +209,17 @@ void led_blink_set_oneshot(struct led_classdev *led_cdev,
> unsigned long *delay_off,
> int invert)
> {
> - if ((led_cdev->flags & LED_BLINK_ONESHOT) &&
> + if (test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) &&
> timer_pending(&led_cdev->blink_timer))
> return;
>
> - led_cdev->flags |= LED_BLINK_ONESHOT;
> - led_cdev->flags &= ~LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags);
> + clear_bit(LED_BLINK_ONESHOT_STOP, &led_cdev->work_flags);
>
> if (invert)
> - led_cdev->flags |= LED_BLINK_INVERT;
> + set_bit(LED_BLINK_INVERT, &led_cdev->work_flags);
> else
> - led_cdev->flags &= ~LED_BLINK_INVERT;
> + clear_bit(LED_BLINK_INVERT, &led_cdev->work_flags);
>
> led_blink_setup(led_cdev, delay_on, delay_off);
> }
> @@ -229,7 +230,7 @@ void led_stop_software_blink(struct led_classdev *led_cdev)
> del_timer_sync(&led_cdev->blink_timer);
> led_cdev->blink_delay_on = 0;
> led_cdev->blink_delay_off = 0;
> - led_cdev->flags &= ~LED_BLINK_SW;
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> }
> EXPORT_SYMBOL_GPL(led_stop_software_blink);
>
> @@ -240,17 +241,18 @@ void led_set_brightness(struct led_classdev *led_cdev,
> * If software blink is active, delay brightness setting
> * until the next timer tick.
> */
> - if (led_cdev->flags & LED_BLINK_SW) {
> + if (test_bit(LED_BLINK_SW, &led_cdev->work_flags)) {
> /*
> * If we need to disable soft blinking delegate this to the
> * work queue task to avoid problems in case we are called
> * from hard irq context.
> */
> if (brightness == LED_OFF) {
> - led_cdev->flags |= LED_BLINK_DISABLE;
> + set_bit(LED_BLINK_DISABLE, &led_cdev->work_flags);
> schedule_work(&led_cdev->set_brightness_work);
> } else {
> - led_cdev->flags |= LED_BLINK_BRIGHTNESS_CHANGE;
> + set_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> + &led_cdev->work_flags);
> led_cdev->blink_brightness = brightness;
> }
> return;
> diff --git a/include/linux/leds.h b/include/linux/leds.h
> index eebcd8c..1dc69df 100644
> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -43,16 +43,20 @@ struct led_classdev {
> #define LED_UNREGISTERING (1 << 1)
> /* Upper 16 bits reflect control information */
> #define LED_CORE_SUSPENDRESUME (1 << 16)
> -#define LED_BLINK_SW (1 << 17)
> -#define LED_BLINK_ONESHOT (1 << 18)
> -#define LED_BLINK_ONESHOT_STOP (1 << 19)
> -#define LED_BLINK_INVERT (1 << 20)
> -#define LED_BLINK_BRIGHTNESS_CHANGE (1 << 21)
> -#define LED_BLINK_DISABLE (1 << 22)
> -#define LED_SYSFS_DISABLE (1 << 23)
> -#define LED_DEV_CAP_FLASH (1 << 24)
> -#define LED_HW_PLUGGABLE (1 << 25)
> -#define LED_PANIC_INDICATOR (1 << 26)
> +#define LED_SYSFS_DISABLE (1 << 17)
> +#define LED_DEV_CAP_FLASH (1 << 18)
> +#define LED_HW_PLUGGABLE (1 << 19)
> +#define LED_PANIC_INDICATOR (1 << 20)
> +
> + /* set_brightness_work / blink_timer flags, atomic, private. */
> + unsigned long work_flags;
> +
> +#define LED_BLINK_SW 0
> +#define LED_BLINK_ONESHOT 1
> +#define LED_BLINK_ONESHOT_STOP 2
> +#define LED_BLINK_INVERT 3
> +#define LED_BLINK_BRIGHTNESS_CHANGE 4
> +#define LED_BLINK_DISABLE 5
>
> /* Set LED brightness level
> * Must not sleep. Use brightness_set_blocking for drivers
>
^ permalink raw reply
* Re: [PATCH v2] leds: ledtrig-heartbeat: Make top brightness adjustable
From: Jacek Anaszewski @ 2016-11-09 11:50 UTC (permalink / raw)
To: Pavel Machek; +Cc: linux-leds, linux-kernel, Hans de Goede
In-Reply-To: <20161109112117.GA1556@amd>
Hi Pavel,
On 11/09/2016 12:21 PM, Pavel Machek wrote:
> On Wed 2016-11-09 11:43:46, Jacek Anaszewski wrote:
>> LED class heartbeat trigger allowed only for blinking with max_brightness
>> value. This patch adds more flexibility by exploiting part of LED core
>> software blink infrastructure.
>>
>> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
>
> Acked-by: Pavel Machek <pavel@ucw.cz>
>
Thanks. Reapplied on top of blink_brightness race fixes.
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH] pinctrl: intel: Configure pin as GPIO input when used directly through irqchip
From: Jarkko Nikula @ 2016-11-09 11:48 UTC (permalink / raw)
To: Mika Westerberg, Linus Walleij; +Cc: Heikki Krogerus, linux-gpio
In-Reply-To: <20161109112231.122700-1-mika.westerberg@linux.intel.com>
On 11/09/2016 01:22 PM, Mika Westerberg wrote:
> If a pin is used directly through irqchip without requesting it first as
> GPIO, it might be in wrong mode (for example input buffer disabled). This
> means the user may never get any interrupts.
>
> Fix this by configuring the pin as GPIO input when its type is first set in
> irq_set_type().
>
> Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
> Since we probably need to do this for cherryview and baytrail pinctrl
> drivers as well, I'm thinking is this something that the GPIO core could do
> automatically?
>
> drivers/pinctrl/intel/pinctrl-intel.c | 46 +++++++++++++++++++++++------------
> 1 file changed, 31 insertions(+), 15 deletions(-)
>
Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
^ permalink raw reply
* Re: [PATCH for-4.8] libxc: fix unmap of ACPI guest memory region
From: Andrew Cooper @ 2016-11-09 11:51 UTC (permalink / raw)
To: Roger Pau Monne, xen-devel; +Cc: Ian Jackson, Boris Ostrovsky, Wei Liu
In-Reply-To: <1478622135-22192-1-git-send-email-roger.pau@citrix.com>
On 08/11/16 16:22, Roger Pau Monne wrote:
> Commit fac7f7 changed the value of ptr so that it points to the right memory
> area, taking the page offset into account, but failed to remove this when
> doing the unmap, which caused the region to not be unmapped. Fix this by not
> modifying ptr and instead adding the page offset directly in the memcpy
> call.
Coverity-ID: 1394285
(Coverity scan has now run and found this issue, so we have a public ID
to use).
> Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* Re: [PATCH/RFC v2] tools/leds: Add led_notify_mon program for monitoring brightness changes
From: Hans de Goede @ 2016-11-09 11:50 UTC (permalink / raw)
To: Jacek Anaszewski, linux-leds; +Cc: linux-kernel
In-Reply-To: <1478604994-29854-1-git-send-email-j.anaszewski@samsung.com>
Hi,
On 08-11-16 12:36, Jacek Anaszewski wrote:
> LED subsystem supports POLLPRI on "brightness" sysfs file of LED
> class devices. This tool demonstrates how to use the feature.
>
> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
Thank you.
Patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
> ---
> Changes since v1:
> - added lseek which fixes non-blocking poll() behaviour
>
> tools/leds/Makefile | 4 +--
> tools/leds/led_notify_mon.c | 83 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 85 insertions(+), 2 deletions(-)
> create mode 100644 tools/leds/led_notify_mon.c
>
> diff --git a/tools/leds/Makefile b/tools/leds/Makefile
> index c03a79e..0fa948a 100644
> --- a/tools/leds/Makefile
> +++ b/tools/leds/Makefile
> @@ -3,11 +3,11 @@
> CC = $(CROSS_COMPILE)gcc
> CFLAGS = -Wall -Wextra -g -I../../include/uapi
>
> -all: uledmon
> +all: uledmon led_notify_mon
> %: %.c
> $(CC) $(CFLAGS) -o $@ $^
>
> clean:
> - $(RM) uledmon
> + $(RM) uledmon led_notify_mon
>
> .PHONY: all clean
> diff --git a/tools/leds/led_notify_mon.c b/tools/leds/led_notify_mon.c
> new file mode 100644
> index 0000000..8b6e6f9
> --- /dev/null
> +++ b/tools/leds/led_notify_mon.c
> @@ -0,0 +1,83 @@
> +/*
> + * led_notify_mon.c
> + *
> + * This program monitors LED brightness change notifications,
> + * either having its origin in the hardware or in the software.
> + * A timestamp and brightness value is printed each time the brightness changes.
> + *
> + * Usage: led_notify_mon <device-name>
> + *
> + * <device-name> is the name of the LED class device to be monitored. Pressing
> + * CTRL+C will exit.
> + */
> +
> +#include <fcntl.h>
> +#include <poll.h>
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <time.h>
> +#include <unistd.h>
> +
> +#include <linux/uleds.h>
> +
> +int main(int argc, char const *argv[])
> +{
> + int fd, ret;
> + char brightness_file_path[LEDS_MAX_NAME_SIZE + 11];
> + struct pollfd pollfd;
> + struct timespec ts;
> + char buf[11];
> +
> + if (argc != 2) {
> + fprintf(stderr, "Requires <device-name> argument\n");
> + return 1;
> + }
> +
> + snprintf(brightness_file_path, LEDS_MAX_NAME_SIZE,
> + "/sys/class/leds/%s/brightness", argv[1]);
> +
> + fd = open(brightness_file_path, O_RDONLY);
> + if (fd == -1) {
> + printf("Failed to open %s file\n", brightness_file_path);
> + return 1;
> + }
> +
> + ret = read(fd, buf, sizeof(buf));
> + if (ret < 0) {
> + printf("Failed to read %s file\n", brightness_file_path);
> + goto err_read;
> + }
> +
> + pollfd.fd = fd;
> + pollfd.events = POLLPRI;
> +
> + while (1) {
> + ret = poll(&pollfd, 1, -1);
> + if (ret == -1) {
> + printf("Failed to poll %s file (%d)\n",
> + brightness_file_path, ret);
> + ret = 1;
> + break;
> + }
> +
> + clock_gettime(CLOCK_MONOTONIC, &ts);
> +
> + ret = read(fd, buf, sizeof(buf));
> + if (ret < 0)
> + break;
> +
> + ret = lseek(pollfd.fd, 0, SEEK_SET);
> + if (ret < 0) {
> + printf("lseek failed (%d)\n", ret);
> + break;
> + }
> +
> + printf("[%ld.%09ld] %d\n", ts.tv_sec, ts.tv_nsec, atoi(buf));
> + }
> +
> +err_read:
> + close(fd);
> +
> + return ret;
> +}
>
^ permalink raw reply
* [U-Boot] [PATCH v2 7/7] imx6: icorem6: Rename engicam icorem6 defconfig files
From: Jagan Teki @ 2016-11-09 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Rename defconfig files for better compatible with
respective board names and dts files.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
board/engicam/icorem6/MAINTAINERS | 6 ++-
board/engicam/icorem6/README | 19 ++++-----
...re_mmc_defconfig => imx6dl_icore_mmc_defconfig} | 0
..._nand_defconfig => imx6dl_icore_nand_defconfig} | 0
configs/imx6q_icore_mmc_defconfig | 46 ++++++++++++++++++++++
configs/imx6q_icore_nand_defconfig | 41 +++++++++++++++++++
6 files changed, 98 insertions(+), 14 deletions(-)
rename configs/{imx6qdl_icore_mmc_defconfig => imx6dl_icore_mmc_defconfig} (100%)
rename configs/{imx6qdl_icore_nand_defconfig => imx6dl_icore_nand_defconfig} (100%)
create mode 100644 configs/imx6q_icore_mmc_defconfig
create mode 100644 configs/imx6q_icore_nand_defconfig
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
index a425afb..0ef3a2c 100644
--- a/board/engicam/icorem6/MAINTAINERS
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -3,5 +3,7 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/icorem6
F: include/configs/imx6qdl_icore.h
-F: configs/imx6qdl_icore_mmc_defconfig
-F: configs/imx6qdl_icore_nand_defconfig
+F: configs/imx6q_icore_mmc_defconfig
+F: configs/imx6q_icore_nand_defconfig
+F: configs/imx6dl_icore_mmc_defconfig
+F: configs/imx6dl_icore_nand_defconfig
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
index e47f85f..6461c0a 100644
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@@ -1,18 +1,16 @@
-How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
+How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
-----------------------------------------------------------------------------
-- Configure U-Boot for Engicam i.CoreM6 QDL:
-
$ make mrproper
-$ make imx6qdl_icore_mmc_defconfig
-
-- Build for i.CoreM6 DualLite/Solo
-$ make
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
+$ make imx6q_icore_mmc_defconfig
-- Build for i.CoreM6 Quad/Dual
+- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
+$ make imx6dl_icore_mmc_defconfig
-$ make DEVICE_TREE=imx6q-icore
+- Build U-Boot
+$ make
This will generate the SPL image called SPL and the u-boot-dtb.img.
@@ -33,6 +31,3 @@ MMC Boot: JM3 Closed
- Insert the micro SD card in the board, power it up and U-Boot messages should
come up.
-
-- Note: For loading Linux on Quad/Dual modules set the dtb as
- icorem6qdl> setenv fdt_file imx6q-icore.dtb
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6dl_icore_mmc_defconfig
similarity index 100%
rename from configs/imx6qdl_icore_mmc_defconfig
rename to configs/imx6dl_icore_mmc_defconfig
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
similarity index 100%
rename from configs/imx6qdl_icore_nand_defconfig
rename to configs/imx6dl_icore_nand_defconfig
diff --git a/configs/imx6q_icore_mmc_defconfig b/configs/imx6q_icore_mmc_defconfig
new file mode 100644
index 0000000..adbd4e7
--- /dev/null
+++ b/configs/imx6q_icore_mmc_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FEC_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_VIDEO=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
new file mode 100644
index 0000000..03f5c62
--- /dev/null
+++ b/configs/imx6q_icore_nand_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FEC_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_NAND_MXS=y
+CONFIG_IMX_THERMAL=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_VIDEO=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_DMA_SUPPORT=y
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 6/7] arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial support
From: Jagan Teki @ 2016-11-09 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Boot from MMC:
-------------
U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07)
Trying to boot from MMC1
U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530)
CPU: Freescale i.MX6DL rev1.3 at 792 MHz
Reset cause: POR
Model: Engicam i.CoreM6 DualLite/Solo RQS Starter Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
icorem6qdl-rqs>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6dl-icore-rqs.dts | 50 ++++++++++++++++++++++++++++++++++
board/engicam/icorem6_rqs/MAINTAINERS | 1 +
board/engicam/icorem6_rqs/README | 7 +++--
configs/imx6dl_icore_rqs_mmc_defconfig | 38 ++++++++++++++++++++++++++
5 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-icore-rqs.dts
create mode 100644 configs/imx6dl_icore_rqs_mmc_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index be38c83..31c412e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -284,6 +284,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6dl-icore.dtb \
+ imx6dl-icore-rqs.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6ul-geam-kit.dtb
diff --git a/arch/arm/dts/imx6dl-icore-rqs.dts b/arch/arm/dts/imx6dl-icore-rqs.dts
new file mode 100644
index 0000000..0f1de3f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-rqs.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore-rqs.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit";
+ compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
+};
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS
index 4c6bd62..0556211 100644
--- a/board/engicam/icorem6_rqs/MAINTAINERS
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/engicam/icorem6_rqs
F: include/configs/imx6qdl_icore_rqs.h
F: configs/imx6q_icore_rqs_mmc_defconfig
+F: configs/imx6dl_icore_rqs_mmc_defconfig
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
index f94e6e1..ccce622 100644
--- a/board/engicam/icorem6_rqs/README
+++ b/board/engicam/icorem6_rqs/README
@@ -1,11 +1,14 @@
-How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit:
-----------------------------------------------------------------
+How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
+----------------------------------------------------------------------------------
$ make mrproper
- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
$ make imx6q_icore_rqs_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
+$ make imx6dl_icore_rqs_mmc_defconfig
+
- Build U-Boot
$ make
diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig
new file mode 100644
index 0000000..7fc7fa0
--- /dev/null
+++ b/configs/imx6dl_icore_rqs_mmc_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs"
+CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_UART=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 5/7] arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial support
From: Jagan Teki @ 2016-11-09 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Boot from MMC:
-------------
U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44)
Trying to boot from MMC1
U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530)
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Reset cause: POR
Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
icorem6qdl-rqs>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 11 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6q-icore-rqs.dts | 50 ++++
arch/arm/dts/imx6qdl-icore-rqs.dtsi | 83 +++++++
board/engicam/icorem6_rqs/Kconfig | 12 +
board/engicam/icorem6_rqs/MAINTAINERS | 6 +
board/engicam/icorem6_rqs/Makefile | 6 +
board/engicam/icorem6_rqs/README | 30 +++
board/engicam/icorem6_rqs/icorem6_rqs.c | 402 ++++++++++++++++++++++++++++++++
configs/imx6q_icore_rqs_mmc_defconfig | 38 +++
include/configs/imx6qdl_icore_rqs.h | 124 ++++++++++
11 files changed, 763 insertions(+)
create mode 100644 arch/arm/dts/imx6q-icore-rqs.dts
create mode 100644 arch/arm/dts/imx6qdl-icore-rqs.dtsi
create mode 100644 board/engicam/icorem6_rqs/Kconfig
create mode 100644 board/engicam/icorem6_rqs/MAINTAINERS
create mode 100644 board/engicam/icorem6_rqs/Makefile
create mode 100644 board/engicam/icorem6_rqs/README
create mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c
create mode 100644 configs/imx6q_icore_rqs_mmc_defconfig
create mode 100644 include/configs/imx6qdl_icore_rqs.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 2cc4893..b5e40ea 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -107,6 +107,16 @@ config TARGET_MX6Q_ICORE
select DM_THERMAL
select SUPPORT_SPL
+config TARGET_MX6Q_ICORE_RQS
+ bool "Support Engicam i.Core RQS"
+ select MX6QDL
+ select OF_CONTROL
+ select DM
+ select DM_GPIO
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select DM
@@ -249,6 +259,7 @@ source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/engicam/geam6ul/Kconfig"
source "board/engicam/icorem6/Kconfig"
+source "board/engicam/icorem6_rqs/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d79b2e2..be38c83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -285,6 +285,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6dl-icore.dtb \
imx6q-icore.dtb \
+ imx6q-icore-rqs.dtb \
imx6ul-geam-kit.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
diff --git a/arch/arm/dts/imx6q-icore-rqs.dts b/arch/arm/dts/imx6q-icore-rqs.dts
new file mode 100644
index 0000000..9fa6ba0
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-rqs.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore-rqs.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit";
+ compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
new file mode 100644
index 0000000..343ab35
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
+ >;
+ };
+};
diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig
new file mode 100644
index 0000000..1352c68
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE_RQS
+
+config SYS_BOARD
+ default "icorem6_rqs"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx6qdl_icore_rqs"
+
+endif
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS
new file mode 100644
index 0000000..4c6bd62
--- /dev/null
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -0,0 +1,6 @@
+ICOREM6QDL_RQS BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/engicam/icorem6_rqs
+F: include/configs/imx6qdl_icore_rqs.h
+F: configs/imx6q_icore_rqs_mmc_defconfig
diff --git a/board/engicam/icorem6_rqs/Makefile b/board/engicam/icorem6_rqs/Makefile
new file mode 100644
index 0000000..2e3933c
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := icorem6_rqs.o
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
new file mode 100644
index 0000000..f94e6e1
--- /dev/null
+++ b/board/engicam/icorem6_rqs/README
@@ -0,0 +1,30 @@
+How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit:
+----------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
+$ make imx6q_icore_rqs_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c
new file mode 100644
index 0000000..0368191
--- /dev/null
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -0,0 +1,402 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+int board_early_init_f(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR, 1, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc1_pads);
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_b0ds = 0x30,
+ .grp_b1ds = 0x30,
+ .grp_b2ds = 0x30,
+ .grp_b3ds = 0x30,
+ .grp_b4ds = 0x30,
+ .grp_b5ds = 0x30,
+ .grp_b6ds = 0x30,
+ .grp_b7ds = 0x30,
+ .grp_addds = 0x30,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ctlds = 0x30,
+ .grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x30,
+ .dram_sdcke1 = 0x30,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x30,
+ .grp_ctlds = 0x30,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x28,
+ .grp_b1ds = 0x28,
+ .grp_b2ds = 0x28,
+ .grp_b3ds = 0x28,
+ .grp_b4ds = 0x28,
+ .grp_b5ds = 0x28,
+ .grp_b6ds = 0x28,
+ .grp_b7ds = 0x28,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x000E0009,
+ .p0_mpwldectrl1 = 0x0018000E,
+ .p1_mpwldectrl0 = 0x00000007,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x43280334,
+ .p0_mpdgctrl1 = 0x031C0314,
+ .p1_mpdgctrl0 = 0x4318031C,
+ .p1_mpdgctrl1 = 0x030C0258,
+ .p0_mprddlctl = 0x3E343A40,
+ .p1_mprddlctl = 0x383C3844,
+ .p0_mpwrdlctl = 0x40404440,
+ .p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+ .ddr_type = DDR_TYPE_DDR3,
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 2,
+ .rtt_wr = 2,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001F0024,
+ .p0_mpwldectrl1 = 0x00110018,
+ .p1_mpwldectrl0 = 0x001F0024,
+ .p1_mpwldectrl1 = 0x00110018,
+ .p0_mpdgctrl0 = 0x4230022C,
+ .p0_mpdgctrl1 = 0x02180220,
+ .p1_mpdgctrl0 = 0x42440248,
+ .p1_mpdgctrl1 = 0x02300238,
+ .p0_mprddlctl = 0x44444A48,
+ .p1_mprddlctl = 0x46484A42,
+ .p0_mpwrdlctl = 0x38383234,
+ .p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00003F3F, &ccm->CCGR0);
+ writel(0x0030FC00, &ccm->CCGR1);
+ writel(0x000FC000, &ccm->CCGR2);
+ writel(0x3F300000, &ccm->CCGR3);
+ writel(0xFF00F300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003CC, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6solo()) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dl()) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dq()) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig
new file mode 100644
index 0000000..eeecef8
--- /dev/null
+++ b/configs/imx6q_icore_rqs_mmc_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
+CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_UART=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h
new file mode 100644
index 0000000..5b4f2c9
--- /dev/null
+++ b/include/configs/imx6qdl_icore_rqs.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H
+#define __IMX6QLD_ICORE_RQS_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART4_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 4/7] net: fec: Zap local mac variable
From: Jagan Teki @ 2016-11-09 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Call dev->enetaddr or pdata->enetaddr directly
in eth_ops instead of local mac variable.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/net/fec_mxc.c | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 09433df..787823c 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -934,9 +934,8 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
static int fec_recv(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
- uchar *mac = dev->enetaddr;
- return _fec_recv(fec, mac);
+ return _fec_recv(fec, dev->enetaddr);
}
static int fec_send(struct eth_device *dev, void *packet, int length)
@@ -956,17 +955,15 @@ static void fec_halt(struct eth_device *dev)
static int fec_set_hwaddr(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
- uchar *mac = dev->enetaddr;
- return _fec_set_hwaddr(fec, mac);
+ return _fec_set_hwaddr(fec, dev->enetaddr);
}
static int fec_init(struct eth_device *dev, bd_t *bd)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
- uchar *mac = dev->enetaddr;
- return _fec_init(fec, mac);
+ return _fec_init(fec, dev->enetaddr);
}
static int fec_get_hwaddr(int dev_id, unsigned char *mac)
@@ -1142,9 +1139,8 @@ static int fec_set_hwaddr(struct udevice *dev)
{
struct fec_priv *fec = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- uchar *mac = pdata->enetaddr;
- return _fec_set_hwaddr(fec, mac);
+ return _fec_set_hwaddr(fec, pdata->enetaddr);
}
static void fec_halt(struct udevice *dev)
@@ -1158,9 +1154,8 @@ static int fec_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct fec_priv *fec = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- uchar *mac = pdata->enetaddr;
- return _fec_recv(fec, mac);
+ return _fec_recv(fec, pdata->enetaddr);
}
static int fec_send(struct udevice *dev, void *packet, int length)
@@ -1174,9 +1169,8 @@ static int fec_init(struct udevice *dev)
{
struct fec_priv *fec = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- uchar *mac = pdata->enetaddr;
- return _fec_init(fec, mac);
+ return _fec_init(fec, pdata->enetaddr);
}
static const struct eth_ops fecmxc_ops = {
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 3/7] dm: net: fec: Add .read_rom_hwaddr
From: Jagan Teki @ 2016-11-09 11:49 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add .read_rom_hwaddr on dm eth_ops.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/net/fec_mxc.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 367bc40..09433df 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -348,12 +348,6 @@ static void fec_rbd_clean(int last, struct fec_bd *prbd)
writew(0, &prbd->data_length);
}
-static int fec_get_hwaddr(int dev_id, unsigned char *mac)
-{
- imx_get_mac_from_fuse(dev_id, mac);
- return !is_valid_ethaddr(mac);
-}
-
static int _fec_set_hwaddr(struct fec_priv *fec, uchar *mac)
{
writel(0, &fec->eth->iaddr1);
@@ -975,6 +969,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
return _fec_init(fec, mac);
}
+static int fec_get_hwaddr(int dev_id, unsigned char *mac)
+{
+ imx_get_mac_from_fuse(dev_id, mac);
+ return !is_valid_ethaddr(mac);
+}
+
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
@@ -1128,6 +1128,16 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
#else
+static int fec_read_rom_mac(struct udevice *dev)
+{
+ struct fec_priv *fec = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ imx_get_mac_from_fuse(fec->dev_id, pdata->enetaddr);
+
+ return 0;
+}
+
static int fec_set_hwaddr(struct udevice *dev)
{
struct fec_priv *fec = dev_get_priv(dev);
@@ -1175,6 +1185,7 @@ static const struct eth_ops fecmxc_ops = {
.recv = fec_recv,
.stop = fec_halt,
.write_hwaddr = fec_set_hwaddr,
+ .read_rom_hwaddr = fec_read_rom_mac,
};
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
@@ -1204,7 +1215,6 @@ static int fecmxc_probe(struct udevice *dev)
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
int dev_id = -1;
- unsigned char ethaddr[6];
uint32_t start;
int ret;
@@ -1238,14 +1248,6 @@ static int fecmxc_probe(struct udevice *dev)
fec_reg_setup(priv);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
- ret = fec_get_hwaddr(dev_id, ethaddr);
- if (!ret) {
- debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
- memcpy(pdata->enetaddr, ethaddr, 6);
- if (!getenv("ethaddr"))
- eth_setenv_enetaddr("ethaddr", ethaddr);
- }
-
return 0;
err_timeout:
--
1.9.1
^ permalink raw reply related
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