* [lustre-devel] [PATCH 32/35] staging: lustre: mount: fix lmd_parse() to handle commas in expr_list
From: Greg Kroah-Hartman @ 2016-11-14 15:12 UTC (permalink / raw)
To: James Simmons
Cc: devel, Andreas Dilger, Oleg Drokin, Linux Kernel Mailing List,
Lustre Development List, Jian Yu
In-Reply-To: <1478799065-24841-33-git-send-email-jsimmons@infradead.org>
On Thu, Nov 10, 2016 at 12:31:02PM -0500, James Simmons wrote:
> From: Jian Yu <jian.yu@intel.com>
>
> The lmd_parse() function parses mount options with comma as
> delimiter without considering commas in expr_list as follows
> is a valid LNET nid range syntax:
>
> <expr_list> :== '[' <range_expr> [ ',' <range_expr>] ']'
>
> This patch fixes the above issue by using cfs_parse_nidlist()
> to parse nid range list instead of using class_parse_nid_quiet()
> to parse only one nid.
ugh, parsing mount strings in the kernel in odd ways, what could ever go
wrong...
>
> Signed-off-by: Jian Yu <jian.yu@intel.com>
> Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-5690
> Reviewed-on: http://review.whamcloud.com/17036
> Reviewed-by: Niu Yawei <yawei.niu@intel.com>
> Reviewed-by: Bob Glossman <bob.glossman@intel.com>
> Reviewed-by: Oleg Drokin <oleg.drokin@intel.com>
> Signed-off-by: James Simmons <jsimmons@infradead.org>
> ---
> drivers/staging/lustre/lustre/obdclass/obd_mount.c | 91 ++++++++++++++++++--
> 1 files changed, 85 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/staging/lustre/lustre/obdclass/obd_mount.c b/drivers/staging/lustre/lustre/obdclass/obd_mount.c
> index 2283e92..1eb8e71 100644
> --- a/drivers/staging/lustre/lustre/obdclass/obd_mount.c
> +++ b/drivers/staging/lustre/lustre/obdclass/obd_mount.c
> @@ -871,6 +871,87 @@ static int lmd_parse_mgs(struct lustre_mount_data *lmd, char **ptr)
> return 0;
> }
>
> +/**
> + * Find the first comma delimiter from the specified \a buf and make \a *endh
> + * point to the string starting with the comma. The commas in expression list
> + * [...] will be skipped.
> + *
> + * \param[in] buf a comma-separated string
> + * \param[in] endh a pointer to a pointer that will point to the string
> + * starting with the comma
Please drop this mess of \param, it's not needed and is not kernel-doc
format.
> + *
> + * \retval 0 if comma delimiter is found
> + * \retval 1 if comma delimiter is not found
> + */
> +static int lmd_find_comma(char *buf, char **endh)
> +{
> + char *c = buf;
> + int skip = 0;
> +
> + if (!buf)
> + return 1;
> +
> + while (*c != '\0') {
> + if (*c == '[')
> + skip++;
> + else if (*c == ']')
> + skip--;
> +
> + if (*c == ',' && !skip) {
> + if (endh)
> + *endh = c;
> + return 0;
> + }
> + c++;
> + }
> + return 1;
> +}
Don't we have a standard string search function for finding a string in
a string already in the kernel? Why write another one?
Or better yet, why are you using such a crazy string in the first place
from userspace?
Please fix this up and resend.
thanks,
greg k-h
^ permalink raw reply
* Re: [pcmoore-audit:working-testing 5/6] kernel/audit.c:1457:34: error: 'struct mutex' has no member named 'owner'
From: Paul Moore @ 2016-11-14 15:12 UTC (permalink / raw)
To: Fengguang Wu; +Cc: XXX, linux-audit, kbuild-all
In-Reply-To: <20161114002638.3asa6fkzcggievjs@wfg-t540p.sh.intel.com>
On Sun, Nov 13, 2016 at 7:26 PM, Fengguang Wu <fengguang.wu@intel.com> wrote:
> Hi Paul,
>
> On Fri, Nov 11, 2016 at 08:29:36PM -0500, Paul Moore wrote:
>>
>> On Fri, Nov 11, 2016 at 4:32 PM, kbuild test robot
>> <fengguang.wu@intel.com> wrote:
>>>
>>> tree: git://git.infradead.org/users/pcmoore/audit working-testing
>>> head: a49c8e50dda0d0232dfbed567608724c9666b6ab
>>> commit: 20fb66989030c8f631d687ddaca75b9f7f2ee589 [5/6] Work in progress,
>>> no commit description yet.
>>> config: mips-mtx1_defconfig (attached as .config)
>>> compiler: mipsel-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
>>> reproduce:
>>> wget
>>> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>>> -O ~/bin/make.cross
>>> chmod +x ~/bin/make.cross
>>> git checkout 20fb66989030c8f631d687ddaca75b9f7f2ee589
>>> # save the attached .config to linux build tree
>>> make.cross ARCH=mips
>>>
>>> All error/warnings (new ones prefixed by >>):
>>>
>>> In file included from include/linux/file.h:8:0,
>>> from kernel/audit.c:46:
>>> kernel/audit.c: In function 'audit_log_start':
>>>>>
>>>>> kernel/audit.c:1457:34: error: 'struct mutex' has no member named
>>>>> 'owner'
>>>
>>> (ACCESS_ONCE(audit_cmd_mutex.owner) != current)) {
>>
>>
>> Sorry for the noise folks, I wasn't aware the kbuiler robot was
>> watching this branch/repo. I'll try to move my testing patches to a
>> new repo soon to avoid things like this.
>
> I'm sorry too. The other way is for the robot to only send private
> reports to the committer (ie. you) for the 'working-testing' branch.
> Paul, would you like me to set it up like that?
As long as it is the committer and not the patch author, I think that
would be okay. Would it be possible to do the same for all branches
other than 'next' and 'stable-*'?
If you are tracking the SELinux repository, you could do the same for that repo.
--
paul moore
www.paul-moore.com
^ permalink raw reply
* [PATCH RESEND] spi: atmel: Fix scheduling while atomic
From: Ben Whitten @ 2016-11-14 15:13 UTC (permalink / raw)
To: linux-arm-kernel
A call to clk_get_rate appears to be called in the context of an interrupt,
cache the bus clock for the frequency calculations in transmission.
This fixes a 'BUG: scheduling while atomic' and
'WARNING: CPU: 0 PID: 777 at kernel/sched/core.c:2960 atmel_spi_unlock'
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Steve deRosier <steve.derosier@lairdtech.com>
---
Resending due to missing off the subsystem maintainer in initial submission,
pointed out by Alexandre Belloni, thanks.
---
drivers/spi/spi-atmel.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 8feac59..c281d1a 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -295,6 +295,7 @@ struct atmel_spi {
int irq;
struct clk *clk;
struct platform_device *pdev;
+ unsigned long spi_clk;
struct spi_transfer *current_transfer;
int current_remaining_bytes;
@@ -864,7 +865,7 @@ static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
unsigned long bus_hz;
/* v1 chips start out at half the peripheral bus speed. */
- bus_hz = clk_get_rate(as->clk);
+ bus_hz = as->spi_clk;
if (!atmel_spi_is_v2(as))
bus_hz /= 2;
@@ -1606,6 +1607,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
ret = clk_prepare_enable(clk);
if (ret)
goto out_free_irq;
+
+ as->spi_clk = clk_get_rate(clk);
+
spi_writel(as, CR, SPI_BIT(SWRST));
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
if (as->caps.has_wdrbt) {
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 01/14] drm/i915: Give each sw_fence its own lockclass
From: Chris Wilson @ 2016-11-14 15:13 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
In-Reply-To: <1479134880.2982.4.camel@linux.intel.com>
On Mon, Nov 14, 2016 at 04:48:00PM +0200, Joonas Lahtinen wrote:
> On ma, 2016-11-14 at 08:56 +0000, Chris Wilson wrote:
> > + static struct lock_class_key __key; \
>
> When lockdep is disabled, this becomes zero size. We might still get
> rid of the #fence strings, with some #ifdef, did you measure the
> impact? I remember some for_each_engine_masked cry over bytes.
I was copying mutex_init. To avoid it is not just a little ifdeffery :|
The strings currently cost us around 160 bytes of text.
text data bss dec hex filename
1222524 5077 608 1228209 12bdb1 drivers/gpu/drm/i915/i915.ko
1222364 5077 608 1228049 12bd11 drivers/gpu/drm/i915/i915.ko
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c
index 65fded24a9eb..804af5766650 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -110,6 +110,9 @@ static void i915_sw_fence_await(struct i915_sw_fence *fence)
WARN_ON(atomic_inc_return(&fence->pending) <= 1);
}
+#ifndef CONFIG_LOCKDEP
+static
+#endif
void __i915_sw_fence_init(struct i915_sw_fence *fence,
i915_sw_fence_notify_t fn,
const char *name,
@@ -123,6 +126,16 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
fence->flags = (unsigned long)fn;
}
+#ifndef CONFIG_LOCKDEP
+void i915_sw_fence_init(struct i915_sw_fence *fence,
+ i915_sw_fence_notify_t fn)
+{
+ static struct lock_class_key __key;
+
+ __i915_sw_fence_init(fence, fn, NULL, &__key);
+}
+#endif
+
void i915_sw_fence_commit(struct i915_sw_fence *fence)
{
i915_sw_fence_complete(fence);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h
index 23748a1ae6ae..d8510a4b02bd 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -40,6 +40,7 @@ typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
enum i915_sw_fence_notify state);
#define __i915_sw_fence_call __aligned(4)
+#ifdef CONFIG_LOCKDEP
void __i915_sw_fence_init(struct i915_sw_fence *fence,
i915_sw_fence_notify_t fn,
const char *name,
@@ -49,6 +50,10 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
\
__i915_sw_fence_init((fence), (fn), #fence, &__key); \
} while (0)
+#else
+void i915_sw_fence_init(struct i915_sw_fence *fence,
+ i915_sw_fence_notify_t fn);
+#endif
void i915_sw_fence_commit(struct i915_sw_fence *fence);
Can we do that more neatly?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [PATCH fpga 5/9] fpga zynq: Remove priv->dev
From: atull @ 2016-11-14 15:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478732303-13718-6-git-send-email-jgunthorpe@obsidianresearch.com>
On Wed, 9 Nov 2016, Jason Gunthorpe wrote:
Hi Jason,
Acked-by: Alan Tull <atull@opensource.altera.com>
Alan
> socfpga uses mgr->dev for debug prints, there should be consistency
> here, so standardize on that. The only other use was for dma
> which can be replaced with mgr->dev.parent.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> ---
> drivers/fpga/zynq-fpga.c | 22 ++++++++++------------
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 3ffc5fcc3072..ac2deae92dbd 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -118,7 +118,6 @@
> #define FPGA_RST_NONE_MASK 0x0
>
> struct zynq_fpga_priv {
> - struct device *dev;
> int irq;
> struct clk *clk;
>
> @@ -188,7 +187,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> * least the sync word and something else to do anything.
> */
> if (count <= 4 || (count % 4) != 0) {
> - dev_err(priv->dev,
> + dev_err(&mgr->dev,
> "Invalid bitstream size, must be multiples of 4 bytes\n");
> return -EINVAL;
> }
> @@ -200,7 +199,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> /* don't globally reset PL if we're doing partial reconfig */
> if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> if (!zynq_fpga_has_sync(buf, count)) {
> - dev_err(priv->dev,
> + dev_err(&mgr->dev,
> "Invalid bitstream, could not find a sync word. Bitstream must be a byte swaped .bin file\n");
> err = -EINVAL;
> goto out_err;
> @@ -233,7 +232,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> INIT_POLL_DELAY,
> INIT_POLL_TIMEOUT);
> if (err) {
> - dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n");
> + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
> goto out_err;
> }
>
> @@ -247,7 +246,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> INIT_POLL_DELAY,
> INIT_POLL_TIMEOUT);
> if (err) {
> - dev_err(priv->dev, "Timeout waiting for !PCFG_INIT\n");
> + dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
> goto out_err;
> }
>
> @@ -261,7 +260,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> INIT_POLL_DELAY,
> INIT_POLL_TIMEOUT);
> if (err) {
> - dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n");
> + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
> goto out_err;
> }
> }
> @@ -278,7 +277,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> /* check that we have room in the command queue */
> status = zynq_fpga_read(priv, STATUS_OFFSET);
> if (status & STATUS_DMA_Q_F) {
> - dev_err(priv->dev, "DMA command queue full\n");
> + dev_err(&mgr->dev, "DMA command queue full\n");
> err = -EBUSY;
> goto out_err;
> }
> @@ -309,7 +308,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
>
> priv = mgr->priv;
>
> - kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr, GFP_KERNEL);
> + kbuf =
> + dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
> if (!kbuf)
> return -ENOMEM;
>
> @@ -356,7 +356,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
> goto out_clk;
>
> out_report:
> - dev_err(priv->dev,
> + dev_err(&mgr->dev,
> "%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
> why,
> intr_status,
> @@ -368,7 +368,7 @@ out_report:
> out_clk:
> clk_disable(priv->clk);
> out_free:
> - dma_free_coherent(priv->dev, count, kbuf, dma_addr);
> + dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
> return err;
> }
>
> @@ -445,8 +445,6 @@ static int zynq_fpga_probe(struct platform_device *pdev)
> if (!priv)
> return -ENOMEM;
>
> - priv->dev = dev;
> -
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> priv->io_base = devm_ioremap_resource(dev, res);
> if (IS_ERR(priv->io_base))
> --
> 2.1.4
>
>
^ permalink raw reply
* [Buildroot] [PATCH] config: bump linux kernel to 4.8.6 in synopsys defconfigs
From: Thomas Petazzoni @ 2016-11-14 15:14 UTC (permalink / raw)
To: buildroot
In-Reply-To: <1479134749.4408.54.camel@synopsys.com>
Hello,
On Mon, 14 Nov 2016 14:46:43 +0000, Alexey Brodkin wrote:
> Right, I should have asked Vlad to modify his commit log.
>
> The point is we were sitting on the patch for quite some time and when we saw
> RC1 was cut (as always unexpectedly :)) simply sent out what we had in our tree.
>
> Do you want v2 with modified log to be sent so you may apply it to master branch?
No, I'll just cherry-pick the commit from next to master, and amend the
commit log a bit.
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: sched/autogroup: race if !sysctl_sched_autogroup_enabled ?
From: Oleg Nesterov @ 2016-11-14 15:14 UTC (permalink / raw)
To: Mike Galbraith
Cc: Peter Zijlstra, Ingo Molnar, Linus Torvalds, hartsjc, vbendel,
vlovejoy, linux-kernel
In-Reply-To: <1479045544.12006.8.camel@gmx.de>
On 11/13, Mike Galbraith wrote:
>
> Autogroup never should have had knobs in the first place, and now, Oleg has
> discovered that the dynamic enable/disable capability either has become, or
> perhaps always was racy.
It was always racy afaics, even if sysctl_sched_autogroup_enabled doesn't
change. So this patch is not enough.
But the main reason I dislike it is that I can't backport it ;) rhel7 runs
with sysctl_sched_autogroup_enabled=0 by default, and users actually use
this knob to enable it dynamically.
Mike, et al, sorry for delay. I'll try to finally force myself to write the
comments and the changelog and send 2 (trivial) fixes today.
Oleg.
^ permalink raw reply
* Re: [PATCH v3 2/3] watchdog: add designware driver
From: Sascha Hauer @ 2016-11-14 15:14 UTC (permalink / raw)
To: Steffen Trumtrar; +Cc: barebox
In-Reply-To: <20161017075052.30802-2-s.trumtrar@pengutronix.de>
On Mon, Oct 17, 2016 at 09:50:51AM +0200, Steffen Trumtrar wrote:
> Port the linux v4.8-rc1 Synopsys DesignWare watchdog driver to barebox.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> +static void __noreturn dw_wdt_restart_handle(struct restart_handler *rst)
> +{
> + struct dw_wdt *dw_wdt;
> +
> + dw_wdt = container_of(rst, struct dw_wdt, restart);
> +
> + dw_wdt->wdd.set_timeout(&dw_wdt->wdd, -1);
> +
> + mdelay(1000);
> +
> + hang();
> +}
> +
> +static int dw_wdt_drv_probe(struct device_d *dev)
> +{
> + struct watchdog *wdd;
> + struct dw_wdt *dw_wdt;
> + struct resource *mem;
> + int ret;
> +
> + dw_wdt = xzalloc(sizeof(*dw_wdt));
> +
> + mem = dev_request_mem_resource(dev, 0);
> + dw_wdt->regs = IOMEM(mem->start);
> + if (IS_ERR(dw_wdt->regs))
> + return PTR_ERR(dw_wdt->regs);
Just stumbled upon this. The result of dev_request_mem_resource() must
be error checked, not the IOMEM(). If mem is valid then IOMEM() is valid
aswell.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [U-Boot] [PATCH RESEND 6/9] eeprom: Add DS2431 support
From: Tom Rini @ 2016-11-14 15:14 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161114134259.amnxlolu3urjrskb@lukather>
On Mon, Nov 14, 2016 at 02:42:59PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Fri, Nov 11, 2016 at 11:16:39AM -0800, Moritz Fischer wrote:
> > > +U_BOOT_DRIVER(ds2431) = {
> > > + .name = "ds2431",
> > > + .id = UCLASS_EEPROM,
> > > + .ops = &ds2431_ops,
> >
> > Do you want to add a .flags = DM_UC_FLAG_SEQ_ALIAS here?
>
> I don't know. I was kind of wondering why U-Boot relies on aliases so
> much, especially when the Linux DT maintainers are saying that aliases
> should be avoided entirely, and we'll won't be able to upstream those
> changes.
Bah. Do you have a pointer to some discussion about this handy?
Thanks!
--
Tom
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^ permalink raw reply
* Re: [PATCH 00/35] second batch of missing lustre 2.8 patches
From: Greg Kroah-Hartman @ 2016-11-14 15:16 UTC (permalink / raw)
To: James Simmons
Cc: devel, Andreas Dilger, Oleg Drokin, Linux Kernel Mailing List,
Lustre Development List
In-Reply-To: <1478799065-24841-1-git-send-email-jsimmons@infradead.org>
On Thu, Nov 10, 2016 at 12:30:30PM -0500, James Simmons wrote:
> More fixes missing from the upstream client. Also a nice cleanup
> with the removal of cl_req which is no longer needed. More cleanup
> for lustre_idl.h which is a uapi header. Like the last batch these
> patches are independent of order.
I didn't apply a few of these (string parsing stuff, and build
breakages.)
What's the plan for getting this out of staging? I feel like you all
are still adding new features along with these "cleanups". Normally
that's fine, but I really really want to get this out of staging as it's
been there for way too long. When is that going to happen?
thanks,
greg k-h
^ permalink raw reply
* Re: A VM with 6 volumes - hangs
From: German Anders @ 2016-11-14 15:16 UTC (permalink / raw)
To: M Ranga Swami Reddy; +Cc: ceph-users, ceph-devel
In-Reply-To: <CANA9Uk5XPHyE41QuTNz-Q-hcM0n8a_DoVWcYixR-genHcLLZ5Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 1471 bytes --]
try to see the specific logs for those particularly osd's, and see if
something is there, also take a deep close to the pg's that hold those osds
Best,
*German*
2016-11-14 12:04 GMT-03:00 M Ranga Swami Reddy <swamireddy-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> When this issue seen, ceph logs shows "slow requests to OSD"
>
> But Ceph status is in OK state.
>
> Thanks
> Swami
>
> On Mon, Nov 14, 2016 at 8:27 PM, German Anders <ganders-LWDKa8F8PCdWk0Htik3J/w@public.gmane.org>
> wrote:
>
>> Could you share some info about the ceph cluster? logs? did you see
>> anything different from normal op on the logs?
>>
>> Best,
>>
>>
>> *German*
>>
>> 2016-11-14 11:46 GMT-03:00 M Ranga Swami Reddy <swamireddy-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
>>
>>> +ceph-devel
>>>
>>> On Fri, Nov 11, 2016 at 5:09 PM, M Ranga Swami Reddy <
>>> swamireddy-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>>
>>>> Hello,
>>>> I am using the ceph volumes with a VM. Details are below:
>>>>
>>>> VM:
>>>> OS: Ubuntu 14.0.4
>>>> CPU: 12 Cores
>>>> RAM: 40 GB
>>>>
>>>> Volumes:
>>>> Size: 1 TB
>>>> No: 6 Volumes
>>>>
>>>>
>>>> With above, VM got hung without any read/write operation.
>>>>
>>>> Any suggestions..
>>>>
>>>> Thanks
>>>> Swami
>>>>
>>>
>>>
>>> _______________________________________________
>>> ceph-users mailing list
>>> ceph-users-idqoXFIVOFJgJs9I8MT0rw@public.gmane.org
>>> http://lists.ceph.com/listinfo.cgi/ceph-users-ceph.com
>>>
>>>
>>
>
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_______________________________________________
ceph-users mailing list
ceph-users-idqoXFIVOFJgJs9I8MT0rw@public.gmane.org
http://lists.ceph.com/listinfo.cgi/ceph-users-ceph.com
^ permalink raw reply
* [lustre-devel] [PATCH 00/35] second batch of missing lustre 2.8 patches
From: Greg Kroah-Hartman @ 2016-11-14 15:16 UTC (permalink / raw)
To: James Simmons
Cc: devel, Andreas Dilger, Oleg Drokin, Linux Kernel Mailing List,
Lustre Development List
In-Reply-To: <1478799065-24841-1-git-send-email-jsimmons@infradead.org>
On Thu, Nov 10, 2016 at 12:30:30PM -0500, James Simmons wrote:
> More fixes missing from the upstream client. Also a nice cleanup
> with the removal of cl_req which is no longer needed. More cleanup
> for lustre_idl.h which is a uapi header. Like the last batch these
> patches are independent of order.
I didn't apply a few of these (string parsing stuff, and build
breakages.)
What's the plan for getting this out of staging? I feel like you all
are still adding new features along with these "cleanups". Normally
that's fine, but I really really want to get this out of staging as it's
been there for way too long. When is that going to happen?
thanks,
greg k-h
^ permalink raw reply
* Re: [Qemu-devel] [kvm-unit-tests PATCH v5 09/11] arm/arm64: add initial gicv3 support
From: Andrew Jones @ 2016-11-14 15:17 UTC (permalink / raw)
To: Andre Przywara; +Cc: kvm, marc.zyngier, qemu-devel, qemu-arm, pbonzini, kvmarm
In-Reply-To: <cd9014e3-07a7-939e-49eb-3a0c154031f9@arm.com>
On Fri, Nov 11, 2016 at 04:31:36PM +0000, Andre Przywara wrote:
> Hi,
>
> On 10/11/16 17:21, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones <drjones@redhat.com>
> >
> > ---
> > v5: use modern register names [Andre]
> > v4:
> > - only take defines from kernel we need now [Andre]
> > - simplify enable by not caring if we reinit the distributor [drew]
> > v2:
> > - configure irqs as NS GRP1
> > ---
> > lib/arm/asm/arch_gicv3.h | 42 +++++++++++++++++++++
> > lib/arm/asm/gic-v3.h | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> > lib/arm/asm/gic.h | 6 ++-
> > lib/arm/gic.c | 65 ++++++++++++++++++++++++++++++++
> > lib/arm64/asm/arch_gicv3.h | 44 ++++++++++++++++++++++
> > lib/arm64/asm/gic-v3.h | 1 +
> > lib/arm64/asm/sysreg.h | 44 ++++++++++++++++++++++
> > 7 files changed, 294 insertions(+), 2 deletions(-)
> > create mode 100644 lib/arm/asm/arch_gicv3.h
> > create mode 100644 lib/arm/asm/gic-v3.h
> > create mode 100644 lib/arm64/asm/arch_gicv3.h
> > create mode 100644 lib/arm64/asm/gic-v3.h
> > create mode 100644 lib/arm64/asm/sysreg.h
> >
> > diff --git a/lib/arm/asm/arch_gicv3.h b/lib/arm/asm/arch_gicv3.h
> > new file mode 100644
> > index 000000000000..81a1e5f6c29c
> > --- /dev/null
> > +++ b/lib/arm/asm/arch_gicv3.h
> > @@ -0,0 +1,42 @@
> > +/*
> > + * All ripped off from arch/arm/include/asm/arch_gicv3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM_ARCH_GICV3_H_
> > +#define _ASMARM_ARCH_GICV3_H_
> > +
> > +#ifndef __ASSEMBLY__
> > +#include <libcflat.h>
> > +#include <asm/barrier.h>
> > +#include <asm/io.h>
> > +
> > +#define __stringify xstr
> > +
> > +#define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2
> > +
> > +#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
> > +#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
> > +
> > +static inline void gicv3_write_pmr(u32 val)
> > +{
> > + asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
> > +}
> > +
> > +static inline void gicv3_write_grpen1(u32 val)
> > +{
> > + asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
> > + isb();
> > +}
> > +
> > +static inline u64 gicv3_read_typer(const volatile void __iomem *addr)
>
> It may be worth to add that this is for GICR_TYPER (or GITS_TYPER),
> because GICD_TYPER is 32-bit only.
> Or to make the naming generic (because the code actually is), along the
> lines of read_64bit_reg or the like?
Hmm, the fact that these two consecutive mmio addresses allow me to
read and combine them into one address isn't a general property, but
rather one of this particular register. So I think we want typer in
the name. I'm not sure how to improve on the name, since it's useful
for both GICR_ and GITS_. I'll just add a comment above it.
>
> > +{
> > + u64 val = readl(addr);
> > + val |= (u64)readl(addr + 4) << 32;
> > + return val;
> > +}
> > +
> > +#endif /* !__ASSEMBLY__ */
> > +#endif /* _ASMARM_ARCH_GICV3_H_ */
> > diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
> > new file mode 100644
> > index 000000000000..e0f303d82508
> > --- /dev/null
> > +++ b/lib/arm/asm/gic-v3.h
> > @@ -0,0 +1,94 @@
> > +/*
> > + * All GIC* defines are lifted from include/linux/irqchip/arm-gic-v3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM_GIC_V3_H_
> > +#define _ASMARM_GIC_V3_H_
> > +
> > +#ifndef _ASMARM_GIC_H_
> > +#error Do not directly include <asm/gic-v3.h>. Include <asm/gic.h>
> > +#endif
> > +
> > +#define GICD_CTLR_RWP (1U << 31)
> > +#define GICD_CTLR_ARE_NS (1U << 4)
> > +#define GICD_CTLR_ENABLE_G1A (1U << 1)
> > +#define GICD_CTLR_ENABLE_G1 (1U << 0)
>
> +1 to Alex for adding a comment noting the non-secure view here.
Will do.
>
> > +
> > +/* Re-Distributor registers, offsets from RD_base */
> > +#define GICR_TYPER 0x0008
> > +
> > +#define GICR_TYPER_LAST (1U << 4)
> > +
> > +/* Re-Distributor registers, offsets from SGI_base */
> > +#define GICR_IGROUPR0 GICD_IGROUPR
> > +#define GICR_ISENABLER0 GICD_ISENABLER
> > +#define GICR_IPRIORITYR0 GICD_IPRIORITYR
> > +
> > +#include <asm/arch_gicv3.h>
> > +
> > +#ifndef __ASSEMBLY__
> > +#include <asm/setup.h>
> > +#include <asm/smp.h>
> > +#include <asm/processor.h>
> > +#include <asm/io.h>
> > +
> > +struct gicv3_data {
> > + void *dist_base;
> > + void *redist_base[NR_CPUS];
> > + unsigned int irq_nr;
> > +};
> > +extern struct gicv3_data gicv3_data;
> > +
> > +#define gicv3_dist_base() (gicv3_data.dist_base)
> > +#define gicv3_redist_base() (gicv3_data.redist_base[smp_processor_id()])
> > +#define gicv3_sgi_base() (gicv3_data.redist_base[smp_processor_id()] + SZ_64K)
> > +
> > +extern int gicv3_init(void);
> > +extern void gicv3_enable_defaults(void);
> > +extern void gicv3_set_redist_base(void);
> > +
> > +static inline void gicv3_do_wait_for_rwp(void *base)
> > +{
> > + int count = 100000; /* 1s */
> > +
> > + while (readl(base + GICD_CTLR) & GICD_CTLR_RWP) {
> > + if (!--count) {
> > + printf("GICv3: RWP timeout!\n");
> > + abort();
> > + }
> > + cpu_relax();
> > + udelay(10);
> > + };
> > +}
> > +
> > +static inline void gicv3_dist_wait_for_rwp(void)
> > +{
> > + gicv3_do_wait_for_rwp(gicv3_dist_base());
> > +}
> > +
> > +static inline void gicv3_redist_wait_for_rwp(void)
>
> Careful here. RWP is bit 3 in GICR_CTLR, while UWP (with a slightly
> different semantic) is bit 31. I guess it's bit 3 you are after, so this
> has to be taken into account.
When I stole this from the kernel I noticed that GICD_CTLR_RWP wasn't
mapped the same as GICR_CTLR_RWP, but GICR_CTLR_UWP looked "stronger"
to me, so I figured that was a subtle, but by design decision. I
could make our version less subtle by renaming to _uwp, and also adding
a comment that we abuse the gicr-uwp==gicd-rwp mapping. Maybe that's
something the kernel would like to do too, assuming I'm correct to do it
here...
>
> > +{
> > + gicv3_do_wait_for_rwp(gicv3_redist_base());
> > +}
> > +
> > +static inline u32 mpidr_compress(u64 mpidr)
> > +{
> > + u64 compressed = mpidr & MPIDR_HWID_BITMASK;
> > +
> > + compressed = (((compressed >> 32) & 0xff) << 24) | compressed;
> > + return compressed;
> > +}
> > +
> > +static inline u64 mpidr_uncompress(u32 compressed)
> > +{
> > + u64 mpidr = ((u64)compressed >> 24) << 32;
> > +
> > + mpidr |= compressed & MPIDR_HWID_BITMASK;
> > + return mpidr;
> > +}
> > +
> > +#endif /* !__ASSEMBLY__ */
> > +#endif /* _ASMARM_GIC_V3_H_ */
> > diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
> > index a16645708c35..981518620d18 100644
> > --- a/lib/arm/asm/gic.h
> > +++ b/lib/arm/asm/gic.h
> > @@ -6,10 +6,9 @@
> > #ifndef _ASMARM_GIC_H_
> > #define _ASMARM_GIC_H_
> >
> > -#include <asm/gic-v2.h>
> > -
> > #define GICD_CTLR 0x0000
> > #define GICD_TYPER 0x0004
> > +#define GICD_IGROUPR 0x0080
> > #define GICD_ISENABLER 0x0100
> > #define GICD_IPRIORITYR 0x0400
> > #define GICD_SGIR 0x0f00
> > @@ -26,6 +25,9 @@
> > #define GICC_INT_PRI_THRESHOLD 0xf0
> > #define GICC_INT_SPURIOUS 0x3ff
> >
> > +#include <asm/gic-v2.h>
> > +#include <asm/gic-v3.h>
> > +
> > #ifndef __ASSEMBLY__
> >
> > /*
> > diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> > index d655105e058b..d929d3f0fa05 100644
> > --- a/lib/arm/gic.c
> > +++ b/lib/arm/gic.c
> > @@ -8,9 +8,11 @@
> > #include <asm/io.h>
> >
> > struct gicv2_data gicv2_data;
> > +struct gicv3_data gicv3_data;
> >
> > /*
> > * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> > + * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> > */
> > static bool
> > gic_get_dt_bases(const char *compatible, void **base1, void **base2)
> > @@ -48,10 +50,18 @@ int gicv2_init(void)
> > &gicv2_data.dist_base, &gicv2_data.cpu_base);
> > }
> >
> > +int gicv3_init(void)
> > +{
> > + return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
> > + &gicv3_data.redist_base[0]);
> > +}
> > +
> > int gic_init(void)
> > {
> > if (gicv2_init())
> > return 2;
> > + else if (gicv3_init())
> > + return 3;
> > return 0;
> > }
> >
> > @@ -74,3 +84,58 @@ void gicv2_enable_defaults(void)
> > writel(GICC_INT_PRI_THRESHOLD, cpu_base + GICC_PMR);
> > writel(GICC_ENABLE, cpu_base + GICC_CTLR);
> > }
> > +
> > +void gicv3_set_redist_base(void)
> > +{
> > + u32 aff = mpidr_compress(get_mpidr());
> > + void *ptr = gicv3_data.redist_base[0];
> > + u64 typer;
> > +
> > + do {
> > + typer = gicv3_read_typer(ptr + GICR_TYPER);
> > + if ((typer >> 32) == aff) {
> > + gicv3_redist_base() = ptr;
> > + return;
> > + }
> > + ptr += SZ_64K * 2; /* skip RD_base and SGI_base */
>
> For a GICv4 the stride is four 64K pages instead of 2.
> I guess we don't need to bother atm, but maybe worth a comment or even a
> TODO?
Will fix for v6 by adding a stride parameter to this function
>
> > + } while (!(typer & GICR_TYPER_LAST));
> > + assert(0);
> > +}
> > +
> > +void gicv3_enable_defaults(void)
> > +{
> > + void *dist = gicv3_dist_base();
> > + void *sgi_base;
> > + unsigned int i;
> > +
> > + gicv3_data.irq_nr = GICD_TYPER_IRQS(readl(dist + GICD_TYPER));
> > + if (gicv3_data.irq_nr > 1020)
> > + gicv3_data.irq_nr = 1020;
> > +
> > + writel(0, dist + GICD_CTLR);
> > + gicv3_dist_wait_for_rwp();
> > +
> > + writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
> > + dist + GICD_CTLR);
> > + gicv3_dist_wait_for_rwp();
> > +
> > + for (i = 0; i < gicv3_data.irq_nr; i += 4)
> > + writel(~0, dist + GICD_IGROUPR + i);
> > + gicv3_dist_wait_for_rwp();
>
> I don't think we need this. The spec says that IGROUPR accesses are not
> tracked by this bit.
Indeed, will drop.
>
> > +
> > + if (!gicv3_redist_base())
> > + gicv3_set_redist_base();
> > + sgi_base = gicv3_sgi_base();
> > +
> > + writel(~0, sgi_base + GICR_IGROUPR0);
> > +
> > + for (i = 0; i < 16; i += 4)
> > + writel(GICD_INT_DEF_PRI_X4, sgi_base + GICR_IPRIORITYR0 + i);
> > +
> > + writel(GICD_INT_EN_SET_SGI, sgi_base + GICR_ISENABLER0);
> > +
> > + gicv3_redist_wait_for_rwp();
>
> I think we don't need this either, only for clear enable. That applies
> to both RWP (= bit 3) and UWP (= bit 31).
Seems to work without it, will drop.
Thanks,
drew
>
> Cheers,
> Andre.
>
> > +
> > + gicv3_write_pmr(GICC_INT_PRI_THRESHOLD);
> > + gicv3_write_grpen1(1);
> > +}
> > diff --git a/lib/arm64/asm/arch_gicv3.h b/lib/arm64/asm/arch_gicv3.h
> > new file mode 100644
> > index 000000000000..6d353567f56a
> > --- /dev/null
> > +++ b/lib/arm64/asm/arch_gicv3.h
> > @@ -0,0 +1,44 @@
> > +/*
> > + * All ripped off from arch/arm64/include/asm/arch_gicv3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM64_ARCH_GICV3_H_
> > +#define _ASMARM64_ARCH_GICV3_H_
> > +
> > +#include <asm/sysreg.h>
> > +
> > +#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
> > +#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +#include <libcflat.h>
> > +#include <asm/barrier.h>
> > +
> > +#define __stringify xstr
> > +
> > +/*
> > + * Low-level accessors
> > + *
> > + * These system registers are 32 bits, but we make sure that the compiler
> > + * sets the GP register's most significant bits to 0 with an explicit cast.
> > + */
> > +
> > +static inline void gicv3_write_pmr(u32 val)
> > +{
> > + asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
> > +}
> > +
> > +static inline void gicv3_write_grpen1(u32 val)
> > +{
> > + asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
> > + isb();
> > +}
> > +
> > +#define gicv3_read_typer(c) readq(c)
> > +
> > +#endif /* __ASSEMBLY__ */
> > +#endif /* _ASMARM64_ARCH_GICV3_H_ */
> > diff --git a/lib/arm64/asm/gic-v3.h b/lib/arm64/asm/gic-v3.h
> > new file mode 100644
> > index 000000000000..8ee5d4d9c181
> > --- /dev/null
> > +++ b/lib/arm64/asm/gic-v3.h
> > @@ -0,0 +1 @@
> > +#include "../../arm/asm/gic-v3.h"
> > diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h
> > new file mode 100644
> > index 000000000000..544a46cb8cc5
> > --- /dev/null
> > +++ b/lib/arm64/asm/sysreg.h
> > @@ -0,0 +1,44 @@
> > +/*
> > + * Ripped off from arch/arm64/include/asm/sysreg.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM64_SYSREG_H_
> > +#define _ASMARM64_SYSREG_H_
> > +
> > +#define sys_reg(op0, op1, crn, crm, op2) \
> > + ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
> > +
> > +#ifdef __ASSEMBLY__
> > + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> > + .equ .L__reg_num_x\num, \num
> > + .endr
> > + .equ .L__reg_num_xzr, 31
> > +
> > + .macro mrs_s, rt, sreg
> > + .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
> > + .endm
> > +
> > + .macro msr_s, sreg, rt
> > + .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
> > + .endm
> > +#else
> > +asm(
> > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > +" .equ .L__reg_num_x\\num, \\num\n"
> > +" .endr\n"
> > +" .equ .L__reg_num_xzr, 31\n"
> > +"\n"
> > +" .macro mrs_s, rt, sreg\n"
> > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +"\n"
> > +" .macro msr_s, sreg, rt\n"
> > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +);
> > +#endif
> > +
> > +#endif /* _ASMARM64_SYSREG_H_ */
> >
>
^ permalink raw reply
* Re: [PATCH v4] staging: lustre: mdc: manage number of modify RPCs in flight
From: Greg Kroah-Hartman @ 2016-11-14 15:17 UTC (permalink / raw)
To: James Simmons
Cc: devel, Andreas Dilger, Oleg Drokin, Gregoire Pichon,
Linux Kernel Mailing List, Lustre Development List
In-Reply-To: <1478793073-21814-1-git-send-email-jsimmons@infradead.org>
On Thu, Nov 10, 2016 at 10:51:13AM -0500, James Simmons wrote:
> From: Gregoire Pichon <gregoire.pichon@bull.net>
>
> This patch is the main client part of a new feature that supports
> multiple modify metadata RPCs in parallel. Its goal is to improve
> metadata operations performance of a single client, while maintening
> the consistency of MDT reply reconstruction and MDT recovery
> mechanisms.
>
> It allows to manage the number of modify RPCs in flight within
> the client obd structure and to assign a virtual index (the tag) to
> each modify RPC to help server side cleaning of reply data.
>
> The mdc component uses this feature to send multiple modify RPCs
> in parallel.
Is this a new feature? Why should we take this now and not just wait
until the code is out of staging?
thanks,
greg k-h
^ permalink raw reply
* Re: [Qemu-devel] [kvm-unit-tests PATCH v5 09/11] arm/arm64: add initial gicv3 support
From: Andrew Jones @ 2016-11-14 15:17 UTC (permalink / raw)
To: Andre Przywara
Cc: kvm, kvmarm, qemu-devel, qemu-arm, peter.maydell, marc.zyngier,
eric.auger, pbonzini, alex.bennee, christoffer.dall
In-Reply-To: <cd9014e3-07a7-939e-49eb-3a0c154031f9@arm.com>
On Fri, Nov 11, 2016 at 04:31:36PM +0000, Andre Przywara wrote:
> Hi,
>
> On 10/11/16 17:21, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones <drjones@redhat.com>
> >
> > ---
> > v5: use modern register names [Andre]
> > v4:
> > - only take defines from kernel we need now [Andre]
> > - simplify enable by not caring if we reinit the distributor [drew]
> > v2:
> > - configure irqs as NS GRP1
> > ---
> > lib/arm/asm/arch_gicv3.h | 42 +++++++++++++++++++++
> > lib/arm/asm/gic-v3.h | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> > lib/arm/asm/gic.h | 6 ++-
> > lib/arm/gic.c | 65 ++++++++++++++++++++++++++++++++
> > lib/arm64/asm/arch_gicv3.h | 44 ++++++++++++++++++++++
> > lib/arm64/asm/gic-v3.h | 1 +
> > lib/arm64/asm/sysreg.h | 44 ++++++++++++++++++++++
> > 7 files changed, 294 insertions(+), 2 deletions(-)
> > create mode 100644 lib/arm/asm/arch_gicv3.h
> > create mode 100644 lib/arm/asm/gic-v3.h
> > create mode 100644 lib/arm64/asm/arch_gicv3.h
> > create mode 100644 lib/arm64/asm/gic-v3.h
> > create mode 100644 lib/arm64/asm/sysreg.h
> >
> > diff --git a/lib/arm/asm/arch_gicv3.h b/lib/arm/asm/arch_gicv3.h
> > new file mode 100644
> > index 000000000000..81a1e5f6c29c
> > --- /dev/null
> > +++ b/lib/arm/asm/arch_gicv3.h
> > @@ -0,0 +1,42 @@
> > +/*
> > + * All ripped off from arch/arm/include/asm/arch_gicv3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM_ARCH_GICV3_H_
> > +#define _ASMARM_ARCH_GICV3_H_
> > +
> > +#ifndef __ASSEMBLY__
> > +#include <libcflat.h>
> > +#include <asm/barrier.h>
> > +#include <asm/io.h>
> > +
> > +#define __stringify xstr
> > +
> > +#define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2
> > +
> > +#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
> > +#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
> > +
> > +static inline void gicv3_write_pmr(u32 val)
> > +{
> > + asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
> > +}
> > +
> > +static inline void gicv3_write_grpen1(u32 val)
> > +{
> > + asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
> > + isb();
> > +}
> > +
> > +static inline u64 gicv3_read_typer(const volatile void __iomem *addr)
>
> It may be worth to add that this is for GICR_TYPER (or GITS_TYPER),
> because GICD_TYPER is 32-bit only.
> Or to make the naming generic (because the code actually is), along the
> lines of read_64bit_reg or the like?
Hmm, the fact that these two consecutive mmio addresses allow me to
read and combine them into one address isn't a general property, but
rather one of this particular register. So I think we want typer in
the name. I'm not sure how to improve on the name, since it's useful
for both GICR_ and GITS_. I'll just add a comment above it.
>
> > +{
> > + u64 val = readl(addr);
> > + val |= (u64)readl(addr + 4) << 32;
> > + return val;
> > +}
> > +
> > +#endif /* !__ASSEMBLY__ */
> > +#endif /* _ASMARM_ARCH_GICV3_H_ */
> > diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
> > new file mode 100644
> > index 000000000000..e0f303d82508
> > --- /dev/null
> > +++ b/lib/arm/asm/gic-v3.h
> > @@ -0,0 +1,94 @@
> > +/*
> > + * All GIC* defines are lifted from include/linux/irqchip/arm-gic-v3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM_GIC_V3_H_
> > +#define _ASMARM_GIC_V3_H_
> > +
> > +#ifndef _ASMARM_GIC_H_
> > +#error Do not directly include <asm/gic-v3.h>. Include <asm/gic.h>
> > +#endif
> > +
> > +#define GICD_CTLR_RWP (1U << 31)
> > +#define GICD_CTLR_ARE_NS (1U << 4)
> > +#define GICD_CTLR_ENABLE_G1A (1U << 1)
> > +#define GICD_CTLR_ENABLE_G1 (1U << 0)
>
> +1 to Alex for adding a comment noting the non-secure view here.
Will do.
>
> > +
> > +/* Re-Distributor registers, offsets from RD_base */
> > +#define GICR_TYPER 0x0008
> > +
> > +#define GICR_TYPER_LAST (1U << 4)
> > +
> > +/* Re-Distributor registers, offsets from SGI_base */
> > +#define GICR_IGROUPR0 GICD_IGROUPR
> > +#define GICR_ISENABLER0 GICD_ISENABLER
> > +#define GICR_IPRIORITYR0 GICD_IPRIORITYR
> > +
> > +#include <asm/arch_gicv3.h>
> > +
> > +#ifndef __ASSEMBLY__
> > +#include <asm/setup.h>
> > +#include <asm/smp.h>
> > +#include <asm/processor.h>
> > +#include <asm/io.h>
> > +
> > +struct gicv3_data {
> > + void *dist_base;
> > + void *redist_base[NR_CPUS];
> > + unsigned int irq_nr;
> > +};
> > +extern struct gicv3_data gicv3_data;
> > +
> > +#define gicv3_dist_base() (gicv3_data.dist_base)
> > +#define gicv3_redist_base() (gicv3_data.redist_base[smp_processor_id()])
> > +#define gicv3_sgi_base() (gicv3_data.redist_base[smp_processor_id()] + SZ_64K)
> > +
> > +extern int gicv3_init(void);
> > +extern void gicv3_enable_defaults(void);
> > +extern void gicv3_set_redist_base(void);
> > +
> > +static inline void gicv3_do_wait_for_rwp(void *base)
> > +{
> > + int count = 100000; /* 1s */
> > +
> > + while (readl(base + GICD_CTLR) & GICD_CTLR_RWP) {
> > + if (!--count) {
> > + printf("GICv3: RWP timeout!\n");
> > + abort();
> > + }
> > + cpu_relax();
> > + udelay(10);
> > + };
> > +}
> > +
> > +static inline void gicv3_dist_wait_for_rwp(void)
> > +{
> > + gicv3_do_wait_for_rwp(gicv3_dist_base());
> > +}
> > +
> > +static inline void gicv3_redist_wait_for_rwp(void)
>
> Careful here. RWP is bit 3 in GICR_CTLR, while UWP (with a slightly
> different semantic) is bit 31. I guess it's bit 3 you are after, so this
> has to be taken into account.
When I stole this from the kernel I noticed that GICD_CTLR_RWP wasn't
mapped the same as GICR_CTLR_RWP, but GICR_CTLR_UWP looked "stronger"
to me, so I figured that was a subtle, but by design decision. I
could make our version less subtle by renaming to _uwp, and also adding
a comment that we abuse the gicr-uwp==gicd-rwp mapping. Maybe that's
something the kernel would like to do too, assuming I'm correct to do it
here...
>
> > +{
> > + gicv3_do_wait_for_rwp(gicv3_redist_base());
> > +}
> > +
> > +static inline u32 mpidr_compress(u64 mpidr)
> > +{
> > + u64 compressed = mpidr & MPIDR_HWID_BITMASK;
> > +
> > + compressed = (((compressed >> 32) & 0xff) << 24) | compressed;
> > + return compressed;
> > +}
> > +
> > +static inline u64 mpidr_uncompress(u32 compressed)
> > +{
> > + u64 mpidr = ((u64)compressed >> 24) << 32;
> > +
> > + mpidr |= compressed & MPIDR_HWID_BITMASK;
> > + return mpidr;
> > +}
> > +
> > +#endif /* !__ASSEMBLY__ */
> > +#endif /* _ASMARM_GIC_V3_H_ */
> > diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
> > index a16645708c35..981518620d18 100644
> > --- a/lib/arm/asm/gic.h
> > +++ b/lib/arm/asm/gic.h
> > @@ -6,10 +6,9 @@
> > #ifndef _ASMARM_GIC_H_
> > #define _ASMARM_GIC_H_
> >
> > -#include <asm/gic-v2.h>
> > -
> > #define GICD_CTLR 0x0000
> > #define GICD_TYPER 0x0004
> > +#define GICD_IGROUPR 0x0080
> > #define GICD_ISENABLER 0x0100
> > #define GICD_IPRIORITYR 0x0400
> > #define GICD_SGIR 0x0f00
> > @@ -26,6 +25,9 @@
> > #define GICC_INT_PRI_THRESHOLD 0xf0
> > #define GICC_INT_SPURIOUS 0x3ff
> >
> > +#include <asm/gic-v2.h>
> > +#include <asm/gic-v3.h>
> > +
> > #ifndef __ASSEMBLY__
> >
> > /*
> > diff --git a/lib/arm/gic.c b/lib/arm/gic.c
> > index d655105e058b..d929d3f0fa05 100644
> > --- a/lib/arm/gic.c
> > +++ b/lib/arm/gic.c
> > @@ -8,9 +8,11 @@
> > #include <asm/io.h>
> >
> > struct gicv2_data gicv2_data;
> > +struct gicv3_data gicv3_data;
> >
> > /*
> > * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> > + * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> > */
> > static bool
> > gic_get_dt_bases(const char *compatible, void **base1, void **base2)
> > @@ -48,10 +50,18 @@ int gicv2_init(void)
> > &gicv2_data.dist_base, &gicv2_data.cpu_base);
> > }
> >
> > +int gicv3_init(void)
> > +{
> > + return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
> > + &gicv3_data.redist_base[0]);
> > +}
> > +
> > int gic_init(void)
> > {
> > if (gicv2_init())
> > return 2;
> > + else if (gicv3_init())
> > + return 3;
> > return 0;
> > }
> >
> > @@ -74,3 +84,58 @@ void gicv2_enable_defaults(void)
> > writel(GICC_INT_PRI_THRESHOLD, cpu_base + GICC_PMR);
> > writel(GICC_ENABLE, cpu_base + GICC_CTLR);
> > }
> > +
> > +void gicv3_set_redist_base(void)
> > +{
> > + u32 aff = mpidr_compress(get_mpidr());
> > + void *ptr = gicv3_data.redist_base[0];
> > + u64 typer;
> > +
> > + do {
> > + typer = gicv3_read_typer(ptr + GICR_TYPER);
> > + if ((typer >> 32) == aff) {
> > + gicv3_redist_base() = ptr;
> > + return;
> > + }
> > + ptr += SZ_64K * 2; /* skip RD_base and SGI_base */
>
> For a GICv4 the stride is four 64K pages instead of 2.
> I guess we don't need to bother atm, but maybe worth a comment or even a
> TODO?
Will fix for v6 by adding a stride parameter to this function
>
> > + } while (!(typer & GICR_TYPER_LAST));
> > + assert(0);
> > +}
> > +
> > +void gicv3_enable_defaults(void)
> > +{
> > + void *dist = gicv3_dist_base();
> > + void *sgi_base;
> > + unsigned int i;
> > +
> > + gicv3_data.irq_nr = GICD_TYPER_IRQS(readl(dist + GICD_TYPER));
> > + if (gicv3_data.irq_nr > 1020)
> > + gicv3_data.irq_nr = 1020;
> > +
> > + writel(0, dist + GICD_CTLR);
> > + gicv3_dist_wait_for_rwp();
> > +
> > + writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
> > + dist + GICD_CTLR);
> > + gicv3_dist_wait_for_rwp();
> > +
> > + for (i = 0; i < gicv3_data.irq_nr; i += 4)
> > + writel(~0, dist + GICD_IGROUPR + i);
> > + gicv3_dist_wait_for_rwp();
>
> I don't think we need this. The spec says that IGROUPR accesses are not
> tracked by this bit.
Indeed, will drop.
>
> > +
> > + if (!gicv3_redist_base())
> > + gicv3_set_redist_base();
> > + sgi_base = gicv3_sgi_base();
> > +
> > + writel(~0, sgi_base + GICR_IGROUPR0);
> > +
> > + for (i = 0; i < 16; i += 4)
> > + writel(GICD_INT_DEF_PRI_X4, sgi_base + GICR_IPRIORITYR0 + i);
> > +
> > + writel(GICD_INT_EN_SET_SGI, sgi_base + GICR_ISENABLER0);
> > +
> > + gicv3_redist_wait_for_rwp();
>
> I think we don't need this either, only for clear enable. That applies
> to both RWP (= bit 3) and UWP (= bit 31).
Seems to work without it, will drop.
Thanks,
drew
>
> Cheers,
> Andre.
>
> > +
> > + gicv3_write_pmr(GICC_INT_PRI_THRESHOLD);
> > + gicv3_write_grpen1(1);
> > +}
> > diff --git a/lib/arm64/asm/arch_gicv3.h b/lib/arm64/asm/arch_gicv3.h
> > new file mode 100644
> > index 000000000000..6d353567f56a
> > --- /dev/null
> > +++ b/lib/arm64/asm/arch_gicv3.h
> > @@ -0,0 +1,44 @@
> > +/*
> > + * All ripped off from arch/arm64/include/asm/arch_gicv3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM64_ARCH_GICV3_H_
> > +#define _ASMARM64_ARCH_GICV3_H_
> > +
> > +#include <asm/sysreg.h>
> > +
> > +#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
> > +#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +#include <libcflat.h>
> > +#include <asm/barrier.h>
> > +
> > +#define __stringify xstr
> > +
> > +/*
> > + * Low-level accessors
> > + *
> > + * These system registers are 32 bits, but we make sure that the compiler
> > + * sets the GP register's most significant bits to 0 with an explicit cast.
> > + */
> > +
> > +static inline void gicv3_write_pmr(u32 val)
> > +{
> > + asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
> > +}
> > +
> > +static inline void gicv3_write_grpen1(u32 val)
> > +{
> > + asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
> > + isb();
> > +}
> > +
> > +#define gicv3_read_typer(c) readq(c)
> > +
> > +#endif /* __ASSEMBLY__ */
> > +#endif /* _ASMARM64_ARCH_GICV3_H_ */
> > diff --git a/lib/arm64/asm/gic-v3.h b/lib/arm64/asm/gic-v3.h
> > new file mode 100644
> > index 000000000000..8ee5d4d9c181
> > --- /dev/null
> > +++ b/lib/arm64/asm/gic-v3.h
> > @@ -0,0 +1 @@
> > +#include "../../arm/asm/gic-v3.h"
> > diff --git a/lib/arm64/asm/sysreg.h b/lib/arm64/asm/sysreg.h
> > new file mode 100644
> > index 000000000000..544a46cb8cc5
> > --- /dev/null
> > +++ b/lib/arm64/asm/sysreg.h
> > @@ -0,0 +1,44 @@
> > +/*
> > + * Ripped off from arch/arm64/include/asm/sysreg.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM64_SYSREG_H_
> > +#define _ASMARM64_SYSREG_H_
> > +
> > +#define sys_reg(op0, op1, crn, crm, op2) \
> > + ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
> > +
> > +#ifdef __ASSEMBLY__
> > + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> > + .equ .L__reg_num_x\num, \num
> > + .endr
> > + .equ .L__reg_num_xzr, 31
> > +
> > + .macro mrs_s, rt, sreg
> > + .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
> > + .endm
> > +
> > + .macro msr_s, sreg, rt
> > + .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
> > + .endm
> > +#else
> > +asm(
> > +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> > +" .equ .L__reg_num_x\\num, \\num\n"
> > +" .endr\n"
> > +" .equ .L__reg_num_xzr, 31\n"
> > +"\n"
> > +" .macro mrs_s, rt, sreg\n"
> > +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +"\n"
> > +" .macro msr_s, sreg, rt\n"
> > +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
> > +" .endm\n"
> > +);
> > +#endif
> > +
> > +#endif /* _ASMARM64_SYSREG_H_ */
> >
>
^ permalink raw reply
* [lustre-devel] [PATCH v4] staging: lustre: mdc: manage number of modify RPCs in flight
From: Greg Kroah-Hartman @ 2016-11-14 15:17 UTC (permalink / raw)
To: James Simmons
Cc: devel, Andreas Dilger, Oleg Drokin, Gregoire Pichon,
Linux Kernel Mailing List, Lustre Development List
In-Reply-To: <1478793073-21814-1-git-send-email-jsimmons@infradead.org>
On Thu, Nov 10, 2016 at 10:51:13AM -0500, James Simmons wrote:
> From: Gregoire Pichon <gregoire.pichon@bull.net>
>
> This patch is the main client part of a new feature that supports
> multiple modify metadata RPCs in parallel. Its goal is to improve
> metadata operations performance of a single client, while maintening
> the consistency of MDT reply reconstruction and MDT recovery
> mechanisms.
>
> It allows to manage the number of modify RPCs in flight within
> the client obd structure and to assign a virtual index (the tag) to
> each modify RPC to help server side cleaning of reply data.
>
> The mdc component uses this feature to send multiple modify RPCs
> in parallel.
Is this a new feature? Why should we take this now and not just wait
until the code is out of staging?
thanks,
greg k-h
^ permalink raw reply
* RE: [PATCH v5 3/3] clocksource: Add clockevent support to NPS400 driver
From: Noam Camus @ 2016-11-14 15:17 UTC (permalink / raw)
To: Daniel Lezcano
Cc: robh+dt@kernel.org, mark.rutland@arm.com, tglx@linutronix.de,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <20161114143454.GE2016@mai>
> From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org]
> Sent: Monday, November 14, 2016 4:35 PM
>The function nps_clkevent_timer_event_setup() writes into the NPS_REG_TIMER0_CTRL register but there is no critical section there. What prevents another HW thread to write this register at the same time ?
Correct, during my last email to you I noticed that fact and already started fixing it.
>I do believe we have a framework to access shared registers, otherwise a simple spinlock would be simpler and perhaps faster than disabling the entire hardware scheduling for the system, no ?
When you are saying "we have a framework" do you mean to some generic framework in the kernel?
Anyway to my understanding I cannot guarantee this atomics during my routines without preventing HW from changing the HW thread this core executes.
As SW I am not aware to such HW scheduling, It is much same as with interrupts that we disable them when we reach code that might be shared by the interrupt handler.
>Regarding the comment I did above, it is possible the critical section is reduced and moved into the shutdown function. Thus, the boolean wouldn't be needed anymore, well that is conditional to the above comment. Discard the comment for the moment, until the hw sched vs spinlock vs NPS_REG_TIMER0_CTRL is sorted out.
OK, I will discard that in the meantime.
...
>> >> + .set_state_shutdown = nps_clkevent_timer_shutdown,
>>
>> >Doesn't set_state_shutdown and set_state_oneshot_stopped need to remove the HW thread from the TSI ?
>> You are correct, I will fix that.
>And tick_resume. Perhaps, that is the reason why NO_HZ hangs.
What NO_HZ hang are you referring to in this case?
How calling nps_clkevent_rm_thread() explain such hang?
Anyway I agree, and will add nps_clkevent_rm_thread() to tick_resume.
Appreciating your effort and will gladly provide any more information needed about our SoC.
-Noam
^ permalink raw reply
* [PATCH RESEND] spi: atmel: Fix scheduling while atomic
From: Nicolas Ferre @ 2016-11-14 15:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479136400-10285-1-git-send-email-ben.whitten@lairdtech.com>
Le 14/11/2016 ? 16:13, Ben Whitten a ?crit :
> A call to clk_get_rate appears to be called in the context of an interrupt,
> cache the bus clock for the frequency calculations in transmission.
>
> This fixes a 'BUG: scheduling while atomic' and
> 'WARNING: CPU: 0 PID: 777 at kernel/sched/core.c:2960 atmel_spi_unlock'
>
> Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
> Signed-off-by: Steve deRosier <steve.derosier@lairdtech.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
>
> Resending due to missing off the subsystem maintainer in initial submission,
> pointed out by Alexandre Belloni, thanks.
BTW, it's actually more a "v2" than a "RESEND".
Thanks a lot for your patch.
Best regards,
> ---
> drivers/spi/spi-atmel.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 8feac59..c281d1a 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -295,6 +295,7 @@ struct atmel_spi {
> int irq;
> struct clk *clk;
> struct platform_device *pdev;
> + unsigned long spi_clk;
>
> struct spi_transfer *current_transfer;
> int current_remaining_bytes;
> @@ -864,7 +865,7 @@ static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
> unsigned long bus_hz;
>
> /* v1 chips start out at half the peripheral bus speed. */
> - bus_hz = clk_get_rate(as->clk);
> + bus_hz = as->spi_clk;
> if (!atmel_spi_is_v2(as))
> bus_hz /= 2;
>
> @@ -1606,6 +1607,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
> ret = clk_prepare_enable(clk);
> if (ret)
> goto out_free_irq;
> +
> + as->spi_clk = clk_get_rate(clk);
> +
> spi_writel(as, CR, SPI_BIT(SWRST));
> spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
> if (as->caps.has_wdrbt) {
>
--
Nicolas Ferre
^ permalink raw reply
* Re: [PATCH] multipathd: deferred device adding
From: Bart Van Assche @ 2016-11-14 15:19 UTC (permalink / raw)
To: Gioh Kim, Hannes Reinecke, christophe.varoqui@opensvc.com
Cc: dm-devel@redhat.com, benjamin.drung@profitbricks.com
In-Reply-To: <4b591c27-f1eb-8859-a319-b19e2e3bd200@profitbricks.com>
On 11/14/16 01:23, Gioh Kim wrote:
> I consulted with target side developers in my company.
> They said there are many jobs that should be done on initiator side without disconnecting.
Hello Gioh,
Have you considered to change the ALUA state at the SCST side into
"transitioning" for the LUN that should be ignored by multipathd?
Bart.
^ permalink raw reply
* Re: Summary of LPC guest MSI discussion in Santa Fe
From: Joerg Roedel @ 2016-11-14 15:19 UTC (permalink / raw)
To: Alex Williamson
Cc: linux-arm-kernel, drjones, jason, kvm, marc.zyngier, benh,
punit.agrawal, Will Deacon, linux-kernel, iommu,
pranav.sawargaonkar, arnd, dwmw, jcm, tglx, Christoffer Dall,
eric.auger.pro
In-Reply-To: <20161111090543.57623f2d@t450s.home>
On Fri, Nov 11, 2016 at 09:05:43AM -0700, Alex Williamson wrote:
> On Fri, 11 Nov 2016 08:50:56 -0700
> Alex Williamson <alex.williamson@redhat.com> wrote:
> >
> > It's really just a happenstance that we don't map RAM over the x86 MSI
> > range though. That property really can't be guaranteed once we mix
> > architectures, such as running an aarch64 VM on x86 host via TCG.
> > AIUI, the MSI range is actually handled differently than other DMA
> > ranges, so a iommu_map() overlapping a range that the iommu cannot map
> > should fail just like an attempt to map beyond the address width of the
> > iommu.
>
> (clarification, this is x86 specific, the MSI controller - interrupt
> remapper - is embedded in the iommu AIUI, so the iommu is actually not
> able to provide DMA translation for this range.
Right, on x86 the MSI range can be covered by page-tables, but those are
ignored by the IOMMU hardware. But what I am trying to say is, that
checking for these ranges happens already on a higher level (in the
dma-api implementations by marking these regions as allocted) so that
there is no need to check for them again in the iommu_map/unmap path.
Joerg
^ permalink raw reply
* Summary of LPC guest MSI discussion in Santa Fe
From: Joerg Roedel @ 2016-11-14 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111090543.57623f2d@t450s.home>
On Fri, Nov 11, 2016 at 09:05:43AM -0700, Alex Williamson wrote:
> On Fri, 11 Nov 2016 08:50:56 -0700
> Alex Williamson <alex.williamson@redhat.com> wrote:
> >
> > It's really just a happenstance that we don't map RAM over the x86 MSI
> > range though. That property really can't be guaranteed once we mix
> > architectures, such as running an aarch64 VM on x86 host via TCG.
> > AIUI, the MSI range is actually handled differently than other DMA
> > ranges, so a iommu_map() overlapping a range that the iommu cannot map
> > should fail just like an attempt to map beyond the address width of the
> > iommu.
>
> (clarification, this is x86 specific, the MSI controller - interrupt
> remapper - is embedded in the iommu AIUI, so the iommu is actually not
> able to provide DMA translation for this range.
Right, on x86 the MSI range can be covered by page-tables, but those are
ignored by the IOMMU hardware. But what I am trying to say is, that
checking for these ranges happens already on a higher level (in the
dma-api implementations by marking these regions as allocted) so that
there is no need to check for them again in the iommu_map/unmap path.
Joerg
^ permalink raw reply
* [U-Boot] [PATCH] dfu: dfu_sf: Fix read offset
From: Phil Edworthy @ 2016-11-14 15:19 UTC (permalink / raw)
To: u-boot
The offset was applied to write, but not read, now its applied to
both.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
drivers/dfu/dfu_sf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 9702eee..b6d5fe2 100644
--- a/drivers/dfu/dfu_sf.c
+++ b/drivers/dfu/dfu_sf.c
@@ -20,7 +20,8 @@ static long dfu_get_medium_size_sf(struct dfu_entity *dfu)
static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf,
long *len)
{
- return spi_flash_read(dfu->data.sf.dev, offset, *len, buf);
+ return spi_flash_read(dfu->data.sf.dev, dfu->data.sf.start + offset,
+ *len, buf);
}
static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset)
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] powerpc/mm/hugetlb: Switch hugetlb update to use pte_update
From: Aneesh Kumar K.V @ 2016-11-14 15:20 UTC (permalink / raw)
To: benh, paulus, mpe, akpm; +Cc: linuxppc-dev, linux-mm, Aneesh Kumar K.V
In-Reply-To: <20161114152020.4608-1-aneesh.kumar@linux.vnet.ibm.com>
Now that we have updated hugetlb functions to take vm_area_struct and we can
derive huge page size from vma, switch the pte update to use generic functions.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 34 +++++++---------------------
arch/powerpc/include/asm/hugetlb.h | 2 +-
2 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hugetlb.h b/arch/powerpc/include/asm/book3s/64/hugetlb.h
index 80fa0c828413..0a6db2086140 100644
--- a/arch/powerpc/include/asm/book3s/64/hugetlb.h
+++ b/arch/powerpc/include/asm/book3s/64/hugetlb.h
@@ -31,36 +31,18 @@ static inline int hstate_get_psize(struct hstate *hstate)
}
}
-static inline unsigned long huge_pte_update(struct mm_struct *mm, unsigned long addr,
+static inline unsigned long huge_pte_update(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep, unsigned long clr,
unsigned long set)
{
- if (radix_enabled()) {
- unsigned long old_pte;
+ unsigned long pg_sz;
- if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+ VM_WARN_ON(!is_vm_hugetlb_page(vma));
+ pg_sz = huge_page_size(hstate_vma(vma));
- unsigned long new_pte;
-
- old_pte = __radix_pte_update(ptep, ~0, 0);
- asm volatile("ptesync" : : : "memory");
- /*
- * new value of pte
- */
- new_pte = (old_pte | set) & ~clr;
- /*
- * For now let's do heavy pid flush
- * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
- */
- radix__flush_tlb_mm(mm);
-
- __radix_pte_update(ptep, 0, new_pte);
- } else
- old_pte = __radix_pte_update(ptep, clr, set);
- asm volatile("ptesync" : : : "memory");
- return old_pte;
- }
- return hash__pte_update(mm, addr, ptep, clr, set, true);
+ if (radix_enabled())
+ return radix__pte_update(vma->vm_mm, addr, ptep, clr, set, pg_sz);
+ return hash__pte_update(vma->vm_mm, addr, ptep, clr, set, true);
}
static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
@@ -69,7 +51,7 @@ static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
- huge_pte_update(vma->vm_mm, addr, ptep, _PAGE_WRITE, 0);
+ huge_pte_update(vma, addr, ptep, _PAGE_WRITE, 0);
}
#endif
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index bb1bf23d6f90..f0731dff76c2 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -136,7 +136,7 @@ static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_PPC64
- return __pte(huge_pte_update(vma->vm_mm, addr, ptep, ~0UL, 0));
+ return __pte(huge_pte_update(vma, addr, ptep, ~0UL, 0));
#else
return __pte(pte_update(ptep, ~0UL, 0));
#endif
--
2.10.2
^ permalink raw reply related
* [PATCH v2 2/2] powerpc/mm/hugetlb: Switch hugetlb update to use pte_update
From: Aneesh Kumar K.V @ 2016-11-14 15:20 UTC (permalink / raw)
To: benh, paulus, mpe, akpm; +Cc: linuxppc-dev, linux-mm, Aneesh Kumar K.V
In-Reply-To: <20161114152020.4608-1-aneesh.kumar@linux.vnet.ibm.com>
Now that we have updated hugetlb functions to take vm_area_struct and we can
derive huge page size from vma, switch the pte update to use generic functions.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 34 +++++++---------------------
arch/powerpc/include/asm/hugetlb.h | 2 +-
2 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hugetlb.h b/arch/powerpc/include/asm/book3s/64/hugetlb.h
index 80fa0c828413..0a6db2086140 100644
--- a/arch/powerpc/include/asm/book3s/64/hugetlb.h
+++ b/arch/powerpc/include/asm/book3s/64/hugetlb.h
@@ -31,36 +31,18 @@ static inline int hstate_get_psize(struct hstate *hstate)
}
}
-static inline unsigned long huge_pte_update(struct mm_struct *mm, unsigned long addr,
+static inline unsigned long huge_pte_update(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep, unsigned long clr,
unsigned long set)
{
- if (radix_enabled()) {
- unsigned long old_pte;
+ unsigned long pg_sz;
- if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+ VM_WARN_ON(!is_vm_hugetlb_page(vma));
+ pg_sz = huge_page_size(hstate_vma(vma));
- unsigned long new_pte;
-
- old_pte = __radix_pte_update(ptep, ~0, 0);
- asm volatile("ptesync" : : : "memory");
- /*
- * new value of pte
- */
- new_pte = (old_pte | set) & ~clr;
- /*
- * For now let's do heavy pid flush
- * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
- */
- radix__flush_tlb_mm(mm);
-
- __radix_pte_update(ptep, 0, new_pte);
- } else
- old_pte = __radix_pte_update(ptep, clr, set);
- asm volatile("ptesync" : : : "memory");
- return old_pte;
- }
- return hash__pte_update(mm, addr, ptep, clr, set, true);
+ if (radix_enabled())
+ return radix__pte_update(vma->vm_mm, addr, ptep, clr, set, pg_sz);
+ return hash__pte_update(vma->vm_mm, addr, ptep, clr, set, true);
}
static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
@@ -69,7 +51,7 @@ static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
- huge_pte_update(vma->vm_mm, addr, ptep, _PAGE_WRITE, 0);
+ huge_pte_update(vma, addr, ptep, _PAGE_WRITE, 0);
}
#endif
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index bb1bf23d6f90..f0731dff76c2 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -136,7 +136,7 @@ static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_PPC64
- return __pte(huge_pte_update(vma->vm_mm, addr, ptep, ~0UL, 0));
+ return __pte(huge_pte_update(vma, addr, ptep, ~0UL, 0));
#else
return __pte(pte_update(ptep, ~0UL, 0));
#endif
--
2.10.2
--
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^ permalink raw reply related
* [PATCH v2 1/2] hugetlb: Change the function prototype to take vma_area_struct as arg
From: Aneesh Kumar K.V @ 2016-11-14 15:20 UTC (permalink / raw)
To: benh, paulus, mpe, akpm; +Cc: linuxppc-dev, linux-mm, Aneesh Kumar K.V
This help us to find the hugetlb page size which we need ot use on some
archs like ppc64 for tlbflush. This also make the interface consistent
with other hugetlb functions
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
NOTE: This series is dependent on another series posted here.
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-November/150948.html
arch/arm/include/asm/hugetlb-3level.h | 8 ++++----
arch/arm64/include/asm/hugetlb.h | 4 ++--
arch/arm64/mm/hugetlbpage.c | 7 +++++--
arch/ia64/include/asm/hugetlb.h | 8 ++++----
arch/metag/include/asm/hugetlb.h | 8 ++++----
arch/mips/include/asm/hugetlb.h | 7 ++++---
arch/parisc/include/asm/hugetlb.h | 4 ++--
arch/parisc/mm/hugetlbpage.c | 6 ++++--
arch/powerpc/include/asm/book3s/32/pgtable.h | 4 ++--
arch/powerpc/include/asm/book3s/64/hugetlb.h | 4 ++--
arch/powerpc/include/asm/hugetlb.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pgtable.h | 4 ++--
arch/powerpc/include/asm/nohash/64/pgtable.h | 4 ++--
arch/s390/include/asm/hugetlb.h | 12 ++++++------
arch/s390/mm/hugetlbpage.c | 3 ++-
arch/sh/include/asm/hugetlb.h | 8 ++++----
arch/sparc/include/asm/hugetlb.h | 6 +++---
arch/sparc/mm/hugetlbpage.c | 3 ++-
arch/tile/include/asm/hugetlb.h | 8 ++++----
arch/x86/include/asm/hugetlb.h | 8 ++++----
mm/hugetlb.c | 6 +++---
21 files changed, 68 insertions(+), 60 deletions(-)
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
index d4014fbe5ea3..b71839e1786f 100644
--- a/arch/arm/include/asm/hugetlb-3level.h
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -49,16 +49,16 @@ static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
ptep_clear_flush(vma, addr, ptep);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
index bbc1e35aa601..4e54d4b58d3e 100644
--- a/arch/arm64/include/asm/hugetlb.h
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -76,9 +76,9 @@ extern void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
extern int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep,
pte_t pte, int dirty);
-extern pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+extern pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep);
-extern void huge_ptep_set_wrprotect(struct mm_struct *mm,
+extern void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep);
extern void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep);
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index 2e49bd252fe7..5c8903433cd9 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -197,10 +197,11 @@ pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,
return entry;
}
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t pte;
+ struct mm_struct *mm = vma->vm_mm;
if (pte_cont(*ptep)) {
int ncontig, i;
@@ -263,9 +264,11 @@ int huge_ptep_set_access_flags(struct vm_area_struct *vma,
}
}
-void huge_ptep_set_wrprotect(struct mm_struct *mm,
+void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
+ struct mm_struct *mm = vma->vm_mm;
+
if (pte_cont(*ptep)) {
int ncontig, i;
pte_t *cpte;
diff --git a/arch/ia64/include/asm/hugetlb.h b/arch/ia64/include/asm/hugetlb.h
index ef65f026b11e..eb1c1d674200 100644
--- a/arch/ia64/include/asm/hugetlb.h
+++ b/arch/ia64/include/asm/hugetlb.h
@@ -26,10 +26,10 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -47,10 +47,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/metag/include/asm/hugetlb.h b/arch/metag/include/asm/hugetlb.h
index 905ed422dbeb..310b103127a6 100644
--- a/arch/metag/include/asm/hugetlb.h
+++ b/arch/metag/include/asm/hugetlb.h
@@ -28,10 +28,10 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -49,10 +49,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index 982bc0685330..4380acbff8e2 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -53,11 +53,12 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t clear;
pte_t pte = *ptep;
+ struct mm_struct *mm = vma->vm_mm;
pte_val(clear) = (unsigned long)invalid_pte_table;
set_pte_at(mm, addr, ptep, clear);
@@ -81,10 +82,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/parisc/include/asm/hugetlb.h b/arch/parisc/include/asm/hugetlb.h
index a65d888716c4..3a6070842016 100644
--- a/arch/parisc/include/asm/hugetlb.h
+++ b/arch/parisc/include/asm/hugetlb.h
@@ -8,7 +8,7 @@
void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte);
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep);
static inline int is_hugepage_only_range(struct mm_struct *mm,
@@ -54,7 +54,7 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-void huge_ptep_set_wrprotect(struct mm_struct *mm,
+void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep);
int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/parisc/mm/hugetlbpage.c b/arch/parisc/mm/hugetlbpage.c
index 5d6eea925cf4..e01fd08ed72c 100644
--- a/arch/parisc/mm/hugetlbpage.c
+++ b/arch/parisc/mm/hugetlbpage.c
@@ -142,11 +142,12 @@ void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
}
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep)
{
unsigned long flags;
pte_t entry;
+ struct mm_struct *mm = vma->vma_mm;
purge_tlb_start(flags);
entry = *ptep;
@@ -157,11 +158,12 @@ pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
}
-void huge_ptep_set_wrprotect(struct mm_struct *mm,
+void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
unsigned long flags;
pte_t old_pte;
+ struct mm_struct *mm = vma->vm_mm;
purge_tlb_start(flags);
old_pte = *ptep;
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h
index 0713626e9189..34c8fd0c5d04 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -216,10 +216,10 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
{
pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
diff --git a/arch/powerpc/include/asm/book3s/64/hugetlb.h b/arch/powerpc/include/asm/book3s/64/hugetlb.h
index 9a64f356a8e8..80fa0c828413 100644
--- a/arch/powerpc/include/asm/book3s/64/hugetlb.h
+++ b/arch/powerpc/include/asm/book3s/64/hugetlb.h
@@ -63,13 +63,13 @@ static inline unsigned long huge_pte_update(struct mm_struct *mm, unsigned long
return hash__pte_update(mm, addr, ptep, clr, set, true);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
- huge_pte_update(mm, addr, ptep, _PAGE_WRITE, 0);
+ huge_pte_update(vma->vm_mm, addr, ptep, _PAGE_WRITE, 0);
}
#endif
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 058d6311de87..bb1bf23d6f90 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -132,11 +132,11 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_PPC64
- return __pte(huge_pte_update(mm, addr, ptep, ~0UL, 0));
+ return __pte(huge_pte_update(vma->vm_mm, addr, ptep, ~0UL, 0));
#else
return __pte(pte_update(ptep, ~0UL, 0));
#endif
@@ -146,7 +146,7 @@ static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t pte;
- pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
+ pte = huge_ptep_get_and_clear(vma, addr, ptep);
flush_hugetlb_page(vma, addr);
}
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 24ee66bf7223..db83c15f1d54 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -260,10 +260,10 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
{
pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index 86d49dc60ec6..16c77d923209 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -257,13 +257,13 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
if ((pte_val(*ptep) & _PAGE_RW) == 0)
return;
- pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
+ pte_update(vma->vm_mm, addr, ptep, _PAGE_RW, 0, 1);
}
/*
diff --git a/arch/s390/include/asm/hugetlb.h b/arch/s390/include/asm/hugetlb.h
index 4c7fac75090e..eb411d59ab77 100644
--- a/arch/s390/include/asm/hugetlb.h
+++ b/arch/s390/include/asm/hugetlb.h
@@ -19,7 +19,7 @@
void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte);
pte_t huge_ptep_get(pte_t *ptep);
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep);
/*
@@ -50,7 +50,7 @@ static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long address, pte_t *ptep)
{
- huge_ptep_get_and_clear(vma->vm_mm, address, ptep);
+ huge_ptep_get_and_clear(vma, address, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
@@ -59,17 +59,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
{
int changed = !pte_same(huge_ptep_get(ptep), pte);
if (changed) {
- huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
+ huge_ptep_get_and_clear(vma, addr, ptep);
set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
}
return changed;
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- pte_t pte = huge_ptep_get_and_clear(mm, addr, ptep);
- set_huge_pte_at(mm, addr, ptep, pte_wrprotect(pte));
+ pte_t pte = huge_ptep_get_and_clear(vma, addr, ptep);
+ set_huge_pte_at(vma->vm_mm, addr, ptep, pte_wrprotect(pte));
}
static inline pte_t mk_huge_pte(struct page *page, pgprot_t pgprot)
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index cd404aa3931c..61146137b0d2 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -136,12 +136,13 @@ pte_t huge_ptep_get(pte_t *ptep)
return __rste_to_pte(pte_val(*ptep));
}
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t pte = huge_ptep_get(ptep);
pmd_t *pmdp = (pmd_t *) ptep;
pud_t *pudp = (pud_t *) ptep;
+ struct mm_struct *mm = vma->vm_mm;
if ((pte_val(*ptep) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
pudp_xchg_direct(mm, addr, pudp, __pud(_REGION3_ENTRY_EMPTY));
diff --git a/arch/sh/include/asm/hugetlb.h b/arch/sh/include/asm/hugetlb.h
index ef489a56fcce..925cbc0b4da9 100644
--- a/arch/sh/include/asm/hugetlb.h
+++ b/arch/sh/include/asm/hugetlb.h
@@ -40,10 +40,10 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -61,10 +61,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/sparc/include/asm/hugetlb.h b/arch/sparc/include/asm/hugetlb.h
index dcbf985ab243..c7c21738b46c 100644
--- a/arch/sparc/include/asm/hugetlb.h
+++ b/arch/sparc/include/asm/hugetlb.h
@@ -8,7 +8,7 @@
void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte);
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep);
static inline int is_hugepage_only_range(struct mm_struct *mm,
@@ -46,11 +46,11 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t old_pte = *ptep;
- set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
+ set_huge_pte_at(vma->vm_mm, addr, ptep, pte_wrprotect(old_pte));
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/sparc/mm/hugetlbpage.c b/arch/sparc/mm/hugetlbpage.c
index 988acc8b1b80..c5d1fb4a83a7 100644
--- a/arch/sparc/mm/hugetlbpage.c
+++ b/arch/sparc/mm/hugetlbpage.c
@@ -174,10 +174,11 @@ void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
maybe_tlb_batch_add(mm, addr + REAL_HPAGE_SIZE, ptep, orig, 0);
}
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep)
{
pte_t entry;
+ struct mm_struct *mm = vma->vm_mm;
entry = *ptep;
if (pte_present(entry))
diff --git a/arch/tile/include/asm/hugetlb.h b/arch/tile/include/asm/hugetlb.h
index 2fac5be4de26..aab3ff1cdb10 100644
--- a/arch/tile/include/asm/hugetlb.h
+++ b/arch/tile/include/asm/hugetlb.h
@@ -54,10 +54,10 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte(ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -76,10 +76,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/arch/x86/include/asm/hugetlb.h b/arch/x86/include/asm/hugetlb.h
index 3a106165e03a..47b7a102a6a2 100644
--- a/arch/x86/include/asm/hugetlb.h
+++ b/arch/x86/include/asm/hugetlb.h
@@ -41,10 +41,10 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte_at(mm, addr, ptep, pte);
}
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+static inline pte_t huge_ptep_get_and_clear(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- return ptep_get_and_clear(mm, addr, ptep);
+ return ptep_get_and_clear(vma->vm_mm, addr, ptep);
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -63,10 +63,10 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
return pte_wrprotect(pte);
}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+static inline void huge_ptep_set_wrprotect(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
- ptep_set_wrprotect(mm, addr, ptep);
+ ptep_set_wrprotect(vma->vm_mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index ec49d9ef1eef..6b140f213e33 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -3182,7 +3182,7 @@ int copy_hugetlb_page_range(struct mm_struct *dst, struct mm_struct *src,
set_huge_pte_at(dst, addr, dst_pte, entry);
} else {
if (cow) {
- huge_ptep_set_wrprotect(src, addr, src_pte);
+ huge_ptep_set_wrprotect(vma, addr, src_pte);
mmu_notifier_invalidate_range(src, mmun_start,
mmun_end);
}
@@ -3271,7 +3271,7 @@ void __unmap_hugepage_range(struct mmu_gather *tlb, struct vm_area_struct *vma,
set_vma_resv_flags(vma, HPAGE_RESV_UNMAPPED);
}
- pte = huge_ptep_get_and_clear(mm, address, ptep);
+ pte = huge_ptep_get_and_clear(vma, address, ptep);
tlb_remove_tlb_entry(tlb, ptep, address);
if (huge_pte_dirty(pte))
set_page_dirty(page);
@@ -4020,7 +4020,7 @@ unsigned long hugetlb_change_protection(struct vm_area_struct *vma,
continue;
}
if (!huge_pte_none(pte)) {
- pte = huge_ptep_get_and_clear(mm, address, ptep);
+ pte = huge_ptep_get_and_clear(vma, address, ptep);
pte = pte_mkhuge(huge_pte_modify(pte, newprot));
pte = arch_make_huge_pte(pte, vma, NULL, 0);
set_huge_pte_at(mm, address, ptep, pte);
--
2.10.2
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