* [GIT PULL] arm: mediatek: dts changes for v4.10
From: Matthias Brugger @ 2016-11-14 18:36 UTC (permalink / raw)
To: arm-DgEjT+Ai2ygdnm+yROfE0A
Cc: James Liao, Erin Lo, moderated list:ARM/Mediatek SoC support,
Shunli Wang,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Hi Arnd and Olof,
although late, please pull the following changes.
Thanks,
Matthias
---
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/mbgg/linux-mediatek.git tags/v4.9-next-dts
for you to fetch changes up to 28d6e3647bd7c869bfc251f9a7e283d78cef5fc5:
arm: dts: mt2701: Use real clock for UARTs (2016-11-11 15:25:09 +0100)
----------------------------------------------------------------
- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
----------------------------------------------------------------
Erin Lo (1):
arm: dts: mt2701: Use real clock for UARTs
James Liao (1):
arm: dts: mt2701: Add clock controller device nodes
Matthias Brugger (1):
arm64: dts: mt8173: Fix auxadc node
Shunli Wang (1):
soc: mediatek: Add MT2701 power dt-bindings
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +++---
arch/arm/boot/dts/mt2701.dtsi | 50
+++++++++++++++++++---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 ++
include/dt-bindings/power/mt2701-power.h | 27 ++++++++++++
4 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 include/dt-bindings/power/mt2701-power.h
^ permalink raw reply
* [GIT PULL] arm: mediatek: dts changes for v4.10
From: Matthias Brugger @ 2016-11-14 18:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd and Olof,
although late, please pull the following changes.
Thanks,
Matthias
---
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/mbgg/linux-mediatek.git tags/v4.9-next-dts
for you to fetch changes up to 28d6e3647bd7c869bfc251f9a7e283d78cef5fc5:
arm: dts: mt2701: Use real clock for UARTs (2016-11-11 15:25:09 +0100)
----------------------------------------------------------------
- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
----------------------------------------------------------------
Erin Lo (1):
arm: dts: mt2701: Use real clock for UARTs
James Liao (1):
arm: dts: mt2701: Add clock controller device nodes
Matthias Brugger (1):
arm64: dts: mt8173: Fix auxadc node
Shunli Wang (1):
soc: mediatek: Add MT2701 power dt-bindings
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +++---
arch/arm/boot/dts/mt2701.dtsi | 50
+++++++++++++++++++---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 ++
include/dt-bindings/power/mt2701-power.h | 27 ++++++++++++
4 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 include/dt-bindings/power/mt2701-power.h
^ permalink raw reply
* [PATCH/RESEND] recordmcount: arm: Implement make_nop
From: Steven Rostedt @ 2016-11-14 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018200707.36e549ee@gandalf.local.home>
On Tue, 18 Oct 2016 20:07:07 -0400
Steven Rostedt <rostedt@goodmis.org> wrote:
> On Tue, 18 Oct 2016 16:42:00 -0700
> Stephen Boyd <sboyd@codeaurora.org> wrote:
>
> > In similar spirit to x86 and arm64 support, add a make_nop_arm()
> > to replace calls to mcount with a nop in sections that aren't
> > traced.
> >
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Acked-by: Rabin Vincent <rabin@rab.in>
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> I can take this if I can get an ack from the ARM maintainers.
Any ARM maintainer want to ack this, or take it in their tree if they
haven't already?
-- Steve
^ permalink raw reply
* [PATCH RFC tip/core/rcu] SRCU rewrite
From: Paul E. McKenney @ 2016-11-14 18:36 UTC (permalink / raw)
To: linux-kernel
Cc: mingo, jiangshanlai, dipankar, akpm, mathieu.desnoyers, josh,
tglx, peterz, rostedt, dhowells, edumazet, dvhart, fweisbec, oleg,
bobby.prani, ldr709
SRCU uses two per-cpu counters: a nesting counter to count the number of
active critical sections, and a sequence counter to ensure that the nesting
counters don't change while they are being added together in
srcu_readers_active_idx_check().
This patch instead uses per-cpu lock and unlock counters. Because the both
counters only increase and srcu_readers_active_idx_check() reads the unlock
counter before the lock counter, this achieves the same end without having
to increment two different counters in srcu_read_lock(). This also saves a
smp_mb() in srcu_readers_active_idx_check().
A possible problem with this patch is that it can only handle
ULONG_MAX - NR_CPUS simultaneous readers, whereas the old version could
handle up to ULONG_MAX.
Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Lance Roy <ldr709@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
[ paulmck: Queued for 4.12, that is, merge window after this coming one. ]
diff --git a/include/linux/srcu.h b/include/linux/srcu.h
index dc8eb63c6568..0caea34d8c5f 100644
--- a/include/linux/srcu.h
+++ b/include/linux/srcu.h
@@ -34,8 +34,8 @@
#include <linux/workqueue.h>
struct srcu_struct_array {
- unsigned long c[2];
- unsigned long seq[2];
+ unsigned long lock_count[2];
+ unsigned long unlock_count[2];
};
struct rcu_batch {
diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c
index 87c51225ceec..6e4fd7680c70 100644
--- a/kernel/rcu/rcutorture.c
+++ b/kernel/rcu/rcutorture.c
@@ -564,10 +564,24 @@ static void srcu_torture_stats(void)
pr_alert("%s%s per-CPU(idx=%d):",
torture_type, TORTURE_FLAG, idx);
for_each_possible_cpu(cpu) {
+ unsigned long l0, l1;
+ unsigned long u0, u1;
long c0, c1;
+ struct srcu_struct_array* counts =
+ per_cpu_ptr(srcu_ctlp->per_cpu_ref, cpu);
- c0 = (long)per_cpu_ptr(srcu_ctlp->per_cpu_ref, cpu)->c[!idx];
- c1 = (long)per_cpu_ptr(srcu_ctlp->per_cpu_ref, cpu)->c[idx];
+ u0 = counts->unlock_count[!idx];
+ u1 = counts->unlock_count[idx];
+
+ /* Make sure that a lock is always counted if the corresponding
+ unlock is counted. */
+ smp_rmb();
+
+ l0 = counts->lock_count[!idx];
+ l1 = counts->lock_count[idx];
+
+ c0 = (long)(l0 - u0);
+ c1 = (long)(l1 - u1);
pr_cont(" %d(%ld,%ld)", cpu, c0, c1);
}
pr_cont("\n");
diff --git a/kernel/rcu/srcu.c b/kernel/rcu/srcu.c
index 9b9cdd549caa..edfdfadec821 100644
--- a/kernel/rcu/srcu.c
+++ b/kernel/rcu/srcu.c
@@ -141,34 +141,38 @@ EXPORT_SYMBOL_GPL(init_srcu_struct);
#endif /* #else #ifdef CONFIG_DEBUG_LOCK_ALLOC */
/*
- * Returns approximate total of the readers' ->seq[] values for the
+ * Returns approximate total of the readers' ->lock_count[] values for the
* rank of per-CPU counters specified by idx.
*/
-static unsigned long srcu_readers_seq_idx(struct srcu_struct *sp, int idx)
+static unsigned long srcu_readers_lock_idx(struct srcu_struct *sp, int idx)
{
int cpu;
unsigned long sum = 0;
unsigned long t;
for_each_possible_cpu(cpu) {
- t = READ_ONCE(per_cpu_ptr(sp->per_cpu_ref, cpu)->seq[idx]);
+ struct srcu_struct_array* cpu_counts =
+ per_cpu_ptr(sp->per_cpu_ref, cpu);
+ t = READ_ONCE(cpu_counts->lock_count[idx]);
sum += t;
}
return sum;
}
/*
- * Returns approximate number of readers active on the specified rank
- * of the per-CPU ->c[] counters.
+ * Returns approximate total of the readers' ->unlock_count[] values for the
+ * rank of per-CPU counters specified by idx.
*/
-static unsigned long srcu_readers_active_idx(struct srcu_struct *sp, int idx)
+static unsigned long srcu_readers_unlock_idx(struct srcu_struct *sp, int idx)
{
int cpu;
unsigned long sum = 0;
unsigned long t;
for_each_possible_cpu(cpu) {
- t = READ_ONCE(per_cpu_ptr(sp->per_cpu_ref, cpu)->c[idx]);
+ struct srcu_struct_array* cpu_counts =
+ per_cpu_ptr(sp->per_cpu_ref, cpu);
+ t = READ_ONCE(cpu_counts->unlock_count[idx]);
sum += t;
}
return sum;
@@ -176,79 +180,43 @@ static unsigned long srcu_readers_active_idx(struct srcu_struct *sp, int idx)
/*
* Return true if the number of pre-existing readers is determined to
- * be stably zero. An example unstable zero can occur if the call
- * to srcu_readers_active_idx() misses an __srcu_read_lock() increment,
- * but due to task migration, sees the corresponding __srcu_read_unlock()
- * decrement. This can happen because srcu_readers_active_idx() takes
- * time to sum the array, and might in fact be interrupted or preempted
- * partway through the summation.
+ * be zero.
*/
static bool srcu_readers_active_idx_check(struct srcu_struct *sp, int idx)
{
- unsigned long seq;
+ unsigned long unlocks;
- seq = srcu_readers_seq_idx(sp, idx);
+ unlocks = srcu_readers_unlock_idx(sp, idx);
/*
- * The following smp_mb() A pairs with the smp_mb() B located in
- * __srcu_read_lock(). This pairing ensures that if an
- * __srcu_read_lock() increments its counter after the summation
- * in srcu_readers_active_idx(), then the corresponding SRCU read-side
- * critical section will see any changes made prior to the start
- * of the current SRCU grace period.
+ * Make sure that a lock is always counted if the corresponding unlock
+ * is counted. Needs to be a smp_mb() as the read side may contain a
+ * read from a variable that is written to before the synchronize_srcu()
+ * in the write side. In this case smp_mb()s A and B act like the store
+ * buffering pattern.
*
- * Also, if the above call to srcu_readers_seq_idx() saw the
- * increment of ->seq[], then the call to srcu_readers_active_idx()
- * must see the increment of ->c[].
+ * This smp_mb() also pairs with smp_mb() C to prevent writes after the
+ * synchronize_srcu() from being executed before the grace period ends.
*/
smp_mb(); /* A */
/*
- * Note that srcu_readers_active_idx() can incorrectly return
- * zero even though there is a pre-existing reader throughout.
- * To see this, suppose that task A is in a very long SRCU
- * read-side critical section that started on CPU 0, and that
- * no other reader exists, so that the sum of the counters
- * is equal to one. Then suppose that task B starts executing
- * srcu_readers_active_idx(), summing up to CPU 1, and then that
- * task C starts reading on CPU 0, so that its increment is not
- * summed, but finishes reading on CPU 2, so that its decrement
- * -is- summed. Then when task B completes its sum, it will
- * incorrectly get zero, despite the fact that task A has been
- * in its SRCU read-side critical section the whole time.
- *
- * We therefore do a validation step should srcu_readers_active_idx()
- * return zero.
- */
- if (srcu_readers_active_idx(sp, idx) != 0)
- return false;
-
- /*
- * The remainder of this function is the validation step.
- * The following smp_mb() D pairs with the smp_mb() C in
- * __srcu_read_unlock(). If the __srcu_read_unlock() was seen
- * by srcu_readers_active_idx() above, then any destructive
- * operation performed after the grace period will happen after
- * the corresponding SRCU read-side critical section.
+ * If the locks are the same as the unlocks, then there must of have
+ * been no readers on this index at some time in between. This does not
+ * mean that there are no more readers, as one could have read the
+ * current index but have incremented the lock counter yet.
*
- * Note that there can be at most NR_CPUS worth of readers using
- * the old index, which is not enough to overflow even a 32-bit
- * integer. (Yes, this does mean that systems having more than
- * a billion or so CPUs need to be 64-bit systems.) Therefore,
- * the sum of the ->seq[] counters cannot possibly overflow.
- * Therefore, the only way that the return values of the two
- * calls to srcu_readers_seq_idx() can be equal is if there were
- * no increments of the corresponding rank of ->seq[] counts
- * in the interim. But the missed-increment scenario laid out
- * above includes an increment of the ->seq[] counter by
- * the corresponding __srcu_read_lock(). Therefore, if this
- * scenario occurs, the return values from the two calls to
- * srcu_readers_seq_idx() will differ, and thus the validation
- * step below suffices.
+ * Note that there can be at most NR_CPUS worth of readers using the old
+ * index that haven't incremented ->lock_count[] yet. Therefore, the
+ * sum of the ->lock_count[]s cannot increment enough times to overflow
+ * and end up equal the sum of the ->unlock_count[]s, as long as there
+ * are at most ULONG_MAX - NR_CPUS readers at a time. (Yes, this does
+ * mean that systems having more than a billion or so CPUs need to be
+ * 64-bit systems.) Therefore, the only way that the return values of
+ * the two calls to srcu_readers_(un)lock_idx() can be equal is if there
+ * are no active readers using this index.
*/
- smp_mb(); /* D */
-
- return srcu_readers_seq_idx(sp, idx) == seq;
+ return srcu_readers_lock_idx(sp, idx) == unlocks;
}
/**
@@ -266,8 +234,12 @@ static bool srcu_readers_active(struct srcu_struct *sp)
unsigned long sum = 0;
for_each_possible_cpu(cpu) {
- sum += READ_ONCE(per_cpu_ptr(sp->per_cpu_ref, cpu)->c[0]);
- sum += READ_ONCE(per_cpu_ptr(sp->per_cpu_ref, cpu)->c[1]);
+ struct srcu_struct_array* cpu_counts =
+ per_cpu_ptr(sp->per_cpu_ref, cpu);
+ sum += READ_ONCE(cpu_counts->lock_count[0]);
+ sum += READ_ONCE(cpu_counts->lock_count[1]);
+ sum -= READ_ONCE(cpu_counts->unlock_count[0]);
+ sum -= READ_ONCE(cpu_counts->unlock_count[1]);
}
return sum;
}
@@ -298,9 +270,8 @@ int __srcu_read_lock(struct srcu_struct *sp)
int idx;
idx = READ_ONCE(sp->completed) & 0x1;
- __this_cpu_inc(sp->per_cpu_ref->c[idx]);
+ __this_cpu_inc(sp->per_cpu_ref->lock_count[idx]);
smp_mb(); /* B */ /* Avoid leaking the critical section. */
- __this_cpu_inc(sp->per_cpu_ref->seq[idx]);
return idx;
}
EXPORT_SYMBOL_GPL(__srcu_read_lock);
@@ -314,7 +285,7 @@ EXPORT_SYMBOL_GPL(__srcu_read_lock);
void __srcu_read_unlock(struct srcu_struct *sp, int idx)
{
smp_mb(); /* C */ /* Avoid leaking the critical section. */
- this_cpu_dec(sp->per_cpu_ref->c[idx]);
+ this_cpu_inc(sp->per_cpu_ref->unlock_count[idx]);
}
EXPORT_SYMBOL_GPL(__srcu_read_unlock);
@@ -349,7 +320,7 @@ static bool try_check_zero(struct srcu_struct *sp, int idx, int trycount)
/*
* Increment the ->completed counter so that future SRCU readers will
- * use the other rank of the ->c[] and ->seq[] arrays. This allows
+ * use the other rank of the ->(un)lock_count[] arrays. This allows
* us to wait for pre-existing readers in a starvation-free manner.
*/
static void srcu_flip(struct srcu_struct *sp)
^ permalink raw reply related
* Re: [PATCH/RESEND] recordmcount: arm: Implement make_nop
From: Steven Rostedt @ 2016-11-14 18:36 UTC (permalink / raw)
To: Stephen Boyd; +Cc: linux-kernel, linux-arm-kernel, Andrew Morton, Russell King
In-Reply-To: <20161018200707.36e549ee@gandalf.local.home>
On Tue, 18 Oct 2016 20:07:07 -0400
Steven Rostedt <rostedt@goodmis.org> wrote:
> On Tue, 18 Oct 2016 16:42:00 -0700
> Stephen Boyd <sboyd@codeaurora.org> wrote:
>
> > In similar spirit to x86 and arm64 support, add a make_nop_arm()
> > to replace calls to mcount with a nop in sections that aren't
> > traced.
> >
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Acked-by: Rabin Vincent <rabin@rab.in>
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> I can take this if I can get an ack from the ARM maintainers.
Any ARM maintainer want to ack this, or take it in their tree if they
haven't already?
-- Steve
^ permalink raw reply
* Re: [PATCH] icmp: Restore resistence to abnormal messages
From: David Miller @ 2016-11-14 18:36 UTC (permalink / raw)
To: googuy; +Cc: kuznet, jmorris, yoshfuji, kaber, netdev, linux-kernel
In-Reply-To: <20161111202018.13795-1-googuy@gmail.com>
From: Vicente Jimenez Aguilar <googuy@gmail.com>
Date: Fri, 11 Nov 2016 21:20:18 +0100
> @@ -819,6 +820,12 @@ static bool icmp_unreach(struct sk_buff *skb)
> /* fall through */
> case 0:
> info = ntohs(icmph->un.frag.mtu);
> + /* Handle weird case where next hop MTU is
> + * equal to or exceeding dropped packet size
> + */
> + old_mtu = ntohs(iph->tot_len);
> + if (info >= old_mtu)
> + info = old_mtu - 2;
This isn't something the old code did.
The old code behaved much differently.
In the case where the new mtu was smaller than 68 or larger than
the iph->tot_len value, it would do several things:
1) First it would check for a BSD 4.2 anomaly and subtract old_mtu
by the IP header length.
2) Second, it would try to guess the intended MTU using the
mtu_plateau table.
I don't see any code where a subtraction by a fixed constant of 2
occurred.
Nor can I figure out what that might accomplish. If you really
want to do this, you have to docuement what this 2 means, what
it is accomplishing, and why you have choosen to accomplish it
this way.
Thanks.
^ permalink raw reply
* [PATCH v3 03/11] ARM: dts: r8a73a4: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
- Drop CCCR, as it is not a lone register, but part of the HPB/APB
block,
v2:
- New.
---
arch/arm/boot/dts/r8a73a4.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index ca8672778fe067e1..53183ffe04c11c11 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -751,6 +751,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 05/11] ARM: dts: r8a7790: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7790.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a946474be9cf1e6b..f554ef3c8096726a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1471,6 +1471,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7790-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 04/11] ARM: dts: r8a7779: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7779.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 3005308a1807ca43..9d3bb74bd3f684d5 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -590,6 +590,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0xff000044 4>;
+ };
+
sysc: system-controller@ffd85000 {
compatible = "renesas,r8a7779-sysc";
reg = <0xffd85000 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 06/11] ARM: dts: r8a7791: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7791.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 091d7fb6ee7d53cc..4c50de2faef12301 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1485,6 +1485,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 09/11] ARM: dts: r8a7794: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7794.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 364b4aa8d1c1aa28..63dc7f29d216c32e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1377,6 +1377,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7794-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 01/11] ARM: shmobile: Document DT bindings for Product Register
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add device tree binding documentation for the Product Register (PRR),
which provides product and revision information on most Renesas ARM
SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
---
v3:
- Add Acked-by,
- Drop "renesas,cccr", as the CCCR is not a lone register, but part of
the HPB/APB block, which will need its own set of bindings,
v2:
- New.
---
Documentation/devicetree/bindings/arm/shmobile.txt | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index a1e94da0e322c8f4..1be9e8a7e2c43dfc 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -81,3 +81,21 @@ Boards:
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"
+
+
+Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
+product and revision information. If present, a device node for this register
+should be added.
+
+Required properties:
+ - compatible: Must be "renesas,prr".
+ - reg: Base address and length of the register block.
+
+
+Examples
+--------
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v3 00/11] soc: renesas: Identify SoC and register with the SoC bus
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
Hi Simon, Magnus,
Some Renesas SoCs may exist in different revisions, providing slightly
different functionalities (e.g. R-Car H3 ES1.x and ES2.0), and behavior
(errate and quirks). This needs to be catered for by drivers and/or
platform code. The recently proposed soc_device_match() API is a good
fit to handle this.
This patch series implements the core infrastructure to provide SoC and
revision information through the SoC bus for Renesas ARM SoCs.
Changes compared to v2 (more details in the individual patches):
- Add Acked-by,
- Drop soc_device_match() core infrastructure, as this now exists in
its own immutable branch,
- Re-add SoC families and family names,
- Re-add RZ/A1H and R-Car M1A support, without revision info,
- Drop "renesas,cccr" bindings and patches added CCCR devices nodeas,
as the CCCR is not a lone register, but part of the HPB/APB register
block. DT support for obtaining the CCCR register address from DT is
thus postponed, pending DT bindings for HPB/APB,
- Include patches to add PRR device nodes for all relevant SoCs.
Changes compared to v1:
- Add Acked-by,
- New patches:
- "[4/7] base: soc: Provide a dummy implementation of
soc_device_match()",
- "[5/7] ARM: shmobile: Document DT bindings for CCCR and PRR",
- "[6/7] arm64: dts: r8a7795: Add device node for PRR"
(more similar patches available, I'm not yet spamming you all
with them),
- Drop SoC families and family names; use fixed "Renesas" instead,
- Drop EMEV2, which doesn't have a chip ID register, and doesn't share
devices with other SoCs,
- Drop RZ/A1H and R-CAR M1A, which don't have chip ID registers (for
M1A: not accessible from the ARM core?),
- On arm, move "select SOC_BUS" from ARCH_RENESAS to Kconfig symbols
for SoCs that provide a chip ID register,
- Build renesas-soc only if SOC_BUS is enabled,
- Use "renesas,prr" and "renesas,cccr" device nodes in DT if
available, else fall back to hardcoded addresses for compatibility
with existing DTBs,
- Remove verification of product IDs; just print the ID instead,
- Don't register the SoC bus if the chip ID register is missing,
- Change R-Mobile APE6 fallback to use PRR instead of CCCR (it has
both).
Dependencies:
- Core soc_device_match() infrastructure, available from signed tag
soc-device-match-tag1 in
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git,
- Tag renesas-devel-20161114-v4.9-rc5 in Simon's renesas repository.
Tested on (machine, family, soc_id, optional revision):
Genmai, RZ/A, r7s72100
APE6EVM, R-Mobile, r8a73a4, ES1.0
armadillo 800 eva, R-Mobile, r8a7740, ES2.0
bockw, R-Car Gen1, r8a7778
marzen, R-Car Gen1, r8a7779, ES1.0
Lager, R-Car Gen2, r8a7790, ES1.0
Koelsch, R-Car Gen2, r8a7791, ES1.0
Porter, R-Car Gen2, r8a7791, ES3.0
Blanche, R-Car Gen2, r8a7792, ES1.1
Gose, R-Car Gen2, r8a7793, ES1.0
Alt, R-Car Gen2, r8a7794, ES1.0
Renesas Salvator-X board based on r8a7795, R-Car Gen3, r8a7795, ES1.0
Renesas Salvator-X board based on r8a7795, R-Car Gen3, r8a7795, ES1.1
Renesas Salvator-X board based on r8a7796, R-Car Gen3, r8a7796, ES1.0
KZM-A9-GT, SH-Mobile, sh73a0, ES2.0
For your convenience, this series is also available in the
topic/renesas-soc-id-v3 branch of my renesas-drivers git repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
As this is a dependency for driver updates for R-Car H3 ES2.0 (HDMI,
Ethernet, clock, pinctrl, ...), it would be good if this would be in
v4.10.
Thanks for merging soc-device-match-tag1, and applying this series on
top!
Geert Uytterhoeven (11):
ARM: shmobile: Document DT bindings for Product Register
soc: renesas: Identify SoC and register with the SoC bus
ARM: dts: r8a73a4: Add device node for PRR
ARM: dts: r8a7779: Add device node for PRR
ARM: dts: r8a7790: Add device node for PRR
ARM: dts: r8a7791: Add device node for PRR
ARM: dts: r8a7792: Add device node for PRR
ARM: dts: r8a7793: Add device node for PRR
ARM: dts: r8a7794: Add device node for PRR
arm64: dts: r8a7795: Add device node for PRR
arm64: dts: r8a7796: Add device node for PRR
Documentation/devicetree/bindings/arm/shmobile.txt | 18 ++
arch/arm/boot/dts/r8a73a4.dtsi | 5 +
arch/arm/boot/dts/r8a7779.dtsi | 5 +
arch/arm/boot/dts/r8a7790.dtsi | 5 +
arch/arm/boot/dts/r8a7791.dtsi | 5 +
arch/arm/boot/dts/r8a7792.dtsi | 5 +
arch/arm/boot/dts/r8a7793.dtsi | 5 +
arch/arm/boot/dts/r8a7794.dtsi | 5 +
arch/arm/mach-shmobile/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 257 +++++++++++++++++++++
14 files changed, 324 insertions(+)
create mode 100644 drivers/soc/renesas/renesas-soc.c
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3 07/11] ARM: dts: r8a7792: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7792.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index a75e0cd312c5ecdf..69789020cf39e95f 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -120,6 +120,11 @@
IRQ_TYPE_LEVEL_LOW)>;
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 07/11] ARM: dts: r8a7792: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7792.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index a75e0cd312c5ecdf..69789020cf39e95f 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -120,6 +120,11 @@
IRQ_TYPE_LEVEL_LOW)>;
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 08/11] ARM: dts: r8a7793: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7793.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 629d3d60d1cd7168..a377dda177241da0 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1306,6 +1306,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7793-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 02/11] soc: renesas: Identify SoC and register with the SoC bus
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Identify the SoC type and revision, and register this information with
the SoC bus, so it is available under /sys/devices/soc0/, and can be
checked where needed using soc_device_match().
Identification is done using the Product Register or Common Chip Code
Register, as declared in DT (PRR only for now), or using a hardcoded
fallback if missing.
Example:
Detected Renesas R-Car Gen2 r8a7791 ES1.0
...
# cat /sys/devices/soc0/{machine,family,soc_id,revision}
Koelsch
R-Car Gen2
r8a7791
ES1.0
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Re-add SoC families and family names,
- Re-add RZ/A1H and R-Car M1A, not providing a revision,
- On arm, move "select SOC_BUS" to ARCH_RENESAS again,
- Drop "renesas,cccr" DT support, as the CCCR is not a lone register,
but part of the HPB/APB block, pending full DT bindings for HPB/APB,
- Re-add verification of product IDs,
- Re-add registering the SoC bus if the chip ID register is missing,
- Revert APE6 fallback to CCCR (it has both), as it's a member of the
R-Mobile family,
- Use of_match_node(..., of_root) instead of
of_find_matching_node_and_match(),
- Mark structures __maybe_unused to avoid compiler warnings,
v2:
- Drop SoC families and family names; use fixed "Renesas" instead,
- Drop EMEV2, which doesn't have a chip ID register, and doesn't share
devices with other SoCs,
- Drop RZ/A1H and R-CAR M1A, which don't have chip ID registers (for
M1A: not accessible from the ARM core?),
- On arm, move "select SOC_BUS" from ARCH_RENESAS to Kconfig symbols
for SoCs that provide a chip ID register,
- Build renesas-soc only if SOC_BUS is enabled,
- Use "renesas,prr" and "renesas,cccr" device nodes in DT if
available, else fall back to hardcoded addresses for compatibility
with existing DTBs,
- Remove verification of product IDs; just print the ID instead,
- Don't register the SoC bus if the chip ID register is missing,
- Change R-Mobile APE6 fallback to use PRR instead of CCCR (it has
both).
---
arch/arm/mach-shmobile/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 257 ++++++++++++++++++++++++++++++++++++++
4 files changed, 261 insertions(+)
create mode 100644 drivers/soc/renesas/renesas-soc.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 6fbd9b7d2d67a18f..5e7b0503921e221f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,7 @@ menuconfig ARCH_RENESAS
select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
+ select SOC_BUS
select ZONE_DMA if ARM_LPAE
if ARCH_RENESAS
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 101794f5ce1008b7..b751c6891c6a51ed 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -143,6 +143,7 @@ config ARCH_RENESAS
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
+ select SOC_BUS
help
This enables support for the ARMv8 based Renesas SoCs.
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 9e0bb329594c4fca..1652df037955e0e6 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -1,3 +1,5 @@
+obj-$(CONFIG_SOC_BUS) += renesas-soc.o
+
obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o
obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
new file mode 100644
index 0000000000000000..330960312296f603
--- /dev/null
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -0,0 +1,257 @@
+/*
+ * Renesas SoC Identification
+ *
+ * Copyright (C) 2014-2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+
+struct renesas_family {
+ const char name[16];
+ u32 reg; /* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rcar_gen1 __initconst __maybe_unused = {
+ .name = "R-Car Gen1",
+ .reg = 0xff000044, /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rcar_gen2 __initconst __maybe_unused = {
+ .name = "R-Car Gen2",
+ .reg = 0xff000044, /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = {
+ .name = "R-Car Gen3",
+ .reg = 0xfff00044, /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
+ .name = "R-Mobile",
+ .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
+};
+
+static const struct renesas_family fam_rza __initconst __maybe_unused = {
+ .name = "RZ/A",
+};
+
+static const struct renesas_family fam_rzg __initconst __maybe_unused = {
+ .name = "RZ/G",
+ .reg = 0xff000044, /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
+ .name = "SH-Mobile",
+ .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
+};
+
+
+struct renesas_soc {
+ const struct renesas_family *family;
+ u8 id;
+};
+
+static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = {
+ .family = &fam_rza,
+};
+
+static const struct renesas_soc soc_rmobile_ape6 __initconst __maybe_unused = {
+ .family = &fam_rmobile,
+ .id = 0x3f,
+};
+
+static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = {
+ .family = &fam_rmobile,
+ .id = 0x40,
+};
+
+static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x47,
+};
+
+static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x4c,
+};
+
+static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
+ .family = &fam_rcar_gen1,
+};
+
+static const struct renesas_soc soc_rcar_h1 __initconst __maybe_unused = {
+ .family = &fam_rcar_gen1,
+ .id = 0x3b,
+};
+
+static const struct renesas_soc soc_rcar_h2 __initconst __maybe_unused = {
+ .family = &fam_rcar_gen2,
+ .id = 0x45,
+};
+
+static const struct renesas_soc soc_rcar_m2_w __initconst __maybe_unused = {
+ .family = &fam_rcar_gen2,
+ .id = 0x47,
+};
+
+static const struct renesas_soc soc_rcar_v2h __initconst __maybe_unused = {
+ .family = &fam_rcar_gen2,
+ .id = 0x4a,
+};
+
+static const struct renesas_soc soc_rcar_m2_n __initconst __maybe_unused = {
+ .family = &fam_rcar_gen2,
+ .id = 0x4b,
+};
+
+static const struct renesas_soc soc_rcar_e2 __initconst __maybe_unused = {
+ .family = &fam_rcar_gen2,
+ .id = 0x4c,
+};
+
+static const struct renesas_soc soc_rcar_h3 __initconst __maybe_unused = {
+ .family = &fam_rcar_gen3,
+ .id = 0x4f,
+};
+
+static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
+ .family = &fam_rcar_gen3,
+ .id = 0x52,
+};
+
+static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
+ .family = &fam_shmobile,
+ .id = 0x37,
+};
+
+
+static const struct of_device_id renesas_socs[] __initconst = {
+#ifdef CONFIG_ARCH_R7S72100
+ { .compatible = "renesas,r7s72100", .data = &soc_rz_a1h },
+#endif
+#ifdef CONFIG_ARCH_R8A73A4
+ { .compatible = "renesas,r8a73a4", .data = &soc_rmobile_ape6 },
+#endif
+#ifdef CONFIG_ARCH_R8A7740
+ { .compatible = "renesas,r8a7740", .data = &soc_rmobile_a1 },
+#endif
+#ifdef CONFIG_ARCH_R8A7743
+ { .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
+#endif
+#ifdef CONFIG_ARCH_R8A7745
+ { .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
+#endif
+#ifdef CONFIG_ARCH_R8A7778
+ { .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
+#endif
+#ifdef CONFIG_ARCH_R8A7779
+ { .compatible = "renesas,r8a7779", .data = &soc_rcar_h1 },
+#endif
+#ifdef CONFIG_ARCH_R8A7790
+ { .compatible = "renesas,r8a7790", .data = &soc_rcar_h2 },
+#endif
+#ifdef CONFIG_ARCH_R8A7791
+ { .compatible = "renesas,r8a7791", .data = &soc_rcar_m2_w },
+#endif
+#ifdef CONFIG_ARCH_R8A7792
+ { .compatible = "renesas,r8a7792", .data = &soc_rcar_v2h },
+#endif
+#ifdef CONFIG_ARCH_R8A7793
+ { .compatible = "renesas,r8a7793", .data = &soc_rcar_m2_n },
+#endif
+#ifdef CONFIG_ARCH_R8A7794
+ { .compatible = "renesas,r8a7794", .data = &soc_rcar_e2 },
+#endif
+#ifdef CONFIG_ARCH_R8A7795
+ { .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
+#endif
+#ifdef CONFIG_ARCH_R8A7796
+ { .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
+#endif
+#ifdef CONFIG_ARCH_SH73A0
+ { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
+#endif
+ { /* sentinel */ }
+};
+
+static int __init renesas_soc_init(void)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ const struct renesas_family *family;
+ const struct of_device_id *match;
+ const struct renesas_soc *soc;
+ void __iomem *chipid = NULL;
+ struct soc_device *soc_dev;
+ struct device_node *np;
+ unsigned int product;
+
+ match = of_match_node(renesas_socs, of_root);
+ if (!match)
+ return -ENODEV;
+
+ soc = match->data;
+ family = soc->family;
+
+ /* Try PRR first, then hardcoded fallback */
+ np = of_find_compatible_node(NULL, NULL, "renesas,prr");
+ if (np) {
+ chipid = of_iomap(np, 0);
+ of_node_put(np);
+ } else if (soc->id) {
+ chipid = ioremap(family->reg, 4);
+ }
+ if (chipid) {
+ product = readl(chipid);
+ iounmap(chipid);
+ if (soc->id && ((product >> 8) & 0xff) != soc->id) {
+ pr_warn("SoC mismatch (product = 0x%x)\n", product);
+ return -ENODEV;
+ }
+ }
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return -ENOMEM;
+
+ np = of_find_node_by_path("/");
+ of_property_read_string(np, "model", &soc_dev_attr->machine);
+ of_node_put(np);
+
+ soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
+ soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
+ GFP_KERNEL);
+ if (chipid)
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
+ ((product >> 4) & 0x0f) + 1,
+ product & 0xf);
+
+ pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
+ soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree_const(soc_dev_attr->soc_id);
+ kfree_const(soc_dev_attr->family);
+ kfree(soc_dev_attr);
+ return PTR_ERR(soc_dev);
+ }
+
+ return 0;
+}
+core_initcall(renesas_soc_init);
--
1.9.1
^ permalink raw reply related
* [PATCH v3 08/11] ARM: dts: r8a7793: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7793.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 629d3d60d1cd7168..a377dda177241da0 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1306,6 +1306,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7793-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 10/11] arm64: dts: r8a7795: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- No changes,
v2:
- New.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 681f54422375f4f7..a39a702b904da73c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -321,6 +321,11 @@
#power-domain-cells = <0>;
};
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7795-sysc";
reg = <0 0xe6180000 0 0x0400>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 06/11] ARM: dts: r8a7791: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm/boot/dts/r8a7791.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 091d7fb6ee7d53cc..4c50de2faef12301 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1485,6 +1485,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe6180000 0 0x0200>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 11/11] arm64: dts: r8a7796: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Add to posted series,
v2:
- New.
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 9599f5691099054b..41a050d2f1925552 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -243,6 +243,11 @@
#power-domain-cells = <0>;
};
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7796-sysc";
reg = <0 0xe6180000 0 0x0400>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 03/11] ARM: dts: r8a73a4: Add device node for PRR
From: Geert Uytterhoeven @ 2016-11-14 18:37 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Arnd Bergmann, Rob Herring, Mark Rutland, Dirk Behme,
linux-renesas-soc, devicetree, linux-arm-kernel,
Geert Uytterhoeven
In-Reply-To: <1479148637-5399-1-git-send-email-geert+renesas@glider.be>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Drop CCCR, as it is not a lone register, but part of the HPB/APB
block,
v2:
- New.
---
arch/arm/boot/dts/r8a73a4.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index ca8672778fe067e1..53183ffe04c11c11 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -751,6 +751,11 @@
};
};
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
--
1.9.1
^ permalink raw reply related
* [GIT PULL] arm: mediatek: kconfig changes for v4.10
From: Matthias Brugger @ 2016-11-14 18:37 UTC (permalink / raw)
To: arm-DgEjT+Ai2ygdnm+yROfE0A
Cc: Masahiro Yamada, moderated list:ARM/Mediatek SoC support,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Hi Arnd and Olof,
although late, please pull the following changes.
Thanks,
Matthias
---
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/mbgg/linux-mediatek.git tags/v4.9-next-kconfig
for you to fetch changes up to 494975c9cc00f69bf71de0991dcebda9b2911aa0:
ARM: mediatek: clean up mach-mediatek/Makefile (2016-10-31 15:26:23
-0600)
----------------------------------------------------------------
- clean up mach-mediatek Makefile as kbuild only descends into the folder if
ARCH_MEDIATEK is enabled
----------------------------------------------------------------
Masahiro Yamada (1):
ARM: mediatek: clean up mach-mediatek/Makefile
arch/arm/mach-mediatek/Makefile | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
^ permalink raw reply
* [GIT PULL] arm: mediatek: kconfig changes for v4.10
From: Matthias Brugger @ 2016-11-14 18:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd and Olof,
although late, please pull the following changes.
Thanks,
Matthias
---
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
https://github.com/mbgg/linux-mediatek.git tags/v4.9-next-kconfig
for you to fetch changes up to 494975c9cc00f69bf71de0991dcebda9b2911aa0:
ARM: mediatek: clean up mach-mediatek/Makefile (2016-10-31 15:26:23
-0600)
----------------------------------------------------------------
- clean up mach-mediatek Makefile as kbuild only descends into the folder if
ARCH_MEDIATEK is enabled
----------------------------------------------------------------
Masahiro Yamada (1):
ARM: mediatek: clean up mach-mediatek/Makefile
arch/arm/mach-mediatek/Makefile | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
^ permalink raw reply
* Re: [PATCH] net: alx: use new api ethtool_{get|set}_link_ksettings
From: David Miller @ 2016-11-14 18:38 UTC (permalink / raw)
To: tremyfr; +Cc: jcliburn, chris.snook, netdev, linux-kernel
In-Reply-To: <1478903437-9049-1-git-send-email-tremyfr@gmail.com>
From: Philippe Reynes <tremyfr@gmail.com>
Date: Fri, 11 Nov 2016 23:30:37 +0100
> The ethtool api {get|set}_settings is deprecated.
> We move this driver to new api {get|set}_link_ksettings.
>
> Signed-off-by: Philippe Reynes <tremyfr@gmail.com>
Applied.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.