* Re: corrupt leaf, slot offset bad
From: Kai Krakow @ 2016-11-14 20:28 UTC (permalink / raw)
To: linux-btrfs
In-Reply-To: <20161011140949.GA5284@localhost.localdomain>
Am Tue, 11 Oct 2016 07:09:49 -0700
schrieb Liu Bo <bo.li.liu@oracle.com>:
> On Tue, Oct 11, 2016 at 02:48:09PM +0200, David Sterba wrote:
> > Hi,
> >
> > looks like a lot of random bitflips.
> >
> > On Mon, Oct 10, 2016 at 11:50:14PM +0200, aron@aron.ws wrote:
> > > item 109 has a few strange chars in its name (and it's
> > > truncated): 1-x86_64.pkg.tar.xz 0x62 0x14 0x0a 0x0a
> > >
> > > item 105 key (261 DIR_ITEM 54556048) itemoff 11723
> > > itemsize 72 location key (606286 INODE_ITEM 0) type FILE
> > > namelen 42 datalen 0 name:
> > > python2-gobject-3.20.1-1-x86_64.pkg.tar.xz item 106 key (261
> > > DIR_ITEM 56363628) itemoff 11660 itemsize 63 location key (894298
> > > INODE_ITEM 0) type FILE namelen 33 datalen 0 name:
> > > unrar-1:5.4.5-1-x86_64.pkg.tar.xz item 107 key (261 DIR_ITEM
> > > 66963651) itemoff 11600 itemsize 60 location key (1178 INODE_ITEM
> > > 0) type FILE namelen 30 datalen 0 name:
> > > glibc-2.23-5-x86_64.pkg.tar.xz item 108 key (261 DIR_ITEM
> > > 68561395) itemoff 11532 itemsize 68 location key (660578
> > > INODE_ITEM 0) type FILE namelen 38 datalen 0 name:
> > > squashfs-tools-4.3-4-x86_64.pkg.tar.xz item 109 key (261 DIR_ITEM
> > > 76859450) itemoff 11483 itemsize 65 location key (2397184
> > > UNKNOWN.0 7091317839824617472) type 45 namelen 13102 datalen
> > > 13358 name: 1-x86_64.pkg.tar.xzb\x14
> >
> > namelen must be smaller than 255, but the number itself does not
> > look like a bitflip (0x332e), the name looks like a fragment of.
> >
> > The location key is random garbage, likely an overwritten memory,
> > 7091317839824617472 == 0x62696c0100230000 contains ascii 'bil', the
> > key type is unknown but should be INODE_ITEM.
> >
> > > data
> > > item 110 key (261 DIR_ITEM 9799832789237604651) itemoff
> > > 11405 itemsize 62
> > > location key (388547 INODE_ITEM 0) type FILE
> > > namelen 32 datalen 0 name:
> > > intltool-0.51.0-1-any.pkg.tar.xz item 111 key (261 DIR_ITEM
> > > 81211850) itemoff 11344 itemsize 131133
> >
> > itemsize 131133 == 0x2003d is a clear bitflip, 0x3d == 61,
> > corresponds to the expected item size.
> >
> > There's possibly other random bitflips in the keys or other
> > structures. It's hard to estimate the damage and thus the scope of
> > restorable data.
>
> It makes sense since this's a ssd we may have only one copy for
> metadata.
>
> Thanks,
>
> -liubo
>From this point of view it doesn't make sense to store only one copy of
meta data on SSD... The bit flip probably happened in RAM when taking
the other garbage into account, so dup meta data could have helped here.
If the SSD firmware would collapse duplicate meta data into single
blobs, that's perfectly fine. If the dup meta data arrives with bits
flipped, it won't be deduplicated. So this is fine, too.
BTW: I cannot believe that SSD firmwares really do the quite expensive
job of deduplication other than maybe internal compression. Maybe there
are some drives out there but most won't deduplicate. It's just too
little gain for too much complexity. So I personally would always
switch on duplicate meta data even for SSD. It shouldn't add to wear
leveling too much if you do the usual SSD optimization anyways (like
noatime).
PS: I suggest doing an extensive memtest86 before trying any repairs on
this system... Are you probably mixing different model DIMMs in dual
channel slots? Most of the times I've seen bitflips, this was the
culprit...
--
Regards,
Kai
Replies to list-only preferred.
^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-14 20:28 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: tomas.hlavacek-x+rMaJPWets, Mark Rutland, marex-ynQEQJNshbs,
Jason Cooper, Martin Strba??ka, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
In-Reply-To: <20161114201640.rr32iyjf5a53v33t-jgopVnDzZD+b0XQX99//ntPVjbGH4+40kFgPdswSElo@public.gmane.org>
>
> + i2c@7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> +
> + pcawan: gpio@71 {
> + compatible = "nxp,pca9538";
> + reg = <0x71>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcawan_pins>;
> +
> + interrupt-parent = <&gpio1>;
> + interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
>
> The interrupt-controller part doesn't seem to work though, at least
>
> + interrupt-parent = <&pcawan>;
> + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>
> in the phy node gives an error.
Interrupts don't seem to work very well with the nxp,pca9538. Which
is probably why it is disabled by default.
Andrew
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^ permalink raw reply
* [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-14 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114201640.rr32iyjf5a53v33t@perseus.defre.kleine-koenig.org>
>
> + i2c at 7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> +
> + pcawan: gpio at 71 {
> + compatible = "nxp,pca9538";
> + reg = <0x71>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcawan_pins>;
> +
> + interrupt-parent = <&gpio1>;
> + interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
>
> The interrupt-controller part doesn't seem to work though, at least
>
> + interrupt-parent = <&pcawan>;
> + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>
> in the phy node gives an error.
Interrupts don't seem to work very well with the nxp,pca9538. Which
is probably why it is disabled by default.
Andrew
^ permalink raw reply
* Re: Debugging Ethernet issues
From: Mason @ 2016-11-14 20:27 UTC (permalink / raw)
To: Florian Fainelli
Cc: Sebastian Frias, Andrew Lunn, netdev, Mans Rullgard,
Sergei Shtylyov, Tom Lendacky, Zach Brown, Shaohui Xie, Tim Beale,
Brian Hill, Vince Bridgers, Balakumaran Kannan, David S. Miller,
Kirill Kapranov
In-Reply-To: <2187db98-dc5a-7a3c-7965-7ccbeffc0fa1@gmail.com>
On 14/11/2016 19:20, Florian Fainelli wrote:
> On 11/14/2016 09:59 AM, Sebastian Frias wrote:
>
>> Could you confirm that Mason's patch is correct and/or that it does not
>> has negative side-effects?
>
> The patch is not correct nor incorrect per-se, it changes the default
> policy of having pause frames advertised by default to not having them
> advertised by default. This influences both your Ethernet MAC and the
> link partner in that the result is either flow control is enabled
> (before) or it is not (with the patch). There must be something amiss if
> you see packet loss or some kind of problem like that with an early
> exchange such as DHCP. Flow control tend to kick in under higher packet
> rates (at least, that's what you expect).
Did you note that, without the change under discussion (i.e. with
the eth driver as it is upstream), when the board is connected to
a 100 Mbps switch, then *nothing* works *systematically (no ping,
no DHCP; are there other relevant low-level network tools?).
Also, maybe this comment was lost in my own noise:
If I manually set the link up, then down, then run udhcpc
=> then nothing works, as if something is wedged somewhere
(a kernel thread gets borked by a race condition?)
Could not advertising pause frames result in making such a
race condition impossible? (I don't really believe in a race,
due to the 100% nature of the problem.)
>> Right now we know that Mason's patch makes this work, but we do not understand
>> why nor its implications.
>
> You need to understand why, right now, the way this problem is
> presented, you came up with a workaround, not with the root cause or the
> solution. What does your link partner (switch?) reports, that is, what
> is the ethtool output when you have a link up from your nb8800 adapter?
Isn't that what ethtool -a eth0 prints?
How do I get the link partner information?
Just ethtool eth0?
Regards.
^ permalink raw reply
* Re: [PATCH 1/4] selinux: Minor cleanups
From: Paul Moore @ 2016-11-14 20:28 UTC (permalink / raw)
To: Andreas Gruenbacher; +Cc: Stephen Smalley, Eric Paris, selinux
In-Reply-To: <1478812710-17190-2-git-send-email-agruenba@redhat.com>
On Thu, Nov 10, 2016 at 4:18 PM, Andreas Gruenbacher
<agruenba@redhat.com> wrote:
> Fix the comment for function __inode_security_revalidate, which returns
> an integer.
>
> Use the LABEL_* constants consistently for isec->initialized.
>
> Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
> ---
> security/selinux/hooks.c | 3 ++-
> security/selinux/selinuxfs.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
Applied, thanks.
> diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
> index 09fd610..b98ab2a 100644
> --- a/security/selinux/hooks.c
> +++ b/security/selinux/hooks.c
> @@ -237,6 +237,7 @@ static int inode_alloc_security(struct inode *inode)
> isec->sid = SECINITSID_UNLABELED;
> isec->sclass = SECCLASS_FILE;
> isec->task_sid = sid;
> + isec->initialized = LABEL_INVALID;
> inode->i_security = isec;
>
> return 0;
> @@ -247,7 +248,7 @@ static int inode_doinit_with_dentry(struct inode *inode, struct dentry *opt_dent
> /*
> * Try reloading inode security labels that have been marked as invalid. The
> * @may_sleep parameter indicates when sleeping and thus reloading labels is
> - * allowed; when set to false, returns ERR_PTR(-ECHILD) when the label is
> + * allowed; when set to false, returns -ECHILD when the label is
> * invalid. The @opt_dentry parameter should be set to a dentry of the inode;
> * when no dentry is available, set it to NULL instead.
> */
> diff --git a/security/selinux/selinuxfs.c b/security/selinux/selinuxfs.c
> index 72c145d..50fca20 100644
> --- a/security/selinux/selinuxfs.c
> +++ b/security/selinux/selinuxfs.c
> @@ -1301,7 +1301,7 @@ static int sel_make_bools(void)
> goto out;
>
> isec->sid = sid;
> - isec->initialized = 1;
> + isec->initialized = LABEL_INITIALIZED;
> inode->i_fop = &sel_bool_ops;
> inode->i_ino = i|SEL_BOOL_INO_OFFSET;
> d_add(dentry, inode);
> @@ -1834,7 +1834,7 @@ static int sel_fill_super(struct super_block *sb, void *data, int silent)
> isec = (struct inode_security_struct *)inode->i_security;
> isec->sid = SECINITSID_DEVNULL;
> isec->sclass = SECCLASS_CHR_FILE;
> - isec->initialized = 1;
> + isec->initialized = LABEL_INITIALIZED;
>
> init_special_inode(inode, S_IFCHR | S_IRUGO | S_IWUGO, MKDEV(MEM_MAJOR, 3));
> d_add(dentry, inode);
> --
> 2.7.4
>
--
paul moore
www.paul-moore.com
^ permalink raw reply
* Re: [PATCH v2] mm, thb: propagation of conditional compilation in khugepaged.c
From: Kirill A. Shutemov @ 2016-11-14 20:27 UTC (permalink / raw)
To: Jérémy Lefaure; +Cc: Andrew Morton, Kirill A. Shutemov, linux-mm
In-Reply-To: <20161114201208.11474-1-jeremy.lefaure@lse.epita.fr>
On Mon, Nov 14, 2016 at 03:12:08PM -0500, Jeremy Lefaure wrote:
> Commit b46e756f5e47 ("thp: extract khugepaged from mm/huge_memory.c")
> moved code from huge_memory.c to khugepaged.c. Some of this code should
> be compiled only when CONFIG_SYSFS is enabled but the condition around
> this code was not moved into khugepaged.c. The result is a compilation
> error when CONFIG_SYSFS is disabled:
>
> mm/built-in.o: In function `khugepaged_defrag_store':
> khugepaged.c:(.text+0x2d095): undefined reference to
> `single_hugepage_flag_store'
> mm/built-in.o: In function `khugepaged_defrag_show':
> khugepaged.c:(.text+0x2d0ab): undefined reference to
> `single_hugepage_flag_show'
>
> This commit adds the #ifdef CONFIG_SYSFS around the code related to
> sysfs.
>
> Signed-off-by: Jeremy Lefaure <jeremy.lefaure@lse.epita.fr>
> ---
> After having discuted with Hillf, I changed the subject to replace "thb" by
> "mm, thb". I also rewrote the subject.
s/thb/thp/
--
Kirill A. Shutemov
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^ permalink raw reply
* Re: [PATCH 6/7] drm/i915/fbc: move from crtc_state->enable_fbc to plane_state->enable_fbc
From: Ville Syrjälä @ 2016-11-14 20:26 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
In-Reply-To: <1478897399.19391.61.camel@intel.com>
On Fri, Nov 11, 2016 at 06:49:59PM -0200, Paulo Zanoni wrote:
> Em Sex, 2016-11-11 às 22:24 +0200, Ville Syrjälä escreveu:
> > On Fri, Nov 11, 2016 at 05:57:28PM -0200, Paulo Zanoni wrote:
> > >
> > > Em Sex, 2016-11-11 às 21:13 +0200, Ville Syrjälä escreveu:
> > > >
> > > > On Fri, Nov 11, 2016 at 05:01:54PM -0200, Paulo Zanoni wrote:
> > > > >
> > > > >
> > > > > Em Sex, 2016-11-11 às 20:51 +0200, Ville Syrjälä escreveu:
> > > > > >
> > > > > >
> > > > > > On Fri, Nov 11, 2016 at 02:57:40PM -0200, Paulo Zanoni wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > Ville pointed out that intel_fbc_choose_crtc() is iterating
> > > > > > > over
> > > > > > > all
> > > > > > > planes instead of just the primary planes. There are no
> > > > > > > real
> > > > > > > consequences of this problem for HSW+, and for the other
> > > > > > > platforms
> > > > > > > it
> > > > > > > just means that in some obscure multi-screen cases we'll
> > > > > > > keep
> > > > > > > FBC
> > > > > > > disabled when we could have enabled it. Still, iterating
> > > > > > > over
> > > > > > > all
> > > > > > > planes doesn't seem to be the best thing to do.
> > > > > > >
> > > > > > > My initial idea was to just add a check for plane->type and
> > > > > > > be
> > > > > > > done,
> > > > > > > but then I realized that in commits not involving the
> > > > > > > primary
> > > > > > > plane
> > > > > > > we
> > > > > > > would reset crtc_state->enable_fbc back to false even when
> > > > > > > FBC
> > > > > > > is
> > > > > > > enabled. That also wouldn't result in a bug due to the way
> > > > > > > the
> > > > > > > enable_fbc variable is checked, but, still, our code can be
> > > > > > > better
> > > > > > > than this.
> > > > > > >
> > > > > > > So I went for the solution that involves tracking
> > > > > > > enable_fbc in
> > > > > > > the
> > > > > > > primary plane state instead of the CRTC state. This way, if
> > > > > > > a
> > > > > > > commit
> > > > > > > doesn't involve the primary plane for the CRTC we won't be
> > > > > > > resetting
> > > > > > > enable_fbc back to false, so the variable will always
> > > > > > > reflect
> > > > > > > the
> > > > > > > reality. And this change also makes more sense since FBC is
> > > > > > > actually
> > > > > > > tied to the single plane and not the full pipe. As a bonus,
> > > > > > > we
> > > > > > > only
> > > > > > > iterate over the CRTCs instead of iterating over all
> > > > > > > planes.
> > > > > > >
> > > > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/intel_drv.h | 4 ++--
> > > > > > > drivers/gpu/drm/i915/intel_fbc.c | 36 +++++++++++++++++++-
> > > > > > > ----
> > > > > > > ----
> > > > > > > --------
> > > > > > > 2 files changed, 21 insertions(+), 19 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > > > > index 003afb8..025cb74 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > > > > @@ -403,6 +403,8 @@ struct intel_plane_state {
> > > > > > > int scaler_id;
> > > > > > >
> > > > > > > struct drm_intel_sprite_colorkey ckey;
> > > > > > > +
> > > > > > > + bool enable_fbc;
> > > > > > > };
> > > > > > >
> > > > > > > struct intel_initial_plane_config {
> > > > > > > @@ -648,8 +650,6 @@ struct intel_crtc_state {
> > > > > > >
> > > > > > > bool ips_enabled;
> > > > > > >
> > > > > > > - bool enable_fbc;
> > > > > > > -
> > > > > > > bool double_wide;
> > > > > > >
> > > > > > > bool dp_encoder_is_mst;
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> > > > > > > b/drivers/gpu/drm/i915/intel_fbc.c
> > > > > > > index b095175..fc4ac57 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > > > > > > @@ -1055,16 +1055,17 @@ void intel_fbc_choose_crtc(struct
> > > > > > > drm_i915_private *dev_priv,
> > > > > > > struct drm_atomic_state *state)
> > > > > > > {
> > > > > > > struct intel_fbc *fbc = &dev_priv->fbc;
> > > > > > > - struct drm_plane *plane;
> > > > > > > - struct drm_plane_state *plane_state;
> > > > > > > + struct drm_crtc *crtc;
> > > > > > > + struct drm_crtc_state *crtc_state;
> > > > > > > bool crtc_chosen = false;
> > > > > > > int i;
> > > > > > >
> > > > > > > mutex_lock(&fbc->lock);
> > > > > > >
> > > > > > > - /* Does this atomic commit involve the CRTC
> > > > > > > currently
> > > > > > > tied
> > > > > > > to FBC? */
> > > > > > > + /* Does this atomic commit involve the plane
> > > > > > > currently
> > > > > > > tied to FBC? */
> > > > > > > if (fbc->crtc &&
> > > > > > > - !drm_atomic_get_existing_crtc_state(state,
> > > > > > > &fbc-
> > > > > > > >
> > > > > > > > crtc-
> > > > > > > >
> > > > > > > > base))
> > > > > > > + !drm_atomic_get_existing_plane_state(state,
> > > > > > > + fbc-
> > > > > > > >crtc-
> > > > > > > >
> > > > > > > >
> > > > > > > > base.primary))
> > > > > > > goto out;
> > > > > > >
> > > > > > > if (!intel_fbc_can_enable(dev_priv))
> > > > > > > @@ -1074,25 +1075,26 @@ void intel_fbc_choose_crtc(struct
> > > > > > > drm_i915_private *dev_priv,
> > > > > > > * plane. We could go for fancier schemes such as
> > > > > > > checking
> > > > > > > the plane
> > > > > > > * size, but this would just affect the few
> > > > > > > platforms
> > > > > > > that
> > > > > > > don't tie FBC
> > > > > > > * to pipe or plane A. */
> > > > > > > - for_each_plane_in_state(state, plane, plane_state,
> > > > > > > i)
> > > > > > > {
> > > > > > > - struct intel_plane_state
> > > > > > > *intel_plane_state =
> > > > > > > - to_intel_plane_state(plane_state);
> > > > > > > - struct intel_crtc_state *intel_crtc_state;
> > > > > > > - struct intel_crtc *crtc =
> > > > > > > to_intel_crtc(plane_state->crtc);
> > > > > > > + for_each_crtc_in_state(state, crtc, crtc_state, i)
> > > > > > > {
> > > > > > > + struct intel_plane_state *plane_state =
> > > > > > > to_intel_plane_state(
> > > > > > > + drm_atomic_get_existing_plane_stat
> > > > > > > e(st
> > > > > > > ate,
> > > > > > > +
> > > > > > > cr
> > > > > > > tc-
> > > > > > > >
> > > > > > > >
> > > > > > > > primary));
> > > > > > > + struct intel_crtc *intel_crtc =
> > > > > > > to_intel_crtc(crtc);
> > > > > > >
> > > > > > > - if (!intel_plane_state->base.visible)
> > > > > > > + if (!plane_state)
> > > > > > > continue;
> > > > > > >
> > > > > > > - if (fbc_on_pipe_a_only(dev_priv) && crtc-
> > > > > > > >pipe
> > > > > > > !=
> > > > > > > PIPE_A)
> > > > > > > + if (!plane_state->base.visible)
> > > > > > > continue;
> > > > > > >
> > > > > > > - if (fbc_on_plane_a_only(dev_priv) && crtc-
> > > > > > > >
> > > > > > > > plane
> > > > > > > != PLANE_A)
> > > > > > > + if (fbc_on_pipe_a_only(dev_priv) &&
> > > > > > > intel_crtc-
> > > > > > > >
> > > > > > > >
> > > > > > > > pipe != PIPE_A)
> > > > > > > continue;
> > > > > > >
> > > > > > > - intel_crtc_state = to_intel_crtc_state(
> > > > > > > - drm_atomic_get_existing_crtc_state
> > > > > > > (sta
> > > > > > > te,
> > > > > > > &crtc->base));
> > > > > > > + if (fbc_on_plane_a_only(dev_priv) &&
> > > > > > > + intel_crtc->plane != PLANE_A)
> > > > > > > + continue;
> > > > > > >
> > > > > > > - intel_crtc_state->enable_fbc = true;
> > > > > > > + plane_state->enable_fbc = true;
> > > > > >
> > > > > > So looking at this whole thing, I can't see anything that
> > > > > > would
> > > > > > prevent
> > > > > > enable_fbc being true for multiple primary planes at the same
> > > > > > time
> > > > > > Well, apart from the whole "we enable it only for platforms
> > > > > > that
> > > > > > can
> > > > > > only do
> > > > > > pipe A" thing.
> > > > > >
> > > > > > So what happens in that case? FBC just ends up getting
> > > > > > enabling
> > > > > > on
> > > > > > one of the pipes based on the order intel_fbc_enable() gets
> > > > > > called,
> > > > > > or something?
> > > > >
> > > > > The first check of intel_fbc_choose_crtc() is supposed to
> > > > > prevent
> > > > > this
> > > > > case: if fbc->crtc->primary is not included in the commit we
> > > > > just
> > > > > return without selecting any plane.
> > > >
> > > > The fbc->crtc thing only works if intel_fbc_enable() was already
> > > > called
> > > > for some crtc. But what it it wasn't?
> > > >
> > > > >
> > > > >
> > > > > Otherwise, we only pick one CRTC
> > > > > due to the "break;" statement after setting plane_state-
> > > > > >enable_fbc
> > > > > to
> > > > > true.
> > > >
> > > > Only one per atomic operation. But what if there are several
> > > > happening
> > > > in parallel on different crtcs?
> > >
> > > I see your point now. Yeah, we'll end up with
> > > plane_state.enable_fbc=true for two different planes. Later, the
> > > first
> > > one to call intel_fbc_enable() will win, and the others will be
> > > ignored, so we'll indeed end up with plane states having
> > > enable_fbc=true but FBC not enabled by them. Not a real bug, I
> > > would
> > > still like to avoid this confusion.
> > >
> > > The simplest solution I can think would be to just
> > > s/plane_state.enable_fbc/plane_state.can_enable_fbc/ and just let
> > > the
> > > first one to call intel_fbc_enable() win... And then, if we ever
> > > decide
> > > to enable FBC on the older platforms, we can choose to maybe
> > > implement
> > > a better method
> >
> > Maybe something like "fbc_score"? ;)
>
> The design of the current function was supposed to allow Ville to
> implement his fbc_score in case he wanted. But this certainly didn't
> take into account multiple parallel commits: it would only work if
> multiple CRTCs were included in the same commit (as you just pointed
> today).
>
> But then: if we're having separate parallel commits, when would we be
> able to loop through the scores to only actually enable FBC on the best
> score?
>
> For example, if we do two parallel atomic_check()s and end with
> plane_a_score=1 and plane_b_score=2, then later we do A's commit() and
> call intel_fbc_enable() for it, how do we conclude that we shouldn't
> enable FBC for plane A? We're not even sure if plane B is going to
> actually commit the plane state it calculated (maybe it was
> check_only).
>
> And then, if we decide to only compute everything during commit()
> instead of check(), we'll just also end up enabling FBC for plane A
> since A's commit() will run first and we'll have no idea that B's
> commit is incoming.
>
> The only option would be to disable FBC for plane A and enable for
> plane B during B's commit. But I'm not looking forward to implement
> this right now.
All the enable/disable should be totally async and so you should be
able to kick them off from anywhere. All the state, including the scores,
would be protected by the fbc mutex. I had a vblank worker type of
thing for this purpose in my patches.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [Patch v6.1] x86/kvm: Add AVX512_4VNNIW and AVX512_4FMAPS support
From: kbuild test robot @ 2016-11-14 20:24 UTC (permalink / raw)
To: He Chen
Cc: kbuild-all, Borislav Petkov, kvm, linux-kernel, x86,
Paolo Bonzini, Radim Krčmář, Thomas Gleixner,
Ingo Molnar, H . Peter Anvin, Luwei Kang, Piotr Luc
In-Reply-To: <20161114084556.GA3877@he>
[-- Attachment #1: Type: text/plain, Size: 1961 bytes --]
Hi He,
[auto build test ERROR on kvm/linux-next]
[also build test ERROR on v4.9-rc5]
[cannot apply to next-20161114]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/He-Chen/x86-kvm-Add-AVX512_4VNNIW-and-AVX512_4FMAPS-support/20161114-170941
base: https://git.kernel.org/pub/scm/virt/kvm/kvm.git linux-next
config: x86_64-kexec (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
arch/x86/kvm/cpuid.c: In function '__do_cpuid_ent':
>> arch/x86/kvm/cpuid.c:472:18: error: implicit declaration of function 'get_scattered_cpuid_leaf' [-Werror=implicit-function-declaration]
entry->edx &= get_scattered_cpuid_leaf(7, 0, CPUID_EDX);
^~~~~~~~~~~~~~~~~~~~~~~~
>> arch/x86/kvm/cpuid.c:472:49: error: 'CPUID_EDX' undeclared (first use in this function)
entry->edx &= get_scattered_cpuid_leaf(7, 0, CPUID_EDX);
^~~~~~~~~
arch/x86/kvm/cpuid.c:472:49: note: each undeclared identifier is reported only once for each function it appears in
cc1: some warnings being treated as errors
vim +/get_scattered_cpuid_leaf +472 arch/x86/kvm/cpuid.c
466 entry->ecx &= kvm_cpuid_7_0_ecx_x86_features;
467 cpuid_mask(&entry->ecx, CPUID_7_ECX);
468 /* PKU is not yet implemented for shadow paging. */
469 if (!tdp_enabled)
470 entry->ecx &= ~F(PKU);
471 entry->edx &= kvm_cpuid_7_0_edx_x86_features;
> 472 entry->edx &= get_scattered_cpuid_leaf(7, 0, CPUID_EDX);
473 } else {
474 entry->ebx = 0;
475 entry->ecx = 0;
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 24231 bytes --]
^ permalink raw reply
* [U-Boot] [PATCH RESEND 7/9] video: Allow board hook before video init
From: Maxime Ripard @ 2016-11-14 20:24 UTC (permalink / raw)
To: u-boot
In-Reply-To: <CAPnjgZ1gA03USUjNdDB-yTsRWhRMXaZmwrbmYJnb28CKHcfjTA@mail.gmail.com>
Hi Simon,
On Fri, Nov 11, 2016 at 09:17:28AM -0700, Simon Glass wrote:
> Hi Maxime,
>
> On 8 November 2016 at 03:19, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some boards might need to some additional setup right before initialising
> > the video console.
> >
> > Add some hook to allow that.
>
> Instead of this, can you use driver model (UCLASS_VIDEO)?
I don't really know the device model that well, hence 'm not really
sure how would that help. Can a board register a hook to be called
before a driver is probed?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [nightly] Core TISDK (daisy/1.6) 2015.06 build 2016-11-14_15-01-12
From: Denys Dmytriyenko @ 2016-11-14 20:24 UTC (permalink / raw)
To: meta-arago
[-- Attachment #1: Type: text/html, Size: 5097 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] drm/amd/amdgpu: port of DCE v6 to new headers (v2)
From: Alex Deucher @ 2016-11-14 20:23 UTC (permalink / raw)
To: Tom St Denis; +Cc: Tom St Denis, amd-gfx list
In-Reply-To: <20161114185746.18225-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
On Mon, Nov 14, 2016 at 1:57 PM, Tom St Denis <tstdenis82@gmail.com> wrote:
> Port of SI DCE v6 over to new AMDGPU headers. Tested on a
> Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and
> staging drm/xf86-video-amdgpu.
>
> (v2) Re-factored to remove formatting changes to si_enums.h
> as well rename various defines.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 507 +++++++++++----------
> drivers/gpu/drm/amd/amdgpu/si_enums.h | 78 ++++
> .../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 12 +
> 3 files changed, 350 insertions(+), 247 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index b0fdc291bf43..54e309c1eaf8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -30,8 +30,19 @@
> #include "atombios_encoders.h"
> #include "amdgpu_pll.h"
> #include "amdgpu_connectors.h"
> -#include "si/si_reg.h"
> -#include "si/sid.h"
> +
> +#include "bif/bif_3_0_d.h"
> +#include "bif/bif_3_0_sh_mask.h"
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
> +#include "gca/gfx_6_0_d.h"
> +#include "gca/gfx_6_0_sh_mask.h"
> +#include "gmc/gmc_6_0_d.h"
> +#include "gmc/gmc_6_0_sh_mask.h"
> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +#include "gca/gfx_7_2_enum.h"
> +#include "si_enums.h"
>
> static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
> static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
> @@ -48,12 +59,12 @@ static const u32 crtc_offsets[6] =
>
> static const u32 hpd_offsets[] =
> {
> - DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS,
> - DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS,
> - DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS,
> - DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS,
> - DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS,
> - DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS,
> + mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
> + mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
> + mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
> + mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
> + mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
> + mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
> };
>
> static const uint32_t dig_offsets[] = {
> @@ -73,32 +84,32 @@ static const struct {
> uint32_t hpd;
>
> } interrupt_status_offsets[6] = { {
> - .reg = DISP_INTERRUPT_STATUS,
> + .reg = mmDISP_INTERRUPT_STATUS,
> .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
> }, {
> - .reg = DISP_INTERRUPT_STATUS_CONTINUE,
> + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
> .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
> }, {
> - .reg = DISP_INTERRUPT_STATUS_CONTINUE2,
> + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
> .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
> }, {
> - .reg = DISP_INTERRUPT_STATUS_CONTINUE3,
> + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
> .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
> }, {
> - .reg = DISP_INTERRUPT_STATUS_CONTINUE4,
> + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
> .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
> }, {
> - .reg = DISP_INTERRUPT_STATUS_CONTINUE5,
> + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
> .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
> .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
> .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
> @@ -119,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
>
> static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
> {
> - if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
> + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
> return true;
> else
> return false;
> @@ -129,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
> {
> u32 pos1, pos2;
>
> - pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
> - pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
> + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
> + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
>
> if (pos1 != pos2)
> return true;
> @@ -152,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
> if (crtc >= adev->mode_info.num_crtc)
> return;
>
> - if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
> + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
> return;
>
> /* depending on when we hit vblank, we may be close to active; if so,
> @@ -180,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
> if (crtc >= adev->mode_info.num_crtc)
> return 0;
> else
> - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
> + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
> }
>
> static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
> @@ -220,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
> struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
>
> /* flip at hsync for async, default is vsync */
> - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
> - EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
> + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
> + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
> /* update the scanout addresses */
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> upper_32_bits(crtc_base));
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> (u32)crtc_base);
>
> /* post the write */
> - RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
> + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
> }
>
> static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
> @@ -237,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
> {
> if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
> return -EINVAL;
> - *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]);
> - *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
> + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
> + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
>
> return 0;
>
> @@ -261,7 +272,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
> if (hpd >= adev->mode_info.num_hpd)
> return connected;
>
> - if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE)
> + if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
> connected = true;
>
> return connected;
> @@ -284,12 +295,12 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
> if (hpd >= adev->mode_info.num_hpd)
> return;
>
> - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> if (connected)
> - tmp &= ~DC_HPDx_INT_POLARITY;
> + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
> else
> - tmp |= DC_HPDx_INT_POLARITY;
> - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
> + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
> }
>
> /**
> @@ -312,9 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
> if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
> continue;
>
> - tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> - tmp |= DC_HPDx_EN;
> - WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
> + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> + tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
> + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
> @@ -323,9 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
> * https://bugzilla.redhat.com/show_bug.cgi?id=726143
> * also avoid interrupt storms during dpms.
> */
> - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> - tmp &= ~DC_HPDx_INT_EN;
> - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
> + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
> continue;
> }
>
> @@ -355,9 +366,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
> if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
> continue;
>
> - tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> - tmp &= ~DC_HPDx_EN;
> - WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
> + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
> + tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
> + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
>
> amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
> }
> @@ -365,7 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
>
> static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
> {
> - return SI_DC_GPIO_HPD_A;
> + return mmDC_GPIO_HPD_A;
> }
>
> static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
> @@ -380,7 +391,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
> if (crtc >= adev->mode_info.num_crtc)
> return 0;
> else
> - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
> + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
> }
>
> static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
> @@ -389,25 +400,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
> u32 crtc_enabled, tmp, frame_count;
> int i, j;
>
> - save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
> - save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
> + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
> + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
>
> /* disable VGA render */
> - WREG32(VGA_RENDER_CONTROL, 0);
> + WREG32(mmVGA_RENDER_CONTROL, 0);
>
> /* blank the display controllers */
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
> + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
> if (crtc_enabled) {
> save->crtc_enabled[i] = true;
> - tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
> + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
>
> - if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
> + if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
> dce_v6_0_vblank_wait(adev, i);
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> - tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
> - WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> + tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
> + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> }
> /* wait for the next frame */
> frame_count = evergreen_get_vblank_counter(adev, i);
> @@ -418,11 +429,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
> }
>
> /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> - tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
> - tmp &= ~EVERGREEN_CRTC_MASTER_EN;
> - WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
> + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
> + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> save->crtc_enabled[i] = false;
> /* ***** */
> } else {
> @@ -439,41 +450,41 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
>
> /* update crtc base addresses */
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
> upper_32_bits(adev->mc.vram_start));
> - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
> + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
> upper_32_bits(adev->mc.vram_start));
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
> (u32)adev->mc.vram_start);
> - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
> + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
> (u32)adev->mc.vram_start);
> }
>
> - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
> - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
> + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
> + WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
>
> /* unlock regs and wait for update */
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> if (save->crtc_enabled[i]) {
> - tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
> + tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
> if ((tmp & 0x7) != 3) {
> tmp &= ~0x7;
> tmp |= 0x3;
> - WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
> + WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
> }
> - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
> - if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
> - tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
> - WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
> + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
> + if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
> + tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
> + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
> }
> - tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
> + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
> if (tmp & 1) {
> tmp &= ~1;
> - WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
> + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
> }
> for (j = 0; j < adev->usec_timeout; j++) {
> - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
> - if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
> + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
> + if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
> break;
> udelay(1);
> }
> @@ -481,9 +492,9 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
> }
>
> /* Unlock vga access */
> - WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
> + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
> mdelay(1);
> - WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
> + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
>
> }
>
> @@ -491,8 +502,8 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
> bool render)
> {
> if (!render)
> - WREG32(R_000300_VGA_RENDER_CONTROL,
> - RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
> + WREG32(mmVGA_RENDER_CONTROL,
> + RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
>
> }
>
> @@ -526,14 +537,14 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)
>
> /*Disable crtc*/
> for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
> - crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
> - EVERGREEN_CRTC_MASTER_EN;
> + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
> + CRTC_CONTROL__CRTC_MASTER_EN_MASK;
> if (crtc_enabled) {
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> - tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
> - tmp &= ~EVERGREEN_CRTC_MASTER_EN;
> - WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
> - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
> + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
> + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
> + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> }
> }
> }
> @@ -569,19 +580,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
> case 6:
> if (dither == AMDGPU_FMT_DITHER_ENABLE)
> /* XXX sort out optimal dither settings */
> - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
> - FMT_SPATIAL_DITHER_EN);
> + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
> else
> - tmp |= FMT_TRUNCATE_EN;
> + tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
> break;
> case 8:
> if (dither == AMDGPU_FMT_DITHER_ENABLE)
> /* XXX sort out optimal dither settings */
> - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
> - FMT_RGB_RANDOM_ENABLE |
> - FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
> + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
> else
> - tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
> + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
> + FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
> break;
> case 10:
> default:
> @@ -589,7 +604,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
> break;
> }
>
> - WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
> + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
> }
>
> /**
> @@ -603,7 +618,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
> */
> static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
> {
> - u32 tmp = RREG32(MC_SHARED_CHMAP);
> + u32 tmp = RREG32(mmMC_SHARED_CHMAP);
>
> switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
> case 0:
> @@ -1100,28 +1115,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
> }
>
> /* select wm A */
> - arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
> + arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
> tmp = arb_control3;
> tmp &= ~LATENCY_WATERMARK_MASK(3);
> tmp |= LATENCY_WATERMARK_MASK(1);
> - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
> - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
> - (LATENCY_LOW_WATERMARK(latency_watermark_a) |
> - LATENCY_HIGH_WATERMARK(line_time)));
> + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
> + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
> + ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
> + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
> /* select wm B */
> - tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
> + tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
> tmp &= ~LATENCY_WATERMARK_MASK(3);
> tmp |= LATENCY_WATERMARK_MASK(2);
> - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
> - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
> - (LATENCY_LOW_WATERMARK(latency_watermark_b) |
> - LATENCY_HIGH_WATERMARK(line_time)));
> + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
> + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
> + ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
> + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
> /* restore original selection */
> - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
> + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
>
> /* write the priority marks */
> - WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
> - WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
> + WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
> + WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
>
> /* save values for DPM */
> amdgpu_crtc->line_time = line_time;
> @@ -1139,7 +1154,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
> /*
> * Line Buffer Setup
> * There are 3 line buffers, each one shared by 2 display controllers.
> - * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
> + * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
> * the display controllers. The paritioning is done via one of four
> * preset allocations specified in bits 21:20:
> * 0 - half lb
> @@ -1162,14 +1177,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
> buffer_alloc = 0;
> }
>
> - WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
> + WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
> DC_LB_MEMORY_CONFIG(tmp));
>
> - WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
> - DMIF_BUFFERS_ALLOCATED(buffer_alloc));
> + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
> + (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
> - DMIF_BUFFERS_ALLOCATED_COMPLETED)
> + if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
> + PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
> break;
> udelay(1);
> }
> @@ -1411,12 +1426,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
>
> static const u32 vga_control_regs[6] =
> {
> - AVIVO_D1VGA_CONTROL,
> - AVIVO_D2VGA_CONTROL,
> - EVERGREEN_D3VGA_CONTROL,
> - EVERGREEN_D4VGA_CONTROL,
> - EVERGREEN_D5VGA_CONTROL,
> - EVERGREEN_D6VGA_CONTROL,
> + mmD1VGA_CONTROL,
> + mmD2VGA_CONTROL,
> + mmD3VGA_CONTROL,
> + mmD4VGA_CONTROL,
> + mmD5VGA_CONTROL,
> + mmD6VGA_CONTROL,
> };
>
> static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
> @@ -1436,7 +1451,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> struct drm_device *dev = crtc->dev;
> struct amdgpu_device *adev = dev->dev_private;
>
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
> + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
> }
>
> static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> @@ -1452,7 +1467,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> struct amdgpu_bo *abo;
> uint64_t fb_location, tiling_flags;
> uint32_t fb_format, fb_pitch_pixels, pipe_config;
> - u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
> + u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
> u32 viewport_w, viewport_h;
> int r;
> bool bypass_lut = false;
> @@ -1495,64 +1510,64 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
>
> switch (target_fb->pixel_format) {
> case DRM_FORMAT_C8:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_INDEXED));
> break;
> case DRM_FORMAT_XRGB4444:
> case DRM_FORMAT_ARGB4444:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
> #endif
> break;
> case DRM_FORMAT_XRGB1555:
> case DRM_FORMAT_ARGB1555:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
> #endif
> break;
> case DRM_FORMAT_BGRX5551:
> case DRM_FORMAT_BGRA5551:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
> #endif
> break;
> case DRM_FORMAT_RGB565:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_ARGB565));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
> #endif
> break;
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_ARGB8888:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
> #endif
> break;
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_ARGB2101010:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
> #endif
> /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
> bypass_lut = true;
> break;
> case DRM_FORMAT_BGRX1010102:
> case DRM_FORMAT_BGRA1010102:
> - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
> - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
> + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
> + GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
> #ifdef __BIG_ENDIAN
> - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
> + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
> #endif
> /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
> bypass_lut = true;
> @@ -1572,75 +1587,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
> num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
>
> - fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
> - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
> - fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
> - fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
> - fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
> - fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
> + fb_format |= GRPH_NUM_BANKS(num_banks);
> + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
> + fb_format |= GRPH_TILE_SPLIT(tile_split);
> + fb_format |= GRPH_BANK_WIDTH(bankw);
> + fb_format |= GRPH_BANK_HEIGHT(bankh);
> + fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
> } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
> - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
> + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
> }
>
> pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
> - fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
> + fb_format |= GRPH_PIPE_CONFIG(pipe_config);
>
> dce_v6_0_vga_enable(crtc, false);
>
> /* Make sure surface address is updated at vertical blank rather than
> * horizontal blank
> */
> - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
>
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> upper_32_bits(fb_location));
> - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> upper_32_bits(fb_location));
> - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> - (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
> - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> - (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
> - WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
> - WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap);
> + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
> + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> + (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
> + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
> + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
>
> /*
> * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
> * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
> * retain the full precision throughout the pipeline.
> */
> - WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
> - (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
> - ~EVERGREEN_LUT_10BIT_BYPASS_EN);
> + WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
> + (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
> + ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
>
> if (bypass_lut)
> DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
>
> - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
> - WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
> + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
> + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
>
> fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
> - WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
> + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
>
> dce_v6_0_grph_enable(crtc, true);
>
> - WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
> + WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
> target_fb->height);
> x &= ~3;
> y &= ~1;
> - WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset,
> + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
> (x << 16) | y);
> viewport_w = crtc->mode.hdisplay;
> viewport_h = (crtc->mode.vdisplay + 1) & ~1;
>
> - WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
> + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
> (viewport_w << 16) | viewport_h);
>
> /* set pageflip to happen only at start of vblank interval (front porch) */
> - WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
> + WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
>
> if (!atomic && fb && fb != crtc->primary->fb) {
> amdgpu_fb = to_amdgpu_framebuffer(fb);
> @@ -1667,10 +1682,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset,
> - EVERGREEN_INTERLEAVE_EN);
> + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
> + INTERLEAVE_EN);
> else
> - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
> }
>
> static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
> @@ -1683,54 +1698,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
>
> DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
>
> - WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
> - NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
> - WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
> - NI_GRPH_PRESCALE_BYPASS);
> - WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
> - NI_OVL_PRESCALE_BYPASS);
> - WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
> - NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
> -
> -
> + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
> + (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
> + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
> + PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
> + WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
> + PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
> + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
> + (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
>
> - WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
>
> - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
>
> - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
> - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
> - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
> + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
> + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
> + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
>
> - WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
> - WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
> + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
>
> - WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
> + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
> for (i = 0; i < 256; i++) {
> - WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
> + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
> (amdgpu_crtc->lut_r[i] << 20) |
> (amdgpu_crtc->lut_g[i] << 10) |
> (amdgpu_crtc->lut_b[i] << 0));
> }
>
> - WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
> - NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
> - NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
> - NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
> - WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
> - NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
> - WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
> - NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
> - WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
> - (NI_OUTPUT_CSC_GRPH_MODE(0) |
> - NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
> + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
> + (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
> + ICON_DEGAMMA_MODE(0) |
> + (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
> + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
> + (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
> + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
> + (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
> + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
> + ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
> + (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
> /* XXX match this to the depth of the crtc fmt block, move to modeset? */
> WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
>
> @@ -1809,12 +1822,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> uint32_t cur_lock;
>
> - cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset);
> + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
> if (lock)
> - cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
> + cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
> else
> - cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
> - WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
> + cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
> + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
> }
>
> static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
> @@ -1822,9 +1835,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> struct amdgpu_device *adev = crtc->dev->dev_private;
>
> - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
> - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
> - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
> + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
> + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
> + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
>
>
> }
> @@ -1834,15 +1847,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> struct amdgpu_device *adev = crtc->dev->dev_private;
>
> - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> upper_32_bits(amdgpu_crtc->cursor_addr));
> - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
> lower_32_bits(amdgpu_crtc->cursor_addr));
>
> - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
> - EVERGREEN_CURSOR_EN |
> - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
> - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
> + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
> + CUR_CONTROL__CURSOR_EN_MASK |
> + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
> + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
>
> }
>
> @@ -1869,9 +1882,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
> y = 0;
> }
>
> - WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
> - WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
> - WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset,
> + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
> + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
> + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
> ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
>
> amdgpu_crtc->cursor_x = x;
> @@ -2475,14 +2488,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
>
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> - interrupt_mask = RREG32(INT_MASK + reg_block);
> + interrupt_mask = RREG32(mmINT_MASK + reg_block);
> interrupt_mask &= ~VBLANK_INT_MASK;
> - WREG32(INT_MASK + reg_block, interrupt_mask);
> + WREG32(mmINT_MASK + reg_block, interrupt_mask);
> break;
> case AMDGPU_IRQ_STATE_ENABLE:
> - interrupt_mask = RREG32(INT_MASK + reg_block);
> + interrupt_mask = RREG32(mmINT_MASK + reg_block);
> interrupt_mask |= VBLANK_INT_MASK;
> - WREG32(INT_MASK + reg_block, interrupt_mask);
> + WREG32(mmINT_MASK + reg_block, interrupt_mask);
> break;
> default:
> break;
> @@ -2510,14 +2523,14 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
>
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> - dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
> + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
> dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
> - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
> break;
> case AMDGPU_IRQ_STATE_ENABLE:
> - dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
> + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
> dc_hpd_int_cntl |= DC_HPDx_INT_EN;
> - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
> break;
> default:
> break;
> @@ -2585,7 +2598,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
> switch (entry->src_data) {
> case 0: /* vblank */
> if (disp_int & interrupt_status_offsets[crtc].vblank)
> - WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
> + WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
> else
> DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
>
> @@ -2596,7 +2609,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
> break;
> case 1: /* vline */
> if (disp_int & interrupt_status_offsets[crtc].vline)
> - WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
> + WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
> else
> DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
>
> @@ -2622,12 +2635,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
> return -EINVAL;
> }
>
> - reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]);
> + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
> if (state == AMDGPU_IRQ_STATE_DISABLE)
> - WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
> + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
> reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
> else
> - WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
> + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
> reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
>
> return 0;
> @@ -2650,9 +2663,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
> return -EINVAL;
> }
>
> - if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) &
> + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
> GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
> - WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id],
> + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
> GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
>
> /* IRQ could occur when in initial stage */
> @@ -2703,9 +2716,9 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
> mask = interrupt_status_offsets[hpd].hpd;
>
> if (disp_int & mask) {
> - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
> - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
> schedule_work(&adev->hotplug_work);
> DRM_INFO("IH: HPD%d\n", hpd + 1);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> index 3ecd36f30e2a..fde2086246fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> @@ -23,6 +23,84 @@
> #ifndef SI_ENUMS_H
> #define SI_ENUMS_H
>
> +#define VBLANK_INT_MASK (1 << 0)
> +#define DC_HPDx_INT_EN (1 << 16)
> +#define VBLANK_ACK (1 << 4)
> +#define VLINE_ACK (1 << 4)
> +
> +#define CURSOR_WIDTH 64
> +#define CURSOR_HEIGHT 64
> +
> +#define VGA_VSTATUS_CNTL 0xFFFCFFFF
> +#define PRIORITY_MARK_MASK 0x7fff
> +#define PRIORITY_OFF (1 << 16)
> +#define PRIORITY_ALWAYS_ON (1 << 20)
> +#define INTERLEAVE_EN (1 << 0)
> +
> +#define LATENCY_WATERMARK_MASK(x) ((x) << 16)
> +#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
> +#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
> +
> +#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
> +#define GRPH_ENDIAN_NONE 0
> +#define GRPH_ENDIAN_8IN16 1
> +#define GRPH_ENDIAN_8IN32 2
> +#define GRPH_ENDIAN_8IN64 3
> +
> +#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
> +#define GRPH_DEPTH_8BPP 0
> +#define GRPH_DEPTH_16BPP 1
> +#define GRPH_DEPTH_32BPP 2
> +
> +#define GRPH_FORMAT(x) (((x) & 0x7) << 8)
> +#define GRPH_FORMAT_INDEXED 0
> +#define GRPH_FORMAT_ARGB1555 0
> +#define GRPH_FORMAT_ARGB565 1
> +#define GRPH_FORMAT_ARGB4444 2
> +#define GRPH_FORMAT_AI88 3
> +#define GRPH_FORMAT_MONO16 4
> +#define GRPH_FORMAT_BGRA5551 5
> +#define GRPH_FORMAT_ARGB8888 0
> +#define GRPH_FORMAT_ARGB2101010 1
> +#define GRPH_FORMAT_32BPP_DIG 2
> +#define GRPH_FORMAT_8B_ARGB2101010 3
> +#define GRPH_FORMAT_BGRA1010102 4
> +#define GRPH_FORMAT_8B_BGRA1010102 5
> +#define GRPH_FORMAT_RGB111110 6
> +#define GRPH_FORMAT_BGR101111 7
> +
> +#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
> +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
> +#define GRPH_ARRAY_LINEAR_GENERAL 0
> +#define GRPH_ARRAY_LINEAR_ALIGNED 1
> +#define GRPH_ARRAY_1D_TILED_THIN1 2
> +#define GRPH_ARRAY_2D_TILED_THIN1 4
> +#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
> +#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
> +#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
> +#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
> +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
> +#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
> +
> +#define CURSOR_EN (1 << 0)
> +#define CURSOR_MODE(x) (((x) & 0x3) << 8)
> +#define CURSOR_MONO 0
> +#define CURSOR_24_1 1
> +#define CURSOR_24_8_PRE_MULT 2
> +#define CURSOR_24_8_UNPRE_MULT 3
> +#define CURSOR_2X_MAGNIFY (1 << 16)
> +#define CURSOR_FORCE_MC_ON (1 << 20)
> +#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
> +#define CURSOR_URGENT_ALWAYS 0
> +#define CURSOR_URGENT_1_8 1
> +#define CURSOR_URGENT_1_4 2
> +#define CURSOR_URGENT_3_8 3
> +#define CURSOR_URGENT_1_2 4
> +#define CURSOR_UPDATE_PENDING (1 << 0)
> +#define CURSOR_UPDATE_TAKEN (1 << 1)
> +#define CURSOR_UPDATE_LOCK (1 << 16)
> +#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
> +
> #define AMDGPU_NUM_OF_VMIDS 8
> #define SI_CRTC0_REGISTER_OFFSET 0
> #define SI_CRTC1_REGISTER_OFFSET 0x300
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> index a17973bb63a6..ae798f768853 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> @@ -4442,4 +4442,16 @@
> #define mmXDMA_TEST_DEBUG_DATA 0x041D
> #define mmXDMA_TEST_DEBUG_INDEX 0x041C
>
> +/* Registers that spilled out of sid.h */
> +#define mmDATA_FORMAT 0x1AC0
> +#define mmDESKTOP_HEIGHT 0x1AC1
> +#define mmDC_LB_MEMORY_SPLIT 0x1AC3
> +#define mmPRIORITY_A_CNT 0x1AC6
> +#define mmPRIORITY_B_CNT 0x1AC7
> +#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32
> +#define mmINT_MASK 0x1AD0
> +#define mmVLINE_STATUS 0x1AEE
> +#define mmVBLANK_STATUS 0x1AEF
> +
> +
> #endif
> --
> 2.10.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply
* Re: [Qemu-devel] [PULL] slirp: Fix access to freed memory
From: no-reply @ 2016-11-14 20:23 UTC (permalink / raw)
To: samuel.thibault; +Cc: famz, qemu-devel, peter.maydell
In-Reply-To: <20161114202030.17685-2-samuel.thibault@ens-lyon.org>
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PULL] slirp: Fix access to freed memory
Message-id: 20161114202030.17685-2-samuel.thibault@ens-lyon.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20161114202030.17685-2-samuel.thibault@ens-lyon.org -> patchew/20161114202030.17685-2-samuel.thibault@ens-lyon.org
Switched to a new branch 'test'
438b2d1 slirp: Fix access to freed memory
=== OUTPUT BEGIN ===
Checking PATCH 1/1: slirp: Fix access to freed memory...
ERROR: suspect code indent for conditional statements (4, 6)
#30: FILE: slirp/socket.c:74:
+ if (ifm->ifq_so == so) {
+ ifm->ifq_so = NULL;
ERROR: suspect code indent for conditional statements (4, 6)
#38: FILE: slirp/socket.c:82:
+ if (ifm->ifq_so == so) {
+ ifm->ifq_so = NULL;
total: 2 errors, 0 warnings, 23 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply
* Re: [RFC/PATCH 0/2] git diff <(command1) <(command2)
From: Michael J Gruber @ 2016-11-14 20:23 UTC (permalink / raw)
To: Junio C Hamano
Cc: Johannes Schindelin, Jacob Keller, Dennis Kaarsemaker,
Git mailing list
In-Reply-To: <xmqqoa1ix7nq.fsf@gitster.mtv.corp.google.com>
Junio C Hamano venit, vidit, dixit 14.11.2016 19:01:
> Michael J Gruber <git@drmicha.warpmail.net> writes:
>
>> *My* idea of --no-index was for it to behave as similar to the
>> --index-version as possible, regarding formatting etc., and to be a good
>> substitute for ordinary diff. The proposed patch achieves exactly that -
>
> Does it? It looks to me that it does a lot more.
Yes, I didn't mean to say that it achieves only that - it achieves that
one goal exactly, and more.
>> why should a *file* argument (which is not a pathspec in --no-index
>> mode) not be treated in the same way in which every other command treats
>> a file argument? The patch un-breaks the most natural expectation.
>
> I think a filename given as a command line argument, e.g. <(cmd), is
> now treated more sensibly with [2/2]. Something that is not a
> directory to be descended into and is not a regular file needs to be
> made into a form that we can use as a blob, and reading it into an
> in-core buffer is a workable way to do so.
Yes.
> However, when taken together with [1/2], doesn't the proposed patch
> "achieves" a lot more than "exactly that", namely, by not treating
> symbolic links discovered during traversals of directories given
> from the command line as such and dereferencing?
It's not clear to me what you are saying here - 1/2 makes git diff
follow symbolic links, yes, just like ordinary diff. If I 'diff' two
dirs that contain symbolic links with the same name pointing to
different files I get a diff between the contents, not between the
filenames.
I like the proposed change a lot, maybe that didn't come across clearly.
I think it makes things more "predictable" in the sense that it meets
typical expectations.
Michael
^ permalink raw reply
* Re: [PATCH kvm-unit-tests v2 07/17] pci: introduce struct pci_dev
From: Peter Xu @ 2016-11-14 20:22 UTC (permalink / raw)
To: Andrew Jones; +Cc: kvm, rkrcmar, agordeev, jan.kiszka, pbonzini
In-Reply-To: <20161110192154.m5xt5hvxmeiz4z5t@hawk.localdomain>
On Thu, Nov 10, 2016 at 08:21:54PM +0100, Andrew Jones wrote:
[...]
> > /* Scan bus look for a specific device. Only bus 0 scanned for now. */
> > pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
> > {
> > pcidevaddr_t dev;
> >
> > - for (dev = 0; dev < 256; ++dev) {
> > + for (dev = 0; dev < PCI_DEVFN_MAX; ++dev)
> > if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id &&
> > pci_config_readw(dev, PCI_DEVICE_ID) == device_id)
> > return dev;
> > - }
>
> I liked the {} here because the "one" line spans three.
Sure. I'll keep them.
[...]
> > -void pci_bar_print(pcidevaddr_t dev, int bar_num)
> > +void pci_bar_print(struct pci_dev *dev, int bar_num)
> > {
> > phys_addr_t size, start, end;
> > uint32_t bar;
> > @@ -187,6 +195,9 @@ static void pci_dev_print(pcidevaddr_t dev)
> > uint8_t subclass = pci_config_readb(dev, PCI_CLASS_DEVICE);
> > uint8_t class = pci_config_readb(dev, PCI_CLASS_DEVICE + 1);
> > int i;
> > + struct pci_dev pci_dev;
>
> Putting that above the 'int i' would appease my aesthetics OCD...
Sure.
[...]
> Besides my nits
>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
Thanks,
-- peterx
^ permalink raw reply
* Re: [dm-crypt] License Clarification
From: Milan Broz @ 2016-11-14 20:22 UTC (permalink / raw)
To: Nathaniel McCallum, dm-crypt; +Cc: Sorce, Simo
In-Reply-To: <CAOASepMPZrQaUmL2KTTDk4tEGOypO-xXFcsUj1cgeVPCUZ48dQ@mail.gmail.com>
The original intention is documented here
http://www.saout.de/pipermail/dm-crypt/2012-December/002992.html
Anyway, I have contacted lawyers to check it and for possible
guidance if a fix is needed.
Thanks,
Milan
On 11/10/2016 08:41 PM, Nathaniel McCallum wrote:
> In reviewing the license choices of a set of my projects, I have
> noticed an inconsistency in licensing and I would like to receive some
> clarification.
>
> There is a commit that changes some of the code to LGPLv2.1+:
> https://gitlab.com/cryptsetup/cryptsetup/commit/7eccb7ff5031a4f42f1ae8f7ffaefe80ba0d53dd
>
> However, the main header still reads GPLv2+:
> https://gitlab.com/cryptsetup/cryptsetup/blob/master/lib/libcryptsetup.h
>
> Further, the API examples have LGPLv2.1+:
> https://gitlab.com/cryptsetup/cryptsetup/wikis/API/index.html
>
> Again, the openssl crypto backend are licensed as LGPLv2.1+ w/ openssl
> exception. However, this exception doesn't seem to apply to the whole
> library:
> https://gitlab.com/cryptsetup/cryptsetup/blob/master/lib/crypto_backend/crypto_openssl.c
>
> In short, it is very unclear to me how this licensing is supposed to work.
>
> The best I can ascertain is this:
>
> crypto-backend (LGPLv2+) ==> libcryptsetup (GPLv2+) ==> API examples (LGPLv2+)
>
> It would, thus, seem to me that the API examples are incompatibly
> licensed and cannot actually link against libcryptsetup.
>
> Further, it seems to me that the crypto-backend can link against
> openssl, but not libcryptsetup itself. This further implies that
> consumers of libcryptsetup cannot link against openssl.
>
> Have I understood this correctly?
> _______________________________________________
> dm-crypt mailing list
> dm-crypt@saout.de
> http://www.saout.de/mailman/listinfo/dm-crypt
>
^ permalink raw reply
* Re: [PATCH] audit: tame initialization warning len_abuf in audit_log_execve_info
From: Paul Moore @ 2016-11-14 20:21 UTC (permalink / raw)
To: Richard Guy Briggs; +Cc: linux-audit, linux-kernel
In-Reply-To: <55715f3a839b7d38839d02f3d28a90b3476f7046.1478759919.git.rgb@redhat.com>
On Thu, Nov 10, 2016 at 1:39 AM, Richard Guy Briggs <rgb@redhat.com> wrote:
> Tame initialization warning of len_abuf in audit_log_execve_info even
> though there isn't presently a bug introduced by commit 43761473c254
> ("audit: fix a double fetch in audit_log_single_execve_arg()"). Using
> UNINITIALIZED_VAR instead may mask future bugs.
>
> Signed-off-by: Richard Guy Briggs <rgb@redhat.com>
> ---
> kernel/auditsc.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
Compiler warnings are annoying, regardless of if they are actually
problems or not so I'm going to merge this ... although I'm pretty
sure in a year or two somebody is going to submit a one-liner removing
this because it's unnecessary :)
> diff --git a/kernel/auditsc.c b/kernel/auditsc.c
> index e414dfa..d161b17 100644
> --- a/kernel/auditsc.c
> +++ b/kernel/auditsc.c
> @@ -1000,7 +1000,7 @@ static void audit_log_execve_info(struct audit_context *context,
> long len_rem;
> long len_full;
> long len_buf;
> - long len_abuf;
> + long len_abuf = 0;
> long len_tmp;
> bool require_data;
> bool encode;
> --
> 1.7.1
>
> --
> Linux-audit mailing list
> Linux-audit@redhat.com
> https://www.redhat.com/mailman/listinfo/linux-audit
--
paul moore
www.paul-moore.com
^ permalink raw reply
* Re: [PATCH] Handle SForced in storage_modifiers
From: Luc Van Oostenryck @ 2016-11-14 20:21 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Jeff Layton, Sparse Mailing-list, Al Viro
In-Reply-To: <CA+55aFxbn+ZAyN9zzcEF60UPoRN2hq86LHk9v5ecqg-c+x3pNw@mail.gmail.com>
On Mon, Nov 14, 2016 at 12:17:47PM -0800, Linus Torvalds wrote:
> On Mon, Nov 14, 2016 at 12:04 PM, Luc Van Oostenryck
> <luc.vanoostenryck@gmail.com> wrote:
> >
> > The array is statically initialized and never modified,
> > your patch shouldn't change anything, and this regardless of
> > the memory layout or compiler options.
>
> The problem is the _size_ of the array. Without that initializer for
> SForced case, it is one entry too small, and you get a random access
> past the end of the array.
>
> The patch is definitely correct.
>
> Linus
> --
Ah yes, indeed.
Thanks
^ permalink raw reply
* [PATCH] drm/i915: rewrite FBC's atomic CRTC-choosing code
From: Paulo Zanoni @ 2016-11-14 20:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Ville pointed out that intel_fbc_choose_crtc() is iterating over all
planes instead of just the primary planes. There are no real
consequences of this problem for HSW+, and for the other platforms it
just means that in some obscure multi-screen cases we'll keep FBC
disabled when we could have enabled it. Still, iterating over all
planes doesn't seem to be the best thing to do.
My initial idea was to just add a check for plane->type and be done,
but then I realized that in commits not involving the primary plane we
would reset crtc_state->enable_fbc back to false even when FBC is
enabled. That also wouldn't result in a bug due to the way the
enable_fbc variable is checked, but, still, our code can be better
than this.
So I went for the solution that involves tracking enable_fbc in the
primary plane state instead of the CRTC state. This way, if a commit
doesn't involve the primary plane for the CRTC we won't be resetting
enable_fbc back to false, so the variable will always reflect the
reality. And this change also makes more sense since FBC is actually
tied to the single plane and not the full pipe. As a bonus, we only
iterate over the CRTCs instead of iterating over all planes.
v2:
But Ville pointed that this only works properly if we have a single
commit with multiple CRTCs. If we have multiple parallel commits, each
with its own CRTC, we'll end with enable_fbc set to true in more than
one plane.
So the solution was to rename enable_fbc to can_enable_fbc. If we just
did the rename as the patch was, we'd end up with a single plane with
can_enable_fbc on commits involving multiple CRTCs: we'd choose the
best one, but we'd still end up with a variable that doesn't 100%
reflect reality.
So in the end I adopted Ville's suggestion of the fbc_score variable.
And then, instead of checking the score at intel_fbc_choose_crtc()
it should be possible to check for the score at intel_fbc_enable().
This allows us to simplify intel_fbc_choose_crtc() to the point where
it only needs to look at the given plane in order to assign its score
instead of looking at every primary plane on the same commit.
We still only set scores of 0 and 1 and we don't really do the
score-checking loop.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 8 ++--
drivers/gpu/drm/i915/intel_fbc.c | 85 ++++++++++++------------------------
3 files changed, 35 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 072a0b1..618ddc8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14133,7 +14133,6 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
return ret;
- intel_fbc_choose_crtc(dev_priv, state);
return calc_watermark_data(state);
}
@@ -14897,6 +14896,8 @@ intel_check_primary_plane(struct drm_plane *plane,
return ret;
}
+ intel_fbc_check_plane(state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 003afb8..f2d21d9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -402,6 +402,9 @@ struct intel_plane_state {
*/
int scaler_id;
+ /* 0: not suitable for FBC, 1+: suitable for FBC, more is better. */
+ unsigned int fbc_score;
+
struct drm_intel_sprite_colorkey ckey;
};
@@ -648,8 +651,6 @@ struct intel_crtc_state {
bool ips_enabled;
- bool enable_fbc;
-
bool double_wide;
bool dp_encoder_is_mst;
@@ -1500,8 +1501,7 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev)
#endif
/* intel_fbc.c */
-void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
- struct drm_atomic_state *state);
+void intel_fbc_check_plane(struct intel_plane_state *plane_state);
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
void intel_fbc_pre_update(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 62f215b..54fabe3 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1040,68 +1040,32 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
}
/**
- * intel_fbc_choose_crtc - select a CRTC to enable FBC on
- * @dev_priv: i915 device instance
- * @state: the atomic state structure
+ * intel_fbc_check_plane - check plane for FBC suitability
+ * @plane_state: the plane state
*
- * This function looks at the proposed state for CRTCs and planes, then chooses
- * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
- * true.
+ * This function should set fbc_score based on how suitable the plane is for
+ * FBC. For now the only scores used are 0 and 1.
*
- * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
- * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
+ * We're not changing dev_priv->fbc, so there's no need for the FBC lock.
*/
-void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
- struct drm_atomic_state *state)
+void intel_fbc_check_plane(struct intel_plane_state *plane_state)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
- struct drm_plane *plane;
- struct drm_plane_state *plane_state;
- bool crtc_chosen = false;
- int i;
+ struct drm_plane *plane = plane_state->base.plane;
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
- mutex_lock(&fbc->lock);
-
- /* Does this atomic commit involve the CRTC currently tied to FBC? */
- if (fbc->crtc &&
- !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
- goto out;
+ plane_state->fbc_score = 0;
if (!intel_fbc_can_enable(dev_priv))
- goto out;
-
- /* Simply choose the first CRTC that is compatible and has a visible
- * plane. We could go for fancier schemes such as checking the plane
- * size, but this would just affect the few platforms that don't tie FBC
- * to pipe or plane A. */
- for_each_plane_in_state(state, plane, plane_state, i) {
- struct intel_plane_state *intel_plane_state =
- to_intel_plane_state(plane_state);
- struct intel_crtc_state *intel_crtc_state;
- struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
-
- if (!intel_plane_state->base.visible)
- continue;
-
- if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
- continue;
-
- if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
- continue;
-
- intel_crtc_state = to_intel_crtc_state(
- drm_atomic_get_existing_crtc_state(state, &crtc->base));
-
- intel_crtc_state->enable_fbc = true;
- crtc_chosen = true;
- break;
- }
-
- if (!crtc_chosen)
- fbc->no_fbc_reason = "no suitable CRTC for FBC";
+ return;
+ if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
+ return;
+ if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
+ return;
+ if (!plane_state->base.visible)
+ return;
-out:
- mutex_unlock(&fbc->lock);
+ plane_state->fbc_score = 1;
}
/**
@@ -1114,6 +1078,13 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
* possible. Notice that it doesn't activate FBC. It is valid to call
* intel_fbc_enable multiple times for the same pipe without an
* intel_fbc_disable in the middle, as long as it is deactivated.
+ *
+ * In the future this function could make better use of the fbc_score variable.
+ * We could, for example, loop through all the primary planes involved in the
+ * atomic commit and only enable FBC for the plane with the best fbc_score. We
+ * could also try to do some scheme where a plane with better score takes over
+ * FBC from another plane, but our driver currently can't handle the complexity
+ * of switching planes on the fly. This would only affect from Gen 4 up to IVB.
*/
void intel_fbc_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
@@ -1130,14 +1101,16 @@ void intel_fbc_enable(struct intel_crtc *crtc,
if (fbc->enabled) {
WARN_ON(fbc->crtc == NULL);
if (fbc->crtc == crtc) {
- WARN_ON(!crtc_state->enable_fbc);
+ WARN_ON(plane_state->fbc_score == 0);
WARN_ON(fbc->active);
}
goto out;
}
- if (!crtc_state->enable_fbc)
+ if (plane_state->fbc_score == 0) {
+ fbc->no_fbc_reason = "no suitable CRTC for FBC";
goto out;
+ }
WARN_ON(fbc->active);
WARN_ON(fbc->crtc != NULL);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Qemu-devel] [PULL] slirp: Fix access to freed memory
From: Samuel Thibault @ 2016-11-14 20:20 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Samuel Thibault
In-Reply-To: <20161114202030.17685-1-samuel.thibault@ens-lyon.org>
if_start() goes through the slirp->if_fastq and slirp->if_batchq
list of pending messages, and accesses ifm->ifq_so->so_nqueued of its
elements if ifm->ifq_so != NULL. When freeing a socket, we thus need
to make sure that any pending message for this socket does not refer
to the socket any more.
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Brian Candler <b.candler@pobox.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
---
slirp/socket.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/slirp/socket.c b/slirp/socket.c
index 280050a..6c18971 100644
--- a/slirp/socket.c
+++ b/slirp/socket.c
@@ -66,6 +66,23 @@ void
sofree(struct socket *so)
{
Slirp *slirp = so->slirp;
+ struct mbuf *ifm;
+
+ for (ifm = (struct mbuf *) slirp->if_fastq.qh_link;
+ (struct quehead *) ifm != &slirp->if_fastq;
+ ifm = ifm->ifq_next) {
+ if (ifm->ifq_so == so) {
+ ifm->ifq_so = NULL;
+ }
+ }
+
+ for (ifm = (struct mbuf *) slirp->if_batchq.qh_link;
+ (struct quehead *) ifm != &slirp->if_batchq;
+ ifm = ifm->ifq_next) {
+ if (ifm->ifq_so == so) {
+ ifm->ifq_so = NULL;
+ }
+ }
if (so->so_emu==EMU_RSH && so->extra) {
sofree(so->extra);
--
2.10.2
^ permalink raw reply related
* [Qemu-devel] [PULL] slirp: Fix access to freed memory
From: Samuel Thibault @ 2016-11-14 20:20 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Samuel Thibault
The following changes since commit 83c83f9a5266ff113060f887f106a47920fa6974:
Merge remote-tracking branch 'bonzini/tags/for-upstream' into staging (2016-11-11 12:51:50 +0000)
are available in the git repository at:
http://people.debian.org/~sthibault/qemu.git tags/samuel-thibault
for you to fetch changes up to ea64d5f08817b5e79e17135dce516c7583107f91:
slirp: Fix access to freed memory (2016-11-14 17:36:33 +0100)
----------------------------------------------------------------
slirp updates
----------------------------------------------------------------
Samuel Thibault (1):
slirp: Fix access to freed memory
slirp/socket.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
^ permalink raw reply
* Re: [PATCH] acpi: Use NULL from <linux/stddef.h>
From: Rafael J. Wysocki @ 2016-11-14 20:20 UTC (permalink / raw)
To: Bart Van Assche, Lv, Robert Moore
Cc: Rafael J. Wysocki, Len Brown, linux-acpi@vger.kernel.org
In-Reply-To: <4f698429-49cf-689a-9eb5-978b182bb4bb@sandisk.com>
On Mon, Nov 14, 2016 at 5:50 PM, Bart Van Assche
<bart.vanassche@sandisk.com> wrote:
> Use the definition of NULL from <linux/stddef.h> instead of
> redefining NULL. Additionally, change (void *)NULL into NULL.
>
> Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
> Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
> Cc: Len Brown <lenb@kernel.org>
> Cc: linux-acpi@vger.kernel.org
> ---
> include/acpi/actypes.h | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
> index 1d798ab..f019641 100644
> --- a/include/acpi/actypes.h
> +++ b/include/acpi/actypes.h
> @@ -44,6 +44,8 @@
> #ifndef __ACTYPES_H__
> #define __ACTYPES_H__
>
> +#include <linux/stddef.h> /* NULL */
This is file is based on upstream ACPICA code and it should not
contain Linux-specific includes etc. as a rule.
> +
> /* acpisrc:struct_defs -- for acpisrc conversion */
>
> /*
> @@ -437,10 +439,6 @@ typedef u64 acpi_physical_address;
> #endif
> #define TRUE (1 == 1)
>
> -#ifndef NULL
> -#define NULL (void *) 0
> -#endif
> -
> /*
> * Miscellaneous types
> */
> @@ -530,9 +528,9 @@ typedef u64 acpi_integer;
>
> /* Pointer/Integer type conversions */
>
> -#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL,(acpi_size) i)
> -#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p, (void *) NULL)
> -#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF (&(((d *) 0)->f), (void *) NULL)
> +#define ACPI_TO_POINTER(i) ACPI_ADD_PTR(void, NULL, (acpi_size) i)
> +#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF(p, NULL)
> +#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF(&(((d *) 0)->f), NULL)
> #define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i)
> #define ACPI_PTR_TO_PHYSADDR(i) ACPI_TO_INTEGER(i)
Lv, Bob, can you have a look at this, please?
Thanks,
Rafael
^ permalink raw reply
* Re: [PATCH] NFSv4.1: Don't allow a lock_state to be freed while checking
From: Benjamin Coddington @ 2016-11-14 20:18 UTC (permalink / raw)
To: Trond Myklebust, Anna Schumaker; +Cc: linux-nfs
In-Reply-To: <0e6e9dac991cd93e2ae3e6a4b4b41bd974a040cb.1479142099.git.bcodding@redhat.com>
On 14 Nov 2016, at 11:50, Benjamin Coddington wrote:
> While walking the list of lock_states, keep the current
> nfs4_lock_state
> referenced so that it isn't freed while checking.
>
> Signed-off-by: Benjamin Coddington <bcodding@redhat.com>
> ---
> fs/nfs/nfs4proc.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
> index 7897826d7c51..9a1cb9e8c4fc 100644
> --- a/fs/nfs/nfs4proc.c
> +++ b/fs/nfs/nfs4proc.c
> @@ -2564,12 +2564,15 @@ static void
> nfs41_check_delegation_stateid(struct nfs4_state *state)
> static int nfs41_check_expired_locks(struct nfs4_state *state)
> {
> int status, ret = NFS_OK;
> - struct nfs4_lock_state *lsp;
> + struct nfs4_lock_state *lsp, *tmp;
> struct nfs_server *server = NFS_SERVER(state->inode);
>
> if (!test_bit(LK_STATE_IN_USE, &state->flags))
> goto out;
> - list_for_each_entry(lsp, &state->lock_states, ls_locks) {
> + spin_lock(&state->state_lock);
> + list_for_each_entry_safe(lsp, tmp, &state->lock_states, ls_locks) {
> + atomic_inc(&lsp->ls_count);
> + spin_unlock(&state->state_lock);
> if (test_bit(NFS_LOCK_INITIALIZED, &lsp->ls_flags)) {
> struct rpc_cred *cred = lsp->ls_state->owner->so_cred;
>
> @@ -2588,7 +2591,10 @@ static int nfs41_check_expired_locks(struct
> nfs4_state *state)
> break;
> }
> }
> - };
> + nfs4_put_lock_state(lsp);
> + spin_lock(&state->state_lock);
> + }
> + spin_unlock(&state->state_lock);
> out:
> return ret;
> }
Actually, something else may be wrong here.. after several more hours of
testing with this and Trond's two fixes for CLOSE races this popped up:
[ 8102.015071] BUG: unable to handle kernel NULL pointer dereference at
0000000000000048
[ 8102.015985] IP: [<ffffffff8182717c>] _raw_spin_lock+0xc/0x30
[ 8102.016622] PGD 0
[ 8102.016829]
[ 8102.017014] Oops: 0002 [#1] SMP
[ 8102.017357] Modules linked in: nfsv4 dns_resolver nfs ip6t_rpfilter
ip6t_REJECT nf_reject_ipv6 xt_conntrack ip_set nfnetlink ebtable_nat
ebtable_broute bridge stp llc ip6table_nat nf_conntrack_ipv6
nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_raw
ip6table_security iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4
nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle iptable_raw
iptable_security ebtable_filter ebtables ip6table_filter ip6_tables nfsd
auth_rpcgss nfs_acl lockd grace sunrpc virtio_balloon virtio_console
virtio_net virtio_blk crct10dif_pclmul ppdev crc32_pclmul crc32c_intel
ghash_clmulni_intel virtio_pci serio_raw i2c_piix4 virtio_ring virtio
ata_generic parport_pc pata_acpi parport acpi_cpufreq tpm_tis
tpm_tis_core tpm
[ 8102.025180] CPU: 3 PID: 4475 Comm: ::1-manager Not tainted
4.9.0-rc5-00268-gbb3ec452d27c #45
[ 8102.026093] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996),
BIOS 1.8.1-20150318_183358- 04/01/2014
[ 8102.027122] task: ffff880132b93a80 task.stack: ffffc90003200000
[ 8102.027769] RIP: 0010:[<ffffffff8182717c>] [<ffffffff8182717c>]
_raw_spin_lock+0xc/0x30
[ 8102.028657] RSP: 0018:ffffc90003203d40 EFLAGS: 00010246
[ 8102.029227] RAX: 0000000000000000 RBX: ffff880132d9c31c RCX:
0000000000000001
[ 8102.029996] RDX: 0000000000000001 RSI: 0000000000000048 RDI:
0000000000000048
[ 8102.030771] RBP: ffffc90003203d58 R08: 0000000032b45601 R09:
000000018010000e
[ 8102.031532] R10: 000000008010000e R11: 0000000000100000 R12:
0000000000000048
[ 8102.032291] R13: 0000000000000000 R14: 0000000000000000 R15:
ffff880139fc2050
[ 8102.033064] FS: 0000000000000000(0000) GS:ffff88013fd80000(0000)
knlGS:0000000000000000
[ 8102.033930] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 8102.034546] CR2: 0000000000000048 CR3: 0000000139678000 CR4:
00000000000406e0
[ 8102.035312] Stack:
[ 8102.035542] ffffffff81489818 ffff880132d9c200 0000000000000000
ffffc90003203d78
[ 8102.036400] ffffffffa02f9289 ffff8801314f29c0 0000000000000000
ffffc90003203de8
[ 8102.037259] ffffffffa02e3dd2 ffff88013393f000 ffff8801314f29e0
ffff8801314f2a08
[ 8102.038120] Call Trace:
[ 8102.038392] [<ffffffff81489818>] ? _atomic_dec_and_lock+0x48/0x5b
[ 8102.039073] [<ffffffffa02f9289>] nfs4_put_lock_state+0x29/0x90
[nfsv4]
[ 8102.039797] [<ffffffffa02e3dd2>] nfs41_open_expired+0x192/0x410
[nfsv4]
[ 8102.040523] [<ffffffffa02f859f>] nfs4_do_reclaim+0x1af/0x630 [nfsv4]
[ 8102.041227] [<ffffffffa02f8f30>] nfs4_run_state_manager+0x510/0x7d0
[nfsv4]
[ 8102.041995] [<ffffffffa02f8a20>] ? nfs4_do_reclaim+0x630/0x630
[nfsv4]
[ 8102.042719] [<ffffffffa02f8a20>] ? nfs4_do_reclaim+0x630/0x630
[nfsv4]
[ 8102.043434] [<ffffffff810c96a9>] kthread+0xd9/0xf0
[ 8102.043968] [<ffffffff810c95d0>] ? kthread_park+0x60/0x60
[ 8102.044559] [<ffffffff81827615>] ret_from_fork+0x25/0x30
[ 8102.045150] Code: c0 ba 01 00 00 00 f0 0f b1 17 85 c0 75 02 5d c3 89
c6 e8 18 db 8c ff 5d c3 66 0f 1f 44 00 00 66 66 66 66 90 31 c0 ba 01 00
00 00 <f0> 0f b1 17 85 c0 75 01 c3 55 89 c6 48 89 e5 e8 f0 da 8c ff 5d
[ 8102.048136] RIP [<ffffffff8182717c>] _raw_spin_lock+0xc/0x30
[ 8102.048775] RSP <ffffc90003203d40>
[ 8102.049153] CR2: 0000000000000048
[ 8102.049893] ---[ end trace 8dc47952e274960a ]---
[ 8102.050391] Kernel panic - not syncing: Fatal exception
[ 8102.051090] Kernel Offset: disabled
[ 8102.051475] ---[ end Kernel panic - not syncing: Fatal exception
OK, it now looks like the nfs4_state has been freed while walking the
list of
lock_states. I'll have to look at this a bit more tomorrow. I have to
ferry
the kids around now.
Ben
^ permalink raw reply
* [Buildroot] [PATCH next] package/{mesa3d, mesa3d-headers}: bump version to 13.0.1
From: Thomas Petazzoni @ 2016-11-14 20:18 UTC (permalink / raw)
To: buildroot
In-Reply-To: <20161114140136.33344-1-Vincent.Riera@imgtec.com>
Hello,
On Mon, 14 Nov 2016 14:01:36 +0000, Vicente Olivert Riera wrote:
> Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
> ---
> package/mesa3d-headers/mesa3d-headers.mk | 2 +-
> package/mesa3d/mesa3d.hash | 4 ++--
> package/mesa3d/mesa3d.mk | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
Well, in fact the bump to mesa 13.0 was probably a bad thing, it's
apparently a development version, and it's causing a number of build
issues (not in mesa itself, but in other packages using it).
Does 13.0.1 fixes those issues? See Yann's mail about this:
From: "Yann E. MORIN" <yann.morin.1998@free.fr>
To: Bernd Kuhls <bernd.kuhls@t-online.de>
Cc: buildroot at buildroot.org
Subject: Re: [Buildroot] [PATCH 1/1] package/mesa3d: Remove opengl headers files if opengl support is disabled
Date: Sun, 13 Nov 2016 15:09:18 +0100
Thanks,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH kvm-unit-tests v2 03/17] x86: intel-iommu: add vt-d init test
From: Peter Xu @ 2016-11-14 20:18 UTC (permalink / raw)
To: Andrew Jones; +Cc: kvm, rkrcmar, agordeev, jan.kiszka, pbonzini
In-Reply-To: <20161110190936.bz46qi7g5cij6fmq@hawk.localdomain>
On Thu, Nov 10, 2016 at 08:09:36PM +0100, Andrew Jones wrote:
[...]
> > +static uint64_t vtd_root_table(void)
> > +{
> > + /* No extend root table support yet */
> > + return vtd_readq(DMAR_RTADDR_REG) & VTD_RTA_MASK;
>
> Should use tabs. You can run the kernel's scripts/checkpatch.pl,
> since we're using the same coding standard (pretty much...)
Yes, the indentation is wrong, which is to be fixed. Will try the
script later and see what else I can get.
>
> > +}
> > +
> > +static uint64_t vtd_ir_table(void)
> > +{
> > + return vtd_readq(DMAR_IRTA_REG) & VTD_IRTA_MASK;
> > +}
>
> The above two functions are both only used once each. Do we need them?
They are both used in further patches of this series. Also they might
be used in the future as well. So I'll keep them if you would not
mind.
Thanks,
-- peterx
^ permalink raw reply
* Re: [PATCH] Handle SForced in storage_modifiers
From: Linus Torvalds @ 2016-11-14 20:17 UTC (permalink / raw)
To: Luc Van Oostenryck; +Cc: Jeff Layton, Sparse Mailing-list, Al Viro
In-Reply-To: <20161114200447.GA15866@macbook.local>
On Mon, Nov 14, 2016 at 12:04 PM, Luc Van Oostenryck
<luc.vanoostenryck@gmail.com> wrote:
>
> The array is statically initialized and never modified,
> your patch shouldn't change anything, and this regardless of
> the memory layout or compiler options.
The problem is the _size_ of the array. Without that initializer for
SForced case, it is one entry too small, and you get a random access
past the end of the array.
The patch is definitely correct.
Linus
^ permalink raw reply
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