* Re: [PATCH v7 19/21] iommu/mediatek: Rename enable_4GB to dram_is_4gb
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: Joerg Roedel, Robin Murphy, Rob Herring, Evan Green, Tomasz Figa,
Will Deacon, linux-mediatek, srv_heupstream, devicetree,
linux-kernel, linux-arm-kernel, iommu, yingjoe.chen, youlin.pei,
Nicolas Boichat, anan.sun, Matthias Kaehlcke
In-Reply-To: <9bf13c22-0c73-2950-2204-23d577976b03@gmail.com>
On Tue, 2019-06-18 at 18:06 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > This patch only rename the variable name from enable_4GB to
> > dram_is_4gb for readable.
>
> From my understanding this is true when available RAM > 4GB so I think the name
> should be something like dram_bigger_4gb otherwise it may create confusion again.
Strictly, It is not "dram_bigger_4gb". actually if the dram size is over
3GB (the first 1GB is the register space), the "4GB mode" will be
enabled. then how about the name "dram_enable_32bit"?(the PA 32bit will
be enabled in the 4GB mode.)
There is another option, please see the last part in [1] suggested by
Evan, something like below:
----
data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
if (!data->plat_data->has_4gb_mode)
data->enable_4GB = false;
Then mtk_iommu_map would only have:
if (data->enable_4GB)
paddr |= BIT_ULL(32);
----
Which one do you prefer?
[1] https://lore.kernel.org/patchwork/patch/1028421/
>
> Also from my point of view this patch should be done before
> "[PATCH 06/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode"
OK.
>
> Regards,
> Matthias
>
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Evan Green <evgreen@chromium.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 10 +++++-----
> > drivers/iommu/mtk_iommu.h | 2 +-
> > 2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 86158d8..67cab2d 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -382,7 +382,7 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > int ret;
> >
> > /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
> > - if (data->plat_data->has_4gb_mode && data->enable_4GB)
> > + if (data->plat_data->has_4gb_mode && data->dram_is_4gb)
> > paddr |= BIT_ULL(32);
> >
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > @@ -554,13 +554,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> > writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
> >
> > if (data->plat_data->m4u_plat == M4U_MT8173)
> > - regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
> > + regval = (data->protect_base >> 1) | (data->dram_is_4gb << 31);
> > else
> > regval = lower_32_bits(data->protect_base) |
> > upper_32_bits(data->protect_base);
> > writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
> >
> > - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) {
> > + if (data->dram_is_4gb && data->plat_data->has_vld_pa_rng) {
> > /*
> > * If 4GB mode is enabled, the validate PA range is from
> > * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
> > @@ -611,8 +611,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > return -ENOMEM;
> > data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
> >
> > - /* Whether the current dram is over 4GB */
> > - data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> > + /* Whether the current dram is 4GB. */
> > + data->dram_is_4gb = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > data->base = devm_ioremap_resource(dev, res);
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 753266b..e8114b2 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -65,7 +65,7 @@ struct mtk_iommu_data {
> > struct mtk_iommu_domain *m4u_dom;
> > struct iommu_group *m4u_group;
> > struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
> > - bool enable_4GB;
> > + bool dram_is_4gb;
> > bool tlb_flush_active;
> >
> > struct iommu_device iommu;
> >
^ permalink raw reply
* Re: [PATCH v7 19/21] iommu/mediatek: Rename enable_4GB to dram_is_4gb
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
Will Deacon, linux-kernel, Evan Green, Tomasz Figa, iommu,
Rob Herring, linux-mediatek, yingjoe.chen, anan.sun, Robin Murphy,
Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <9bf13c22-0c73-2950-2204-23d577976b03@gmail.com>
On Tue, 2019-06-18 at 18:06 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > This patch only rename the variable name from enable_4GB to
> > dram_is_4gb for readable.
>
> From my understanding this is true when available RAM > 4GB so I think the name
> should be something like dram_bigger_4gb otherwise it may create confusion again.
Strictly, It is not "dram_bigger_4gb". actually if the dram size is over
3GB (the first 1GB is the register space), the "4GB mode" will be
enabled. then how about the name "dram_enable_32bit"?(the PA 32bit will
be enabled in the 4GB mode.)
There is another option, please see the last part in [1] suggested by
Evan, something like below:
----
data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
if (!data->plat_data->has_4gb_mode)
data->enable_4GB = false;
Then mtk_iommu_map would only have:
if (data->enable_4GB)
paddr |= BIT_ULL(32);
----
Which one do you prefer?
[1] https://lore.kernel.org/patchwork/patch/1028421/
>
> Also from my point of view this patch should be done before
> "[PATCH 06/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode"
OK.
>
> Regards,
> Matthias
>
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Evan Green <evgreen@chromium.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 10 +++++-----
> > drivers/iommu/mtk_iommu.h | 2 +-
> > 2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 86158d8..67cab2d 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -382,7 +382,7 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > int ret;
> >
> > /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
> > - if (data->plat_data->has_4gb_mode && data->enable_4GB)
> > + if (data->plat_data->has_4gb_mode && data->dram_is_4gb)
> > paddr |= BIT_ULL(32);
> >
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > @@ -554,13 +554,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> > writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
> >
> > if (data->plat_data->m4u_plat == M4U_MT8173)
> > - regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
> > + regval = (data->protect_base >> 1) | (data->dram_is_4gb << 31);
> > else
> > regval = lower_32_bits(data->protect_base) |
> > upper_32_bits(data->protect_base);
> > writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
> >
> > - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) {
> > + if (data->dram_is_4gb && data->plat_data->has_vld_pa_rng) {
> > /*
> > * If 4GB mode is enabled, the validate PA range is from
> > * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
> > @@ -611,8 +611,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > return -ENOMEM;
> > data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
> >
> > - /* Whether the current dram is over 4GB */
> > - data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> > + /* Whether the current dram is 4GB. */
> > + data->dram_is_4gb = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > data->base = devm_ioremap_resource(dev, res);
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 753266b..e8114b2 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -65,7 +65,7 @@ struct mtk_iommu_data {
> > struct mtk_iommu_domain *m4u_dom;
> > struct iommu_group *m4u_group;
> > struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
> > - bool enable_4GB;
> > + bool dram_is_4gb;
> > bool tlb_flush_active;
> >
> > struct iommu_device iommu;
> >
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* [U-Boot] [PATCH] fastboot: Remove "bootloader-version" variable
From: Sam Protsenko @ 2019-06-20 14:00 UTC (permalink / raw)
To: u-boot
As per [1], there is no such fastboot variable as "bootloader-version".
Only "version-bootloader" is supported. Let's reflect this and not
confuse users further.
[1] https://android.googlesource.com/platform/system/core/+/master/fastboot/README.md#client-variables
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
doc/README.android-fastboot | 4 ++--
drivers/fastboot/fb_getvar.c | 9 +++------
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot
index 431191c473..ce852a4fd1 100644
--- a/doc/README.android-fastboot
+++ b/doc/README.android-fastboot
@@ -169,8 +169,8 @@ On the client side you can fetch the bootloader version for instance:
::
- $ fastboot getvar bootloader-version
- bootloader-version: U-Boot 2014.04-00005-gd24cabc
+ $ fastboot getvar version-bootloader
+ version-bootloader: U-Boot 2014.04-00005-gd24cabc
finished. total time: 0.000s
or initiate a reboot:
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index fd0823b2bf..ebe5c8a104 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -12,7 +12,7 @@
#include <version.h>
static void getvar_version(char *var_parameter, char *response);
-static void getvar_bootloader_version(char *var_parameter, char *response);
+static void getvar_version_bootloader(char *var_parameter, char *response);
static void getvar_downloadsize(char *var_parameter, char *response);
static void getvar_serialno(char *var_parameter, char *response);
static void getvar_version_baseband(char *var_parameter, char *response);
@@ -37,12 +37,9 @@ static const struct {
{
.variable = "version",
.dispatch = getvar_version
- }, {
- .variable = "bootloader-version",
- .dispatch = getvar_bootloader_version
}, {
.variable = "version-bootloader",
- .dispatch = getvar_bootloader_version
+ .dispatch = getvar_version_bootloader
}, {
.variable = "downloadsize",
.dispatch = getvar_downloadsize
@@ -131,7 +128,7 @@ static void getvar_version(char *var_parameter, char *response)
fastboot_okay(FASTBOOT_VERSION, response);
}
-static void getvar_bootloader_version(char *var_parameter, char *response)
+static void getvar_version_bootloader(char *var_parameter, char *response)
{
fastboot_okay(U_BOOT_VERSION, response);
}
--
2.20.1
^ permalink raw reply related
* Re: [PATCH v7 17/21] memory: mtk-smi: Get rid of need_larbid
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
Joerg Roedel, Will Deacon, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, yingjoe.chen, anan.sun,
Robin Murphy, Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1af7b67a-b73a-efb9-e1f8-5701f05a4af0@gmail.com>
On Tue, 2019-06-18 at 15:45 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> > It's no need to parse it again in SMI driver. Only clean some codes.
> > This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> > and mt8183.
> >
> > After this patch, the "mediatek,larb-id" only be needed for mt2712
> > which have 2 M4Us. In the other SoCs, we can get the larb-id from M4U
> > in which the larbs in the "mediatek,larbs" always are ordered.
> >
> > Correspondingly, the larb_nr in the "struct mtk_smi_iommu" could also
> > be deleted.
> >
>
> I think we can get rid of struct mtk_smi_iommu and just add the
> struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX] directly to mtk_iommu_data,
> passing just that array to the components bind function.
Thanks. I will try this in a new patch.
>
> Never the less this patch looks fine:
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Really appreciate for reviewing so many patches.
>
> > CC: Matthias Brugger <matthias.bgg@gmail.com>
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Evan Green <evgreen@chromium.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 1 -
> > drivers/iommu/mtk_iommu_v1.c | 2 --
> > drivers/memory/mtk-smi.c | 26 ++------------------------
> > include/soc/mediatek/smi.h | 1 -
> > 4 files changed, 2 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index ec4ce74..6053b8b 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -634,7 +634,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > "mediatek,larbs", NULL);
> > if (larb_nr < 0)
> > return larb_nr;
> > - data->smi_imu.larb_nr = larb_nr;
> >
> > for (i = 0; i < larb_nr; i++) {
> > struct device_node *larbnode;
> > diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> > index 52b01e3..73308ad 100644
> > --- a/drivers/iommu/mtk_iommu_v1.c
> > +++ b/drivers/iommu/mtk_iommu_v1.c
> > @@ -624,8 +624,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > larb_nr++;
> > }
> >
> > - data->smi_imu.larb_nr = larb_nr;
> > -
> > platform_set_drvdata(pdev, data);
> >
> > ret = mtk_iommu_hw_init(data);
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index 08cf40d..10e6493 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
> > };
> >
> > struct mtk_smi_larb_gen {
> > - bool need_larbid;
> > int port_in_larb[MTK_LARB_NR_MAX + 1];
> > void (*config_port)(struct device *);
> > unsigned int larb_direct_to_common_mask;
> > @@ -153,18 +152,9 @@ void mtk_smi_larb_put(struct device *larbdev)
> > struct mtk_smi_iommu *smi_iommu = data;
> > unsigned int i;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
> > - return 0;
> > - }
> > -
> > - /*
> > - * If there is no larbid property, Loop to find the corresponding
> > - * iommu information.
> > - */
> > - for (i = 0; i < smi_iommu->larb_nr; i++) {
> > + for (i = 0; i < MTK_LARB_NR_MAX; i++) {
> > if (dev == smi_iommu->larb_imu[i].dev) {
> > - /* The 'mmu' may be updated in iommu-attach/detach. */
> > + larb->larbid = i;
> > larb->mmu = &smi_iommu->larb_imu[i].mmu;
> > return 0;
> > }
> > @@ -243,7 +233,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
> > - .need_larbid = true,
> > .port_in_larb = {
> > LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
> > LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
> > @@ -252,7 +241,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
> > - .need_larbid = true,
> > .config_port = mtk_smi_larb_config_port_gen2_general,
> > .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
> > };
> > @@ -291,7 +279,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *smi_node;
> > struct platform_device *smi_pdev;
> > - int err;
> >
> > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
> > if (!larb)
> > @@ -321,15 +308,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > }
> > larb->smi.dev = dev;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
> > - &larb->larbid);
> > - if (err) {
> > - dev_err(dev, "missing larbid property\n");
> > - return err;
> > - }
> > - }
> > -
> > smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
> > if (!smi_node)
> > return -EINVAL;
> > diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
> > index 5201e90..a65324d 100644
> > --- a/include/soc/mediatek/smi.h
> > +++ b/include/soc/mediatek/smi.h
> > @@ -29,7 +29,6 @@ struct mtk_smi_larb_iommu {
> > };
> >
> > struct mtk_smi_iommu {
> > - unsigned int larb_nr;
> > struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> > };
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] ath11k: fix extended stats update issue
From: Karthikeyan Periyasamy @ 2019-06-20 13:59 UTC (permalink / raw)
To: Kalle Valo; +Cc: ath11k
In-Reply-To: <20190620134957.7A6726137D@smtp.codeaurora.org>
On 2019-06-20 19:19, Kalle Valo wrote:
> Karthikeyan Periyasamy <periyasa@codeaurora.org> wrote:
>
>> user not able to see the valid tx stats. htt stats update
>> process get failed due to the wrong argument pass to
>> ath11k_get_ar_by_pdev_id API. Expected argument is pdev_id not
>> the pdev index. so avoid the conversion logic of pdev id to pdev
>> index in htt stats update process.
>>
>> Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org>
>
> This was already applied, right?
Yes, Its already applied
https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git/commit/?h=ath11k-bringup&id=b24d6461d9cf254e512a91ca430be59e70da0d5d
>
> error: patch failed: drivers/net/wireless/ath/ath11k/dp_rx.c:1294
> error: drivers/net/wireless/ath/ath11k/dp_rx.c: patch does not apply
> stg import: Diff does not apply cleanly
>
> Patch set to Rejected.
_______________________________________________
ath11k mailing list
ath11k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath11k
^ permalink raw reply
* Re: [PATCH v7 19/21] iommu/mediatek: Rename enable_4GB to dram_is_4gb
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA, Nicolas Boichat,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Evan Green, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w,
anan.sun-NuS5LvNUpcJWk0Htik3J/w, Robin Murphy, Matthias Kaehlcke,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <9bf13c22-0c73-2950-2204-23d577976b03-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, 2019-06-18 at 18:06 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > This patch only rename the variable name from enable_4GB to
> > dram_is_4gb for readable.
>
> From my understanding this is true when available RAM > 4GB so I think the name
> should be something like dram_bigger_4gb otherwise it may create confusion again.
Strictly, It is not "dram_bigger_4gb". actually if the dram size is over
3GB (the first 1GB is the register space), the "4GB mode" will be
enabled. then how about the name "dram_enable_32bit"?(the PA 32bit will
be enabled in the 4GB mode.)
There is another option, please see the last part in [1] suggested by
Evan, something like below:
----
data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
if (!data->plat_data->has_4gb_mode)
data->enable_4GB = false;
Then mtk_iommu_map would only have:
if (data->enable_4GB)
paddr |= BIT_ULL(32);
----
Which one do you prefer?
[1] https://lore.kernel.org/patchwork/patch/1028421/
>
> Also from my point of view this patch should be done before
> "[PATCH 06/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode"
OK.
>
> Regards,
> Matthias
>
> >
> > Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > Reviewed-by: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 10 +++++-----
> > drivers/iommu/mtk_iommu.h | 2 +-
> > 2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 86158d8..67cab2d 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -382,7 +382,7 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > int ret;
> >
> > /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
> > - if (data->plat_data->has_4gb_mode && data->enable_4GB)
> > + if (data->plat_data->has_4gb_mode && data->dram_is_4gb)
> > paddr |= BIT_ULL(32);
> >
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > @@ -554,13 +554,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> > writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
> >
> > if (data->plat_data->m4u_plat == M4U_MT8173)
> > - regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
> > + regval = (data->protect_base >> 1) | (data->dram_is_4gb << 31);
> > else
> > regval = lower_32_bits(data->protect_base) |
> > upper_32_bits(data->protect_base);
> > writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
> >
> > - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) {
> > + if (data->dram_is_4gb && data->plat_data->has_vld_pa_rng) {
> > /*
> > * If 4GB mode is enabled, the validate PA range is from
> > * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
> > @@ -611,8 +611,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > return -ENOMEM;
> > data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
> >
> > - /* Whether the current dram is over 4GB */
> > - data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> > + /* Whether the current dram is 4GB. */
> > + data->dram_is_4gb = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > data->base = devm_ioremap_resource(dev, res);
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 753266b..e8114b2 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -65,7 +65,7 @@ struct mtk_iommu_data {
> > struct mtk_iommu_domain *m4u_dom;
> > struct iommu_group *m4u_group;
> > struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
> > - bool enable_4GB;
> > + bool dram_is_4gb;
> > bool tlb_flush_active;
> >
> > struct iommu_device iommu;
> >
^ permalink raw reply
* Re: [PATCH v7 17/21] memory: mtk-smi: Get rid of need_larbid
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: Joerg Roedel, Robin Murphy, Rob Herring, Evan Green, Tomasz Figa,
Will Deacon, linux-mediatek, srv_heupstream, devicetree,
linux-kernel, linux-arm-kernel, iommu, yingjoe.chen, youlin.pei,
Nicolas Boichat, anan.sun, Matthias Kaehlcke
In-Reply-To: <1af7b67a-b73a-efb9-e1f8-5701f05a4af0@gmail.com>
On Tue, 2019-06-18 at 15:45 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> > It's no need to parse it again in SMI driver. Only clean some codes.
> > This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> > and mt8183.
> >
> > After this patch, the "mediatek,larb-id" only be needed for mt2712
> > which have 2 M4Us. In the other SoCs, we can get the larb-id from M4U
> > in which the larbs in the "mediatek,larbs" always are ordered.
> >
> > Correspondingly, the larb_nr in the "struct mtk_smi_iommu" could also
> > be deleted.
> >
>
> I think we can get rid of struct mtk_smi_iommu and just add the
> struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX] directly to mtk_iommu_data,
> passing just that array to the components bind function.
Thanks. I will try this in a new patch.
>
> Never the less this patch looks fine:
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Really appreciate for reviewing so many patches.
>
> > CC: Matthias Brugger <matthias.bgg@gmail.com>
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Evan Green <evgreen@chromium.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 1 -
> > drivers/iommu/mtk_iommu_v1.c | 2 --
> > drivers/memory/mtk-smi.c | 26 ++------------------------
> > include/soc/mediatek/smi.h | 1 -
> > 4 files changed, 2 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index ec4ce74..6053b8b 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -634,7 +634,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > "mediatek,larbs", NULL);
> > if (larb_nr < 0)
> > return larb_nr;
> > - data->smi_imu.larb_nr = larb_nr;
> >
> > for (i = 0; i < larb_nr; i++) {
> > struct device_node *larbnode;
> > diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> > index 52b01e3..73308ad 100644
> > --- a/drivers/iommu/mtk_iommu_v1.c
> > +++ b/drivers/iommu/mtk_iommu_v1.c
> > @@ -624,8 +624,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > larb_nr++;
> > }
> >
> > - data->smi_imu.larb_nr = larb_nr;
> > -
> > platform_set_drvdata(pdev, data);
> >
> > ret = mtk_iommu_hw_init(data);
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index 08cf40d..10e6493 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
> > };
> >
> > struct mtk_smi_larb_gen {
> > - bool need_larbid;
> > int port_in_larb[MTK_LARB_NR_MAX + 1];
> > void (*config_port)(struct device *);
> > unsigned int larb_direct_to_common_mask;
> > @@ -153,18 +152,9 @@ void mtk_smi_larb_put(struct device *larbdev)
> > struct mtk_smi_iommu *smi_iommu = data;
> > unsigned int i;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
> > - return 0;
> > - }
> > -
> > - /*
> > - * If there is no larbid property, Loop to find the corresponding
> > - * iommu information.
> > - */
> > - for (i = 0; i < smi_iommu->larb_nr; i++) {
> > + for (i = 0; i < MTK_LARB_NR_MAX; i++) {
> > if (dev == smi_iommu->larb_imu[i].dev) {
> > - /* The 'mmu' may be updated in iommu-attach/detach. */
> > + larb->larbid = i;
> > larb->mmu = &smi_iommu->larb_imu[i].mmu;
> > return 0;
> > }
> > @@ -243,7 +233,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
> > - .need_larbid = true,
> > .port_in_larb = {
> > LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
> > LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
> > @@ -252,7 +241,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
> > - .need_larbid = true,
> > .config_port = mtk_smi_larb_config_port_gen2_general,
> > .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
> > };
> > @@ -291,7 +279,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *smi_node;
> > struct platform_device *smi_pdev;
> > - int err;
> >
> > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
> > if (!larb)
> > @@ -321,15 +308,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > }
> > larb->smi.dev = dev;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
> > - &larb->larbid);
> > - if (err) {
> > - dev_err(dev, "missing larbid property\n");
> > - return err;
> > - }
> > - }
> > -
> > smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
> > if (!smi_node)
> > return -EINVAL;
> > diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
> > index 5201e90..a65324d 100644
> > --- a/include/soc/mediatek/smi.h
> > +++ b/include/soc/mediatek/smi.h
> > @@ -29,7 +29,6 @@ struct mtk_smi_larb_iommu {
> > };
> >
> > struct mtk_smi_iommu {
> > - unsigned int larb_nr;
> > struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> > };
> >
> >
^ permalink raw reply
* Re: [PATCH v7 17/21] memory: mtk-smi: Get rid of need_larbid
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
Will Deacon, linux-kernel, Evan Green, Tomasz Figa, iommu,
Rob Herring, linux-mediatek, yingjoe.chen, anan.sun, Robin Murphy,
Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1af7b67a-b73a-efb9-e1f8-5701f05a4af0@gmail.com>
On Tue, 2019-06-18 at 15:45 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> > It's no need to parse it again in SMI driver. Only clean some codes.
> > This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> > and mt8183.
> >
> > After this patch, the "mediatek,larb-id" only be needed for mt2712
> > which have 2 M4Us. In the other SoCs, we can get the larb-id from M4U
> > in which the larbs in the "mediatek,larbs" always are ordered.
> >
> > Correspondingly, the larb_nr in the "struct mtk_smi_iommu" could also
> > be deleted.
> >
>
> I think we can get rid of struct mtk_smi_iommu and just add the
> struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX] directly to mtk_iommu_data,
> passing just that array to the components bind function.
Thanks. I will try this in a new patch.
>
> Never the less this patch looks fine:
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Really appreciate for reviewing so many patches.
>
> > CC: Matthias Brugger <matthias.bgg@gmail.com>
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Evan Green <evgreen@chromium.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 1 -
> > drivers/iommu/mtk_iommu_v1.c | 2 --
> > drivers/memory/mtk-smi.c | 26 ++------------------------
> > include/soc/mediatek/smi.h | 1 -
> > 4 files changed, 2 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index ec4ce74..6053b8b 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -634,7 +634,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > "mediatek,larbs", NULL);
> > if (larb_nr < 0)
> > return larb_nr;
> > - data->smi_imu.larb_nr = larb_nr;
> >
> > for (i = 0; i < larb_nr; i++) {
> > struct device_node *larbnode;
> > diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> > index 52b01e3..73308ad 100644
> > --- a/drivers/iommu/mtk_iommu_v1.c
> > +++ b/drivers/iommu/mtk_iommu_v1.c
> > @@ -624,8 +624,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > larb_nr++;
> > }
> >
> > - data->smi_imu.larb_nr = larb_nr;
> > -
> > platform_set_drvdata(pdev, data);
> >
> > ret = mtk_iommu_hw_init(data);
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index 08cf40d..10e6493 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
> > };
> >
> > struct mtk_smi_larb_gen {
> > - bool need_larbid;
> > int port_in_larb[MTK_LARB_NR_MAX + 1];
> > void (*config_port)(struct device *);
> > unsigned int larb_direct_to_common_mask;
> > @@ -153,18 +152,9 @@ void mtk_smi_larb_put(struct device *larbdev)
> > struct mtk_smi_iommu *smi_iommu = data;
> > unsigned int i;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
> > - return 0;
> > - }
> > -
> > - /*
> > - * If there is no larbid property, Loop to find the corresponding
> > - * iommu information.
> > - */
> > - for (i = 0; i < smi_iommu->larb_nr; i++) {
> > + for (i = 0; i < MTK_LARB_NR_MAX; i++) {
> > if (dev == smi_iommu->larb_imu[i].dev) {
> > - /* The 'mmu' may be updated in iommu-attach/detach. */
> > + larb->larbid = i;
> > larb->mmu = &smi_iommu->larb_imu[i].mmu;
> > return 0;
> > }
> > @@ -243,7 +233,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
> > - .need_larbid = true,
> > .port_in_larb = {
> > LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
> > LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
> > @@ -252,7 +241,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
> > - .need_larbid = true,
> > .config_port = mtk_smi_larb_config_port_gen2_general,
> > .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
> > };
> > @@ -291,7 +279,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *smi_node;
> > struct platform_device *smi_pdev;
> > - int err;
> >
> > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
> > if (!larb)
> > @@ -321,15 +308,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > }
> > larb->smi.dev = dev;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
> > - &larb->larbid);
> > - if (err) {
> > - dev_err(dev, "missing larbid property\n");
> > - return err;
> > - }
> > - }
> > -
> > smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
> > if (!smi_node)
> > return -EINVAL;
> > diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
> > index 5201e90..a65324d 100644
> > --- a/include/soc/mediatek/smi.h
> > +++ b/include/soc/mediatek/smi.h
> > @@ -29,7 +29,6 @@ struct mtk_smi_larb_iommu {
> > };
> >
> > struct mtk_smi_iommu {
> > - unsigned int larb_nr;
> > struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> > };
> >
> >
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: [PATCH v7 17/21] memory: mtk-smi: Get rid of need_larbid
From: Yong Wu @ 2019-06-20 13:59 UTC (permalink / raw)
To: Matthias Brugger
Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA, Nicolas Boichat,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Evan Green, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Rob Herring,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w,
anan.sun-NuS5LvNUpcJWk0Htik3J/w, Robin Murphy, Matthias Kaehlcke,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1af7b67a-b73a-efb9-e1f8-5701f05a4af0-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, 2019-06-18 at 15:45 +0200, Matthias Brugger wrote:
>
> On 10/06/2019 14:17, Yong Wu wrote:
> > The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> > It's no need to parse it again in SMI driver. Only clean some codes.
> > This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> > and mt8183.
> >
> > After this patch, the "mediatek,larb-id" only be needed for mt2712
> > which have 2 M4Us. In the other SoCs, we can get the larb-id from M4U
> > in which the larbs in the "mediatek,larbs" always are ordered.
> >
> > Correspondingly, the larb_nr in the "struct mtk_smi_iommu" could also
> > be deleted.
> >
>
> I think we can get rid of struct mtk_smi_iommu and just add the
> struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX] directly to mtk_iommu_data,
> passing just that array to the components bind function.
Thanks. I will try this in a new patch.
>
> Never the less this patch looks fine:
> Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Really appreciate for reviewing so many patches.
>
> > CC: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > Reviewed-by: Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> > ---
> > drivers/iommu/mtk_iommu.c | 1 -
> > drivers/iommu/mtk_iommu_v1.c | 2 --
> > drivers/memory/mtk-smi.c | 26 ++------------------------
> > include/soc/mediatek/smi.h | 1 -
> > 4 files changed, 2 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index ec4ce74..6053b8b 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -634,7 +634,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > "mediatek,larbs", NULL);
> > if (larb_nr < 0)
> > return larb_nr;
> > - data->smi_imu.larb_nr = larb_nr;
> >
> > for (i = 0; i < larb_nr; i++) {
> > struct device_node *larbnode;
> > diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> > index 52b01e3..73308ad 100644
> > --- a/drivers/iommu/mtk_iommu_v1.c
> > +++ b/drivers/iommu/mtk_iommu_v1.c
> > @@ -624,8 +624,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> > larb_nr++;
> > }
> >
> > - data->smi_imu.larb_nr = larb_nr;
> > -
> > platform_set_drvdata(pdev, data);
> >
> > ret = mtk_iommu_hw_init(data);
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index 08cf40d..10e6493 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
> > };
> >
> > struct mtk_smi_larb_gen {
> > - bool need_larbid;
> > int port_in_larb[MTK_LARB_NR_MAX + 1];
> > void (*config_port)(struct device *);
> > unsigned int larb_direct_to_common_mask;
> > @@ -153,18 +152,9 @@ void mtk_smi_larb_put(struct device *larbdev)
> > struct mtk_smi_iommu *smi_iommu = data;
> > unsigned int i;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
> > - return 0;
> > - }
> > -
> > - /*
> > - * If there is no larbid property, Loop to find the corresponding
> > - * iommu information.
> > - */
> > - for (i = 0; i < smi_iommu->larb_nr; i++) {
> > + for (i = 0; i < MTK_LARB_NR_MAX; i++) {
> > if (dev == smi_iommu->larb_imu[i].dev) {
> > - /* The 'mmu' may be updated in iommu-attach/detach. */
> > + larb->larbid = i;
> > larb->mmu = &smi_iommu->larb_imu[i].mmu;
> > return 0;
> > }
> > @@ -243,7 +233,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
> > - .need_larbid = true,
> > .port_in_larb = {
> > LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
> > LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
> > @@ -252,7 +241,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> > };
> >
> > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
> > - .need_larbid = true,
> > .config_port = mtk_smi_larb_config_port_gen2_general,
> > .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
> > };
> > @@ -291,7 +279,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *smi_node;
> > struct platform_device *smi_pdev;
> > - int err;
> >
> > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
> > if (!larb)
> > @@ -321,15 +308,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
> > }
> > larb->smi.dev = dev;
> >
> > - if (larb->larb_gen->need_larbid) {
> > - err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
> > - &larb->larbid);
> > - if (err) {
> > - dev_err(dev, "missing larbid property\n");
> > - return err;
> > - }
> > - }
> > -
> > smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
> > if (!smi_node)
> > return -EINVAL;
> > diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
> > index 5201e90..a65324d 100644
> > --- a/include/soc/mediatek/smi.h
> > +++ b/include/soc/mediatek/smi.h
> > @@ -29,7 +29,6 @@ struct mtk_smi_larb_iommu {
> > };
> >
> > struct mtk_smi_iommu {
> > - unsigned int larb_nr;
> > struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> > };
> >
> >
^ permalink raw reply
* [Buildroot] [PATCH 1/1] package/dnsmasq: drop wchar dependency on IDN option
From: Thomas Petazzoni @ 2019-06-20 13:59 UTC (permalink / raw)
To: buildroot
In-Reply-To: <20190619180903.2467-1-fontaine.fabrice@gmail.com>
On Wed, 19 Jun 2019 20:09:03 +0200
Fabrice Fontaine <fontaine.fabrice@gmail.com> wrote:
> wchar dependency on IDN option has been added with commit
> 126a2e75f5948b30f842862906fca8ed99ffff26 because of libintl
>
> However libintl dependency has been dropped with commit
> bbcbed1829057121f9f9459f62f913626206e823 so remove unneeded wchar
> dependency
>
> Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
> ---
> package/dnsmasq/Config.in | 1 -
> 1 file changed, 1 deletion(-)
Applied to master, thanks.
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [Qemu-devel] [PATCH v2 4/4] target/mips: Fix emulation of ILVR.<B|H|W> on big endian host
From: Aleksandar Markovic @ 2019-06-20 13:45 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
In-Reply-To: <1561038349-17105-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Fix emulation of ILVR.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/msa_helper.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 458c840..7a9bfb3 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2001,6 +2001,24 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_BYTE:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->b[8] = pws->b[0];
+ pwd->b[9] = pwt->b[0];
+ pwd->b[10] = pws->b[1];
+ pwd->b[11] = pwt->b[1];
+ pwd->b[12] = pws->b[2];
+ pwd->b[13] = pwt->b[2];
+ pwd->b[14] = pws->b[3];
+ pwd->b[15] = pwt->b[3];
+ pwd->b[0] = pws->b[4];
+ pwd->b[1] = pwt->b[4];
+ pwd->b[2] = pws->b[5];
+ pwd->b[3] = pwt->b[5];
+ pwd->b[4] = pws->b[6];
+ pwd->b[5] = pwt->b[6];
+ pwd->b[6] = pws->b[7];
+ pwd->b[7] = pwt->b[7];
+#else
pwd->b[15] = pws->b[7];
pwd->b[14] = pwt->b[7];
pwd->b[13] = pws->b[6];
@@ -2017,8 +2035,19 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
pwd->b[2] = pwt->b[1];
pwd->b[1] = pws->b[0];
pwd->b[0] = pwt->b[0];
+#endif
break;
case DF_HALF:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->h[4] = pws->h[0];
+ pwd->h[5] = pwt->h[0];
+ pwd->h[6] = pws->h[1];
+ pwd->h[7] = pwt->h[1];
+ pwd->h[0] = pws->h[2];
+ pwd->h[1] = pwt->h[2];
+ pwd->h[2] = pws->h[3];
+ pwd->h[3] = pwt->h[3];
+#else
pwd->h[7] = pws->h[3];
pwd->h[6] = pwt->h[3];
pwd->h[5] = pws->h[2];
@@ -2027,12 +2056,20 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
pwd->h[2] = pwt->h[1];
pwd->h[1] = pws->h[0];
pwd->h[0] = pwt->h[0];
+#endif
break;
case DF_WORD:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->w[2] = pws->w[0];
+ pwd->w[3] = pwt->w[0];
+ pwd->w[0] = pws->w[1];
+ pwd->w[1] = pwt->w[1];
+#else
pwd->w[3] = pws->w[1];
pwd->w[2] = pwt->w[1];
pwd->w[1] = pws->w[0];
pwd->w[0] = pwt->w[0];
+#endif
break;
case DF_DOUBLE:
pwd->d[1] = pws->d[0];
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 2/2] coresight: Abort probe for missing CPU phandle
From: Suzuki K Poulose @ 2019-06-20 13:58 UTC (permalink / raw)
To: saiprakash.ranjan, mathieu.poirier, leo.yan, alexander.shishkin,
david.brown, mark.rutland
Cc: rnayak, linux-arm-msm, linux-kernel, sibis, vivek.gautam,
linux-arm-kernel
In-Reply-To: <d93e28fc80227f9a385130a766a24f8f39a1dcf0.1561037262.git.saiprakash.ranjan@codeaurora.org>
On 20/06/2019 14:45, Sai Prakash Ranjan wrote:
> Currently the coresight etm and cpu-debug drivers
> assume the affinity to CPU0 returned by coresight
> platform and continue the probe in case of missing
> CPU phandle. This is not true and leads to crash
> in some cases, so abort the probe in case of missing
> CPU phandle.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +++
> drivers/hwtracing/coresight/coresight-etm3x.c | 3 +++
> drivers/hwtracing/coresight/coresight-etm4x.c | 3 +++
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> index 07a1367c733f..43f32fa71ff9 100644
> --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
> +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> @@ -579,6 +579,9 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id)
> return -ENOMEM;
>
> drvdata->cpu = coresight_get_cpu(dev);
> + if (drvdata->cpu == -ENODEV)
> + return -ENODEV;
if (drvdata->cpu < 0)
return drvdata->cpu;
Same everywhere below ?
Also, I would like to hear Mathieu's thoughts on this change. If he's OK
with it:
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> with the change above.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/2] coresight: Abort probe for missing CPU phandle
From: Suzuki K Poulose @ 2019-06-20 13:58 UTC (permalink / raw)
To: saiprakash.ranjan, mathieu.poirier, leo.yan, alexander.shishkin,
david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm
In-Reply-To: <d93e28fc80227f9a385130a766a24f8f39a1dcf0.1561037262.git.saiprakash.ranjan@codeaurora.org>
On 20/06/2019 14:45, Sai Prakash Ranjan wrote:
> Currently the coresight etm and cpu-debug drivers
> assume the affinity to CPU0 returned by coresight
> platform and continue the probe in case of missing
> CPU phandle. This is not true and leads to crash
> in some cases, so abort the probe in case of missing
> CPU phandle.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +++
> drivers/hwtracing/coresight/coresight-etm3x.c | 3 +++
> drivers/hwtracing/coresight/coresight-etm4x.c | 3 +++
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> index 07a1367c733f..43f32fa71ff9 100644
> --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
> +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> @@ -579,6 +579,9 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id)
> return -ENOMEM;
>
> drvdata->cpu = coresight_get_cpu(dev);
> + if (drvdata->cpu == -ENODEV)
> + return -ENODEV;
if (drvdata->cpu < 0)
return drvdata->cpu;
Same everywhere below ?
Also, I would like to hear Mathieu's thoughts on this change. If he's OK
with it:
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> with the change above.
^ permalink raw reply
* [Buildroot] [git commit] package/dnsmasq: drop wchar dependency on IDN option
From: Thomas Petazzoni @ 2019-06-20 13:58 UTC (permalink / raw)
To: buildroot
commit: https://git.buildroot.net/buildroot/commit/?id=a895bd3426d3f80327600becdc40e46ae6c33a40
branch: https://git.buildroot.net/buildroot/commit/?id=refs/heads/master
wchar dependency on IDN option has been added with commit
126a2e75f5948b30f842862906fca8ed99ffff26 because of libintl
However libintl dependency has been dropped with commit
bbcbed1829057121f9f9459f62f913626206e823 so remove unneeded wchar
dependency
Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
package/dnsmasq/Config.in | 1 -
1 file changed, 1 deletion(-)
diff --git a/package/dnsmasq/Config.in b/package/dnsmasq/Config.in
index 262aca688e..cec68a9eba 100644
--- a/package/dnsmasq/Config.in
+++ b/package/dnsmasq/Config.in
@@ -29,7 +29,6 @@ config BR2_PACKAGE_DNSMASQ_DNSSEC
config BR2_PACKAGE_DNSMASQ_IDN
bool "IDN support"
- depends on BR2_USE_WCHAR
select BR2_PACKAGE_LIBIDN
help
Enable IDN support in dnsmasq.
^ permalink raw reply related
* [Bug 203923] Running a nested freedos on AMD Athlon i686-pae results in NULL pointer dereference in L0 (kvm_mmu_load)
From: bugzilla-daemon @ 2019-06-20 13:57 UTC (permalink / raw)
To: kvm
In-Reply-To: <bug-203923-28872@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=203923
--- Comment #3 from Jiri Palecek (jpalecek@web.de) ---
Good! Could you point me to the patch please?
--
You are receiving this mail because:
You are watching the assignee of the bug.
^ permalink raw reply
* Re: [PATCH 2/3] drm/i915/execlists: Minimalistic timeslicing
From: Chris Wilson @ 2019-06-20 13:57 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
In-Reply-To: <87y31w5pr7.fsf@gaia.fi.intel.com>
Quoting Mika Kuoppala (2019-06-20 14:51:24)
> > +static void
> > +defer_request(struct i915_request * const rq, struct list_head * const pl)
> > +{
> > + struct i915_dependency *p;
> > +
> > + /*
> > + * We want to move the interrupted request to the back of
> > + * the round-robin list (i.e. its priority level), but
> > + * in doing so, we must then move all requests that were in
> > + * flight and were waiting for the interrupted request to
> > + * be run after it again.
> > + */
> > + list_move_tail(&rq->sched.link, pl);
> > +
> > + list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
> > + struct i915_request *w =
> > + container_of(p->waiter, typeof(*w), sched);
> > +
> > + /* Leave semaphores spinning on the other engines */
> > + if (w->engine != rq->engine)
> > + continue;
> > +
> > + /* No waiter should start before the active request completed */
> > + GEM_BUG_ON(i915_request_started(w));
> > +
> > + GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
> > + if (rq_prio(w) < rq_prio(rq))
> > + continue;
> > +
> > + if (list_empty(&w->sched.link))
> > + continue; /* Not yet submitted; unready */
> > +
> > + /*
> > + * This should be very shallow as it is limited by the
> > + * number of requests that can fit in a ring (<64) and
>
> s/and/or ?
I think "and" works better as each context has their own ring, so it's a
multiplicative effect.
> > + * the number of contexts that can be in flight on this
> > + * engine.
> > + */
> > + defer_request(w, pl);
>
> So the stack frame will be 64*(3*8 + preample/return) at worst case?
> can be over 2k
Ok, that makes it sound scary -- but we are well within the 8k irq
limit. (Even interrupts now have 2 pages iirc, but even at 4k we are
well within bounds.)
> > @@ -906,6 +982,27 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > */
> > last->hw_context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
> > last = NULL;
> > + } else if (need_timeslice(engine, last) &&
> > + !timer_pending(&engine->execlists.timer)) {
> > + GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
> > + engine->name,
> > + last->fence.context,
> > + last->fence.seqno,
> > + last->sched.attr.priority,
> > + execlists->queue_priority_hint);
> > +
> > + ring_pause(engine) = 1;
> > + defer_active(engine);
> > +
> > + /*
> > + * Unlike for preemption, if we rewind and continue
> > + * executing the same context as previously active,
> > + * the order of execution will remain the same and
> > + * the tail will only advance. We do not need to
> > + * force a full context restore, as a lite-restore
> > + * is sufficient to resample the monotonic TAIL.
> > + */
>
> I would have asked about the force preemption without this fine comment.
>
> But this is a similar as the other kind of preemption. So what happens
> when the contexts are not the same?
It's just a normal preemption event. The old ring regs are saved and we
don't try and scribble over them. Any future use of the old context will
have the same RING_TAIL as before or later (new request) so we will
never try to program a backwards step.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [LTP] [PATCH v5 0/4] syscalls/fanotify: FAN_REPORT_FID and Directory Modification Events
From: Amir Goldstein @ 2019-06-20 13:57 UTC (permalink / raw)
To: ltp
In-Reply-To: <20190620132436.GA9804@dell5510>
On Thu, Jun 20, 2019 at 4:24 PM Petr Vorel <pvorel@suse.cz> wrote:
>
> Hi Amir, Matthew,
>
> LGTM. Just one of this commits fails on centos 6
Hi Petr,
Can you please try attached patch.
Thanks,
Amir.
-------------- next part --------------
From 7d0feb7d7d9677cf348643bddf10507d2d1f0c3a Mon Sep 17 00:00:00 2001
From: Amir Goldstein <amir73il@gmail.com>
Date: Thu, 20 Jun 2019 16:53:46 +0300
Subject: [PATCH] syscalls/fanotify: fix build errors on centos 6
Signed-off-by: Amir Goldstein <amir73il@gmail.com>
---
testcases/kernel/syscalls/fanotify/fanotify.h | 22 +++++++++++--------
.../kernel/syscalls/fanotify/fanotify13.c | 2 +-
.../kernel/syscalls/fanotify/fanotify15.c | 2 +-
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/testcases/kernel/syscalls/fanotify/fanotify.h b/testcases/kernel/syscalls/fanotify/fanotify.h
index f9803c1cc..05b4d9f2c 100644
--- a/testcases/kernel/syscalls/fanotify/fanotify.h
+++ b/testcases/kernel/syscalls/fanotify/fanotify.h
@@ -125,21 +125,25 @@ struct fanotify_event_info_header {
uint16_t len;
};
+typedef struct {
+ int val[2];
+} ltp_fsid_t;
+
struct fanotify_event_info_fid {
struct fanotify_event_info_header hdr;
- __kernel_fsid_t fsid;
+ ltp_fsid_t fsid;
unsigned char handle[0];
};
#endif
+#ifdef HAVE_NAME_TO_HANDLE_AT
/*
- * Helper function used to obtain __kernel_fsid_t and file_handle objects
- * for a given path. Used by test files correlated to FAN_REPORT_FID
- * functionality.
+ * Helper function used to obtain fsid and file_handle for a given path.
+ * Used by test files correlated to FAN_REPORT_FID functionality.
*/
-static inline void fanotify_get_fid(const char *path, __kernel_fsid_t *fsid,
- struct file_handle *handle)
+static inline void fanotify_get_fid(const char *path, ltp_fsid_t *fsid,
+ struct file_handle *handle)
{
int mount_id;
struct statfs stats;
@@ -149,7 +153,6 @@ static inline void fanotify_get_fid(const char *path, __kernel_fsid_t *fsid,
"statfs(%s, ...) failed", path);
memcpy(fsid, &stats.f_fsid, sizeof(stats.f_fsid));
-#ifdef HAVE_NAME_TO_HANDLE_AT
if (name_to_handle_at(AT_FDCWD, path, handle, &mount_id, 0) == -1) {
if (errno == EOPNOTSUPP) {
tst_brk(TCONF,
@@ -159,10 +162,11 @@ static inline void fanotify_get_fid(const char *path, __kernel_fsid_t *fsid,
tst_brk(TBROK | TERRNO,
"name_to_handle_at(AT_FDCWD, %s, ...) failed", path);
}
+}
#else
- tst_brk(TCONF, "name_to_handle_at() is not implmented");
+#define fanotify_get_fid(path, fsid, handle) \
+ tst_brk(TCONF, "System does not have required name_to_handle_at() support")
#endif /* HAVE_NAME_TO_HANDLE_AT */
-}
#define INIT_FANOTIFY_MARK_TYPE(t) \
{ FAN_MARK_ ## t, "FAN_MARK_" #t }
diff --git a/testcases/kernel/syscalls/fanotify/fanotify13.c b/testcases/kernel/syscalls/fanotify/fanotify13.c
index 8f9baacfa..f79322fd0 100644
--- a/testcases/kernel/syscalls/fanotify/fanotify13.c
+++ b/testcases/kernel/syscalls/fanotify/fanotify13.c
@@ -40,7 +40,7 @@
struct event_t {
unsigned long long expected_mask;
- __kernel_fsid_t fsid;
+ ltp_fsid_t fsid;
struct file_handle handle;
char buf[MAX_HANDLE_SZ];
};
diff --git a/testcases/kernel/syscalls/fanotify/fanotify15.c b/testcases/kernel/syscalls/fanotify/fanotify15.c
index 6981b7891..3be913ba4 100644
--- a/testcases/kernel/syscalls/fanotify/fanotify15.c
+++ b/testcases/kernel/syscalls/fanotify/fanotify15.c
@@ -37,7 +37,7 @@
struct event_t {
unsigned long long mask;
- __kernel_fsid_t fsid;
+ ltp_fsid_t fsid;
struct file_handle handle;
char buf[MAX_HANDLE_SZ];
};
--
2.17.1
^ permalink raw reply related
* [Qemu-devel] [PATCH v2 3/4] target/mips: Fix emulation of ILVL.<B|H|W> on big endian host
From: Aleksandar Markovic @ 2019-06-20 13:45 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
In-Reply-To: <1561038349-17105-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Fix emulation of ILVL.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/msa_helper.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 9f411c1..458c840 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1913,6 +1913,24 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_BYTE:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->b[7] = pwt->b[15];
+ pwd->b[6] = pws->b[15];
+ pwd->b[5] = pwt->b[14];
+ pwd->b[4] = pws->b[14];
+ pwd->b[3] = pwt->b[13];
+ pwd->b[2] = pws->b[13];
+ pwd->b[1] = pwt->b[12];
+ pwd->b[0] = pws->b[12];
+ pwd->b[15] = pwt->b[11];
+ pwd->b[14] = pws->b[11];
+ pwd->b[13] = pwt->b[10];
+ pwd->b[12] = pws->b[10];
+ pwd->b[11] = pwt->b[9];
+ pwd->b[10] = pws->b[9];
+ pwd->b[9] = pwt->b[8];
+ pwd->b[8] = pws->b[8];
+#else
pwd->b[0] = pwt->b[8];
pwd->b[1] = pws->b[8];
pwd->b[2] = pwt->b[9];
@@ -1929,8 +1947,19 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
pwd->b[13] = pws->b[14];
pwd->b[14] = pwt->b[15];
pwd->b[15] = pws->b[15];
+#endif
break;
case DF_HALF:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->h[3] = pwt->h[7];
+ pwd->h[2] = pws->h[7];
+ pwd->h[1] = pwt->h[6];
+ pwd->h[0] = pws->h[6];
+ pwd->h[7] = pwt->h[5];
+ pwd->h[6] = pws->h[5];
+ pwd->h[5] = pwt->h[4];
+ pwd->h[4] = pws->h[4];
+#else
pwd->h[0] = pwt->h[4];
pwd->h[1] = pws->h[4];
pwd->h[2] = pwt->h[5];
@@ -1939,12 +1968,20 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
pwd->h[5] = pws->h[6];
pwd->h[6] = pwt->h[7];
pwd->h[7] = pws->h[7];
+#endif
break;
case DF_WORD:
+#if defined(TARGET_WORDS_BIGENDIAN)
+ pwd->w[1] = pwt->w[3];
+ pwd->w[0] = pws->w[3];
+ pwd->w[3] = pwt->w[2];
+ pwd->w[2] = pws->w[2];
+#else
pwd->w[0] = pwt->w[2];
pwd->w[1] = pws->w[2];
pwd->w[2] = pwt->w[3];
pwd->w[3] = pws->w[3];
+#endif
break;
case DF_DOUBLE:
pwd->d[0] = pwt->d[1];
--
2.7.4
^ permalink raw reply related
* [Buildroot] [PATCH v2 2/2] configs/qemu_riscv32_virt: Update to 5.1 kernel
From: Thomas Petazzoni @ 2019-06-20 13:57 UTC (permalink / raw)
To: buildroot
In-Reply-To: <20190619165406.19615-2-alistair.francis@wdc.com>
On Wed, 19 Jun 2019 09:54:06 -0700
Alistair Francis <alistair.francis@wdc.com> wrote:
> # Kernel
> BR2_LINUX_KERNEL=y
> BR2_LINUX_KERNEL_CUSTOM_VERSION=y
> -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.20.17"
> -BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
> -BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="board/qemu/riscv32-virt/linux.config.fragment"
> +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.1.12"
> +BR2_LINUX_KERNEL_DEFCONFIG="rv32"
> +BR2_LINUX_KERNEL_PATCH="board/qemu/riscv32-virt/0001-Revert-riscv-Use-latest-system-call-ABI.patch"
We prefer using the BR2_GLOBAL_PATCH_DIR mechanism nowadays, so I've
adjusted your patch to use that and applied. Thanks!
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [Qemu-devel] [PATCH v4 3/4] target/mips: Fix some space checkpatch errors in translate.c
From: Aleksandar Markovic @ 2019-06-20 13:33 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
In-Reply-To: <1561037595-14413-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Remove some space-related checkpatch warning.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/mips/translate.c | 240 ++++++++++++++++++++++++------------------------
1 file changed, 122 insertions(+), 118 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3cf976..54e0160 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2617,7 +2617,7 @@ static const char * const mxuregnames[] = {
} while (0)
/* General purpose registers moves. */
-static inline void gen_load_gpr (TCGv t, int reg)
+static inline void gen_load_gpr(TCGv t, int reg)
{
if (reg == 0)
tcg_gen_movi_tl(t, 0);
@@ -2625,14 +2625,14 @@ static inline void gen_load_gpr (TCGv t, int reg)
tcg_gen_mov_tl(t, cpu_gpr[reg]);
}
-static inline void gen_store_gpr (TCGv t, int reg)
+static inline void gen_store_gpr(TCGv t, int reg)
{
if (reg != 0)
tcg_gen_mov_tl(cpu_gpr[reg], t);
}
/* Moves to/from shadow registers. */
-static inline void gen_load_srsgpr (int from, int to)
+static inline void gen_load_srsgpr(int from, int to)
{
TCGv t0 = tcg_temp_new();
@@ -2839,7 +2839,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static inline int get_fp_bit (int cc)
+static inline int get_fp_bit(int cc)
{
if (cc)
return 24 + cc;
@@ -2848,7 +2848,8 @@ static inline int get_fp_bit (int cc)
}
/* Addresses computation */
-static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
+static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,
+ TCGv arg1)
{
tcg_gen_add_tl(ret, arg0, arg1);
@@ -3328,8 +3329,8 @@ OP_LD_ATOMIC(lld,ld64);
#endif
#undef OP_LD_ATOMIC
-static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
- int base, int offset)
+static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
+ int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
@@ -3341,7 +3342,7 @@ static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
}
}
-static target_ulong pc_relative_pc (DisasContext *ctx)
+static target_ulong pc_relative_pc(DisasContext *ctx)
{
target_ulong pc = ctx->base.pc_next;
@@ -3578,8 +3579,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
}
/* Store */
-static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
- int base, int offset)
+static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
+ int base, int offset)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -3717,8 +3718,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
}
/* Load and store */
-static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
- TCGv t0)
+static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
+ TCGv t0)
{
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
@@ -5132,8 +5133,8 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
-static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
+static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -5196,8 +5197,8 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
-static void gen_cl (DisasContext *ctx, uint32_t opc,
- int rd, int rs)
+static void gen_cl(DisasContext *ctx, uint32_t opc,
+ int rd, int rs)
{
TCGv t0;
@@ -6188,8 +6189,8 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
/* special3 bitfield operations */
-static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
- int rs, int lsb, int msb)
+static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
+ int rs, int lsb, int msb)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -6259,7 +6260,7 @@ fail:
tcg_temp_free(t1);
}
-static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
+static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
{
TCGv t0;
@@ -6502,7 +6503,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
tcg_temp_free_i64(t0);
}
-static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
+static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -6511,13 +6512,13 @@ static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
tcg_temp_free_i32(t0);
}
-static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
+static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
{
tcg_gen_ld_tl(arg, cpu_env, off);
tcg_gen_ext32s_tl(arg, arg);
}
-static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
+static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -10077,7 +10078,8 @@ die:
generate_exception_end(ctx, EXCP_RI);
}
-static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
+static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
+ int rt, int rd)
{
const char *opn = "ldst";
@@ -10465,22 +10467,22 @@ enum fopcode {
OPC_CVT_W_S = FOP(36, FMT_S),
OPC_CVT_L_S = FOP(37, FMT_S),
OPC_CVT_PS_S = FOP(38, FMT_S),
- OPC_CMP_F_S = FOP (48, FMT_S),
- OPC_CMP_UN_S = FOP (49, FMT_S),
- OPC_CMP_EQ_S = FOP (50, FMT_S),
- OPC_CMP_UEQ_S = FOP (51, FMT_S),
- OPC_CMP_OLT_S = FOP (52, FMT_S),
- OPC_CMP_ULT_S = FOP (53, FMT_S),
- OPC_CMP_OLE_S = FOP (54, FMT_S),
- OPC_CMP_ULE_S = FOP (55, FMT_S),
- OPC_CMP_SF_S = FOP (56, FMT_S),
- OPC_CMP_NGLE_S = FOP (57, FMT_S),
- OPC_CMP_SEQ_S = FOP (58, FMT_S),
- OPC_CMP_NGL_S = FOP (59, FMT_S),
- OPC_CMP_LT_S = FOP (60, FMT_S),
- OPC_CMP_NGE_S = FOP (61, FMT_S),
- OPC_CMP_LE_S = FOP (62, FMT_S),
- OPC_CMP_NGT_S = FOP (63, FMT_S),
+ OPC_CMP_F_S = FOP(48, FMT_S),
+ OPC_CMP_UN_S = FOP(49, FMT_S),
+ OPC_CMP_EQ_S = FOP(50, FMT_S),
+ OPC_CMP_UEQ_S = FOP(51, FMT_S),
+ OPC_CMP_OLT_S = FOP(52, FMT_S),
+ OPC_CMP_ULT_S = FOP(53, FMT_S),
+ OPC_CMP_OLE_S = FOP(54, FMT_S),
+ OPC_CMP_ULE_S = FOP(55, FMT_S),
+ OPC_CMP_SF_S = FOP(56, FMT_S),
+ OPC_CMP_NGLE_S = FOP(57, FMT_S),
+ OPC_CMP_SEQ_S = FOP(58, FMT_S),
+ OPC_CMP_NGL_S = FOP(59, FMT_S),
+ OPC_CMP_LT_S = FOP(60, FMT_S),
+ OPC_CMP_NGE_S = FOP(61, FMT_S),
+ OPC_CMP_LE_S = FOP(62, FMT_S),
+ OPC_CMP_NGT_S = FOP(63, FMT_S),
OPC_ADD_D = FOP(0, FMT_D),
OPC_SUB_D = FOP(1, FMT_D),
@@ -10521,22 +10523,22 @@ enum fopcode {
OPC_CVT_S_D = FOP(32, FMT_D),
OPC_CVT_W_D = FOP(36, FMT_D),
OPC_CVT_L_D = FOP(37, FMT_D),
- OPC_CMP_F_D = FOP (48, FMT_D),
- OPC_CMP_UN_D = FOP (49, FMT_D),
- OPC_CMP_EQ_D = FOP (50, FMT_D),
- OPC_CMP_UEQ_D = FOP (51, FMT_D),
- OPC_CMP_OLT_D = FOP (52, FMT_D),
- OPC_CMP_ULT_D = FOP (53, FMT_D),
- OPC_CMP_OLE_D = FOP (54, FMT_D),
- OPC_CMP_ULE_D = FOP (55, FMT_D),
- OPC_CMP_SF_D = FOP (56, FMT_D),
- OPC_CMP_NGLE_D = FOP (57, FMT_D),
- OPC_CMP_SEQ_D = FOP (58, FMT_D),
- OPC_CMP_NGL_D = FOP (59, FMT_D),
- OPC_CMP_LT_D = FOP (60, FMT_D),
- OPC_CMP_NGE_D = FOP (61, FMT_D),
- OPC_CMP_LE_D = FOP (62, FMT_D),
- OPC_CMP_NGT_D = FOP (63, FMT_D),
+ OPC_CMP_F_D = FOP(48, FMT_D),
+ OPC_CMP_UN_D = FOP(49, FMT_D),
+ OPC_CMP_EQ_D = FOP(50, FMT_D),
+ OPC_CMP_UEQ_D = FOP(51, FMT_D),
+ OPC_CMP_OLT_D = FOP(52, FMT_D),
+ OPC_CMP_ULT_D = FOP(53, FMT_D),
+ OPC_CMP_OLE_D = FOP(54, FMT_D),
+ OPC_CMP_ULE_D = FOP(55, FMT_D),
+ OPC_CMP_SF_D = FOP(56, FMT_D),
+ OPC_CMP_NGLE_D = FOP(57, FMT_D),
+ OPC_CMP_SEQ_D = FOP(58, FMT_D),
+ OPC_CMP_NGL_D = FOP(59, FMT_D),
+ OPC_CMP_LT_D = FOP(60, FMT_D),
+ OPC_CMP_NGE_D = FOP(61, FMT_D),
+ OPC_CMP_LE_D = FOP(62, FMT_D),
+ OPC_CMP_NGT_D = FOP(63, FMT_D),
OPC_CVT_S_W = FOP(32, FMT_W),
OPC_CVT_D_W = FOP(33, FMT_W),
@@ -10568,22 +10570,22 @@ enum fopcode {
OPC_PLU_PS = FOP(45, FMT_PS),
OPC_PUL_PS = FOP(46, FMT_PS),
OPC_PUU_PS = FOP(47, FMT_PS),
- OPC_CMP_F_PS = FOP (48, FMT_PS),
- OPC_CMP_UN_PS = FOP (49, FMT_PS),
- OPC_CMP_EQ_PS = FOP (50, FMT_PS),
- OPC_CMP_UEQ_PS = FOP (51, FMT_PS),
- OPC_CMP_OLT_PS = FOP (52, FMT_PS),
- OPC_CMP_ULT_PS = FOP (53, FMT_PS),
- OPC_CMP_OLE_PS = FOP (54, FMT_PS),
- OPC_CMP_ULE_PS = FOP (55, FMT_PS),
- OPC_CMP_SF_PS = FOP (56, FMT_PS),
- OPC_CMP_NGLE_PS = FOP (57, FMT_PS),
- OPC_CMP_SEQ_PS = FOP (58, FMT_PS),
- OPC_CMP_NGL_PS = FOP (59, FMT_PS),
- OPC_CMP_LT_PS = FOP (60, FMT_PS),
- OPC_CMP_NGE_PS = FOP (61, FMT_PS),
- OPC_CMP_LE_PS = FOP (62, FMT_PS),
- OPC_CMP_NGT_PS = FOP (63, FMT_PS),
+ OPC_CMP_F_PS = FOP(48, FMT_PS),
+ OPC_CMP_UN_PS = FOP(49, FMT_PS),
+ OPC_CMP_EQ_PS = FOP(50, FMT_PS),
+ OPC_CMP_UEQ_PS = FOP(51, FMT_PS),
+ OPC_CMP_OLT_PS = FOP(52, FMT_PS),
+ OPC_CMP_ULT_PS = FOP(53, FMT_PS),
+ OPC_CMP_OLE_PS = FOP(54, FMT_PS),
+ OPC_CMP_ULE_PS = FOP(55, FMT_PS),
+ OPC_CMP_SF_PS = FOP(56, FMT_PS),
+ OPC_CMP_NGLE_PS = FOP(57, FMT_PS),
+ OPC_CMP_SEQ_PS = FOP(58, FMT_PS),
+ OPC_CMP_NGL_PS = FOP(59, FMT_PS),
+ OPC_CMP_LT_PS = FOP(60, FMT_PS),
+ OPC_CMP_NGE_PS = FOP(61, FMT_PS),
+ OPC_CMP_LE_PS = FOP(62, FMT_PS),
+ OPC_CMP_NGT_PS = FOP(63, FMT_PS),
};
enum r6_f_cmp_op {
@@ -10633,7 +10635,8 @@ enum r6_f_cmp_op {
R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
};
-static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
+
+static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
{
TCGv t0 = tcg_temp_new();
@@ -10714,7 +10717,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
tcg_temp_free(t0);
}
-static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
+static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
{
TCGLabel *l1;
TCGCond cond;
@@ -10763,7 +10766,8 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
tcg_temp_free_i32(t0);
}
-static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
+static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
+ int tf)
{
int cond;
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -10886,8 +10890,8 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
tcg_temp_free_i64(t1);
}
-static void gen_farith (DisasContext *ctx, enum fopcode op1,
- int ft, int fs, int fd, int cc)
+static void gen_farith(DisasContext *ctx, enum fopcode op1,
+ int ft, int fs, int fd, int cc)
{
uint32_t func = ctx->opcode & 0x3f;
switch (op1) {
@@ -12314,8 +12318,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
}
/* Coprocessor 3 (FPU) */
-static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
- int fd, int fs, int base, int index)
+static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
+ int fd, int fs, int base, int index)
{
TCGv t0 = tcg_temp_new();
@@ -12394,8 +12398,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
-static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
- int fd, int fr, int fs, int ft)
+static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
+ int fd, int fr, int fs, int ft)
{
switch (opc) {
case OPC_ALNV_PS:
@@ -13157,17 +13161,17 @@ enum {
RR_RY_CNVT_SEW = 0x6,
};
-static int xlat (int r)
+static int xlat(int r)
{
static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
return map[r];
}
-static void gen_mips16_save (DisasContext *ctx,
- int xsregs, int aregs,
- int do_ra, int do_s0, int do_s1,
- int framesize)
+static void gen_mips16_save(DisasContext *ctx,
+ int xsregs, int aregs,
+ int do_ra, int do_s0, int do_s1,
+ int framesize)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -13322,10 +13326,10 @@ static void gen_mips16_save (DisasContext *ctx,
tcg_temp_free(t2);
}
-static void gen_mips16_restore (DisasContext *ctx,
- int xsregs, int aregs,
- int do_ra, int do_s0, int do_s1,
- int framesize)
+static void gen_mips16_restore(DisasContext *ctx,
+ int xsregs, int aregs,
+ int do_ra, int do_s0, int do_s1,
+ int framesize)
{
int astatic;
TCGv t0 = tcg_temp_new();
@@ -13428,8 +13432,8 @@ static void gen_mips16_restore (DisasContext *ctx,
tcg_temp_free(t2);
}
-static void gen_addiupc (DisasContext *ctx, int rx, int imm,
- int is_64_bit, int extended)
+static void gen_addiupc(DisasContext *ctx, int rx, int imm,
+ int is_64_bit, int extended)
{
TCGv t0;
@@ -13459,9 +13463,9 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
}
#if defined(TARGET_MIPS64)
-static void decode_i64_mips16 (DisasContext *ctx,
- int ry, int funct, int16_t offset,
- int extended)
+static void decode_i64_mips16(DisasContext *ctx,
+ int ry, int funct, int16_t offset,
+ int extended)
{
switch (funct) {
case I64_LDSP:
@@ -13520,7 +13524,7 @@ static void decode_i64_mips16 (DisasContext *ctx,
}
#endif
-static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
+static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
{
int extend = cpu_lduw_code(env, ctx->base.pc_next + 2);
int op, rx, ry, funct, sa;
@@ -13734,7 +13738,7 @@ static inline void gen_helper_do_semihosting(void *env)
}
#endif
-static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
+static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
{
int rx, ry;
int sa;
@@ -13957,7 +13961,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
case M16_OPC_LWPC:
gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
break;
-#if defined (TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case M16_OPC_LWU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
@@ -14061,7 +14065,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
case RR_SRAV:
gen_shift(ctx, OPC_SRAV, ry, rx, ry);
break;
-#if defined (TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case RR_DSRL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
@@ -14124,7 +14128,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
case RR_MFLO:
gen_HILO(ctx, OPC_MFLO, 0, rx);
break;
-#if defined (TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case RR_DSRA:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
@@ -14158,7 +14162,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
case RR_DIVU:
gen_muldiv(ctx, OPC_DIVU, 0, rx, ry);
break;
-#if defined (TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case RR_DMULT:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
@@ -14802,7 +14806,7 @@ enum {
ADDIUR1SP = 0x1
};
-static int mmreg (int r)
+static int mmreg(int r)
{
static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
@@ -14810,7 +14814,7 @@ static int mmreg (int r)
}
/* Used for 16-bit store instructions. */
-static int mmreg2 (int r)
+static int mmreg2(int r)
{
static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
@@ -14885,8 +14889,8 @@ static void gen_andi16(DisasContext *ctx)
gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]);
}
-static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
- int base, int16_t offset)
+static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
+ int base, int16_t offset)
{
TCGv t0, t1;
TCGv_i32 t2;
@@ -15159,7 +15163,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
}
}
-static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
+static void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -15179,8 +15183,8 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
tcg_temp_free(t1);
}
-static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
- int base, int16_t offset)
+static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
+ int base, int16_t offset)
{
TCGv t0, t1;
@@ -15205,14 +15209,14 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
- gen_store_gpr(t1, rd+1);
+ gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- gen_load_gpr(t1, rd+1);
+ gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
break;
#ifdef TARGET_MIPS64
@@ -15226,14 +15230,14 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
- gen_store_gpr(t1, rd+1);
+ gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- gen_load_gpr(t1, rd+1);
+ gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
break;
#endif
@@ -15270,7 +15274,7 @@ static void gen_sync(int stype)
tcg_gen_mb(tcg_mo);
}
-static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
+static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
{
int extension = (ctx->opcode >> 6) & 0x3f;
int minor = (ctx->opcode >> 12) & 0xf;
@@ -17234,7 +17238,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
+static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
@@ -27881,11 +27885,11 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
eval_big = 0x8000000000000000ULL;
break;
}
- tcg_gen_subi_i64(t0, msa_wr_d[wt<<1], eval_zero_or_big);
- tcg_gen_andc_i64(t0, t0, msa_wr_d[wt<<1]);
+ tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
+ tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
tcg_gen_andi_i64(t0, t0, eval_big);
- tcg_gen_subi_i64(t1, msa_wr_d[(wt<<1)+1], eval_zero_or_big);
- tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt<<1)+1]);
+ tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big);
+ tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]);
tcg_gen_andi_i64(t1, t1, eval_big);
tcg_gen_or_i64(t0, t0, t1);
/* if all bits are zero then all elements are not zero */
@@ -27913,7 +27917,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
case OPC_BNZ_V:
{
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_or_i64(t0, msa_wr_d[wt<<1], msa_wr_d[(wt<<1)+1]);
+ tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
--
2.7.4
^ permalink raw reply related
* Re: linux-next: build failure after merge of the netfilter-next tree
From: Pablo Neira Ayuso @ 2019-06-20 13:57 UTC (permalink / raw)
To: Stephen Rothwell
Cc: NetFilter, Linux Next Mailing List, Linux Kernel Mailing List,
Fernando Fernandez Mancera
In-Reply-To: <20190620234743.42e9d3e8@canb.auug.org.au>
On Thu, Jun 20, 2019 at 11:47:43PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the netfilter-next tree, today's linux-next build
> (arm imx_v4_v5_defconfig and several others) failed like this:
>
> In file included from net/netfilter/core.c:19:0:
> include/linux/netfilter_ipv6.h: In function 'nf_ipv6_cookie_init_sequence':
> include/linux/netfilter_ipv6.h:174:2: error: implicit declaration of function '__cookie_v6_init_sequence' [-Werror=implicit-function-declaration]
> include/linux/netfilter_ipv6.h: In function 'nf_cookie_v6_check':
> include/linux/netfilter_ipv6.h:189:2: error: implicit declaration of function '__cookie_v6_check' [-Werror=implicit-function-declaration]
>
> Caused by commit
>
> 3006a5224f15 ("netfilter: synproxy: remove module dependency on IPv6 SYNPROXY")
>
> This has been happening for a few days, sorry.
>
> # CONFIG_IPV6 is not set
https://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next.git/commit/?id=8527fa6cc68a489f735823e61b31ec6cb266274a
^ permalink raw reply
* Re: [PATCH 4/4] gtk-icon-cache.bbclass: Depends on gtk+3
From: Burton, Ross @ 2019-06-20 13:56 UTC (permalink / raw)
To: Robert Yang; +Cc: OE-core
In-Reply-To: <3b30ab5eae1506d44fc9c95543d7ae833018c087.camel@linuxfoundation.org>
Why DEPENDS on gtk? The recipes will typically already do this, but
all this class needs is the rdepends. Also, there's no explanation
for the hicolor addition.
Ross
On Thu, 20 Jun 2019 at 14:54, Richard Purdie
<richard.purdie@linuxfoundation.org> wrote:
>
> On Thu, 2019-06-20 at 17:58 +0800, Robert Yang wrote:
> >
> > On 6/20/19 5:19 PM, Adrian Bunk wrote:
> > > On Thu, Jun 20, 2019 at 04:46:16PM +0800, Robert Yang wrote:
> > > > ...
> > > > Maybe gtk+2 is out of date? Since gtk+4 is on the way, so I think
> > > > that we
> > > > need something like virtual/gtk to fix these problems totally?
> > >
> > > GTK+2 is mostly obsolete.
> > >
> > > I just checked the GTK4 sources, and there it is renamed to
> > > gtk4-update-icon-cache. Based on that I would say that your
> > > patch is actually fine at least for now.
> >
> > Thanks, I updated the commit message in the PULL:
>
> Please resend patches rather than updating the branch as they get lost
> really easily and also don't get reviewed properly this way.
>
> Cheers,
>
> Richard
>
> --
> _______________________________________________
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.openembedded.org/mailman/listinfo/openembedded-core
^ permalink raw reply
* Re: Re: [PATCH] backlight: gpio-backlight: Set power state instead of brightness at probe
From: Daniel Thompson @ 2019-06-20 13:56 UTC (permalink / raw)
To: Paul Kocialkowski, dri-devel, linux-fbdev, linux-kernel
Cc: Lee Jones, Jingoo Han, Bartlomiej Zolnierkiewicz,
Thomas Petazzoni, Laurent Pinchart, Peter Ujfalusi
In-Reply-To: <bee40295b2c6b489468d4e1fc12d7a1ac122cb9b.camel@bootlin.com>
On 18/06/2019 13:58, Paul Kocialkowski wrote:
> Hi,
>
> On Fri, 2019-05-17 at 17:05 +0200, Paul Kocialkowski wrote:
>> On a trivial gpio-backlight setup with a panel using the backlight but
>> no boot software to enable it beforehand, we fall in a case where the
>> backlight is disabled (not just blanked) and thus remains disabled when
>> the panel gets enabled.
>>
>> Setting gbl->def_value via the device-tree prop allows enabling the
>> backlight in this situation, but it will be unblanked straight away,
>> in compliance with the binding. This does not work well when there was no
>> boot software to display something before, since we really need to unblank
>> by the time the panel is enabled, not before.
>>
>> Resolve the situation by setting the brightness to 1 at probe and
>> managing the power state accordingly, a bit like it's done in
>> pwm-backlight.
>
> Any feedback on this? I was under the impression that it could be quite
> controversial, as it implies that the backlight can no longer be
> enabled without a bound panel (which IMO makes good sense but could be
> a matter to debate).
My apologies. This patch brought on such severe deja-vu I got rather
confused. Then when I went digging I've also dropped the ball on the
same feature previously.
Peter Ujfalusi provided a similar patch to yours but with a slightly
different implementation:
https://lore.kernel.org/patchwork/patch/1002359/
On the whole I think it is important to read the GPIO pin since
otherwise we swap problems when there bootloader does setup the
backlight for problems where it does not.
The thing I don't get is why both patches try to avoid setting the
backlight brightness from def_value. Simple displays, especially
monochrome ones are perfectly readable with the backlight off... zero
brightness is not a "bad" value.
Not sure if Peter is still willing to rev his version of this code
(given how badly we neglected him previously) or whether you want to try
and combine both ideas.
Daniel.
>
> Cheers,
>
> Paul
>
>> Fixes: 8b770e3c9824 ("backlight: Add GPIO-based backlight driver")
>> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
>> ---
>> drivers/video/backlight/gpio_backlight.c | 19 ++++++++++++++++++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c
>> index e470da95d806..c9cb97fa13d0 100644
>> --- a/drivers/video/backlight/gpio_backlight.c
>> +++ b/drivers/video/backlight/gpio_backlight.c
>> @@ -57,6 +57,21 @@ static const struct backlight_ops gpio_backlight_ops = {
>> .check_fb = gpio_backlight_check_fb,
>> };
>>
>> +static int gpio_backlight_initial_power_state(struct gpio_backlight *gbl)
>> +{
>> + struct device_node *node = gbl->dev->of_node;
>> +
>> + /* If we absolutely want the backlight enabled at boot. */
>> + if (gbl->def_value)
>> + return FB_BLANK_UNBLANK;
>> +
>> + /* If there's no panel to unblank the backlight later. */
>> + if (!node || !node->phandle)
>> + return FB_BLANK_UNBLANK;
>> +
>> + return FB_BLANK_POWERDOWN;
>> +}
>> +
>> static int gpio_backlight_probe_dt(struct platform_device *pdev,
>> struct gpio_backlight *gbl)
>> {
>> @@ -142,7 +157,9 @@ static int gpio_backlight_probe(struct platform_device *pdev)
>> return PTR_ERR(bl);
>> }
>>
>> - bl->props.brightness = gbl->def_value;
>> + bl->props.brightness = 1;
>> + bl->props.power = gpio_backlight_initial_power_state(gbl);
>> +
>> backlight_update_status(bl);
>>
>> platform_set_drvdata(pdev, bl);
^ permalink raw reply
* Re: Re: [PATCH] backlight: gpio-backlight: Set power state instead of brightness at probe
From: Daniel Thompson @ 2019-06-20 13:56 UTC (permalink / raw)
To: Paul Kocialkowski, dri-devel, linux-fbdev, linux-kernel
Cc: Lee Jones, Jingoo Han, Bartlomiej Zolnierkiewicz,
Thomas Petazzoni, Laurent Pinchart, Peter Ujfalusi
In-Reply-To: <bee40295b2c6b489468d4e1fc12d7a1ac122cb9b.camel@bootlin.com>
On 18/06/2019 13:58, Paul Kocialkowski wrote:
> Hi,
>
> On Fri, 2019-05-17 at 17:05 +0200, Paul Kocialkowski wrote:
>> On a trivial gpio-backlight setup with a panel using the backlight but
>> no boot software to enable it beforehand, we fall in a case where the
>> backlight is disabled (not just blanked) and thus remains disabled when
>> the panel gets enabled.
>>
>> Setting gbl->def_value via the device-tree prop allows enabling the
>> backlight in this situation, but it will be unblanked straight away,
>> in compliance with the binding. This does not work well when there was no
>> boot software to display something before, since we really need to unblank
>> by the time the panel is enabled, not before.
>>
>> Resolve the situation by setting the brightness to 1 at probe and
>> managing the power state accordingly, a bit like it's done in
>> pwm-backlight.
>
> Any feedback on this? I was under the impression that it could be quite
> controversial, as it implies that the backlight can no longer be
> enabled without a bound panel (which IMO makes good sense but could be
> a matter to debate).
My apologies. This patch brought on such severe deja-vu I got rather
confused. Then when I went digging I've also dropped the ball on the
same feature previously.
Peter Ujfalusi provided a similar patch to yours but with a slightly
different implementation:
https://lore.kernel.org/patchwork/patch/1002359/
On the whole I think it is important to read the GPIO pin since
otherwise we swap problems when there bootloader does setup the
backlight for problems where it does not.
The thing I don't get is why both patches try to avoid setting the
backlight brightness from def_value. Simple displays, especially
monochrome ones are perfectly readable with the backlight off... zero
brightness is not a "bad" value.
Not sure if Peter is still willing to rev his version of this code
(given how badly we neglected him previously) or whether you want to try
and combine both ideas.
Daniel.
>
> Cheers,
>
> Paul
>
>> Fixes: 8b770e3c9824 ("backlight: Add GPIO-based backlight driver")
>> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
>> ---
>> drivers/video/backlight/gpio_backlight.c | 19 ++++++++++++++++++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c
>> index e470da95d806..c9cb97fa13d0 100644
>> --- a/drivers/video/backlight/gpio_backlight.c
>> +++ b/drivers/video/backlight/gpio_backlight.c
>> @@ -57,6 +57,21 @@ static const struct backlight_ops gpio_backlight_ops = {
>> .check_fb = gpio_backlight_check_fb,
>> };
>>
>> +static int gpio_backlight_initial_power_state(struct gpio_backlight *gbl)
>> +{
>> + struct device_node *node = gbl->dev->of_node;
>> +
>> + /* If we absolutely want the backlight enabled at boot. */
>> + if (gbl->def_value)
>> + return FB_BLANK_UNBLANK;
>> +
>> + /* If there's no panel to unblank the backlight later. */
>> + if (!node || !node->phandle)
>> + return FB_BLANK_UNBLANK;
>> +
>> + return FB_BLANK_POWERDOWN;
>> +}
>> +
>> static int gpio_backlight_probe_dt(struct platform_device *pdev,
>> struct gpio_backlight *gbl)
>> {
>> @@ -142,7 +157,9 @@ static int gpio_backlight_probe(struct platform_device *pdev)
>> return PTR_ERR(bl);
>> }
>>
>> - bl->props.brightness = gbl->def_value;
>> + bl->props.brightness = 1;
>> + bl->props.power = gpio_backlight_initial_power_state(gbl);
>> +
>> backlight_update_status(bl);
>>
>> platform_set_drvdata(pdev, bl);
^ permalink raw reply
* [Qemu-devel] [PATCH v4 4/4] target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c
From: Aleksandar Markovic @ 2019-06-20 13:33 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
In-Reply-To: <1561037595-14413-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Remove if-else-switch-case-arms-related checkpatch errors.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/mips/translate.c | 205 +++++++++++++++++++++++++++++++-----------------
1 file changed, 133 insertions(+), 72 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 54e0160..e3a0f08 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] = {
/* General purpose registers moves. */
static inline void gen_load_gpr(TCGv t, int reg)
{
- if (reg == 0)
+ if (reg == 0) {
tcg_gen_movi_tl(t, 0);
- else
+ } else {
tcg_gen_mov_tl(t, cpu_gpr[reg]);
+ }
}
static inline void gen_store_gpr(TCGv t, int reg)
{
- if (reg != 0)
+ if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
+ }
}
/* Moves to/from shadow registers. */
@@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to)
{
TCGv t0 = tcg_temp_new();
- if (from == 0)
+ if (from == 0) {
tcg_gen_movi_tl(t0, 0);
- else {
+ } else {
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
@@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
static inline int get_fp_bit(int cc)
{
- if (cc)
+ if (cc) {
return 24 + cc;
- else
+ } else {
return 23;
+ }
}
/* Addresses computation */
@@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
static inline void check_cp0_enabled(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
generate_exception_err(ctx, EXCP_CpU, 0);
+ }
}
static inline void check_cp1_enabled(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
+ }
}
/* Verify that the processor is running with COP1X instructions enabled.
@@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ctx)
static inline void check_cop1x(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
generate_exception_end(ctx, EXCP_RI);
+ }
}
/* Verify that the processor is running with 64-bit floating-point
@@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx)
static inline void check_cp1_64bitmode(DisasContext *ctx)
{
- if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
+ if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
generate_exception_end(ctx, EXCP_RI);
+ }
}
/*
@@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
*/
static inline void check_cp1_registers(DisasContext *ctx, int regs)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
generate_exception_end(ctx, EXCP_RI);
+ }
}
/* Verify that the processor is running with DSP instructions enabled.
@@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx)
instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
+ }
}
#endif
@@ -3126,13 +3135,12 @@ static inline void check_nms(DisasContext *ctx)
*/
static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
{
- if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
- !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
- !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
- !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
- !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
- !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
- {
+ if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
+ !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
+ !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
+ !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
+ !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
+ !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
generate_exception_end(ctx, EXCP_RI);
}
}
@@ -3180,23 +3188,56 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
gen_ldcmp_fpr##bits (ctx, fp0, fs); \
gen_ldcmp_fpr##bits (ctx, fp1, ft); \
switch (n) { \
- case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
- case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
- case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
- case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
- case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
- case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
- case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
- case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
- case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
- case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
- case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
- case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
- case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
- case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
- case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
- case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
- default: abort(); \
+ case 0: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
+ break; \
+ case 1: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
+ break; \
+ case 2: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
+ break; \
+ case 3: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
+ break; \
+ case 4: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
+ break; \
+ case 5: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
+ break; \
+ case 6: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
+ break; \
+ case 7: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
+ break; \
+ case 8: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
+ break; \
+ case 9: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
+ break; \
+ case 10: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
+ break; \
+ case 11: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
+ break; \
+ case 12: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
+ break; \
+ case 13: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
+ break; \
+ case 14: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
+ break; \
+ case 15: \
+ gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
+ break; \
+ default: \
+ abort(); \
} \
tcg_temp_free_i##bits (fp0); \
tcg_temp_free_i##bits (fp1); \
@@ -3882,22 +3923,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
uimm = (uint16_t)imm;
switch (opc) {
case OPC_ANDI:
- if (likely(rs != 0))
+ if (likely(rs != 0)) {
tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
- else
+ } else {
tcg_gen_movi_tl(cpu_gpr[rt], 0);
+ }
break;
case OPC_ORI:
- if (rs != 0)
+ if (rs != 0) {
tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
- else
+ } else {
tcg_gen_movi_tl(cpu_gpr[rt], uimm);
+ }
break;
case OPC_XORI:
- if (likely(rs != 0))
+ if (likely(rs != 0)) {
tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
- else
+ } else {
tcg_gen_movi_tl(cpu_gpr[rt], uimm);
+ }
break;
case OPC_LUI:
if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
@@ -6060,8 +6104,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
}
out:
- if (insn_bytes == 2)
+ if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16;
+ }
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@@ -6708,8 +6753,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *register_name = "invalid";
- if (sel != 0)
+ if (sel != 0) {
check_insn(ctx, ISA_MIPS32);
+ }
switch (reg) {
case CP0_REGISTER_00:
@@ -7464,8 +7510,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *register_name = "invalid";
- if (sel != 0)
+ if (sel != 0) {
check_insn(ctx, ISA_MIPS32);
+ }
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -8210,8 +8257,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *register_name = "invalid";
- if (sel != 0)
+ if (sel != 0) {
check_insn(ctx, ISA_MIPS64);
+ }
switch (reg) {
case CP0_REGISTER_00:
@@ -8920,8 +8968,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *register_name = "invalid";
- if (sel != 0)
+ if (sel != 0) {
check_insn(ctx, ISA_MIPS64);
+ }
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -9658,12 +9707,12 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
- (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
+ (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
tcg_gen_movi_tl(t0, -1);
- else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
+ (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
tcg_gen_movi_tl(t0, -1);
- else if (u == 0) {
+ } else if (u == 0) {
switch (rt) {
case 1:
switch (sel) {
@@ -9883,12 +9932,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
- (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
+ (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
/* NOP */ ;
- else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
+ (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
/* NOP */ ;
- else if (u == 0) {
+ } else if (u == 0) {
switch (rd) {
case 1:
switch (sel) {
@@ -10162,8 +10211,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_TLBWI:
opn = "tlbwi";
- if (!env->tlb->helper_tlbwi)
+ if (!env->tlb->helper_tlbwi) {
goto die;
+ }
gen_helper_tlbwi(cpu_env);
break;
case OPC_TLBINV:
@@ -10186,20 +10236,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_TLBWR:
opn = "tlbwr";
- if (!env->tlb->helper_tlbwr)
+ if (!env->tlb->helper_tlbwr) {
goto die;
+ }
gen_helper_tlbwr(cpu_env);
break;
case OPC_TLBP:
opn = "tlbp";
- if (!env->tlb->helper_tlbp)
+ if (!env->tlb->helper_tlbp) {
goto die;
+ }
gen_helper_tlbp(cpu_env);
break;
case OPC_TLBR:
opn = "tlbr";
- if (!env->tlb->helper_tlbr)
+ if (!env->tlb->helper_tlbr) {
goto die;
+ }
gen_helper_tlbr(cpu_env);
break;
case OPC_ERET: /* OPC_ERETNC */
@@ -10273,8 +10326,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
goto out;
}
- if (cc != 0)
+ if (cc != 0) {
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ }
btarget = ctx->base.pc_next + 4 + offset;
@@ -10728,10 +10782,11 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
return;
}
- if (tf)
+ if (tf) {
cond = TCG_COND_EQ;
- else
+ } else {
cond = TCG_COND_NE;
+ }
l1 = gen_new_label();
t0 = tcg_temp_new_i32();
@@ -10753,10 +10808,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
TCGv_i32 t0 = tcg_temp_new_i32();
TCGLabel *l1 = gen_new_label();
- if (tf)
+ if (tf) {
cond = TCG_COND_EQ;
- else
+ } else {
cond = TCG_COND_NE;
+ }
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
@@ -10774,10 +10830,11 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
TCGv_i64 fp0;
TCGLabel *l1 = gen_new_label();
- if (tf)
+ if (tf) {
cond = TCG_COND_EQ;
- else
+ } else {
cond = TCG_COND_NE;
+ }
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
@@ -10797,10 +10854,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- if (tf)
+ if (tf) {
cond = TCG_COND_EQ;
- else
+ } else {
cond = TCG_COND_NE;
+ }
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
@@ -12096,8 +12154,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
- if (ft != 0)
+ if (ft != 0) {
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
+ }
fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
@@ -29991,12 +30050,14 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
env->hflags, env->btarget, env->bcond);
for (i = 0; i < 32; i++) {
- if ((i & 3) == 0)
+ if ((i & 3) == 0) {
qemu_fprintf(f, "GPR%02d:", i);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx,
regnames[i], env->active_tc.gpr[i]);
- if ((i & 3) == 3)
+ if ((i & 3) == 3) {
qemu_fprintf(f, "\n");
+ }
}
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
--
2.7.4
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