* cron job: media_tree daily build: ERRORS
From: Hans Verkuil @ 2020-07-17 3:41 UTC (permalink / raw)
To: linux-media
This message is generated daily by a cron job that builds media_tree for
the kernels and architectures in the list below.
Results of the daily build of media_tree:
date: Fri Jul 17 05:00:10 CEST 2020
media-tree git hash: 6f01dfb760c027d5dd6199d91ee9599f2676b5c6
media_build git hash: 3b826169bba299e5a7352f79759f3c67a4c9fb7a
v4l-utils git hash: e50041186be9f69dd94b64fb924115201726e72a
edid-decode git hash: f20c85d7b4c537e0d458f85c4da9f45cd3c0fbd2
gcc version: i686-linux-gcc (GCC) 9.3.0
sparse repo: https://git.linuxtv.org/mchehab/sparse.git
sparse version: 0.6.1
smatch repo: https://git.linuxtv.org/mchehab/smatch.git
smatch version: v0.5.0-6381-g344ef612
build-scripts repo: https://git.linuxtv.org/hverkuil/build-scripts.git
build-scripts git hash: 5540ce1b67f5015886e850a4775d2eace9efe922
host hardware: x86_64
host os: 5.6.0-1-amd64
linux-git-sh: OK
linux-git-arm-at91: OK
linux-git-arm-davinci: OK
linux-git-arm-stm32: OK
linux-git-arm-pxa: OK
linux-git-mips: OK
linux-git-arm64: OK
linux-git-powerpc64: OK
linux-git-arm-multi: OK
linux-git-i686: OK
linux-git-x86_64: OK
Check COMPILE_TEST: WARNINGS: VIDEO_TEGRA
Check for strcpy/strncpy/strlcpy: WARNINGS: found 3 strcpy(), 3 strncpy(), 3 strlcpy()
linux-3.10.108-i686: OK
linux-3.10.108-x86_64: OK
linux-3.11.10-i686: OK
linux-3.11.10-x86_64: OK
linux-3.12.74-i686: OK
linux-3.12.74-x86_64: OK
linux-3.13.11-i686: OK
linux-3.13.11-x86_64: OK
linux-3.14.79-i686: OK
linux-3.14.79-x86_64: OK
linux-3.15.10-i686: OK
linux-3.15.10-x86_64: OK
linux-3.16.81-i686: OK
linux-3.16.81-x86_64: OK
linux-3.17.8-i686: OK
linux-3.17.8-x86_64: OK
linux-3.18.136-i686: OK
linux-3.18.136-x86_64: OK
linux-3.19.8-i686: OK
linux-3.19.8-x86_64: OK
linux-4.0.9-i686: OK
linux-4.0.9-x86_64: OK
linux-4.1.52-i686: OK
linux-4.1.52-x86_64: OK
linux-4.2.8-i686: OK
linux-4.2.8-x86_64: OK
linux-4.3.6-i686: OK
linux-4.3.6-x86_64: OK
linux-4.4.212-i686: OK
linux-4.4.212-x86_64: OK
linux-4.5.7-i686: OK
linux-4.5.7-x86_64: OK
linux-4.6.7-i686: OK
linux-4.6.7-x86_64: OK
linux-4.7.10-i686: OK
linux-4.7.10-x86_64: OK
linux-4.8.17-i686: OK
linux-4.8.17-x86_64: OK
linux-4.9.212-i686: OK
linux-4.9.212-x86_64: OK
linux-4.10.17-i686: OK
linux-4.10.17-x86_64: OK
linux-4.11.12-i686: OK
linux-4.11.12-x86_64: OK
linux-4.12.14-i686: OK
linux-4.12.14-x86_64: OK
linux-4.13.16-i686: OK
linux-4.13.16-x86_64: OK
linux-4.14.169-i686: OK
linux-4.14.169-x86_64: OK
linux-4.15.18-i686: OK
linux-4.15.18-x86_64: OK
linux-4.16.18-i686: OK
linux-4.16.18-x86_64: OK
linux-4.17.19-i686: OK
linux-4.17.19-x86_64: OK
linux-4.18.20-i686: OK
linux-4.18.20-x86_64: OK
linux-4.19.101-i686: OK
linux-4.19.101-x86_64: OK
linux-4.20.15-i686: OK
linux-4.20.15-x86_64: OK
linux-5.0.15-i686: OK
linux-5.0.15-x86_64: OK
linux-5.1.1-i686: OK
linux-5.1.1-x86_64: OK
linux-5.2.1-i686: OK
linux-5.2.1-x86_64: OK
linux-5.3.1-i686: OK
linux-5.3.1-x86_64: OK
linux-5.4.17-i686: OK
linux-5.4.17-x86_64: OK
linux-5.5.1-i686: OK
linux-5.5.1-x86_64: OK
linux-5.6.1-i686: OK
linux-5.6.1-x86_64: OK
linux-5.7.2-i686: OK
linux-5.7.2-x86_64: OK
linux-5.8-rc1-i686: OK
linux-5.8-rc1-x86_64: OK
apps: OK
spec-git: OK
virtme: WARNINGS: Final Summary: 2943, Succeeded: 2943, Failed: 0, Warnings: 1
virtme-32: WARNINGS: Final Summary: 2779, Succeeded: 2779, Failed: 0, Warnings: 4
sparse: OK
smatch: ERRORS
Detailed results are available here:
http://www.xs4all.nl/~hverkuil/logs/Friday.log
Detailed regression test results are available here:
http://www.xs4all.nl/~hverkuil/logs/Friday-test-media.log
http://www.xs4all.nl/~hverkuil/logs/Friday-test-media-32.log
http://www.xs4all.nl/~hverkuil/logs/Friday-test-media-dmesg.log
Full logs are available here:
http://www.xs4all.nl/~hverkuil/logs/Friday.tar.bz2
The Media Infrastructure API from this daily build is here:
http://www.xs4all.nl/~hverkuil/spec/index.html
^ permalink raw reply
* linux-next: build failure after merge of the mfd tree
From: Stephen Rothwell @ 2020-07-17 3:41 UTC (permalink / raw)
To: Lee Jones; +Cc: Linux Next Mailing List, Linux Kernel Mailing List
[-- Attachment #1: Type: text/plain, Size: 3068 bytes --]
Hi all,
After merging the mfd tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
drivers/mfd/kempld-core.c: In function 'kempld_register_cells_generic':
drivers/mfd/kempld-core.c:105:13: error: assignment of read-only location 'devs[i++]'
105 | devs[i++] = kempld_devs[KEMPLD_I2C];
| ^
drivers/mfd/kempld-core.c:108:13: error: assignment of read-only location 'devs[i++]'
108 | devs[i++] = kempld_devs[KEMPLD_WDT];
| ^
drivers/mfd/kempld-core.c:111:13: error: assignment of read-only location 'devs[i++]'
111 | devs[i++] = kempld_devs[KEMPLD_GPIO];
| ^
drivers/mfd/kempld-core.c:114:13: error: assignment of read-only location 'devs[i++]'
114 | devs[i++] = kempld_devs[KEMPLD_UART];
| ^
Caused by commit
70d48975c152 ("mfd: core: Make a best effort attempt to match devices with the correct of_nodes")
I have added the following fix patch for today (I assume that there is
a better solution):
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Fri, 17 Jul 2020 13:36:22 +1000
Subject: [PATCH] fix up for struct mfd_cell change
Fixes: 70d48975c152 ("mfd: core: Make a best effort attempt to match devices with the correct of_nodes")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
drivers/mfd/kempld-core.c | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/mfd/kempld-core.c b/drivers/mfd/kempld-core.c
index f48e21d8b97c..ad68ee699cb5 100644
--- a/drivers/mfd/kempld-core.c
+++ b/drivers/mfd/kempld-core.c
@@ -79,39 +79,31 @@ enum kempld_cells {
KEMPLD_UART,
};
-static const struct mfd_cell kempld_devs[] = {
- [KEMPLD_I2C] = {
- .name = "kempld-i2c",
- },
- [KEMPLD_WDT] = {
- .name = "kempld-wdt",
- },
- [KEMPLD_GPIO] = {
- .name = "kempld-gpio",
- },
- [KEMPLD_UART] = {
- .name = "kempld-uart",
- },
+static const char *kempld_devs[] = {
+ [KEMPLD_I2C] = "kempld-i2c",
+ [KEMPLD_WDT] = "kempld-wdt",
+ [KEMPLD_GPIO] = "kempld-gpio",
+ [KEMPLD_UART] = "kempld-uart",
};
#define KEMPLD_MAX_DEVS ARRAY_SIZE(kempld_devs)
static int kempld_register_cells_generic(struct kempld_device_data *pld)
{
- struct mfd_cell devs[KEMPLD_MAX_DEVS];
+ struct mfd_cell devs[KEMPLD_MAX_DEVS] = {};
int i = 0;
if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C)
- devs[i++] = kempld_devs[KEMPLD_I2C];
+ devs[i++].name = kempld_devs[KEMPLD_I2C];
if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG)
- devs[i++] = kempld_devs[KEMPLD_WDT];
+ devs[i++].name = kempld_devs[KEMPLD_WDT];
if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO)
- devs[i++] = kempld_devs[KEMPLD_GPIO];
+ devs[i++].name = kempld_devs[KEMPLD_GPIO];
if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART)
- devs[i++] = kempld_devs[KEMPLD_UART];
+ devs[i++].name = kempld_devs[KEMPLD_UART];
return mfd_add_devices(pld->dev, -1, devs, i, NULL, 0, NULL);
}
--
2.27.0
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* Re: [PATCH] clocksource: nomadik-mtu: Handle 32kHz clock
From: Daniel Lezcano @ 2020-07-17 3:40 UTC (permalink / raw)
To: Linus Walleij, Thomas Gleixner; +Cc: linux-kernel
In-Reply-To: <20200628220153.67011-1-linus.walleij@linaro.org>
On 29/06/2020 00:01, Linus Walleij wrote:
> It happens on the U8420-sysclk Ux500 PRCMU firmware
> variant that the MTU clock is just 32768 Hz, and in this
> mode the minimum ticks is 5 rather than two.
>
> I think this is simply so that there is enough time
> for the register write to propagate through the
> interconnect to the registers.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [Intel-wired-lan] PROBLEM: [e1000e] 10% throughput drop on I219-LM after the buffer overrun fix even with TSO&GSO disabled
From: Shangshu Qian @ 2020-07-17 3:37 UTC (permalink / raw)
To: intel-wired-lan
In-Reply-To: <SJ0PR07MB7584B6DC5998006092D4D8859C7C0@SJ0PR07MB7584.namprd07.prod.outlook.com>
[1.] One line summary of the problem:
[e1000e] 10% throughput drop on I219-LM after the buffer overrun fix even with TSO&GSO disabled
[2.] Full description of the problem/report:
With e1000e 3.6.2-k and 3.8.4-NAPI driver, which include the fix for the buffer overrun problem (https://github.com/torvalds/linux/commit/b10effb92e272051dd1ec0d7be56bf9ca85ab927, discussion: https://www.spinics.net/lists/netdev/msg460589.html), I219-LM network card have a 10% throughput drop in the iperf3 test (with TSO and GSO disabled) compared with the driver without such patch, and the client is initiating the stream in such test (iperf3 client mode without -R option). If the server is initiating the stream (with -R option in iperf3 client mode), the performance is not impacted.
That is to say, disabling TSO and GSO as suggested in that patch still have performance impact on the TCP stream, and the throughput drops about 10%.
I tried to rollback the patch introduced to fix the buffer overrun problem in the 3.8.4-NAPI driver, with TSO and GSO enabled, iperf3 test still cannot max out my 1Gbps uplink. However, with TSO and GSO disabled, 1Gbps uplink can be fully saturated.
I'll attach iperf3 test results for all these situations later in this email.
[3.] Keywords
Network driver, e1000e
[4.] Kernel information
[4.1.] Kernel version (from /proc/version):
Linux version 5.4.0-31-generic (buildd at lgw01-amd64-059) (gcc version 9.3.0 (Ubuntu 9.3.0-10ubuntu2)) #35-Ubuntu SMP Thu May 7 20:20:34 UTC 2020
[4.2.] Kernel .config file:
https://kernel.ubuntu.com/~kernel-ppa/config/focal/linux/5.4.0-31.35/amd64-config.flavour.generic
[5.] Most recent kernel version which did not have the bug:
V4.14.2
[6.] Environment
00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection (2) I219-LM (rev 31)
driver: e1000e
version: 3.2.6-k
firmware-version: 0.8-4
expansion-rom-version:
bus-info: 0000:00:1f.6
supports-statistics: yes
supports-test: yes
supports-eeprom-access: yes
supports-register-dump: yes
supports-priv-flags: no
iperf3:
iperf 3.7 (cJSON 1.5.2)
Linux Hetzner 5.4.0-31-generic #35-Ubuntu SMP Thu May 7 20:20:34 UTC 2020 x86_64
Optional features available: CPU affinity setting, IPv6 flow label, SCTP, TCP congestion algorithm setting, sendfile / zerocopy, socket pacing, authentication
[X.] Other notes, patches, fixes, workarounds:
3.6.2-k w/ TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 120 MBytes?? 101 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 119 MBytes? 99.4 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 120 MBytes?? 101 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 119 MBytes? 99.4 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 120 MBytes?? 101 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 119 MBytes? 99.4 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 120 MBytes?? 101 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 119 MBytes? 99.5 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 120 MBytes?? 101 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 119 MBytes? 99.5 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec?? 601 MBytes?? 504 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec?? 594 MBytes?? 497 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.02? sec?? 351 MBytes?? 293 Mbits/sec? 134???????????? sender
[? 5]?? 0.00-10.00? sec?? 344 MBytes?? 289 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 204 MBytes?? 171 Mbits/sec? 331???????????? sender
[? 7]?? 0.00-10.00? sec?? 201 MBytes?? 168 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 174 MBytes?? 146 Mbits/sec? 226???????????? sender
[? 9]?? 0.00-10.00? sec?? 171 MBytes?? 144 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 177 MBytes?? 148 Mbits/sec? 226???????????? sender
[ 11]?? 0.00-10.00? sec?? 173 MBytes?? 145 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 164 MBytes?? 138 Mbits/sec? 229???????????? sender
[ 13]?? 0.00-10.00? sec?? 161 MBytes?? 135 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.04 GBytes?? 896 Mbits/sec? 1146?????? ??????sender
[SUM]?? 0.00-10.00? sec? 1.03 GBytes?? 881 Mbits/sec????????????????? receiver
3.6.2-k w/o TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 190 MBytes?? 159 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 188 MBytes?? 157 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 190 MBytes?? 160 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 188 MBytes?? 157 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 191 MBytes?? 160 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 188 MBytes?? 158 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 190 MBytes?? 160 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 188 MBytes?? 158 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 191 MBytes?? 160 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 188 MBytes?? 157 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec?? 953 MBytes?? 799 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec?? 940 MBytes?? 787 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.02? sec?? 256 MBytes?? 214 Mbits/sec? 128???????????? sender
[? 5]?? 0.00-10.00? sec?? 252 MBytes?? 211 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 238 MBytes?? 199 Mbits/sec? 119???????????? sender
[? 7]?? 0.00-10.00? sec?? 234 MBytes?? 196 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 166 MBytes?? 139 Mbits/sec? 207???????????? sender
[? 9]?? 0.00-10.00? sec?? 162 MBytes?? 136 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 222 MBytes?? 186 Mbits/sec? 316???????????? sender
[ 11]?? 0.00-10.00? sec?? 219 MBytes?? 184 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 225 MBytes?? 189 Mbits/sec? 138???????????? sender
[ 13]?? 0.00-10.00? sec?? 222 MBytes?? 186 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.08 GBytes?? 927 Mbits/sec? 908??????? ?????sender
[SUM]?? 0.00-10.00? sec? 1.06 GBytes?? 913 Mbits/sec????????????????? receiver
3.8.4-NAPI w/ TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 120 MBytes?? 100 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 117 MBytes? 97.5 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 115 MBytes? 96.4 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 114 MBytes? 95.1 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 118 MBytes? 98.9 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 117 MBytes? 97.6 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 118 MBytes? 99.3 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 117 MBytes? 97.5 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 118 MBytes? 99.3 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 116 MBytes? 97.5 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec?? 589 MBytes?? 494 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec?? 580 MBytes?? 485 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.02? sec?? 289 MBytes?? 241 Mbits/sec? 187???????????? sender
[? 5]?? 0.00-10.00? sec?? 282 MBytes?? 236 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 355 MBytes?? 297 Mbits/sec? 324???????????? sender
[? 7]?? 0.00-10.00? sec?? 350 MBytes?? 293 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 144 MBytes?? 121 Mbits/sec? 239???????????? sender
[? 9]?? 0.00-10.00? sec?? 141 MBytes?? 118 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 136 MBytes?? 113 Mbits/sec? 286???????????? sender
[ 11]?? 0.00-10.00? sec?? 133 MBytes?? 111 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 188 MBytes?? 157 Mbits/sec? 156???????????? sender
[ 13]?? 0.00-10.00? sec?? 185 MBytes?? 155 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.09 GBytes?? 930 Mbits/sec? 1192?????? ??????sender
[SUM]?? 0.00-10.00? sec? 1.06 GBytes?? 914 Mbits/sec????????????????? receiver
3.8.4-NAPI w/o TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 194 MBytes?? 163 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 192 MBytes?? 160 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 194 MBytes?? 163 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 192 MBytes?? 160 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 195 MBytes?? 163 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 192 MBytes?? 160 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 195 MBytes?? 163 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 192 MBytes?? 160 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 195 MBytes?? 163 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 192 MBytes?? 161 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec?? 973 MBytes?? 816 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec?? 958 MBytes?? 802 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.02? sec?? 499 MBytes?? 418 Mbits/sec? 1208???????????? sender
[? 5]?? 0.00-10.00? sec?? 487 MBytes?? 409 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 149 MBytes?? 125 Mbits/sec? 262???????????? sender
[? 7]?? 0.00-10.00? sec?? 146 MBytes?? 122 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 158 MBytes?? 132 Mbits/sec? 199???????????? sender
[? 9]?? 0.00-10.00? sec?? 154 MBytes?? 129 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 179 MBytes?? 149 Mbits/sec? 209???????????? sender
[ 11]?? 0.00-10.00? sec?? 175 MBytes?? 147 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 128 MBytes?? 107 Mbits/sec? 386???????????? sender
[ 13]?? 0.00-10.00? sec?? 125 MBytes?? 105 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.09 GBytes?? 931 Mbits/sec? 2264?????? ??????sender
[SUM]?? 0.00-10.00? sec? 1.06 GBytes?? 912 Mbits/sec????????????????? receiver
3.8.4-NAPI w/ TSO & GSO (Without buffer overrun patch)
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 204 MBytes?? 171 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 201 MBytes?? 169 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 203 MBytes?? 170 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 201 MBytes?? 168 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 205 MBytes?? 172 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 202 MBytes?? 169 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 204 MBytes?? 171 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 201 MBytes?? 169 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 204 MBytes?? 171 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 200 MBytes?? 168 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec? 1019 MBytes?? 855 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec? 1006 MBytes?? 842 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[? 5]?? 0.00-10.02? sec?? 281 MBytes?? 235 Mbits/sec? 128???????????? sender
[? 5]?? 0.00-10.00? sec?? 277 MBytes?? 232 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 267 MBytes?? 223 Mbits/sec? 154???????????? sender
[? 7]?? 0.00-10.00? sec?? 263 MBytes?? 221 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 170 MBytes?? 142 Mbits/sec? 154???????????? sender
[? 9]?? 0.00-10.00? sec?? 166 MBytes?? 139 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 161 MBytes?? 135 Mbits/sec? 211???????????? sender
[ 11]?? 0.00-10.00? sec?? 158 MBytes?? 132 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 219 MBytes?? 183 Mbits/sec? 116???????????? sender
[ 13]?? 0.00-10.00? sec?? 216 MBytes?? 181 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.07 GBytes?? 919 Mbits/sec? 763???????????? sender
[SUM]?? 0.00-10.00? sec? 1.05 GBytes?? 906 Mbits/sec?????????????? ???receiver
3.8.4-NAPI w/o TSO & GSO (Without buffer overrun patch)
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.00? sec?? 220 MBytes?? 184 Mbits/sec??? 0???????????? sender
[? 5]?? 0.00-10.02? sec?? 218 MBytes?? 182 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.00? sec?? 220 MBytes?? 185 Mbits/sec??? 0???????????? sender
[? 7]?? 0.00-10.02? sec?? 217 MBytes?? 182 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.00? sec?? 216 MBytes?? 182 Mbits/sec??? 0???????????? sender
[? 9]?? 0.00-10.02? sec?? 213 MBytes?? 179 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.00? sec?? 220 MBytes?? 185 Mbits/sec??? 0???????????? sender
[ 11]?? 0.00-10.02? sec?? 218 MBytes?? 182 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.00? sec?? 221 MBytes?? 185 Mbits/sec??? 0???????????? sender
[ 13]?? 0.00-10.02? sec?? 218 MBytes?? 182 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.00? sec? 1.07 GBytes?? 920 Mbits/sec??? 0??????? ?????sender
[SUM]?? 0.00-10.02? sec? 1.06 GBytes?? 907 Mbits/sec????????????????? receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval?????????? Transfer???? Bitrate???????? Retr
[? 5]?? 0.00-10.02? sec?? 259 MBytes?? 217 Mbits/sec?? 67???????????? sender
[? 5]?? 0.00-10.00? sec?? 255 MBytes?? 214 Mbits/sec????????????????? receiver
[? 7]?? 0.00-10.02? sec?? 256 MBytes?? 214 Mbits/sec? 168???????????? sender
[? 7]?? 0.00-10.00? sec?? 252 MBytes?? 212 Mbits/sec????????????????? receiver
[? 9]?? 0.00-10.02? sec?? 260 MBytes?? 217 Mbits/sec? 189???????????? sender
[? 9]?? 0.00-10.00? sec?? 256 MBytes?? 215 Mbits/sec????????????????? receiver
[ 11]?? 0.00-10.02? sec?? 165 MBytes?? 138 Mbits/sec? 237???????????? sender
[ 11]?? 0.00-10.00? sec?? 161 MBytes?? 135 Mbits/sec????????????????? receiver
[ 13]?? 0.00-10.02? sec?? 172 MBytes?? 144 Mbits/sec? 220???????????? sender
[ 13]?? 0.00-10.00? sec?? 169 MBytes?? 142 Mbits/sec????????????????? receiver
[SUM]?? 0.00-10.02? sec? 1.08 GBytes?? 930 Mbits/sec? 881??????? ?????sender
[SUM]?? 0.00-10.00? sec? 1.07 GBytes?? 917 Mbits/sec????????????????? receiver
^ permalink raw reply
* [PULL SUBSYSTEM qemu-pseries] pseries: Update SLOF firmware image
From: Alexey Kardashevskiy @ 2020-07-17 3:27 UTC (permalink / raw)
To: David Gibson; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel
The following changes since commit 1038a309ec829f05a3a3e52a9951cfdb24dfd02c:
spapr: Add a new level of NUMA for GPUs (2020-07-17 10:36:28 +1000)
are available in the Git repository at:
git@github.com:aik/qemu.git tags/qemu-slof-20200717
for you to fetch changes up to 7f5258dd8327d574de455a2271788474fa25548d:
pseries: Update SLOF firmware image (2020-07-17 13:23:00 +1000)
----------------------------------------------------------------
Alexey Kardashevskiy (1):
pseries: Update SLOF firmware image
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 965112 -> 968368 bytes
roms/SLOF | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
*** Note: this is not for master, this is for pseries
This adds tcgbios (this was posted earlier [1] but got lost)
and fixes FDT update at ibm,client-architecture-support
for huge guests.
The full list of changes:
Alexey Kardashevskiy (4):
make: Define default rule for .c when V=1 or V=2
version: update to 20200513
fdt: Avoid recursion when traversing tree
version: update to 20200717
Gustavo Romero (1):
board-qemu: Fix comment about SLOF start address
Stefan Berger (6):
tcgbios: Only write logs for PCRs that are allocated
tcgbios: Fix the vendorInfoSize to be of type uint8_t
tcgbios: Add support for SHA3 type of algorithms
elf: Implement elf_get_file_size to determine size of an ELF image
tcgbios: Implement tpm_hash_log_extend_event_buffer
tcgbios: Measure the bootloader file read from disk
[1] https://patchwork.ozlabs.org/project/qemu-devel/patch/20200513024355.121476-1-aik@ozlabs.ru/
^ permalink raw reply
* drivers/tty/serial/ip22zilog.c:114:22: sparse: sparse: incorrect type in argument 2 (different address spaces)
From: kernel test robot @ 2020-07-17 3:32 UTC (permalink / raw)
To: Luc Van Oostenryck; +Cc: kbuild-all, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 17375 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 07a56bb875afbe39dabbf6ba7b83783d166863db
commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to define address spaces
date: 4 weeks ago
config: mips-randconfig-s032-20200717 (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.2-49-g707c5017-dirty
git checkout 670d0a4b10704667765f7d18f7592993d02783aa
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/tty/serial/ip22zilog.c:114:22: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
>> drivers/tty/serial/ip22zilog.c:114:22: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:114:22: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:116:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
>> drivers/tty/serial/ip22zilog.c:116:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:116:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:125:22: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:125:22: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:125:22: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:127:24: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:127:24: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:127:24: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:138:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:138:33: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:138:33: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:144:24: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:144:24: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:144:24: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:148:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:148:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:148:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:170:26: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:170:26: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:170:26: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:256:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:256:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:256:29: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:263:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:263:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:263:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:268:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:268:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:268:29: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:318:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:318:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:318:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:321:30: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:321:30: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:321:30: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:361:47: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:361:47: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:361:47: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:390:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:390:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:390:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:408:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:408:40: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:408:40: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:421:27: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:421:27: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:421:27: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:432:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:441:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:441:44: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:441:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:459:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:464:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:464:44: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:464:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:546:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:580:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:586:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:586:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:586:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:597:39: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:597:39: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:597:39: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:608:48: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:608:48: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:608:48: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:629:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:641:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:658:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:691:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:701:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:715:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:722:34: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:722:34: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:722:34: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:782:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:896:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:995:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:1002:44: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:1002:44: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:1002:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:1010:21: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:1010:21: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:1010:21: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:1100:57: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected unsigned char [noderef] __iomem *membase @@ got char * @@
>> drivers/tty/serial/ip22zilog.c:1100:57: sparse: expected unsigned char [noderef] __iomem *membase
drivers/tty/serial/ip22zilog.c:1100:57: sparse: got char *
drivers/tty/serial/ip22zilog.c:1101:57: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected unsigned char [noderef] __iomem *membase @@ got char * @@
drivers/tty/serial/ip22zilog.c:1101:57: sparse: expected unsigned char [noderef] __iomem *membase
drivers/tty/serial/ip22zilog.c:1101:57: sparse: got char *
>> drivers/tty/serial/ip22zilog.c:1205:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
>> drivers/tty/serial/ip22zilog.c:1205:29: sparse: expected void const volatile [noderef] __iomem *addr
drivers/tty/serial/ip22zilog.c:1205:29: sparse: got void *
drivers/tty/serial/ip22zilog.c:1209:34: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/tty/serial/ip22zilog.c:1209:34: sparse: expected void const volatile [noderef] __iomem *addr
drivers/tty/serial/ip22zilog.c:1209:34: sparse: got void *
drivers/tty/serial/ip22zilog.c:494:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:495:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:495:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:495:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:494:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:495:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:495:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:495:25: sparse: got unsigned char volatile *
vim +114 drivers/tty/serial/ip22zilog.c
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 100
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 101 /* Reading and writing Zilog8530 registers. The delays are to make this
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 102 * driver work on the IP22 which needs a settling delay after each chip
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 103 * register access, other machines handle this in hardware via auxiliary
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 104 * flip-flops which implement the settle time we do in software.
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 105 *
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 106 * The port lock must be held and local IRQs must be disabled
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 107 * when {read,write}_zsreg is invoked.
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 108 */
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 109 static unsigned char read_zsreg(struct zilog_channel *channel,
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 110 unsigned char reg)
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 111 {
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 112 unsigned char retval;
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 113
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 @114 writeb(reg, &channel->control);
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 115 ZSDELAY();
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 @116 retval = readb(&channel->control);
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 117 ZSDELAY();
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 118
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 119 return retval;
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 120 }
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 121
:::::: The code at line 114 was first introduced by commit
:::::: 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Linux-2.6.12-rc2
:::::: TO: Linus Torvalds <torvalds@ppc970.osdl.org>
:::::: CC: Linus Torvalds <torvalds@ppc970.osdl.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 19008 bytes --]
^ permalink raw reply
* [PATCH] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL975x
From: Ben Chuang @ 2020-07-17 3:33 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson
Cc: linux-mmc, linux-kernel, ben.chuang, greg.tu, SeanHY.Chen,
Ben Chuang
From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Set SDR104's clock to 205MHz and enable SSC for GL9750 and GL9755
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
---
drivers/mmc/host/sdhci-pci-gli.c | 220 ++++++++++++++++++++++++++++++-
1 file changed, 218 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index ca0166d9bf82..5da2b06d84ae 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -31,10 +31,18 @@
#define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
#define SDHCI_GLI_9750_PLL 0x864
+#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
+#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
+#define SDHCI_GLI_9750_PLL_DIR BIT(15)
#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
#define GLI_9750_PLL_TX2_INV_VALUE 0x1
#define GLI_9750_PLL_TX2_DLY_VALUE 0x0
+#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
+#define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
+
+#define SDHCI_GLI_9750_PLLSSC 0x86C
+#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
#define SDHCI_GLI_9750_SW_CTRL 0x874
#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
@@ -76,6 +84,21 @@
#define PCIE_GLI_9763E_SCR 0x8E0
#define GLI_9763E_SCR_AXI_REQ BIT(9)
+#define PCI_GLI_9755_WT 0x800
+#define PCI_GLI_9755_WT_EN BIT(0)
+#define GLI_9755_WT_EN_ON 0x1
+#define GLI_9755_WT_EN_OFF 0x0
+
+#define PCI_GLI_9755_PLL 0x64
+#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
+#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
+#define PCI_GLI_9755_PLL_DIR BIT(15)
+#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
+#define PCI_GLI_9755_PLLSSC_EN BIT(31)
+
+#define PCI_GLI_9755_PLLSSC 0x68
+#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
+
#define GLI_MAX_TUNING_LOOP 40
/* Genesys Logic chipset */
@@ -280,6 +303,84 @@ static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
return 0;
}
+static void gl9750_disable_ssc_pll(struct sdhci_host *host)
+{
+ u32 pll;
+
+ gl9750_wt_on(host);
+ pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
+ pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
+ sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
+ gl9750_wt_off(host);
+}
+
+static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
+{
+ u32 pll;
+
+ gl9750_wt_on(host);
+ pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
+ pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
+ SDHCI_GLI_9750_PLL_PDIV |
+ SDHCI_GLI_9750_PLL_DIR);
+ pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
+ FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
+ FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
+ sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
+ gl9750_wt_off(host);
+
+ /* wait for pll stable */
+ mdelay(1);
+}
+
+static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
+{
+ u32 pll;
+ u32 ssc;
+
+ gl9750_wt_on(host);
+ pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
+ ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
+ pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
+ SDHCI_GLI_9750_PLLSSC_EN);
+ ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
+ pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
+ FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
+ ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
+ sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
+ sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
+ gl9750_wt_off(host);
+}
+
+static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
+{
+ /* set pll to 205MHz and enable ssc */
+ gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
+ gl9750_set_pll(host, 0x1, 0x246, 0x0);
+}
+
+static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct mmc_ios *ios = &host->mmc->ios;
+ u16 clk;
+
+ host->mmc->actual_clock = 0;
+
+ gl9750_disable_ssc_pll(host);
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+ if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
+ host->mmc->actual_clock = 205000000;
+ gl9750_set_ssc_pll_205mhz(host);
+ }
+
+ sdhci_enable_clk(host, clk);
+}
+
static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
{
int ret;
@@ -295,6 +396,121 @@ static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
}
+static inline void gl9755_wt_on(struct pci_dev *pdev)
+{
+ u32 wt_value;
+ u32 wt_enable;
+
+ pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
+ wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
+
+ if (wt_enable == GLI_9755_WT_EN_ON)
+ return;
+
+ wt_value &= ~PCI_GLI_9755_WT_EN;
+ wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
+
+ pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
+}
+
+static inline void gl9755_wt_off(struct pci_dev *pdev)
+{
+ u32 wt_value;
+ u32 wt_enable;
+
+ pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
+ wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
+
+ if (wt_enable == GLI_9755_WT_EN_OFF)
+ return;
+
+ wt_value &= ~PCI_GLI_9755_WT_EN;
+ wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
+
+ pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
+}
+
+static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
+{
+ u32 pll;
+
+ gl9755_wt_on(pdev);
+ pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
+ pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
+ pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
+ gl9755_wt_off(pdev);
+}
+
+static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
+{
+ u32 pll;
+
+ gl9755_wt_on(pdev);
+ pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
+ pll &= ~(PCI_GLI_9755_PLL_LDIV |
+ PCI_GLI_9755_PLL_PDIV |
+ PCI_GLI_9755_PLL_DIR);
+ pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
+ FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
+ FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
+ pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
+ gl9755_wt_off(pdev);
+
+ /* wait for pll stable */
+ mdelay(1);
+}
+
+static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
+{
+ u32 pll;
+ u32 ssc;
+
+ gl9755_wt_on(pdev);
+ pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
+ pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
+ pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
+ PCI_GLI_9755_PLLSSC_EN);
+ ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
+ pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
+ FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
+ ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
+ pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
+ pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
+ gl9755_wt_off(pdev);
+}
+
+static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
+{
+ /* set pll to 205MHz and enable ssc */
+ gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
+ gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
+}
+
+static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pci_slot *slot = sdhci_priv(host);
+ struct mmc_ios *ios = &host->mmc->ios;
+ struct pci_dev *pdev;
+ u16 clk;
+
+ pdev = slot->chip->pdev;
+ host->mmc->actual_clock = 0;
+
+ gl9755_disable_ssc_pll(pdev);
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+ if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
+ host->mmc->actual_clock = 205000000;
+ gl9755_set_ssc_pll_205mhz(pdev);
+ }
+
+ sdhci_enable_clk(host, clk);
+}
+
static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
{
struct sdhci_host *host = slot->host;
@@ -440,7 +656,7 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
}
static const struct sdhci_ops sdhci_gl9755_ops = {
- .set_clock = sdhci_set_clock,
+ .set_clock = sdhci_gl9755_set_clock,
.enable_dma = sdhci_pci_enable_dma,
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_reset,
@@ -460,7 +676,7 @@ const struct sdhci_pci_fixes sdhci_gl9755 = {
static const struct sdhci_ops sdhci_gl9750_ops = {
.read_l = sdhci_gl9750_readl,
- .set_clock = sdhci_set_clock,
+ .set_clock = sdhci_gl9750_set_clock,
.enable_dma = sdhci_pci_enable_dma,
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_gl9750_reset,
--
2.27.0
^ permalink raw reply related
* Re: [PATCH] perf evsel: Don't set sample_regs_intr/sample_regs_user for dummy event
From: Jin, Yao @ 2020-07-17 3:33 UTC (permalink / raw)
To: Ian Rogers, Jiri Olsa, Arnaldo Carvalho de Melo
Cc: Jiri Olsa, Peter Zijlstra, Ingo Molnar, Alexander Shishkin, LKML,
Andi Kleen, kan.liang, Jin, Yao, Adrian Hunter
In-Reply-To: <b527838b-42e8-b48a-debc-fd91923150d5@linux.intel.com>
Hi,
On 7/6/2020 8:55 AM, Jin, Yao wrote:
> Hi Ian,
>
> On 7/6/2020 8:47 AM, Ian Rogers wrote:
>> On Fri, Jul 3, 2020 at 5:31 PM Jin, Yao <yao.jin@linux.intel.com> wrote:
>>>
>>> Hi Jiri,
>>>
>>> On 7/3/2020 7:00 PM, Jiri Olsa wrote:
>>>> On Fri, Jul 03, 2020 at 08:42:15AM +0800, Jin Yao wrote:
>>>>> Since commit 0a892c1c9472 ("perf record: Add dummy event during system wide synthesis"),
>>>>> a dummy event is added to capture mmaps.
>>>>>
>>>>> But if we run perf-record as,
>>>>>
>>>>> # perf record -e cycles:p -IXMM0 -a -- sleep 1
>>>>> Error:
>>>>> dummy:HG: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'
>>>>>
>>
>> Sorry for the breakage caused by modifying the dummy event. Could we
>> add a test to cover the issue? Perhaps in tools/perf/tests/shell/.
>> Trying to reproduce with a register on my skylakex on a 5.6.14 kernel
>> with:
>>
>> $ perf record -e cycles:p -IAX -a -- sleep 1
>>
>> succeeds.
>>
>> Thanks,
>> Ian
>>
>
> -IAX should be no problem. The issue only occurs on the platform with extended regs supports, such
> as ICL. So I don't know if it's suitable to add it to perf test suite.
>
> Thanks
> Jin Yao
>
Can this fix patch be accepted?
Thanks
Jin Yao
>>>>> The issue is, if we enable the extended regs (-IXMM0), but the
>>>>> pmu->capabilities is not set with PERF_PMU_CAP_EXTENDED_REGS, the kernel
>>>>> will return -EOPNOTSUPP error.
>>>>>
>>>>> See following code pieces.
>>>>>
>>>>> /* in kernel/events/core.c */
>>>>> static int perf_try_init_event(struct pmu *pmu, struct perf_event *event)
>>>>>
>>>>> {
>>>>> ....
>>>>> if (!(pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS) &&
>>>>> has_extended_regs(event))
>>>>> ret = -EOPNOTSUPP;
>>>>> ....
>>>>> }
>>>>>
>>>>> For software dummy event, the PMU should be not set with
>>>>> PERF_PMU_CAP_EXTENDED_REGS. But unfortunately in current code, the dummy
>>>>> event has possibility to be set with PERF_REG_EXTENDED_MASK bit.
>>>>>
>>>>> In evsel__config, /* tools/perf/util/evsel.c */
>>>>>
>>>>> if (opts->sample_intr_regs) {
>>>>> attr->sample_regs_intr = opts->sample_intr_regs;
>>>>> }
>>>>>
>>>>> If we use -IXMM0, the attr>sample_regs_intr will be set with
>>>>> PERF_REG_EXTENDED_MASK bit.
>>>>>
>>>>> It doesn't make sense to set attr->sample_regs_intr for a
>>>>> software dummy event.
>>>>>
>>>>> This patch adds dummy event checking before setting
>>>>> attr->sample_regs_intr.
>>>>>
>>>>> After:
>>>>> # ./perf record -e cycles:p -IXMM0 -a -- sleep 1
>>>>> [ perf record: Woken up 1 times to write data ]
>>>>> [ perf record: Captured and wrote 0.413 MB perf.data (45 samples) ]
>>>>
>>>> LGTM, Adrian (cc-ed) just added another check to the same place,
>>>> but it looks like both of them should be there:
>>>>
>>>> https://lore.kernel.org/lkml/20200630133935.11150-2-adrian.hunter@intel.com/
>>>>
>>>> jirka
>>>>
>>>
>>> Thanks Jiri! Yes, it looks like both of checks should be added here.
>>>
>>> So do I post v2 (just rebase) once Adrian's patch gets merged?
>>>
>>> Thanks
>>> Jin Yao
>>>
>>>>>
>>>>> Fixes: 0a892c1c9472 ("perf record: Add dummy event during system wide synthesis")
>>>>> Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
>>>>> ---
>>>>> tools/perf/util/evsel.c | 4 ++--
>>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
>>>>> index 96e5171dce41..df3315543e86 100644
>>>>> --- a/tools/perf/util/evsel.c
>>>>> +++ b/tools/perf/util/evsel.c
>>>>> @@ -1020,12 +1020,12 @@ void evsel__config(struct evsel *evsel, struct record_opts *opts,
>>>>> if (callchain && callchain->enabled && !evsel->no_aux_samples)
>>>>> evsel__config_callchain(evsel, opts, callchain);
>>>>>
>>>>> - if (opts->sample_intr_regs) {
>>>>> + if (opts->sample_intr_regs && !is_dummy_event(evsel)) {
>>>>> attr->sample_regs_intr = opts->sample_intr_regs;
>>>>> evsel__set_sample_bit(evsel, REGS_INTR);
>>>>> }
>>>>>
>>>>> - if (opts->sample_user_regs) {
>>>>> + if (opts->sample_user_regs && !is_dummy_event(evsel)) {
>>>>> attr->sample_regs_user |= opts->sample_user_regs;
>>>>> evsel__set_sample_bit(evsel, REGS_USER);
>>>>> }
>>>>> --
>>>>> 2.17.1
>>>>>
>>>>
^ permalink raw reply
* Re: [PATCH 01/14] rtlwifi: Replace RT_TRACE with RT_DEBUG
From: Joe Perches @ 2020-07-17 3:32 UTC (permalink / raw)
To: Larry Finger, kvalo; +Cc: linux-wireless
In-Reply-To: <20200717020201.18209-2-Larry.Finger@lwfinger.net>
On Thu, 2020-07-16 at 21:01 -0500, Larry Finger wrote:
> The macro name RT_TRACE makes it seem that it is used for tracing, when
> is actually used for debugging. Change the name to RT_DEBUG.
>
> In the initial step, RT_TRACE must be kept to allow building. It will
> be removed at the end of the patch series.
Likely this patch could be broken out
so that the addition of RT_DEBUG is
patch 1 and the remainder of this patch
is patch 2.
And I'd suggest not using RT_DEBUG as the
macro but use rtl_dbg instead.
Lastly, the _rtl_dbg_trace function
should probably be renamed _rtl_dbg.
Other than that, I think this entire
series is sensible, thanks.
^ permalink raw reply
* drivers/tty/serial/ip22zilog.c:114:22: sparse: sparse: incorrect type in argument 2 (different address spaces)
From: kernel test robot @ 2020-07-17 3:32 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 17541 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 07a56bb875afbe39dabbf6ba7b83783d166863db
commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to define address spaces
date: 4 weeks ago
config: mips-randconfig-s032-20200717 (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.2-49-g707c5017-dirty
git checkout 670d0a4b10704667765f7d18f7592993d02783aa
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/tty/serial/ip22zilog.c:114:22: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
>> drivers/tty/serial/ip22zilog.c:114:22: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:114:22: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:116:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
>> drivers/tty/serial/ip22zilog.c:116:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:116:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:125:22: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:125:22: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:125:22: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:127:24: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:127:24: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:127:24: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:138:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:138:33: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:138:33: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:144:24: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:144:24: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:144:24: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:148:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:148:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:148:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:170:26: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:170:26: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:170:26: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:256:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:256:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:256:29: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:263:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:263:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:263:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:268:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:268:29: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:268:29: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:318:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:318:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:318:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:321:30: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:321:30: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:321:30: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:361:47: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:361:47: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:361:47: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:390:42: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:390:42: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:390:42: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:408:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:408:40: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:408:40: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:421:27: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:421:27: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:421:27: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:432:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:441:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:441:44: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:441:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:459:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:464:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:464:44: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:464:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:546:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:580:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:586:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:586:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:586:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:597:39: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:597:39: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:597:39: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:608:48: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:608:48: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:608:48: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:629:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:641:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:658:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:691:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:701:27: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:715:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:722:34: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:722:34: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:722:34: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:782:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:896:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:995:41: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:1002:44: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:1002:44: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:1002:44: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:1010:21: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:1010:21: sparse: expected void volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:1010:21: sparse: got unsigned char volatile *
>> drivers/tty/serial/ip22zilog.c:1100:57: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected unsigned char [noderef] __iomem *membase @@ got char * @@
>> drivers/tty/serial/ip22zilog.c:1100:57: sparse: expected unsigned char [noderef] __iomem *membase
drivers/tty/serial/ip22zilog.c:1100:57: sparse: got char *
drivers/tty/serial/ip22zilog.c:1101:57: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected unsigned char [noderef] __iomem *membase @@ got char * @@
drivers/tty/serial/ip22zilog.c:1101:57: sparse: expected unsigned char [noderef] __iomem *membase
drivers/tty/serial/ip22zilog.c:1101:57: sparse: got char *
>> drivers/tty/serial/ip22zilog.c:1205:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
>> drivers/tty/serial/ip22zilog.c:1205:29: sparse: expected void const volatile [noderef] __iomem *addr
drivers/tty/serial/ip22zilog.c:1205:29: sparse: got void *
drivers/tty/serial/ip22zilog.c:1209:34: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/tty/serial/ip22zilog.c:1209:34: sparse: expected void const volatile [noderef] __iomem *addr
drivers/tty/serial/ip22zilog.c:1209:34: sparse: got void *
drivers/tty/serial/ip22zilog.c:494:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:495:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:495:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:495:25: sparse: got unsigned char volatile *
drivers/tty/serial/ip22zilog.c:494:19: sparse: sparse: cast removes address space '__iomem' of expression
drivers/tty/serial/ip22zilog.c:495:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned char volatile * @@
drivers/tty/serial/ip22zilog.c:495:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/ip22zilog.c:495:25: sparse: got unsigned char volatile *
vim +114 drivers/tty/serial/ip22zilog.c
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 100
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 101 /* Reading and writing Zilog8530 registers. The delays are to make this
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 102 * driver work on the IP22 which needs a settling delay after each chip
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 103 * register access, other machines handle this in hardware via auxiliary
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 104 * flip-flops which implement the settle time we do in software.
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 105 *
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 106 * The port lock must be held and local IRQs must be disabled
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 107 * when {read,write}_zsreg is invoked.
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 108 */
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 109 static unsigned char read_zsreg(struct zilog_channel *channel,
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 110 unsigned char reg)
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 111 {
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 112 unsigned char retval;
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 113
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 @114 writeb(reg, &channel->control);
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 115 ZSDELAY();
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 @116 retval = readb(&channel->control);
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 117 ZSDELAY();
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 118
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 119 return retval;
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 120 }
^1da177e4c3f41 drivers/serial/ip22zilog.c Linus Torvalds 2005-04-16 121
:::::: The code at line 114 was first introduced by commit
:::::: 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Linux-2.6.12-rc2
:::::: TO: Linus Torvalds <torvalds@ppc970.osdl.org>
:::::: CC: Linus Torvalds <torvalds@ppc970.osdl.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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^ permalink raw reply
* RE: [PATCH] drm/amdgpu: load asd for sienna cichlid
From: Zhang, Hawking @ 2020-07-17 3:32 UTC (permalink / raw)
To: Clements, John, amd-gfx list
In-Reply-To: <MN2PR12MB4032A940BE0A5268028FFFFFFB7C0@MN2PR12MB4032.namprd12.prod.outlook.com>
[-- Attachment #1.1: Type: text/plain, Size: 405 bytes --]
[AMD Public Use]
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
From: Clements, John <John.Clements@amd.com>
Sent: Friday, July 17, 2020 11:04
To: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: load asd for sienna cichlid
[AMD Public Use]
Submitting patch to enable ASD loading for Sienna Cichlid
[-- Attachment #1.2: Type: text/html, Size: 3035 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply
* Re: [PATCH V2 1/6] vhost: introduce vhost_call_ctx
From: Jason Wang @ 2020-07-17 3:32 UTC (permalink / raw)
To: Zhu Lingshan, mst, alex.williamson, pbonzini,
sean.j.christopherson, wanpengli
Cc: virtualization, netdev, kvm
In-Reply-To: <1594898629-18790-2-git-send-email-lingshan.zhu@intel.com>
On 2020/7/16 下午7:23, Zhu Lingshan wrote:
> This commit introduces struct vhost_call_ctx which replaced
> raw struct eventfd_ctx *call_ctx in struct vhost_virtqueue.
> Besides eventfd_ctx, it contains a spin lock and an
> irq_bypass_producer in its structure.
>
> Signed-off-by: Zhu Lingshan <lingshan.zhu@intel.com>
> Suggested-by: Jason Wang <jasowang@redhat.com>
> ---
> drivers/vhost/vdpa.c | 4 ++--
> drivers/vhost/vhost.c | 22 ++++++++++++++++------
> drivers/vhost/vhost.h | 9 ++++++++-
> 3 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
> index 7580e34..2fcc422 100644
> --- a/drivers/vhost/vdpa.c
> +++ b/drivers/vhost/vdpa.c
> @@ -96,7 +96,7 @@ static void handle_vq_kick(struct vhost_work *work)
> static irqreturn_t vhost_vdpa_virtqueue_cb(void *private)
> {
> struct vhost_virtqueue *vq = private;
> - struct eventfd_ctx *call_ctx = vq->call_ctx;
> + struct eventfd_ctx *call_ctx = vq->call_ctx.ctx;
>
> if (call_ctx)
> eventfd_signal(call_ctx, 1);
> @@ -382,7 +382,7 @@ static long vhost_vdpa_vring_ioctl(struct vhost_vdpa *v, unsigned int cmd,
> break;
>
> case VHOST_SET_VRING_CALL:
> - if (vq->call_ctx) {
> + if (vq->call_ctx.ctx) {
> cb.callback = vhost_vdpa_virtqueue_cb;
> cb.private = vq;
> } else {
> diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
> index d7b8df3..4004e94 100644
> --- a/drivers/vhost/vhost.c
> +++ b/drivers/vhost/vhost.c
> @@ -298,6 +298,13 @@ static void vhost_vq_meta_reset(struct vhost_dev *d)
> __vhost_vq_meta_reset(d->vqs[i]);
> }
>
> +static void vhost_call_ctx_reset(struct vhost_call_ctx *call_ctx)
> +{
> + call_ctx->ctx = NULL;
> + memset(&call_ctx->producer, 0x0, sizeof(struct irq_bypass_producer));
> + spin_lock_init(&call_ctx->ctx_lock);
> +}
> +
> static void vhost_vq_reset(struct vhost_dev *dev,
> struct vhost_virtqueue *vq)
> {
> @@ -319,13 +326,13 @@ static void vhost_vq_reset(struct vhost_dev *dev,
> vq->log_base = NULL;
> vq->error_ctx = NULL;
> vq->kick = NULL;
> - vq->call_ctx = NULL;
> vq->log_ctx = NULL;
> vhost_reset_is_le(vq);
> vhost_disable_cross_endian(vq);
> vq->busyloop_timeout = 0;
> vq->umem = NULL;
> vq->iotlb = NULL;
> + vhost_call_ctx_reset(&vq->call_ctx);
> __vhost_vq_meta_reset(vq);
> }
>
> @@ -685,8 +692,8 @@ void vhost_dev_cleanup(struct vhost_dev *dev)
> eventfd_ctx_put(dev->vqs[i]->error_ctx);
> if (dev->vqs[i]->kick)
> fput(dev->vqs[i]->kick);
> - if (dev->vqs[i]->call_ctx)
> - eventfd_ctx_put(dev->vqs[i]->call_ctx);
> + if (dev->vqs[i]->call_ctx.ctx)
> + eventfd_ctx_put(dev->vqs[i]->call_ctx.ctx);
> vhost_vq_reset(dev, dev->vqs[i]);
> }
> vhost_dev_free_iovecs(dev);
> @@ -1629,7 +1636,10 @@ long vhost_vring_ioctl(struct vhost_dev *d, unsigned int ioctl, void __user *arg
> r = PTR_ERR(ctx);
> break;
> }
> - swap(ctx, vq->call_ctx);
> +
> + spin_lock(&vq->call_ctx.ctx_lock);
> + swap(ctx, vq->call_ctx.ctx);
> + spin_unlock(&vq->call_ctx.ctx_lock);
> break;
> case VHOST_SET_VRING_ERR:
> if (copy_from_user(&f, argp, sizeof f)) {
> @@ -2440,8 +2450,8 @@ static bool vhost_notify(struct vhost_dev *dev, struct vhost_virtqueue *vq)
> void vhost_signal(struct vhost_dev *dev, struct vhost_virtqueue *vq)
> {
> /* Signal the Guest tell them we used something up. */
> - if (vq->call_ctx && vhost_notify(dev, vq))
> - eventfd_signal(vq->call_ctx, 1);
> + if (vq->call_ctx.ctx && vhost_notify(dev, vq))
> + eventfd_signal(vq->call_ctx.ctx, 1);
> }
> EXPORT_SYMBOL_GPL(vhost_signal);
>
> diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
> index c8e96a0..402c62e 100644
> --- a/drivers/vhost/vhost.h
> +++ b/drivers/vhost/vhost.h
> @@ -13,6 +13,7 @@
> #include <linux/virtio_ring.h>
> #include <linux/atomic.h>
> #include <linux/vhost_iotlb.h>
> +#include <linux/irqbypass.h>
>
> struct vhost_work;
> typedef void (*vhost_work_fn_t)(struct vhost_work *work);
> @@ -60,6 +61,12 @@ enum vhost_uaddr_type {
> VHOST_NUM_ADDRS = 3,
> };
>
> +struct vhost_call_ctx {
I think maybe "vhost_vring_call" is a better name since it contains not
only the eventfd_ctx now.
Thanks
> + struct eventfd_ctx *ctx;
> + struct irq_bypass_producer producer;
> + spinlock_t ctx_lock;
> +};
> +
> /* The virtqueue structure describes a queue attached to a device. */
> struct vhost_virtqueue {
> struct vhost_dev *dev;
> @@ -72,7 +79,7 @@ struct vhost_virtqueue {
> vring_used_t __user *used;
> const struct vhost_iotlb_map *meta_iotlb[VHOST_NUM_ADDRS];
> struct file *kick;
> - struct eventfd_ctx *call_ctx;
> + struct vhost_call_ctx call_ctx;
> struct eventfd_ctx *error_ctx;
> struct eventfd_ctx *log_ctx;
>
^ permalink raw reply
* RE: [PATCH] drm/amdgpu: enable xgmi support for sienna cichlid
From: Zhang, Hawking @ 2020-07-17 3:31 UTC (permalink / raw)
To: Clements, John, amd-gfx list
In-Reply-To: <MN2PR12MB403253A79DD30D2BCF42B744FB7C0@MN2PR12MB4032.namprd12.prod.outlook.com>
[-- Attachment #1.1: Type: text/plain, Size: 417 bytes --]
[AMD Public Use]
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
From: Clements, John <John.Clements@amd.com>
Sent: Friday, July 17, 2020 11:05
To: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: enable xgmi support for sienna cichlid
[AMD Public Use]
Submitting patch to enable XGMI support for Sienna Cichlid
[-- Attachment #1.2: Type: text/html, Size: 3047 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply
* [dpdk-dev] [PATCH] net/ice: fix issue for GTPU and GTPU extension packet
From: Simei Su @ 2020-07-17 3:27 UTC (permalink / raw)
To: qi.z.zhang; +Cc: dev, jia.guo, Simei Su
Because of incomplete protocol header fields, GTPU_INNER_IPV4_UDP
and GTPU_INNER_IPV4_TCP profile aren't included in inner ipv4 group.
This patch complements header fields for GTPU/GTPU_EH ipv4 rss config.
Besides, after configuring L4 port, GTPU and GTPU_EH packets don't do
hash for UDP/TCP/SCTP. This patch also enables L4 hash for GTPU and GTPU
extension packets.
Fixes: d117de460035 ("net/ice: fix GTPU/PPPoE packets with no hash value")
Signed-off-by: Simei Su <simei.su@intel.com>
---
drivers/net/ice/ice_ethdev.c | 104 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 100 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 3534d18..7dd3fcd 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2524,13 +2524,25 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_IPV4) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
- ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ ICE_FLOW_SEG_HDR_GTPU_IP |
+ ICE_FLOW_SEG_HDR_IPV4 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
__func__, ret);
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
- ICE_FLOW_SEG_HDR_PPPOE, 0);
+ ICE_FLOW_SEG_HDR_GTPU_EH |
+ ICE_FLOW_SEG_HDR_IPV4 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
+ ICE_FLOW_SEG_HDR_PPPOE |
+ ICE_FLOW_SEG_HDR_IPV4 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
__func__, ret);
@@ -2538,13 +2550,25 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_IPV6) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
- ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ ICE_FLOW_SEG_HDR_GTPU_IP |
+ ICE_FLOW_SEG_HDR_IPV6 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
__func__, ret);
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
- ICE_FLOW_SEG_HDR_PPPOE, 0);
+ ICE_FLOW_SEG_HDR_GTPU_EH |
+ ICE_FLOW_SEG_HDR_IPV6 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
+ ICE_FLOW_SEG_HDR_PPPOE |
+ ICE_FLOW_SEG_HDR_IPV6 |
+ ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
__func__, ret);
@@ -2552,6 +2576,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
@@ -2560,6 +2596,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
@@ -2568,6 +2616,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
@@ -2576,6 +2636,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
@@ -2584,6 +2656,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV4,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV4,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_SCTP rss flow fail %d",
@@ -2592,6 +2676,18 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV6,
+ ICE_FLOW_SEG_HDR_GTPU_EH, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
+ __func__, ret);
+
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_SCTP_IPV6,
ICE_FLOW_SEG_HDR_PPPOE, 0);
if (ret)
PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_SCTP rss flow fail %d",
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH 1/1] clocksource: Ingenic: Add high resolution timer support for SMP/SMT.
From: Daniel Lezcano @ 2020-07-17 3:29 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), linux-kernel
Cc: tglx, hns, paul, dongsheng.qiu, aric.pzqi, sernia.zhou,
zhenwenjin, paul
In-Reply-To: <20200526162154.15443-3-zhouyanjie@wanyeetech.com>
On 26/05/2020 18:21, 周琰杰 (Zhou Yanjie) wrote:
> Enable clock event handling on per CPU core basis. Make sure that
> interrupts raised on the first core execute event handlers on the
> correct CPU core. This driver is required by Ingenic processors
> that support SMP/SMT, such as JZ4780 and X2000.
>
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [rdma:wip/jgg-for-rc] BUILD SUCCESS 87c4c774cbef5c68b3df96827c2fb07f1aa80152
From: kernel test robot @ 2020-07-17 3:28 UTC (permalink / raw)
To: Jason Gunthorpe; +Cc: linux-rdma, Doug Ledford
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git wip/jgg-for-rc
branch HEAD: 87c4c774cbef5c68b3df96827c2fb07f1aa80152 RDMA/cm: Protect access to remote_sidr_table
elapsed time: 723m
configs tested: 92
configs skipped: 1
The following configs have been built successfully.
More configs may be tested in the coming days.
arm defconfig
arm allyesconfig
arm allmodconfig
arm allnoconfig
arm64 allyesconfig
arm64 defconfig
arm64 allmodconfig
arm64 allnoconfig
i386 allnoconfig
i386 allyesconfig
i386 defconfig
i386 debian-10.3
ia64 allmodconfig
ia64 defconfig
ia64 allnoconfig
ia64 allyesconfig
m68k allmodconfig
m68k allnoconfig
m68k sun3_defconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
nios2 allyesconfig
openrisc defconfig
c6x allyesconfig
c6x allnoconfig
openrisc allyesconfig
nds32 defconfig
nds32 allnoconfig
csky allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
h8300 allmodconfig
xtensa defconfig
arc defconfig
arc allyesconfig
sh allmodconfig
sh allnoconfig
microblaze allnoconfig
mips allyesconfig
mips allnoconfig
mips allmodconfig
parisc allnoconfig
parisc defconfig
parisc allyesconfig
parisc allmodconfig
powerpc defconfig
powerpc allyesconfig
powerpc rhel-kconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a001-20200716
i386 randconfig-a005-20200716
i386 randconfig-a002-20200716
i386 randconfig-a006-20200716
i386 randconfig-a003-20200716
i386 randconfig-a004-20200716
x86_64 randconfig-a012-20200716
x86_64 randconfig-a011-20200716
x86_64 randconfig-a016-20200716
x86_64 randconfig-a014-20200716
x86_64 randconfig-a013-20200716
x86_64 randconfig-a015-20200716
i386 randconfig-a016-20200716
i386 randconfig-a011-20200716
i386 randconfig-a015-20200716
i386 randconfig-a012-20200716
i386 randconfig-a013-20200716
i386 randconfig-a014-20200716
riscv allyesconfig
riscv allnoconfig
riscv defconfig
riscv allmodconfig
s390 allyesconfig
s390 allnoconfig
s390 allmodconfig
s390 defconfig
sparc allyesconfig
sparc defconfig
sparc64 defconfig
sparc64 allnoconfig
sparc64 allyesconfig
sparc64 allmodconfig
x86_64 rhel-7.6-kselftests
x86_64 rhel-8.3
x86_64 kexec
x86_64 rhel
x86_64 lkp
x86_64 fedora-25
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [Intel-wired-lan] PROBLEM: [e1000e] 10% throughput drop on I219-LM after the buffer overrun fix even with TSO&GSO disabled
From: Shangshu Qian @ 2020-07-17 3:28 UTC (permalink / raw)
To: intel-wired-lan
[1.] One line summary of the problem:
[e1000e] 10% throughput drop on I219-LM after the buffer overrun fix even with TSO&GSO disabled
[2.] Full description of the problem/report:
With e1000e 3.6.2-k and 3.8.4-NAPI driver, which include the fix for the buffer overrun problem (https://github.com/torvalds/linux/commit/b10effb92e272051dd1ec0d7be56bf9ca85ab927, discussion: https://www.spinics.net/lists/netdev/msg460589.html), I219-LM network card have a 10% throughput drop in the iperf3 test (with TSO and GSO disabled) compared with the driver without such patch, and the client is initiating the stream in such test (iperf3 client mode without -R option). If the server is initiating the stream (with -R option in iperf3 client mode), the performance is not impacted.
That is to say, disabling TSO and GSO as suggested in that patch still have performance impact on the TCP stream, and the throughput drops about 10%.
I tried to rollback the patch introduced to fix the buffer overrun problem in the 3.8.4-NAPI driver, with TSO and GSO enabled, iperf3 test still cannot max out my 1Gbps uplink. However, with TSO and GSO disabled, 1Gbps uplink can be fully saturated.
I'll attach iperf3 test results for all these situations later in this email.
[3.] Keywords
Network driver, e1000e
[4.] Kernel information
[4.1.] Kernel version (from /proc/version):
Linux version 5.4.0-31-generic (buildd at lgw01-amd64-059) (gcc version 9.3.0 (Ubuntu 9.3.0-10ubuntu2)) #35-Ubuntu SMP Thu May 7 20:20:34 UTC 2020
[4.2.] Kernel .config file:
https://kernel.ubuntu.com/~kernel-ppa/config/focal/linux/5.4.0-31.35/amd64-config.flavour.generic
[5.] Most recent kernel version which did not have the bug:
V4.14.2
[6.] Environment
00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection (2) I219-LM (rev 31)
driver: e1000e
version: 3.2.6-k
firmware-version: 0.8-4
expansion-rom-version:
bus-info: 0000:00:1f.6
supports-statistics: yes
supports-test: yes
supports-eeprom-access: yes
supports-register-dump: yes
supports-priv-flags: no
iperf3:
iperf 3.7 (cJSON 1.5.2)
Linux Hetzner 5.4.0-31-generic #35-Ubuntu SMP Thu May 7 20:20:34 UTC 2020 x86_64
Optional features available: CPU affinity setting, IPv6 flow label, SCTP, TCP congestion algorithm setting, sendfile / zerocopy, socket pacing, authentication
[X.] Other notes, patches, fixes, workarounds:
3.6.2-k w/ TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 120 MBytes 101 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 119 MBytes 99.4 Mbits/sec receiver
[ 7] 0.00-10.00 sec 120 MBytes 101 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 119 MBytes 99.4 Mbits/sec receiver
[ 9] 0.00-10.00 sec 120 MBytes 101 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 119 MBytes 99.4 Mbits/sec receiver
[ 11] 0.00-10.00 sec 120 MBytes 101 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 119 MBytes 99.5 Mbits/sec receiver
[ 13] 0.00-10.00 sec 120 MBytes 101 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 119 MBytes 99.5 Mbits/sec receiver
[SUM] 0.00-10.00 sec 601 MBytes 504 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 594 MBytes 497 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.02 sec 351 MBytes 293 Mbits/sec 134 sender
[ 5] 0.00-10.00 sec 344 MBytes 289 Mbits/sec receiver
[ 7] 0.00-10.02 sec 204 MBytes 171 Mbits/sec 331 sender
[ 7] 0.00-10.00 sec 201 MBytes 168 Mbits/sec receiver
[ 9] 0.00-10.02 sec 174 MBytes 146 Mbits/sec 226 sender
[ 9] 0.00-10.00 sec 171 MBytes 144 Mbits/sec receiver
[ 11] 0.00-10.02 sec 177 MBytes 148 Mbits/sec 226 sender
[ 11] 0.00-10.00 sec 173 MBytes 145 Mbits/sec receiver
[ 13] 0.00-10.02 sec 164 MBytes 138 Mbits/sec 229 sender
[ 13] 0.00-10.00 sec 161 MBytes 135 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.04 GBytes 896 Mbits/sec 1146 sender
[SUM] 0.00-10.00 sec 1.03 GBytes 881 Mbits/sec receiver
3.6.2-k w/o TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 190 MBytes 159 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 188 MBytes 157 Mbits/sec receiver
[ 7] 0.00-10.00 sec 190 MBytes 160 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 188 MBytes 157 Mbits/sec receiver
[ 9] 0.00-10.00 sec 191 MBytes 160 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 188 MBytes 158 Mbits/sec receiver
[ 11] 0.00-10.00 sec 190 MBytes 160 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 188 MBytes 158 Mbits/sec receiver
[ 13] 0.00-10.00 sec 191 MBytes 160 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 188 MBytes 157 Mbits/sec receiver
[SUM] 0.00-10.00 sec 953 MBytes 799 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 940 MBytes 787 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.02 sec 256 MBytes 214 Mbits/sec 128 sender
[ 5] 0.00-10.00 sec 252 MBytes 211 Mbits/sec receiver
[ 7] 0.00-10.02 sec 238 MBytes 199 Mbits/sec 119 sender
[ 7] 0.00-10.00 sec 234 MBytes 196 Mbits/sec receiver
[ 9] 0.00-10.02 sec 166 MBytes 139 Mbits/sec 207 sender
[ 9] 0.00-10.00 sec 162 MBytes 136 Mbits/sec receiver
[ 11] 0.00-10.02 sec 222 MBytes 186 Mbits/sec 316 sender
[ 11] 0.00-10.00 sec 219 MBytes 184 Mbits/sec receiver
[ 13] 0.00-10.02 sec 225 MBytes 189 Mbits/sec 138 sender
[ 13] 0.00-10.00 sec 222 MBytes 186 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.08 GBytes 927 Mbits/sec 908 sender
[SUM] 0.00-10.00 sec 1.06 GBytes 913 Mbits/sec receiver
3.8.4-NAPI w/ TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 120 MBytes 100 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 117 MBytes 97.5 Mbits/sec receiver
[ 7] 0.00-10.00 sec 115 MBytes 96.4 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 114 MBytes 95.1 Mbits/sec receiver
[ 9] 0.00-10.00 sec 118 MBytes 98.9 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 117 MBytes 97.6 Mbits/sec receiver
[ 11] 0.00-10.00 sec 118 MBytes 99.3 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 117 MBytes 97.5 Mbits/sec receiver
[ 13] 0.00-10.00 sec 118 MBytes 99.3 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 116 MBytes 97.5 Mbits/sec receiver
[SUM] 0.00-10.00 sec 589 MBytes 494 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 580 MBytes 485 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.02 sec 289 MBytes 241 Mbits/sec 187 sender
[ 5] 0.00-10.00 sec 282 MBytes 236 Mbits/sec receiver
[ 7] 0.00-10.02 sec 355 MBytes 297 Mbits/sec 324 sender
[ 7] 0.00-10.00 sec 350 MBytes 293 Mbits/sec receiver
[ 9] 0.00-10.02 sec 144 MBytes 121 Mbits/sec 239 sender
[ 9] 0.00-10.00 sec 141 MBytes 118 Mbits/sec receiver
[ 11] 0.00-10.02 sec 136 MBytes 113 Mbits/sec 286 sender
[ 11] 0.00-10.00 sec 133 MBytes 111 Mbits/sec receiver
[ 13] 0.00-10.02 sec 188 MBytes 157 Mbits/sec 156 sender
[ 13] 0.00-10.00 sec 185 MBytes 155 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.09 GBytes 930 Mbits/sec 1192 sender
[SUM] 0.00-10.00 sec 1.06 GBytes 914 Mbits/sec receiver
3.8.4-NAPI w/o TSO & GSO
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 194 MBytes 163 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 192 MBytes 160 Mbits/sec receiver
[ 7] 0.00-10.00 sec 194 MBytes 163 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 192 MBytes 160 Mbits/sec receiver
[ 9] 0.00-10.00 sec 195 MBytes 163 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 192 MBytes 160 Mbits/sec receiver
[ 11] 0.00-10.00 sec 195 MBytes 163 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 192 MBytes 160 Mbits/sec receiver
[ 13] 0.00-10.00 sec 195 MBytes 163 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 192 MBytes 161 Mbits/sec receiver
[SUM] 0.00-10.00 sec 973 MBytes 816 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 958 MBytes 802 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.02 sec 499 MBytes 418 Mbits/sec 1208 sender
[ 5] 0.00-10.00 sec 487 MBytes 409 Mbits/sec receiver
[ 7] 0.00-10.02 sec 149 MBytes 125 Mbits/sec 262 sender
[ 7] 0.00-10.00 sec 146 MBytes 122 Mbits/sec receiver
[ 9] 0.00-10.02 sec 158 MBytes 132 Mbits/sec 199 sender
[ 9] 0.00-10.00 sec 154 MBytes 129 Mbits/sec receiver
[ 11] 0.00-10.02 sec 179 MBytes 149 Mbits/sec 209 sender
[ 11] 0.00-10.00 sec 175 MBytes 147 Mbits/sec receiver
[ 13] 0.00-10.02 sec 128 MBytes 107 Mbits/sec 386 sender
[ 13] 0.00-10.00 sec 125 MBytes 105 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.09 GBytes 931 Mbits/sec 2264 sender
[SUM] 0.00-10.00 sec 1.06 GBytes 912 Mbits/sec receiver
3.8.4-NAPI w/ TSO & GSO (Without buffer overrun patch)
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 204 MBytes 171 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 201 MBytes 169 Mbits/sec receiver
[ 7] 0.00-10.00 sec 203 MBytes 170 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 201 MBytes 168 Mbits/sec receiver
[ 9] 0.00-10.00 sec 205 MBytes 172 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 202 MBytes 169 Mbits/sec receiver
[ 11] 0.00-10.00 sec 204 MBytes 171 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 201 MBytes 169 Mbits/sec receiver
[ 13] 0.00-10.00 sec 204 MBytes 171 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 200 MBytes 168 Mbits/sec receiver
[SUM] 0.00-10.00 sec 1019 MBytes 855 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 1006 MBytes 842 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ 5] 0.00-10.02 sec 281 MBytes 235 Mbits/sec 128 sender
[ 5] 0.00-10.00 sec 277 MBytes 232 Mbits/sec receiver
[ 7] 0.00-10.02 sec 267 MBytes 223 Mbits/sec 154 sender
[ 7] 0.00-10.00 sec 263 MBytes 221 Mbits/sec receiver
[ 9] 0.00-10.02 sec 170 MBytes 142 Mbits/sec 154 sender
[ 9] 0.00-10.00 sec 166 MBytes 139 Mbits/sec receiver
[ 11] 0.00-10.02 sec 161 MBytes 135 Mbits/sec 211 sender
[ 11] 0.00-10.00 sec 158 MBytes 132 Mbits/sec receiver
[ 13] 0.00-10.02 sec 219 MBytes 183 Mbits/sec 116 sender
[ 13] 0.00-10.00 sec 216 MBytes 181 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.07 GBytes 919 Mbits/sec 763 sender
[SUM] 0.00-10.00 sec 1.05 GBytes 906 Mbits/sec receiver
3.8.4-NAPI w/o TSO & GSO (Without buffer overrun patch)
iperf3 -c bouygues.iperf.fr -d -P 5
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 220 MBytes 184 Mbits/sec 0 sender
[ 5] 0.00-10.02 sec 218 MBytes 182 Mbits/sec receiver
[ 7] 0.00-10.00 sec 220 MBytes 185 Mbits/sec 0 sender
[ 7] 0.00-10.02 sec 217 MBytes 182 Mbits/sec receiver
[ 9] 0.00-10.00 sec 216 MBytes 182 Mbits/sec 0 sender
[ 9] 0.00-10.02 sec 213 MBytes 179 Mbits/sec receiver
[ 11] 0.00-10.00 sec 220 MBytes 185 Mbits/sec 0 sender
[ 11] 0.00-10.02 sec 218 MBytes 182 Mbits/sec receiver
[ 13] 0.00-10.00 sec 221 MBytes 185 Mbits/sec 0 sender
[ 13] 0.00-10.02 sec 218 MBytes 182 Mbits/sec receiver
[SUM] 0.00-10.00 sec 1.07 GBytes 920 Mbits/sec 0 sender
[SUM] 0.00-10.02 sec 1.06 GBytes 907 Mbits/sec receiver
iperf3 -c bouygues.iperf.fr -d -P 5 -R
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.02 sec 259 MBytes 217 Mbits/sec 67 sender
[ 5] 0.00-10.00 sec 255 MBytes 214 Mbits/sec receiver
[ 7] 0.00-10.02 sec 256 MBytes 214 Mbits/sec 168 sender
[ 7] 0.00-10.00 sec 252 MBytes 212 Mbits/sec receiver
[ 9] 0.00-10.02 sec 260 MBytes 217 Mbits/sec 189 sender
[ 9] 0.00-10.00 sec 256 MBytes 215 Mbits/sec receiver
[ 11] 0.00-10.02 sec 165 MBytes 138 Mbits/sec 237 sender
[ 11] 0.00-10.00 sec 161 MBytes 135 Mbits/sec receiver
[ 13] 0.00-10.02 sec 172 MBytes 144 Mbits/sec 220 sender
[ 13] 0.00-10.00 sec 169 MBytes 142 Mbits/sec receiver
[SUM] 0.00-10.02 sec 1.08 GBytes 930 Mbits/sec 881 sender
[SUM] 0.00-10.00 sec 1.07 GBytes 917 Mbits/sec receiver
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^ permalink raw reply
* [PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route
structures.
This patch do nothing change, only do some codingstyle.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 674 +++++------------------------
1 file changed, 104 insertions(+), 570 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71a367896297..50558ffcc05c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -78,6 +78,9 @@ enum rockchip_pinctrl_type {
#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+#define RK_GENMASK_VAL(h, l, v) \
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -290,6 +293,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
+ { \
+ .bank_num = ID, \
+ .pin = PIN, \
+ .func = FUNC, \
+ .route_offset = REG, \
+ .route_val = VAL, \
+ .route_location = FLAG, \
+ }
+
+#define MR_SAME(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define MR_GRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define MR_PMU(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @num: bank number.
@@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
}
static struct rockchip_mux_route_data px30_mux_route_data[] = {
- {
- /* cif-d2m0 */
- .bank_num = 2,
- .pin = 0,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7),
- }, {
- /* cif-d2m1 */
- .bank_num = 3,
- .pin = 3,
- .func = 3,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* pdm-m0 */
- .bank_num = 3,
- .pin = 22,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8),
- }, {
- /* pdm-m1 */
- .bank_num = 2,
- .pin = 22,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart2-rxm0 */
- .bank_num = 1,
- .pin = 27,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10),
- }, {
- /* uart2-rxm1 */
- .bank_num = 2,
- .pin = 14,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* uart3-rxm0 */
- .bank_num = 0,
- .pin = 17,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9),
- }, {
- /* uart3-rxm1 */
- .bank_num = 1,
- .pin = 15,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */
+ MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */
+ MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */
+ MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */
+ MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */
+ MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */
+ MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */
+ MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */
};
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
- {
- /* spi-0 */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4),
- }, {
- /* spi-1 */
- .bank_num = 1,
- .pin = 27,
- .func = 3,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
- }, {
- /* spi-2 */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
- }, {
- /* i2s-0 */
- .bank_num = 1,
- .pin = 5,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5),
- }, {
- /* i2s-1 */
- .bank_num = 0,
- .pin = 14,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6),
- }, {
- /* emmc-1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6) | BIT(6),
- },
+ MR_SAME(1, 10, 1, 0x144, RK_GENMASK_VAL(4, 3, 0)), /* spi-0 */
+ MR_SAME(1, 27, 3, 0x144, RK_GENMASK_VAL(4, 3, 1)), /* spi-1 */
+ MR_SAME(0, 13, 2, 0x144, RK_GENMASK_VAL(4, 3, 2)), /* spi-2 */
+ MR_SAME(1, 5, 1, 0x144, RK_GENMASK_VAL(5, 5, 0)), /* i2s-0 */
+ MR_SAME(1, 14, 1, 0x144, RK_GENMASK_VAL(5, 5, 1)), /* i2s-1 */
+ MR_SAME(1, 22, 2, 0x144, RK_GENMASK_VAL(6, 6, 0)), /* emmc-0 */
+ MR_SAME(2, 4, 2, 0x144, RK_GENMASK_VAL(6, 6, 1)), /* emmc-1 */
};
static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
- {
- /* non-iomuxed emmc/flash pins on flash-dqs */
- .bank_num = 0,
- .pin = 24,
- .func = 1,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11),
- }, {
- /* non-iomuxed emmc/flash pins on emmc-clk */
- .bank_num = 0,
- .pin = 24,
- .func = 2,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ /* non-iomuxed emmc/flash pins on flash-dqs */
+ MR_GRF(0, 24, 1, 0xa0, RK_GENMASK_VAL(11, 11, 0)),
+ /* non-iomuxed emmc/flash pins on emmc-clk */
+ MR_GRF(0, 24, 2, 0xa0, RK_GENMASK_VAL(11, 11, 1)),
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
- {
- /* pwm0-0 */
- .bank_num = 0,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16),
- }, {
- /* pwm0-1 */
- .bank_num = 3,
- .pin = 21,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(0),
- }, {
- /* pwm1-0 */
- .bank_num = 0,
- .pin = 27,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1),
- }, {
- /* pwm1-1 */
- .bank_num = 0,
- .pin = 30,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1) | BIT(1),
- }, {
- /* pwm2-0 */
- .bank_num = 0,
- .pin = 28,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2),
- }, {
- /* pwm2-1 */
- .bank_num = 1,
- .pin = 12,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* pwm3-0 */
- .bank_num = 3,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pwm3-1 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* sdio-0_d0 */
- .bank_num = 1,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4),
- }, {
- /* sdio-1_d0 */
- .bank_num = 3,
- .pin = 2,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(4),
- }, {
- /* spi-0_rx */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5),
- }, {
- /* spi-1_rx */
- .bank_num = 2,
- .pin = 0,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0_cmd */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7),
- }, {
- /* emmc-1_cmd */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* uart2-0_rx */
- .bank_num = 1,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8),
- }, {
- /* uart2-1_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart1-0_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11),
- }, {
- /* uart1-1_rx */
- .bank_num = 3,
- .pin = 13,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ MR_SAME(0, 26, 1, 0x50, RK_GENMASK_VAL(0, 0, 0)), /* pwm0-0 */
+ MR_SAME(3, 21, 1, 0x50, RK_GENMASK_VAL(0, 0, 1)), /* pwm0-1 */
+ MR_SAME(0, 27, 1, 0x50, RK_GENMASK_VAL(1, 1, 0)), /* pwm1-0 */
+ MR_SAME(0, 30, 2, 0x50, RK_GENMASK_VAL(1, 1, 1)), /* pwm1-1 */
+ MR_SAME(0, 28, 1, 0x50, RK_GENMASK_VAL(2, 2, 0)), /* pwm2-0 */
+ MR_SAME(1, 12, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* pwm2-1 */
+ MR_SAME(3, 26, 1, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pwm3-0 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pwm3-1 */
+ MR_SAME(1, 1, 1, 0x50, RK_GENMASK_VAL(4, 4, 0)), /* sdio-0_d0 */
+ MR_SAME(3, 2, 1, 0x50, RK_GENMASK_VAL(4, 4, 1)), /* sdio-1_d0 */
+ MR_SAME(0, 13, 2, 0x50, RK_GENMASK_VAL(5, 5, 0)), /* spi-0_rx */
+ MR_SAME(2, 0, 2, 0x50, RK_GENMASK_VAL(5, 5, 1)), /* spi-1_rx */
+ MR_SAME(1, 22, 2, 0x50, RK_GENMASK_VAL(7, 7, 0)), /* emmc-0_cmd */
+ MR_SAME(2, 4, 2, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* emmc-1_cmd */
+ MR_SAME(1, 19, 2, 0x50, RK_GENMASK_VAL(8, 8, 0)), /* uart2-0_rx */
+ MR_SAME(1, 10, 2, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* uart2-1_rx */
+ MR_SAME(1, 10, 1, 0x50, RK_GENMASK_VAL(11, 11, 0)), /* uart1-0_rx */
+ MR_SAME(3, 13, 1, 0x50, RK_GENMASK_VAL(11, 11, 1)), /* uart1-1_rx */
};
static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
- {
- /* edphdmi_cecinoutt1 */
- .bank_num = 7,
- .pin = 16,
- .func = 2,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12) | BIT(12),
- }, {
- /* edphdmi_cecinout */
- .bank_num = 7,
- .pin = 23,
- .func = 4,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12),
- },
+ MR_SAME(7, 16, 2, 0x264, RK_GENMASK_VAL(12, 12, 1)), /* edphdmi_cecinoutt1 */
+ MR_SAME(7, 23, 4, 0x264, RK_GENMASK_VAL(12, 12, 0)), /* edphdmi_cecinout */
};
static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
- {
- /* rtc_clk */
- .bank_num = 0,
- .pin = 19,
- .func = 1,
- .route_offset = 0x314,
- .route_val = BIT(16 + 0) | BIT(0),
- }, {
- /* uart2_rxm0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3),
- }, {
- /* uart2_rxm1 */
- .bank_num = 4,
- .pin = 26,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
- }, {
- /* i2c3_sdam0 */
- .bank_num = 0,
- .pin = 15,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9),
- }, {
- /* i2c3_sdam1 */
- .bank_num = 3,
- .pin = 12,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
- }, {
- /* i2c3_sdam2 */
- .bank_num = 2,
- .pin = 0,
- .func = 3,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
- }, {
- /* i2s-8ch-1-sclktxm0 */
- .bank_num = 1,
- .pin = 3,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclkrxm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclktxm1 */
- .bank_num = 1,
- .pin = 13,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* i2s-8ch-1-sclkrxm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* pdm-clkm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 3,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* pdm-clkm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 4,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* pdm-clkm2 */
- .bank_num = 2,
- .pin = 6,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* pdm-clkm-m2 */
- .bank_num = 2,
- .pin = 4,
- .func = 3,
- .route_offset = 0x600,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* spi1_miso */
- .bank_num = 3,
- .pin = 10,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9),
- }, {
- /* spi1_miso_m1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9) | BIT(9),
- }, {
- /* owire_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* owire_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 7,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* owire_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* can_rxd_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* can_rxd_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* can_rxd_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* mac_rxd0_m0 */
- .bank_num = 1,
- .pin = 20,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14),
- }, {
- /* mac_rxd0_m1 */
- .bank_num = 4,
- .pin = 2,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14) | BIT(14),
- }, {
- /* uart3_rx */
- .bank_num = 3,
- .pin = 12,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15),
- }, {
- /* uart3_rx_m1 */
- .bank_num = 0,
- .pin = 17,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15) | BIT(15),
- },
+ MR_SAME(0, 19, 1, 0x314, RK_GENMASK_VAL(0, 0, 1)), /* rtc_clk */
+ MR_SAME(1, 22, 2, 0x314, RK_GENMASK_VAL(3, 2, 0)), /* uart2_rxm0 */
+ MR_SAME(4, 26, 2, 0x314, RK_GENMASK_VAL(3, 2, 1)), /* uart2_rxm1 */
+ MR_SAME(0, 15, 2, 0x608, RK_GENMASK_VAL(9, 8, 0)), /* i2c3_sdam0 */
+ MR_SAME(3, 12, 2, 0x608, RK_GENMASK_VAL(9, 8, 1)), /* i2c3_sdam1 */
+ MR_SAME(2, 0, 3, 0x608, RK_GENMASK_VAL(9, 8, 2)), /* i2c3_sdam2 */
+ MR_SAME(1, 3, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclktxm0 */
+ MR_SAME(1, 4, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclkrxm0 */
+ MR_SAME(1, 13, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclktxm1 */
+ MR_SAME(1, 14, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclkrxm1 */
+ MR_SAME(1, 4, 3, 0x308, RK_GENMASK_VAL(13, 12, 0)), /* pdm-clkm0 */
+ MR_SAME(1, 14, 4, 0x308, RK_GENMASK_VAL(13, 12, 1)), /* pdm-clkm1 */
+ MR_SAME(2, 6, 2, 0x308, RK_GENMASK_VAL(13, 12, 2)), /* pdm-clkm2 */
+ MR_SAME(2, 4, 3, 0x600, RK_GENMASK_VAL(2, 2, 1)), /* pdm-clkm-m2 */
+ MR_SAME(3, 10, 3, 0x314, RK_GENMASK_VAL(9, 9, 0)), /* spi1_miso */
+ MR_SAME(2, 4, 2, 0x314, RK_GENMASK_VAL(9, 9, 1)), /* spi1_miso_m1 */
+ MR_SAME(0, 11, 3, 0x314, RK_GENMASK_VAL(11, 10, 0)), /* owire_m0 */
+ MR_SAME(1, 22, 7, 0x314, RK_GENMASK_VAL(11, 10, 1)), /* owire_m1 */
+ MR_SAME(2, 2, 5, 0x314, RK_GENMASK_VAL(11, 10, 2)), /* owire_m2 */
+ MR_SAME(0, 11, 2, 0x314, RK_GENMASK_VAL(13, 12, 0)), /* can_rxd_m0 */
+ MR_SAME(1, 22, 5, 0x314, RK_GENMASK_VAL(13, 12, 1)), /* can_rxd_m1 */
+ MR_SAME(2, 2, 4, 0x314, RK_GENMASK_VAL(13, 12, 2)), /* can_rxd_m2 */
+ MR_SAME(1, 20, 3, 0x314, RK_GENMASK_VAL(14, 14, 0)), /* mac_rxd0_m0 */
+ MR_SAME(4, 2, 2, 0x314, RK_GENMASK_VAL(14, 14, 1)), /* mac_rxd0_m1 */
+ MR_SAME(3, 12, 4, 0x314, RK_GENMASK_VAL(15, 15, 0)), /* uart3_rx */
+ MR_SAME(0, 17, 3, 0x314, RK_GENMASK_VAL(15, 15, 1)), /* uart3_rx_m1 */
};
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
- {
- /* uart2dbg_rxm0 */
- .bank_num = 1,
- .pin = 1,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1),
- }, {
- /* uart2dbg_rxm1 */
- .bank_num = 2,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
- }, {
- /* gmac-m1_rxd0 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* gmac-m1-optimized_rxd3 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* pdm_sdi0m0 */
- .bank_num = 2,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pdm_sdi0m1 */
- .bank_num = 1,
- .pin = 23,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* spi_rxdm2 */
- .bank_num = 3,
- .pin = 2,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
- }, {
- /* i2s2_sdim0 */
- .bank_num = 1,
- .pin = 24,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6),
- }, {
- /* i2s2_sdim1 */
- .bank_num = 3,
- .pin = 2,
- .func = 6,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6) | BIT(6),
- }, {
- /* card_iom1 */
- .bank_num = 2,
- .pin = 22,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* tsp_d5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* cif_data5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(1, 1, 2, 0x50, RK_GENMASK_VAL(1, 0, 0)), /* uart2dbg_rxm0 */
+ MR_SAME(2, 1, 1, 0x50, RK_GENMASK_VAL(1, 0, 1)), /* uart2dbg_rxm1 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* gmac-m1_rxd0 */
+ MR_SAME(1, 14, 2, 0x50, RK_GENMASK_VAL(10, 10, 1)), /* gmac-m1-optimized_rxd3 */
+ MR_SAME(2, 19, 2, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pdm_sdi0m0 */
+ MR_SAME(1, 23, 3, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pdm_sdi0m1 */
+ MR_SAME(3, 2, 4, 0x50, RK_GENMASK_VAL(5, 4, 2)), /* spi_rxdm2 */
+ MR_SAME(1, 24, 1, 0x50, RK_GENMASK_VAL(6, 6, 0)), /* i2s2_sdim0 */
+ MR_SAME(3, 2, 6, 0x50, RK_GENMASK_VAL(6, 6, 1)), /* i2s2_sdim1 */
+ MR_SAME(2, 22, 3, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* card_iom1 */
+ MR_SAME(2, 16, 3, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* tsp_d5m1 */
+ MR_SAME(2, 16, 4, 0x50, RK_GENMASK_VAL(9, 9, 1)), /* cif_data5m1 */
};
static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
- {
- /* uart2dbga_rx */
- .bank_num = 4,
- .pin = 8,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* uart2dbgb_rx */
- .bank_num = 4,
- .pin = 16,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* uart2dbgc_rx */
- .bank_num = 4,
- .pin = 19,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* pcie_clkreqn */
- .bank_num = 2,
- .pin = 26,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14),
- }, {
- /* pcie_clkreqnb */
- .bank_num = 4,
- .pin = 24,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14) | BIT(14),
- },
+ MR_SAME(4, 8, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 0)), /* uart2dbga_rx */
+ MR_SAME(4, 16, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 1)), /* uart2dbgb_rx */
+ MR_SAME(4, 19, 1, 0xe21c, RK_GENMASK_VAL(11, 10, 2)), /* uart2dbgc_rx */
+ MR_SAME(2, 26, 2, 0xe21c, RK_GENMASK_VAL(14, 14, 0)), /* pcie_clkreqn */
+ MR_SAME(4, 24, 1, 0xe21c, RK_GENMASK_VAL(14, 14, 1)), /* pcie_clkreqnb */
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
--
2.17.1
^ permalink raw reply related
* [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
+#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
-#define RK3399_DRV_3BITS_PER_PIN 3
#define RK3399_PULL_BITS_PER_PIN 2
#define RK3399_PULL_PINS_PER_REG 8
#define RK3399_PULL_BANK_STRIDE 16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
--
2.17.1
^ permalink raw reply related
* [PATCH 11/13] pinctrl: rockchip: Add RK3128 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3128 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 04e7027ec8e1..3b74455dcdb2 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1799,6 +1799,8 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
};
#define RK3128_PULL_OFFSET 0x118
+#define RK3128_PULL_PINS_PER_REG 16
+#define RK3128_PULL_BANK_STRIDE 8
static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1808,10 +1810,10 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
- *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+ *bit = pin_num % RK3128_PULL_PINS_PER_REG;
}
#define RK3188_PULL_OFFSET 0x164
--
2.17.1
^ permalink raw reply related
* [PATCH 10/13] pinctrl: rockchip: Add RK3288 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3288 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ec6a1a08f8b1..04e7027ec8e1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3288_PULL_OFFSET 0x140
+#define RK3288_PULL_PMU_OFFSET 0x64
+#define RK3288_PULL_BITS_PER_PIN 2
+#define RK3288_PULL_PINS_PER_REG 8
+#define RK3288_PULL_BANK_STRIDE 16
+
static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
@@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
- *reg = RK3188_PULL_PMU_OFFSET;
+ *reg = RK3288_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_PULL_PINS_PER_REG;
+ *bit *= RK3288_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3288_PULL_PINS_PER_REG);
+ *bit *= RK3288_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 09/13] pinctrl: rockchip: Add RK3228 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3228 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 44f051af97c6..ec6a1a08f8b1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1918,6 +1918,9 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3228_PULL_OFFSET 0x100
+#define RK3228_PULL_BITS_PER_PIN 2
+#define RK3228_PULL_PINS_PER_REG 8
+#define RK3228_PULL_BANK_STRIDE 16
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1927,14 +1930,17 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3228_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3228_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3228_PULL_PINS_PER_REG);
+ *bit *= RK3228_PULL_BITS_PER_PIN;
}
#define RK3228_DRV_GRF_OFFSET 0x200
+#define RK3228_DRV_BITS_PER_PIN 2
+#define RK3228_DRV_PINS_PER_REG 8
+#define RK3228_DRV_BANK_STRIDE 16
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1944,11 +1950,11 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3228_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3228_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3228_DRV_PINS_PER_REG);
+ *bit *= RK3228_DRV_BITS_PER_PIN;
}
#define RK3308_PULL_OFFSET 0xa0
--
2.17.1
^ permalink raw reply related
* [PATCH 08/13] pinctrl: rockchip: Add RK3308 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:27 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3308 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 8e3fa9011165..44f051af97c6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1952,6 +1952,9 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3308_PULL_OFFSET 0xa0
+#define RK3308_PULL_BITS_PER_PIN 2
+#define RK3308_PULL_PINS_PER_REG 8
+#define RK3308_PULL_BANK_STRIDE 16
static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1961,14 +1964,17 @@ static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3308_PULL_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3308_PULL_PINS_PER_REG);
+ *bit *= RK3308_PULL_BITS_PER_PIN;
}
#define RK3308_DRV_GRF_OFFSET 0x100
+#define RK3308_DRV_BITS_PER_PIN 2
+#define RK3308_DRV_PINS_PER_REG 8
+#define RK3308_DRV_BANK_STRIDE 16
static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1978,11 +1984,11 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3308_DRV_GRF_OFFSET;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3308_DRV_PINS_PER_REG);
+ *bit *= RK3308_DRV_BITS_PER_PIN;
}
#define RK3368_PULL_GRF_OFFSET 0x100
--
2.17.1
^ permalink raw reply related
* [PATCH 07/13] pinctrl: rockchip: Add RK3368 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:26 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3368 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71335ed003b3..8e3fa9011165 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
+#define RK3368_PULL_BITS_PER_PIN 2
+#define RK3368_PULL_PINS_PER_REG 8
+#define RK3368_PULL_BANK_STRIDE 16
static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_PULL_PINS_PER_REG;
+ *bit *= RK3368_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_PULL_PINS_PER_REG);
+ *bit *= RK3368_PULL_BITS_PER_PIN;
}
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
+#define RK3368_DRV_BITS_PER_PIN 2
+#define RK3368_DRV_PINS_PER_REG 8
+#define RK3368_DRV_BANK_STRIDE 16
static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % RK3288_DRV_PINS_PER_REG;
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_DRV_PINS_PER_REG;
+ *bit *= RK3368_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_DRV_PINS_PER_REG);
+ *bit *= RK3368_DRV_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 06/13] pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:26 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3399 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
+#define RK3399_PULL_BITS_PER_PIN 2
+#define RK3399_PULL_PINS_PER_REG 8
+#define RK3399_PULL_BANK_STRIDE 16
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+ *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+ *bit *= RK3399_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
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