Re: [PATCH v5 12/12] drm/xe/vram: Report VRAM errors using structured xe_log API

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] xe: structured log location hardcoded to device instead of tile
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commit 21686fbec5b38511b4c76320b0afbe7eefda858f
Author: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

drm/xe/vram: Report VRAM errors using structured xe_log API

This commit replaces standard DRM log macros with structured xe_log API
functions in xe_vram.c. It intends to update the VRAM initialization path to
correctly report whether a "no CPU visible VRAM" error is at the tile or
device level depending on the caller's context.

> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 2441ffe77edb2..d44a92e97195d 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
[ ... ]
> @@ -254,8 +255,9 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
>  	vram->io_size = min_t(u64, usable_size, remain_io_size);
>  
>  	if (!vram->io_size) {
> -		drm_err(&xe->drm, "%s without any CPU visible VRAM. Aborting.\n",
> -			tile ? "Tile" : "Device");
> +		xe_log_err_fatal(xe, VRAM, -ENODEV,
> +				 "%s without any CPU visible VRAM. Aborting.\n",
> +				 tile ? "Tile" : "Device");

[Severity: Medium]
Is it possible that passing xe unconditionally here causes the telemetry
metadata to incorrectly tag tile-specific errors as device-level errors?

The xe_log API deduces the structured log location from the pointer type of its
first argument. By passing the struct xe_device *xe pointer unconditionally,
the telemetry location appears to be permanently recorded as a device-level
error, while only the human-readable string receives the tile context.

Could the first argument conditionally pass the tile pointer when it is
non-NULL to fulfill the commit message's intent?

>  		return -ENODEV;
>  	}
>

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Sashiko AI review · https://sashiko.dev/#/patchset/20261007211417.2093611-1-dnyaneshwar.bhadane@intel.com?part=12