* [PATCH v9 0/3] clk: add support for Airoha AN7583 clock
@ 2026-10-12 11:59 Christian Marangi
2026-10-12 11:59 ` [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for " Christian Marangi
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Christian Marangi @ 2026-10-12 11:59 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
This small series introduce some cleanup and support for
clock and reset of Airoha AN7583.
The implementation is similar to EN7581 but AN7583 introduce
new reset and more clock divisor support.
Changes v9:
- Fix compilation error for priv (again) (this time fixed)
Changes v8:
- Add ACK tag by Connor
- Fix missing priv->base assign
Changes v7:
- Add further info for DT patch
- Add serdes selection support
- Rebase on top of linux-next
Link: https://lore.kernel.org/all/20261009070725.13196-1-ansuelsmth@gmail.com/
Changes v6:
- Address bot suggestion for DT patch
- Add further information on chip-scu phandle
- Add dedicated PERSTOUT reset and PCIE_HB reset
Link: https://lore.kernel.org/all/20260819221458.30040-1-ansuelsmth@gmail.com/
Changes v5:
- Rebase on top of linux-next
- Drop even more patch to reduce patch delta
- Make chip-scu specific to AN7583
Link: https://lore.kernel.org/all/20260528190000.9164-1-ansuelsmth@gmail.com
Changes v4:
- Add review tag for DT patch
- Fix clock patch to use en7581-chip-scu compatible
- Drop PCIE SCU SSR write
Changes v3:
- Drop .set_rate patch (will be proposed later)
- Drop chip-scu binding and related patch
Link: https://lore.kernel.org/all/20251106195935.1767696-1-ansuelsmth@gmail.com
Changes v2:
- Add .set_rate support
- Rework DT to EN7581 implementation (clock driver is parent)
- Add additional cleanup patch
- Merge binding with schema patch
- Add chip_scu phandle
Christian Marangi (3):
dt-bindings: clock: airoha: Document support for AN7583 clock
clk: en7523: generalize register clocks function
clk: en7523: add support for Airoha AN7583 clock
.../bindings/clock/airoha,en7523-scu.yaml | 23 ++
drivers/clk/clk-en7523.c | 258 +++++++++++++++++-
include/dt-bindings/clock/en7523-clk.h | 3 +
.../dt-bindings/reset/airoha,an7583-reset.h | 65 +++++
4 files changed, 347 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for AN7583 clock
2026-10-12 11:59 [PATCH v9 0/3] clk: add support for Airoha AN7583 clock Christian Marangi
@ 2026-10-12 11:59 ` Christian Marangi
2026-10-12 12:06 ` sashiko-bot
2026-10-12 11:59 ` [PATCH v9 2/3] clk: en7523: generalize register clocks function Christian Marangi
2026-10-12 11:59 ` [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
2 siblings, 1 reply; 6+ messages in thread
From: Christian Marangi @ 2026-10-12 11:59 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi, Conor Dooley
Document support for Airoha AN7583 clock. This is based on the EN7523
clock schema with the new requirement of the "airoha,chip-scu".
The register for clock and reset for normal system and PCIe are scattered
between the "SCU" and "chip SCU" registers (they are 2 different register
block, the name is taken from the programming guide)
- Chip SCU provide register access to some clk gate and clk rate
- SCU provide register for reset, PCIe clock, other clock gate and PHY
SERDES.
Upcoming and current airoha clock driver all follow this pattern of
declaring one of the 2 register and use a sysconf for the other as the 2
register block are tighlty coupled.
EN7581 internally handle the syscon with a direct reference by the use of
syscon_regmap_lookup_by_compatible while AN7583 wants to make this
explicit in DT with the new "airoha,chip-scu" phandle.
Similar to EN7581, also AN7583 permit the selection of the serdes line.
Add additional binding for additional clock and reset lines.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/clock/airoha,en7523-scu.yaml | 23 +++++++
include/dt-bindings/clock/en7523-clk.h | 3 +
.../dt-bindings/reset/airoha,an7583-reset.h | 65 +++++++++++++++++++
3 files changed, 91 insertions(+)
create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
index fc37786ac7ed..8b94113d00ab 100644
--- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -31,6 +31,7 @@ properties:
compatible:
items:
- enum:
+ - airoha,an7583-scu
- airoha,en7523-scu
- airoha,en7581-scu
- econet,en751221-scu
@@ -57,12 +58,34 @@ properties:
available serdes port.
const: 1
+ airoha,chip-scu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the Chip SCU providing the registers required
+ for configuring the PCIe related clocks and resets.
+
required:
- compatible
- reg
- '#clock-cells'
allOf:
+ - if:
+ properties:
+ compatible:
+ const: airoha,an7583-scu
+
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - airoha,chip-scu
+
+ else:
+ properties:
+ airoha,chip-scu: false
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h
index edfa64045f52..0fbbcb7b1b25 100644
--- a/include/dt-bindings/clock/en7523-clk.h
+++ b/include/dt-bindings/clock/en7523-clk.h
@@ -14,4 +14,7 @@
#define EN7581_CLK_EMMC 8
+#define AN7583_CLK_MDIO0 9
+#define AN7583_CLK_MDIO1 10
+
#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-bindings/reset/airoha,an7583-reset.h
new file mode 100644
index 000000000000..410e19802cf7
--- /dev/null
+++ b/include/dt-bindings/reset/airoha,an7583-reset.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
+
+/* RST_CTRL2 */
+#define AN7583_XPON_PHY_RST 0
+#define AN7583_GPON_OLT_RST 1
+#define AN7583_CPU_TIMER2_RST 2
+#define AN7583_HSUART_RST 3
+#define AN7583_UART4_RST 4
+#define AN7583_UART5_RST 5
+#define AN7583_I2C2_RST 6
+#define AN7583_XSI_MAC_RST 7
+#define AN7583_XSI_PHY_RST 8
+#define AN7583_NPU_RST 9
+#define AN7583_TRNG_MSTART_RST 10
+#define AN7583_DUAL_HSI0_RST 11
+#define AN7583_DUAL_HSI1_RST 12
+#define AN7583_DUAL_HSI0_MAC_RST 13
+#define AN7583_DUAL_HSI1_MAC_RST 14
+#define AN7583_XPON_XFI_RST 15
+#define AN7583_WDMA_RST 16
+#define AN7583_WOE0_RST 17
+#define AN7583_HSDMA_RST 18
+#define AN7583_TDMA_RST 19
+#define AN7583_EMMC_RST 20
+#define AN7583_SOE_RST 21
+#define AN7583_XFP_MAC_RST 22
+#define AN7583_MDIO0_RST 23
+#define AN7583_MDIO1_RST 24
+/* RST_CTRL1 */
+#define AN7583_PCM1_ZSI_ISI_RST 25
+#define AN7583_FE_PDMA_RST 26
+#define AN7583_FE_QDMA_RST 27
+#define AN7583_PCM_SPIWP_RST 28
+#define AN7583_CRYPTO_RST 29
+#define AN7583_TIMER_RST 30
+#define AN7583_PCM1_RST 31
+#define AN7583_UART_RST 32
+#define AN7583_GPIO_RST 33
+#define AN7583_GDMA_RST 34
+#define AN7583_I2C_MASTER_RST 35
+#define AN7583_PCM2_ZSI_ISI_RST 36
+#define AN7583_SFC_RST 37
+#define AN7583_UART2_RST 38
+#define AN7583_GDMP_RST 39
+#define AN7583_FE_RST 40
+#define AN7583_USB_HOST_P0_RST 41
+#define AN7583_GSW_RST 42
+#define AN7583_SFC2_PCM_RST 43
+#define AN7583_PCIE0_RST 44
+#define AN7583_PCIE1_RST 45
+#define AN7583_CPU_TIMER_RST 46
+#define AN7583_PCIE_HB_RST 47
+#define AN7583_XPON_MAC_RST 48
+/* RST_PCIC */
+#define AN7583_PCIC_PERSTOUT0_RST 49
+#define AN7583_PCIC_PERSTOUT1_RST 50
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */
--
2.55.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v9 2/3] clk: en7523: generalize register clocks function
2026-10-12 11:59 [PATCH v9 0/3] clk: add support for Airoha AN7583 clock Christian Marangi
2026-10-12 11:59 ` [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for " Christian Marangi
@ 2026-10-12 11:59 ` Christian Marangi
2026-10-12 11:59 ` [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
2 siblings, 0 replies; 6+ messages in thread
From: Christian Marangi @ 2026-10-12 11:59 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to
register clocks. Generalize it to register clocks defined in soc_data.
Add the clocks definition in EN7581 SoC to support this new implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 24fdec2e6198..ec66a504d4c5 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -147,6 +147,7 @@ struct en_clk_priv {
struct en_clk_soc_data {
u32 num_clocks;
+ const struct en_clk_desc *base_clks;
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev,
struct clk_hw_onecell_data *clk_data);
@@ -745,12 +746,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
struct regmap *map, void __iomem *base)
{
+ const struct en_clk_soc_data *soc_data;
struct clk_hw *hw;
u32 rate;
int i;
- for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
- const struct en_clk_desc *desc = &en7581_base_clks[i];
+ soc_data = device_get_match_data(dev);
+
+ for (i = 0; i < soc_data->num_clocks - 1; i++) {
+ const struct en_clk_desc *desc = &soc_data->base_clks[i];
u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
int err;
@@ -1226,6 +1230,7 @@ static const struct en_clk_soc_data en7523_data = {
};
static const struct en_clk_soc_data en7581_data = {
+ .base_clks = en7581_base_clks,
/* We increment num_clocks by 1 to account for additional PCIe clock */
.num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
.pcie_ops = {
--
2.55.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock
2026-10-12 11:59 [PATCH v9 0/3] clk: add support for Airoha AN7583 clock Christian Marangi
2026-10-12 11:59 ` [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for " Christian Marangi
2026-10-12 11:59 ` [PATCH v9 2/3] clk: en7523: generalize register clocks function Christian Marangi
@ 2026-10-12 11:59 ` Christian Marangi
2026-10-12 12:29 ` sashiko-bot
2 siblings, 1 reply; 6+ messages in thread
From: Christian Marangi @ 2026-10-12 11:59 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
Add support for Airoha AN7583 clock and reset.
Airoha AN7583 SoC have the same register address of EN7581 but implement
different bits and additional base clocks. Also reset are different with
the introduction of 2 dedicated MDIO line and drop of some reset lines.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 249 +++++++++++++++++++++++++++++++++++++++
1 file changed, 249 insertions(+)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index ec66a504d4c5..92c88f140798 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -13,6 +13,7 @@
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/reset/airoha,an7583-reset.h>
#include <dt-bindings/reset/airoha,en7523-reset.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
#include <dt-bindings/clock/econet,en751221-scu.h>
@@ -166,6 +167,14 @@ static const u32 crypto_base[] = { 540000000, 480000000 };
static const u32 emmc7581_base[] = { 200000000, 150000000 };
/* EN751221 */
static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
+/* AN7583 */
+static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
+static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
+static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
+static const u32 spi7583_base[] = { 400000000, 12500000 };
+static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
+static const u32 crypto7583_base[] = { 540672000, 400000000 };
+static const u32 emmc7583_base[] = { 150000000, 200000000 };
static const struct en_clk_desc en7523_base_clks[] = {
{
@@ -368,6 +377,138 @@ static const struct en_clk_desc en7581_base_clks[] = {
}
};
+static const struct en_clk_desc an7583_base_clks[] = {
+ {
+ .id = EN7523_CLK_GSW,
+ .name = "gsw",
+
+ .base_reg = REG_GSW_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = gsw7583_base,
+ .n_base_values = ARRAY_SIZE(gsw7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_EMI,
+ .name = "emi",
+
+ .base_reg = REG_EMI_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = emi7583_base,
+ .n_base_values = ARRAY_SIZE(emi7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_BUS,
+ .name = "bus",
+
+ .base_reg = REG_BUS_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = bus7583_base,
+ .n_base_values = ARRAY_SIZE(bus7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_SLIC,
+ .name = "slic",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 1,
+ .base_values = slic_base,
+ .n_base_values = ARRAY_SIZE(slic_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 24,
+ .div_val0 = 20,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_SPI,
+ .name = "spi",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = spi7583_base,
+ .n_base_values = ARRAY_SIZE(spi7583_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 8,
+ .div_val0 = 40,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_NPU,
+ .name = "npu",
+
+ .base_reg = REG_NPU_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 9,
+ .base_values = npu7583_base,
+ .n_base_values = ARRAY_SIZE(npu7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_CRYPTO,
+ .name = "crypto",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = crypto7583_base,
+ .n_base_values = ARRAY_SIZE(crypto7583_base),
+ }, {
+ .id = EN7581_CLK_EMMC,
+ .name = "emmc",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+ .base_bits = 1,
+ .base_shift = 13,
+ .base_values = emmc7583_base,
+ .n_base_values = ARRAY_SIZE(emmc7583_base),
+ }, {
+ .id = AN7583_CLK_MDIO0,
+ .name = "mdio0",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+
+ .base_value = 25000000,
+
+ .div_bits = 4,
+ .div_shift = 15,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = AN7583_CLK_MDIO1,
+ .name = "mdio1",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+
+ .base_value = 25000000,
+
+ .div_bits = 4,
+ .div_shift = 19,
+ .div_step = 1,
+ .div_offset = 1,
+ }
+};
+
static const u16 en7581_rst_ofs[] = {
REG_RST_CTRL2,
REG_RST_CTRL1,
@@ -543,6 +684,64 @@ static const u16 en751221_rst_map[] = {
[EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
};
+static const u16 an7583_rst_map[] = {
+ /* RST_CTRL2 */
+ [AN7583_XPON_PHY_RST] = 0,
+ [AN7583_GPON_OLT_RST] = 1,
+ [AN7583_CPU_TIMER2_RST] = 2,
+ [AN7583_HSUART_RST] = 3,
+ [AN7583_UART4_RST] = 4,
+ [AN7583_UART5_RST] = 5,
+ [AN7583_I2C2_RST] = 6,
+ [AN7583_XSI_MAC_RST] = 7,
+ [AN7583_XSI_PHY_RST] = 8,
+ [AN7583_NPU_RST] = 9,
+ [AN7583_TRNG_MSTART_RST] = 12,
+ [AN7583_DUAL_HSI0_RST] = 13,
+ [AN7583_DUAL_HSI1_RST] = 14,
+ [AN7583_DUAL_HSI0_MAC_RST] = 16,
+ [AN7583_DUAL_HSI1_MAC_RST] = 17,
+ [AN7583_XPON_XFI_RST] = 18,
+ [AN7583_WDMA_RST] = 19,
+ [AN7583_WOE0_RST] = 20,
+ [AN7583_HSDMA_RST] = 22,
+ [AN7583_TDMA_RST] = 24,
+ [AN7583_EMMC_RST] = 25,
+ [AN7583_SOE_RST] = 26,
+ [AN7583_XFP_MAC_RST] = 28,
+ [AN7583_MDIO0_RST] = 30,
+ [AN7583_MDIO1_RST] = 31,
+ /* RST_CTRL1 */
+ [AN7583_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
+ [AN7583_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
+ [AN7583_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
+ [AN7583_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
+ [AN7583_CRYPTO_RST] = RST_NR_PER_BANK + 6,
+ [AN7583_TIMER_RST] = RST_NR_PER_BANK + 8,
+ [AN7583_PCM1_RST] = RST_NR_PER_BANK + 11,
+ [AN7583_UART_RST] = RST_NR_PER_BANK + 12,
+ [AN7583_GPIO_RST] = RST_NR_PER_BANK + 13,
+ [AN7583_GDMA_RST] = RST_NR_PER_BANK + 14,
+ [AN7583_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
+ [AN7583_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
+ [AN7583_SFC_RST] = RST_NR_PER_BANK + 18,
+ [AN7583_UART2_RST] = RST_NR_PER_BANK + 19,
+ [AN7583_GDMP_RST] = RST_NR_PER_BANK + 20,
+ [AN7583_FE_RST] = RST_NR_PER_BANK + 21,
+ [AN7583_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
+ [AN7583_GSW_RST] = RST_NR_PER_BANK + 23,
+ [AN7583_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
+ [AN7583_PCIE0_RST] = RST_NR_PER_BANK + 26,
+ [AN7583_PCIE1_RST] = RST_NR_PER_BANK + 27,
+ [AN7583_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
+ [AN7583_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
+ [AN7583_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
+
+ /* RST_PCIC */
+ [AN7583_PCIC_PERSTOUT0_RST] = 2 * RST_NR_PER_BANK + 29,
+ [AN7583_PCIC_PERSTOUT1_RST] = 2 * RST_NR_PER_BANK + 26,
+};
+
static int en7581_reset_register(struct device *dev, void __iomem *base,
const u16 *rst_map, int nr_resets,
const u16 *rst_reg_ofs);
@@ -1088,6 +1287,43 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
return en7581_serdes_phy_register(&pdev->dev);
}
+static int an7583_clk_hw_init(struct platform_device *pdev,
+ struct clk_hw_onecell_data *clk_data)
+{
+ struct en_clk_priv *priv = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ struct regmap *map;
+ void __iomem *base;
+ u32 val;
+ int ret;
+
+ map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu");
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->base = base;
+
+ en7581_register_clocks(dev, clk_data, map, base);
+
+ val = readl(base + REG_RST_CTRL1);
+ val |= REG_PCIE_HB_RST;
+ writel(val, base + REG_RST_CTRL1);
+ val &= ~REG_PCIE_HB_RST;
+ writel(val, base + REG_RST_CTRL1);
+
+ ret = en7581_reset_register(dev, base, an7583_rst_map,
+ ARRAY_SIZE(an7583_rst_map),
+ en7581_rst_ofs);
+ if (ret)
+ return ret;
+
+ return en7581_serdes_phy_register(dev);
+}
+
static enum en_hir get_hw_id(void __iomem *np_base)
{
u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
@@ -1241,6 +1477,18 @@ static const struct en_clk_soc_data en7581_data = {
.hw_init = en7581_clk_hw_init,
};
+static const struct en_clk_soc_data an7583_data = {
+ .base_clks = an7583_base_clks,
+ /* We increment num_clocks by 1 to account for additional PCIe clock */
+ .num_clocks = ARRAY_SIZE(an7583_base_clks) + 1,
+ .pcie_ops = {
+ .is_enabled = en7581_pci_is_enabled,
+ .enable = en7581_pci_enable,
+ .disable = en7581_pci_disable,
+ },
+ .hw_init = an7583_clk_hw_init,
+};
+
static const struct en_clk_soc_data en751221_data = {
.num_clocks = EN751221_MAX_CLKS,
.pcie_ops = {
@@ -1254,6 +1502,7 @@ static const struct en_clk_soc_data en751221_data = {
static const struct of_device_id of_match_clk_en7523[] = {
{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
+ { .compatible = "airoha,an7583-scu", .data = &an7583_data },
{ .compatible = "econet,en751221-scu", .data = &en751221_data },
{ /* sentinel */ }
};
--
2.55.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for AN7583 clock
2026-10-12 11:59 ` [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for " Christian Marangi
@ 2026-10-12 12:06 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-10-12 12:06 UTC (permalink / raw)
To: Christian Marangi; +Cc: conor+dt, robh, devicetree, linux-clk
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: missing #reset-cells and #phy-cells in required properties for airoha,an7583-scu
--
commit 538a7c87406554f4bcd77061661b7f96dc72a786
Author: Christian Marangi <ansuelsmth@gmail.com>
dt-bindings: clock: airoha: Document support for AN7583 clock
This commit documents support for the Airoha AN7583 clock, based on the
EN7523 schema. It adds the airoha,chip-scu phandle to make the separation
of SCU and chip SCU registers explicit, and introduces bindings for new
clock and reset lines.
> diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
> index fc37786ac7ed8..8b94113d00ab7 100644
> --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
> +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
[ ... ]
> @@ -57,12 +58,34 @@ properties:
> available serdes port.
> const: 1
>
> + airoha,chip-scu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle to the Chip SCU providing the registers required
> + for configuring the PCIe related clocks and resets.
> +
> required:
> - compatible
> - reg
> - '#clock-cells'
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + const: airoha,an7583-scu
> +
> + then:
> + properties:
> + reg:
> + maxItems: 1
> +
> + required:
> + - airoha,chip-scu
[Severity: Medium]
Does this list of required properties for the airoha,an7583-scu variant need
to include '#reset-cells' and '#phy-cells'?
Since this variant functions as a reset provider and permits PHY serdes
selection, omitting these from the required properties in this conditional
block could allow incomplete device tree nodes to pass schema validation.
> +
> + else:
> + properties:
> + airoha,chip-scu: false
> +
> - if:
> properties:
> compatible:
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261012115954.92718-1-ansuelsmth@gmail.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock
2026-10-12 11:59 ` [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
@ 2026-10-12 12:29 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-10-12 12:29 UTC (permalink / raw)
To: Christian Marangi; +Cc: robh, conor+dt, linux-clk, devicetree
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] clk: uaf and leak on probe error path due to unmanaged clock registration
- [High] clk: en7523: race condition in RMW operations on shared SCU registers
--
commit 8fb64358a2b708163ffd1fa2a6071fd191ad66a7
Author: Christian Marangi <ansuelsmth@gmail.com>
clk: en7523: add support for Airoha AN7583 clock
Add support for Airoha AN7583 clock and reset.
> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
> @@ -1088,6 +1287,43 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
> return en7581_serdes_phy_register(&pdev->dev);
> }
>
> +static int an7583_clk_hw_init(struct platform_device *pdev,
> + struct clk_hw_onecell_data *clk_data)
> +{
> + struct en_clk_priv *priv = platform_get_drvdata(pdev);
> + struct device *dev = &pdev->dev;
> + struct regmap *map;
> + void __iomem *base;
> + u32 val;
> + int ret;
> +
> + map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu");
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + priv->base = base;
> +
> + en7581_register_clocks(dev, clk_data, map, base);
> +
> + val = readl(base + REG_RST_CTRL1);
> + val |= REG_PCIE_HB_RST;
> + writel(val, base + REG_RST_CTRL1);
> + val &= ~REG_PCIE_HB_RST;
> + writel(val, base + REG_RST_CTRL1);
> +
> + ret = en7581_reset_register(dev, base, an7583_rst_map,
> + ARRAY_SIZE(an7583_rst_map),
> + en7581_rst_ofs);
> + if (ret)
> + return ret;
[Severity: High]
Does this early return path leak the fixed-rate clocks and cause a
use-after-free for the PCIe clock?
an7583_clk_hw_init() calls en7581_register_clocks(), which registers
fixed-rate clocks via clk_hw_register_fixed_rate() and a PCIe clock
via en7523_register_pcie_clk().
Looking at en7523_register_pcie_clk(), it allocates a struct en_clk_gate
using devm_kzalloc(), but registers it using the unmanaged
clk_hw_register().
If en7581_reset_register() fails here and we return early, the probe fails.
The devres framework will automatically free the devm_kzalloc'd
en_clk_gate structure. However, because the clock was not registered
with a managed API (like devm_clk_hw_register()), it remains linked in
the Common Clock Framework.
Can this cause a use-after-free when the framework later accesses this
clock, as well as a memory leak for the fixed-rate clocks?
[ ... ]
> @@ -1241,6 +1477,18 @@ static const struct en_clk_soc_data en7581_data = {
> .hw_init = en7581_clk_hw_init,
> };
>
> +static const struct en_clk_soc_data an7583_data = {
> + .base_clks = an7583_base_clks,
> + /* We increment num_clocks by 1 to account for additional PCIe clock */
> + .num_clocks = ARRAY_SIZE(an7583_base_clks) + 1,
> + .pcie_ops = {
> + .is_enabled = en7581_pci_is_enabled,
> + .enable = en7581_pci_enable,
> + .disable = en7581_pci_disable,
> + },
[Severity: High]
Is there a race condition here between the clock and reset operations
on shared SCU registers?
This struct assigns en7581_pci_enable() to the pcie_ops.enable callback.
Meanwhile, an7583_clk_hw_init() registers reset controls using
an7583_rst_map.
A driver invoking a clock operation could trigger en7581_pci_enable(),
while another execution context invoking a reset operation could trigger
en7523_reset_update().
Both of these operations appear to modify the exact same physical registers
(like REG_PCI_CONTROL/REG_NP_SCU_PCIC at 0x88 and
REG_RESET_CONTROL1/REG_RST_CTRL1 at 0x834) using unprotected readl() and
writel() read-modify-write sequences. Since they belong to different
frameworks, there is no shared lock protecting the state.
Could this cause data corruption of the SCU register state, leading to
lost clock enable/disable or reset assert/deassert updates?
> + .hw_init = an7583_clk_hw_init,
> +};
> +
> static const struct en_clk_soc_data en751221_data = {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261012115954.92718-1-ansuelsmth@gmail.com?part=3
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-12 12:29 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-12 11:59 [PATCH v9 0/3] clk: add support for Airoha AN7583 clock Christian Marangi
2026-10-12 11:59 ` [PATCH v9 1/3] dt-bindings: clock: airoha: Document support for " Christian Marangi
2026-10-12 12:06 ` sashiko-bot
2026-10-12 11:59 ` [PATCH v9 2/3] clk: en7523: generalize register clocks function Christian Marangi
2026-10-12 11:59 ` [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
2026-10-12 12:29 ` sashiko-bot
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