Re: [PATCH 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: missing bootph-pre-ram on pinctrl and regulator dependencies for SPL
--

commit 76ae02e32445137eb75156ac64fdd5ee85cb4ef0
Author: Hung-Chun Tseng <alan.tseng.cs@gmail.com>

riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

This patch adds the bootph-pre-ram property to I2C buses, board EEPROMs, PMICs,
and QSPI flashes on various SpacemiT K1 boards. These additions enable
U-Boot's SPL to access the devices during the early boot phase before
DRAM training.

> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
> index 81c40df2a3663..6269d2ba78ed0 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
> @@ -93,6 +95,7 @@ serial-number {
>  };
>  
>  &i2c8 {
> +	bootph-pre-ram;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&i2c8_cfg>;
>  	status = "okay";

[Severity: Medium]
Will this I2C pinmux setup fail in the SPL?

The I2C bus is marked for SPL, but the pin configuration node i2c8_cfg in
k1-pinctrl.dtsi and the base pinctrl controller pinctrl@d401e000 in k1.dtsi
both lack the bootph-pre-ram property.

U-Boot's fdtgrep will strip these unmarked nodes from the SPL device tree,
which will prevent the I2C pins from being multiplexed correctly.

> @@ -100,6 +103,7 @@ &i2c8 {
>  	pmic@41 {
>  		compatible = "spacemit,p1";
>  		reg = <0x41>;
> +		bootph-pre-ram;
>  		interrupts = <64>;
>  		vin1-supply = <&reg_vcc_4v>;
>  		vin2-supply = <&reg_vcc_4v>;

[Severity: Medium]
Will this PMIC probe fail in the SPL phase?

The PMIC relies on the reg_vcc_4v fixed regulator as its input supply, but
the reg_vcc_4v node was not marked with bootph-pre-ram.

Without this property, the fixed regulator will be excluded from the SPL
device tree, leading to dangling phandles and early boot probe failures for
the PMIC.

> diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
> index 635e95aad14a5..406b7ca163db8 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts

[ ... ]

> @@ -386,6 +393,7 @@ &qspi {
>  	flash@0 {
>  		compatible = "jedec,spi-nor";
>  		reg = <0>;
> +		bootph-pre-ram;
>  		spi-max-frequency = <26500000>;
>  		spi-rx-bus-width = <4>;
>  		spi-tx-bus-width = <4>;

[Severity: Medium]
Will this flash fail to operate during early boot?

The flash@0 node uses buck4_3v3 as its vcc-supply. While buck1 and buck3 were
marked with bootph-pre-ram in this patch, buck4_3v3 was omitted.

The missing property on buck4_3v3 will cause the supply node to be stripped
from the SPL device tree, breaking flash access before RAM is initialized.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012235624.77993-1-alan.tseng.cs@gmail.com?part=2