* [PATCH v3 0/7] riscv: Add device tree support for UltraRISC DP1000
@ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay
0 siblings, 0 replies; 28+ messages in thread
From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Conor Dooley
Add Devicetree support for the UltraRISC DP1000 RISC-V SoC and two
DP1000-based motherboards: Shenzhen Rongda M0 and Milk-V Titan.
DP1000 integrates eight UltraRISC CP100 CPU cores. The SoC description
includes the CPU and cache topology, CLINT, PLIC, clock controller,
pinctrl, GPIO, four UARTs, two SPI controllers, four I2C controllers,
three PCIe root complexes, GMAC, and the DMA controller.
The Shenzhen Rongda M0 and Milk-V Titan device trees add their
board-specific pin multiplexing, RTC devices, and Ethernet PHY
configuration. Both boards enable the three PCIe root complexes and
the GMAC described as disabled by default in the SoC DTS. The Titan
description also provides its GPIO wakeup keys.
The binding patches add the vendor, CPU, board, and peripheral compatible
strings consumed by the new device trees. The SPI, I2C, and AXI DMA nodes
use their respective generic DesignWare compatible strings as fallbacks.
An earlier version of the DP1000 SoC and board Devicetree support was
posted as part of a combined Devicetree and pinctrl series. The pinctrl
binding and driver were subsequently split out and merged separately.
This series carries the updated Devicetree portion.
Link: https://lore.kernel.org/all/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com/
The following prerequisites have been applied to their respective
subsystem trees but are not yet included in the base:
- net: stmmac: Add common internal RGMII delay handling and DP1000 support
https://lore.kernel.org/netdev/20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com/
- dt-bindings: i2c: dw: Add compatible for UltraRISC DP1000 SoC
https://patch.msgid.link/20260907-ultrarisc-dts-v2-6-5eb4c97477c5@ultrarisc.com
- dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible
https://patch.msgid.link/20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com
Testing:
- Built dp1000-shenrongda-m0.dtb and dp1000-milkv-titan.dtb with
ARCH=riscv and W=1.
- Ran dt_binding_check for the modified and prerequisite bindings.
- Validated both DTBs against the relevant Devicetree schemas with
CHECK_DTBS=y and all prerequisite changes applied.
- Boot-tested both DTBs on Shenzhen Rongda M0 and Milk-V Titan. Verified
the CPU topology and CBO selftests, UART, SPI, I2C/RTC, system memory,
and all three PCIe root complexes. The expected PCIe endpoints were
enumerated on both boards.
- With the prerequisite GMAC series applied, ultrarisc-dwmac established
1000 Mb/s full-duplex links with the YT8531S PHY on M0 and the RTL8211F
PHY on Titan.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com>
---
Changes in v3:
- Drop the DP1000 SPI binding patch, which has been merged, and the I2C
and DMA binding patches, which have been applied.
- Correct the reg property address ranges and sizes for DMA and I2C nodes in the DP1000 base device tree.
- Link to v2: https://patch.msgid.link/20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com
Changes in v2:
- Remove the dependency on the DP1000 clock series, which has since
been merged.
- Drop the generic DWMAC compatible patch; DP1000 GMAC support is handled
by a separate prerequisite series.
- Drop the RISC-V CPU binding yamllint fix, which has been applied.
- Add DP1000-specific resource constraints and hardware descriptions to
the SPI, I2C and DMA bindings.
- Correct the native chip-select count of SPI1 from three to four.
- Describe all eight per-channel DMA interrupts.
- Update the DP1000 GMAC nodes for the separate GMAC support series:
remove the generic DWMAC fallback, use "rgmii-id" for both boards, and
clarify the fixed MAC-side RGMII delays.
- Link to v1: https://patch.msgid.link/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Paul Walmsley <pjw@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>
To: Albert Ou <aou@eecs.berkeley.edu>
To: Alexandre Ghiti <alex@ghiti.fr>
To: Jia Wang <wangjia@ultrarisc.com>
To: Daniel Lezcano <daniel.lezcano@kernel.org>
To: Thomas Gleixner <tglx@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
To: Anup Patel <anup@brainfault.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org
---
Jia Wang (7):
dt-bindings: vendor-prefixes: Add shenrongda
dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible
dt-bindings: riscv: Add UltraRISC DP1000 board compatibles
dt-bindings: timer: Add UltraRISC DP1000 CLINT
riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree
riscv: dts: ultrarisc: Add Milk-V Titan board device tree
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/ultrarisc.yaml | 27 +
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/ultrarisc/Makefile | 3 +
.../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++
.../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++
arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++
.../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++
.../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++
arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 +++++++++++++++++++++
13 files changed, 1508 insertions(+)
---
base-commit: 704340f1cd0dcef829eb62f5b48ae95a2ce17bdf
change-id: 20260522-ultrarisc-dts-9dab3a2316b6
prerequisite-message-id: <20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com>
prerequisite-patch-id: 92e6cf1352d54e283d7721dc1542b580b8a41be1
prerequisite-patch-id: 875c2058e9d8a983d785d7447374758f994dc847
prerequisite-patch-id: 060a9b129c32c623a52ab1ba66f7a357e54575ff
prerequisite-patch-id: 9aafbac6d2531a378b2057bf57787c814523f9d3
prerequisite-patch-id: d75120a112276bd966d37441bd4d631e1539d0e8
prerequisite-patch-id: f526d36e1a4adb659a812fd4145dca2e69b19453
prerequisite-patch-id: 7d5e12085468dba34526d9047c62b357f874f91e
Best regards,
--
Xincheng Ji <jixincheng@ultrarisc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v3 0/7] riscv: Add device tree support for UltraRISC DP1000 @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley Add Devicetree support for the UltraRISC DP1000 RISC-V SoC and two DP1000-based motherboards: Shenzhen Rongda M0 and Milk-V Titan. DP1000 integrates eight UltraRISC CP100 CPU cores. The SoC description includes the CPU and cache topology, CLINT, PLIC, clock controller, pinctrl, GPIO, four UARTs, two SPI controllers, four I2C controllers, three PCIe root complexes, GMAC, and the DMA controller. The Shenzhen Rongda M0 and Milk-V Titan device trees add their board-specific pin multiplexing, RTC devices, and Ethernet PHY configuration. Both boards enable the three PCIe root complexes and the GMAC described as disabled by default in the SoC DTS. The Titan description also provides its GPIO wakeup keys. The binding patches add the vendor, CPU, board, and peripheral compatible strings consumed by the new device trees. The SPI, I2C, and AXI DMA nodes use their respective generic DesignWare compatible strings as fallbacks. An earlier version of the DP1000 SoC and board Devicetree support was posted as part of a combined Devicetree and pinctrl series. The pinctrl binding and driver were subsequently split out and merged separately. This series carries the updated Devicetree portion. Link: https://lore.kernel.org/all/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com/ The following prerequisites have been applied to their respective subsystem trees but are not yet included in the base: - net: stmmac: Add common internal RGMII delay handling and DP1000 support https://lore.kernel.org/netdev/20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com/ - dt-bindings: i2c: dw: Add compatible for UltraRISC DP1000 SoC https://patch.msgid.link/20260907-ultrarisc-dts-v2-6-5eb4c97477c5@ultrarisc.com - dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible https://patch.msgid.link/20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com Testing: - Built dp1000-shenrongda-m0.dtb and dp1000-milkv-titan.dtb with ARCH=riscv and W=1. - Ran dt_binding_check for the modified and prerequisite bindings. - Validated both DTBs against the relevant Devicetree schemas with CHECK_DTBS=y and all prerequisite changes applied. - Boot-tested both DTBs on Shenzhen Rongda M0 and Milk-V Titan. Verified the CPU topology and CBO selftests, UART, SPI, I2C/RTC, system memory, and all three PCIe root complexes. The expected PCIe endpoints were enumerated on both boards. - With the prerequisite GMAC series applied, ultrarisc-dwmac established 1000 Mb/s full-duplex links with the YT8531S PHY on M0 and the RTL8211F PHY on Titan. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com> --- Changes in v3: - Drop the DP1000 SPI binding patch, which has been merged, and the I2C and DMA binding patches, which have been applied. - Correct the reg property address ranges and sizes for DMA and I2C nodes in the DP1000 base device tree. - Link to v2: https://patch.msgid.link/20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com Changes in v2: - Remove the dependency on the DP1000 clock series, which has since been merged. - Drop the generic DWMAC compatible patch; DP1000 GMAC support is handled by a separate prerequisite series. - Drop the RISC-V CPU binding yamllint fix, which has been applied. - Add DP1000-specific resource constraints and hardware descriptions to the SPI, I2C and DMA bindings. - Correct the native chip-select count of SPI1 from three to four. - Describe all eight per-channel DMA interrupts. - Update the DP1000 GMAC nodes for the separate GMAC support series: remove the generic DWMAC fallback, use "rgmii-id" for both boards, and clarify the fixed MAC-side RGMII delays. - Link to v1: https://patch.msgid.link/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com To: Rob Herring <robh@kernel.org> To: Krzysztof Kozlowski <krzk+dt@kernel.org> To: Conor Dooley <conor+dt@kernel.org> To: Paul Walmsley <pjw@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com> To: Albert Ou <aou@eecs.berkeley.edu> To: Alexandre Ghiti <alex@ghiti.fr> To: Jia Wang <wangjia@ultrarisc.com> To: Daniel Lezcano <daniel.lezcano@kernel.org> To: Thomas Gleixner <tglx@kernel.org> To: Samuel Holland <samuel.holland@sifive.com> To: Anup Patel <anup@brainfault.org> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Conor Dooley <conor@kernel.org> Cc: linux-riscv@lists.infradead.org --- Jia Wang (7): dt-bindings: vendor-prefixes: Add shenrongda dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible dt-bindings: riscv: Add UltraRISC DP1000 board compatibles dt-bindings: timer: Add UltraRISC DP1000 CLINT riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree riscv: dts: ultrarisc: Add Milk-V Titan board device tree Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/ultrarisc.yaml | 27 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 8 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 3 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++ arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++ arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 +++++++++++++++++++++ 13 files changed, 1508 insertions(+) --- base-commit: 704340f1cd0dcef829eb62f5b48ae95a2ce17bdf change-id: 20260522-ultrarisc-dts-9dab3a2316b6 prerequisite-message-id: <20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com> prerequisite-patch-id: 92e6cf1352d54e283d7721dc1542b580b8a41be1 prerequisite-patch-id: 875c2058e9d8a983d785d7447374758f994dc847 prerequisite-patch-id: 060a9b129c32c623a52ab1ba66f7a357e54575ff prerequisite-patch-id: 9aafbac6d2531a378b2057bf57787c814523f9d3 prerequisite-patch-id: d75120a112276bd966d37441bd4d631e1539d0e8 prerequisite-patch-id: f526d36e1a4adb659a812fd4145dca2e69b19453 prerequisite-patch-id: 7d5e12085468dba34526d9047c62b357f874f91e Best regards, -- Xincheng Ji <jixincheng@ultrarisc.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 0/7] riscv: Add device tree support for UltraRISC DP1000 @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley Add Devicetree support for the UltraRISC DP1000 RISC-V SoC and two DP1000-based motherboards: Shenzhen Rongda M0 and Milk-V Titan. DP1000 integrates eight UltraRISC CP100 CPU cores. The SoC description includes the CPU and cache topology, CLINT, PLIC, clock controller, pinctrl, GPIO, four UARTs, two SPI controllers, four I2C controllers, three PCIe root complexes, GMAC, and the DMA controller. The Shenzhen Rongda M0 and Milk-V Titan device trees add their board-specific pin multiplexing, RTC devices, and Ethernet PHY configuration. Both boards enable the three PCIe root complexes and the GMAC described as disabled by default in the SoC DTS. The Titan description also provides its GPIO wakeup keys. The binding patches add the vendor, CPU, board, and peripheral compatible strings consumed by the new device trees. The SPI, I2C, and AXI DMA nodes use their respective generic DesignWare compatible strings as fallbacks. An earlier version of the DP1000 SoC and board Devicetree support was posted as part of a combined Devicetree and pinctrl series. The pinctrl binding and driver were subsequently split out and merged separately. This series carries the updated Devicetree portion. Link: https://lore.kernel.org/all/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com/ The following prerequisites have been applied to their respective subsystem trees but are not yet included in the base: - net: stmmac: Add common internal RGMII delay handling and DP1000 support https://lore.kernel.org/netdev/20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com/ - dt-bindings: i2c: dw: Add compatible for UltraRISC DP1000 SoC https://patch.msgid.link/20260907-ultrarisc-dts-v2-6-5eb4c97477c5@ultrarisc.com - dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible https://patch.msgid.link/20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com Testing: - Built dp1000-shenrongda-m0.dtb and dp1000-milkv-titan.dtb with ARCH=riscv and W=1. - Ran dt_binding_check for the modified and prerequisite bindings. - Validated both DTBs against the relevant Devicetree schemas with CHECK_DTBS=y and all prerequisite changes applied. - Boot-tested both DTBs on Shenzhen Rongda M0 and Milk-V Titan. Verified the CPU topology and CBO selftests, UART, SPI, I2C/RTC, system memory, and all three PCIe root complexes. The expected PCIe endpoints were enumerated on both boards. - With the prerequisite GMAC series applied, ultrarisc-dwmac established 1000 Mb/s full-duplex links with the YT8531S PHY on M0 and the RTL8211F PHY on Titan. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com> --- Changes in v3: - Drop the DP1000 SPI binding patch, which has been merged, and the I2C and DMA binding patches, which have been applied. - Correct the reg property address ranges and sizes for DMA and I2C nodes in the DP1000 base device tree. - Link to v2: https://patch.msgid.link/20260907-ultrarisc-dts-v2-0-5eb4c97477c5@ultrarisc.com Changes in v2: - Remove the dependency on the DP1000 clock series, which has since been merged. - Drop the generic DWMAC compatible patch; DP1000 GMAC support is handled by a separate prerequisite series. - Drop the RISC-V CPU binding yamllint fix, which has been applied. - Add DP1000-specific resource constraints and hardware descriptions to the SPI, I2C and DMA bindings. - Correct the native chip-select count of SPI1 from three to four. - Describe all eight per-channel DMA interrupts. - Update the DP1000 GMAC nodes for the separate GMAC support series: remove the generic DWMAC fallback, use "rgmii-id" for both boards, and clarify the fixed MAC-side RGMII delays. - Link to v1: https://patch.msgid.link/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com To: Rob Herring <robh@kernel.org> To: Krzysztof Kozlowski <krzk+dt@kernel.org> To: Conor Dooley <conor+dt@kernel.org> To: Paul Walmsley <pjw@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com> To: Albert Ou <aou@eecs.berkeley.edu> To: Alexandre Ghiti <alex@ghiti.fr> To: Jia Wang <wangjia@ultrarisc.com> To: Daniel Lezcano <daniel.lezcano@kernel.org> To: Thomas Gleixner <tglx@kernel.org> To: Samuel Holland <samuel.holland@sifive.com> To: Anup Patel <anup@brainfault.org> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Conor Dooley <conor@kernel.org> Cc: linux-riscv@lists.infradead.org --- Jia Wang (7): dt-bindings: vendor-prefixes: Add shenrongda dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible dt-bindings: riscv: Add UltraRISC DP1000 board compatibles dt-bindings: timer: Add UltraRISC DP1000 CLINT riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree riscv: dts: ultrarisc: Add Milk-V Titan board device tree Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/ultrarisc.yaml | 27 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 8 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 3 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++ arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++ arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 +++++++++++++++++++++ 13 files changed, 1508 insertions(+) --- base-commit: 704340f1cd0dcef829eb62f5b48ae95a2ce17bdf change-id: 20260522-ultrarisc-dts-9dab3a2316b6 prerequisite-message-id: <20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com> prerequisite-patch-id: 92e6cf1352d54e283d7721dc1542b580b8a41be1 prerequisite-patch-id: 875c2058e9d8a983d785d7447374758f994dc847 prerequisite-patch-id: 060a9b129c32c623a52ab1ba66f7a357e54575ff prerequisite-patch-id: 9aafbac6d2531a378b2057bf57787c814523f9d3 prerequisite-patch-id: d75120a112276bd966d37441bd4d631e1539d0e8 prerequisite-patch-id: f526d36e1a4adb659a812fd4145dca2e69b19453 prerequisite-patch-id: 7d5e12085468dba34526d9047c62b357f874f91e Best regards, -- Xincheng Ji <jixincheng@ultrarisc.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 1/7] dt-bindings: vendor-prefixes: Add shenrongda 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ba2002969373..e100f3993e57 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1507,6 +1507,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenrongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 1/7] dt-bindings: vendor-prefixes: Add shenrongda @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ba2002969373..e100f3993e57 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1507,6 +1507,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenrongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 1/7] dt-bindings: vendor-prefixes: Add shenrongda @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ba2002969373..e100f3993e57 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1507,6 +1507,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenrongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the UltraRISC CP100 CPU compatible. The CP100 CPU is used in the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 0da219ae6769..85adf72899c9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the UltraRISC CP100 CPU compatible. The CP100 CPU is used in the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 0da219ae6769..85adf72899c9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the UltraRISC CP100 CPU compatible. The CP100 CPU is used in the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 0da219ae6769..85adf72899c9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the compatibles for the Shenzhen Rongda M0 and Milk-V Titan boards, both based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++++++ MAINTAINERS | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..a51e63dbeca3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index ff1c1aea9a98..7eb1b2971bea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23639,6 +23639,13 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang <wangjia@ultrarisc.com> +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> M: Jack Wang <jinpu.wang@ionos.com> -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the compatibles for the Shenzhen Rongda M0 and Milk-V Titan boards, both based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++++++ MAINTAINERS | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..a51e63dbeca3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index ff1c1aea9a98..7eb1b2971bea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23639,6 +23639,13 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang <wangjia@ultrarisc.com> +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> M: Jack Wang <jinpu.wang@ionos.com> -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Document the compatibles for the Shenzhen Rongda M0 and Milk-V Titan boards, both based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++++++ MAINTAINERS | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..a51e63dbeca3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index ff1c1aea9a98..7eb1b2971bea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23639,6 +23639,13 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang <wangjia@ultrarisc.com> +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> M: Jack Wang <jinpu.wang@ionos.com> -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add compatible string for UltraRISC DP1000 CLINT. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..878f267d089b 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add compatible string for UltraRISC DP1000 CLINT. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..878f267d089b 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv, Conor Dooley From: Jia Wang <wangjia@ultrarisc.com> Add compatible string for UltraRISC DP1000 CLINT. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..878f267d089b 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals including CLINT, PLIC, the clock controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC, and the DMA controller. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com> --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 ++++++++++++++++++++++++++++++ 2 files changed, 900 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7eb1b2971bea..a97926dadba4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23645,6 +23645,7 @@ L: linux-riscv@lists.infradead.org S: Supported T: git https://github.com/ultrarisc/linux.git F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..86d7f5533aa8 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/clock/ultrarisc,dp1000-clk.h> + +/ { + compatible = "ultrarisc,dp1000"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + cpu0: cpu@0 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x0>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache0>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache0: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x1>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache1>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache1: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x2>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache2>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache2: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x3>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache3>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache3: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x10>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache4>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache4: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x11>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache5>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache5: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x12>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache6>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache6: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x13>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache7>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache7: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + /* + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <4>; + cache-size = <0x1000000>; + cache-sets = <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clint: clint@8000000 { + compatible = "ultrarisc,dp1000-clint", "sifive,clint0"; + reg = <0x0 0x8000000 0x0 0x100000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg = <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10>, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev = <160>; + }; + + clkc: clock-controller@11080000 { + compatible = "ultrarisc,dp1000-clk"; + reg = <0x0 0x11080000 0x0 0x1000>; + clocks = <&osc_24m>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x20200000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "bus", "db"; + clocks = <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <16>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&plic>; + interrupts = <34>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20300000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <17>; + clocks = <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart1: serial@20310000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20310000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <18>; + clocks = <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart2: serial@20400000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20400000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <25>; + clocks = <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart3: serial@20410000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20410000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <26>; + clocks = <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + spi0: spi@20320000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <19>; + num-cs = <3>; + }; + + spi1: spi@20420000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <27>; + num-cs = <4>; + }; + + i2c0: i2c@20330000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20330000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <20>; + }; + + i2c1: i2c@20340000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20340000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <21>; + }; + + i2c2: i2c@20430000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20430000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <28>; + }; + + i2c3: i2c@20440000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20440000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <29>; + }; + + pcie_x16: pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status = "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <63>, <64>, <65>, <66>, <67>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status = "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <73>, <74>, <75>, <76>, <77>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status = "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20"; + reg = <0x0 0x38000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_GMAC>; + clock-names = "stmmaceth"; + interrupt-parent = <&plic>; + interrupts = <84>; + interrupt-names = "macirq"; + snps,txpbl = <8>; + snps,rxpbl = <8>; + + status = "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible = "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x39000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_SYSPLL_DIV2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <8>; + interrupt-parent = <&plic>; + interrupts = <152>, <153>, <154>, <155>, + <156>, <157>, <158>, <159>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <512 512 512 512 512 512 512 512>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len = <256>; + }; + }; +}; -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals including CLINT, PLIC, the clock controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC, and the DMA controller. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com> --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 ++++++++++++++++++++++++++++++ 2 files changed, 900 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7eb1b2971bea..a97926dadba4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23645,6 +23645,7 @@ L: linux-riscv@lists.infradead.org S: Supported T: git https://github.com/ultrarisc/linux.git F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..86d7f5533aa8 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/clock/ultrarisc,dp1000-clk.h> + +/ { + compatible = "ultrarisc,dp1000"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + cpu0: cpu@0 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x0>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache0>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache0: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x1>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache1>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache1: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x2>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache2>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache2: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x3>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache3>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache3: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x10>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache4>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache4: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x11>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache5>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache5: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x12>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache6>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache6: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x13>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache7>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache7: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + /* + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <4>; + cache-size = <0x1000000>; + cache-sets = <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clint: clint@8000000 { + compatible = "ultrarisc,dp1000-clint", "sifive,clint0"; + reg = <0x0 0x8000000 0x0 0x100000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg = <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10>, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev = <160>; + }; + + clkc: clock-controller@11080000 { + compatible = "ultrarisc,dp1000-clk"; + reg = <0x0 0x11080000 0x0 0x1000>; + clocks = <&osc_24m>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x20200000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "bus", "db"; + clocks = <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <16>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&plic>; + interrupts = <34>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20300000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <17>; + clocks = <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart1: serial@20310000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20310000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <18>; + clocks = <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart2: serial@20400000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20400000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <25>; + clocks = <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart3: serial@20410000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20410000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <26>; + clocks = <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + spi0: spi@20320000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <19>; + num-cs = <3>; + }; + + spi1: spi@20420000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <27>; + num-cs = <4>; + }; + + i2c0: i2c@20330000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20330000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <20>; + }; + + i2c1: i2c@20340000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20340000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <21>; + }; + + i2c2: i2c@20430000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20430000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <28>; + }; + + i2c3: i2c@20440000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20440000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <29>; + }; + + pcie_x16: pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status = "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <63>, <64>, <65>, <66>, <67>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status = "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <73>, <74>, <75>, <76>, <77>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status = "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20"; + reg = <0x0 0x38000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_GMAC>; + clock-names = "stmmaceth"; + interrupt-parent = <&plic>; + interrupts = <84>; + interrupt-names = "macirq"; + snps,txpbl = <8>; + snps,rxpbl = <8>; + + status = "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible = "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x39000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_SYSPLL_DIV2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <8>; + interrupt-parent = <&plic>; + interrupts = <152>, <153>, <154>, <155>, + <156>, <157>, <158>, <159>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <512 512 512 512 512 512 512 512>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len = <256>; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals including CLINT, PLIC, the clock controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC, and the DMA controller. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Xincheng Ji <jixincheng@ultrarisc.com> --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 ++++++++++++++++++++++++++++++ 2 files changed, 900 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7eb1b2971bea..a97926dadba4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23645,6 +23645,7 @@ L: linux-riscv@lists.infradead.org S: Supported T: git https://github.com/ultrarisc/linux.git F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..86d7f5533aa8 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/clock/ultrarisc,dp1000-clk.h> + +/ { + compatible = "ultrarisc,dp1000"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + cpu0: cpu@0 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x0>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache0>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache0: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x1>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache1>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache1: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x2>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache2>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache2: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x3>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache3>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache3: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x10>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache4>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache4: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x11>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache5>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache5: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x12>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache6>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache6: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x13>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache7>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache7: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + /* + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <4>; + cache-size = <0x1000000>; + cache-sets = <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clint: clint@8000000 { + compatible = "ultrarisc,dp1000-clint", "sifive,clint0"; + reg = <0x0 0x8000000 0x0 0x100000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg = <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10>, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev = <160>; + }; + + clkc: clock-controller@11080000 { + compatible = "ultrarisc,dp1000-clk"; + reg = <0x0 0x11080000 0x0 0x1000>; + clocks = <&osc_24m>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x20200000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "bus", "db"; + clocks = <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <16>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&plic>; + interrupts = <34>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20300000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <17>; + clocks = <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart1: serial@20310000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20310000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <18>; + clocks = <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart2: serial@20400000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20400000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <25>; + clocks = <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart3: serial@20410000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20410000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <26>; + clocks = <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + spi0: spi@20320000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <19>; + num-cs = <3>; + }; + + spi1: spi@20420000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <27>; + num-cs = <4>; + }; + + i2c0: i2c@20330000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20330000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <20>; + }; + + i2c1: i2c@20340000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20340000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <21>; + }; + + i2c2: i2c@20430000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20430000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <28>; + }; + + i2c3: i2c@20440000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20440000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <29>; + }; + + pcie_x16: pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status = "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <63>, <64>, <65>, <66>, <67>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status = "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <73>, <74>, <75>, <76>, <77>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status = "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20"; + reg = <0x0 0x38000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_GMAC>; + clock-names = "stmmaceth"; + interrupt-parent = <&plic>; + interrupts = <84>; + interrupt-names = "macirq"; + snps,txpbl = <8>; + snps,rxpbl = <8>; + + status = "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible = "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x39000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_SYSPLL_DIV2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <8>; + interrupt-parent = <&plic>; + interrupts = <152>, <153>, <154>, <155>, + <156>, <157>, <158>, <159>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <512 512 512 512 512 512 512 512>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len = <256>; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v3 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) (?) @ 2026-10-13 10:36 ` sashiko-bot -1 siblings, 0 replies; 28+ messages in thread From: sashiko-bot @ 2026-10-13 10:36 UTC (permalink / raw) To: Xincheng Ji; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] dts: L2 cache nodes are incorrectly nested as children of cpu nodes -- commit 72d6d58d85f9aab9e46d9c7167175451c2551346 Author: Jia Wang <wangjia@ultrarisc.com> riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals. > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi > new file mode 100644 > index 0000000000000..86d7f5533aa84 > --- /dev/null > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi > @@ -0,0 +1,899 @@ [ ... ] > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <10000000>; > + > + cpu0: cpu@0 { > + compatible = "ultrarisc,cp100", "riscv"; [ ... ] > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + l2_cache0: l2-cache { [Severity: Medium] Does this incorrectly nest the L2 cache nodes as children of the cpu nodes? Standard Devicetree topologies for CPU schemas require cache nodes to be defined as siblings under the /cpus node or globally, rather than as direct children of the cpu nodes. Instantiating l2-cache here can cause dt_binding_check validation failures and break generic kernel cache topology parsers that expect the cache nodes at the root of /cpus and referenced via the next-level-cache phandle. Should these cache nodes be moved outside of the cpu@0 node? > + /* > + * L2 cache: > + * cache-unified, block-size 64B > + * 8-way set associative, size 512KB > + * per-core. > + */ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-size = <0x80000>; > + cache-sets = <1024>; > + cache-unified; > + next-level-cache = <&cluster0_l3>; > + }; > + }; [ ... ] > + cpu4: cpu@10 { > + compatible = "ultrarisc,cp100", "riscv"; [ ... ] > + cpu4_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + l2_cache4: l2-cache { [Severity: Medium] The same structural error appears to be repeated across all CPU nodes in the cluster. Could these cache nodes be moved outside their respective cpu nodes as well? > + /* > + * L2 cache: > + * cache-unified, block-size 64B > + * 8-way set associative, size 512KB -- Sashiko AI review · https://sashiko.dev/#/patchset/20261013-ultrarisc-dts-v3-0-5ff3ebb2a90d@ultrarisc.com?part=5 ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++++++++++++++++++++ 5 files changed, 258 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y += spacemit subdir-y += starfive subdir-y += tenstorrent subdir-y += thead +subdir-y += ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile new file mode 100644 index 000000000000..454d849a6ce4 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 000000000000..4668e45d2335 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif /* _DP1000_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..ab927c6cd614 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 000000000000..43f713bcea25 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Shenzhen Rongda M0 Board"; + compatible = "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + }; + }; +}; -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++++++++++++++++++++ 5 files changed, 258 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y += spacemit subdir-y += starfive subdir-y += tenstorrent subdir-y += thead +subdir-y += ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile new file mode 100644 index 000000000000..454d849a6ce4 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 000000000000..4668e45d2335 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif /* _DP1000_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..ab927c6cd614 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 000000000000..43f713bcea25 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Shenzhen Rongda M0 Board"; + compatible = "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++++++++++++++++++++ 5 files changed, 258 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y += spacemit subdir-y += starfive subdir-y += tenstorrent subdir-y += thead +subdir-y += ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile new file mode 100644 index 000000000000..454d849a6ce4 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 000000000000..4668e45d2335 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif /* _DP1000_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..ab927c6cd614 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 000000000000..43f713bcea25 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Shenzhen Rongda M0 Board"; + compatible = "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay -1 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++++++++++++++++++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile index 454d849a6ce4..dfd15c064d07 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..7a812e40a249 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + io_pins: io-pins { + pins = <PA10 PA15 PB0 PB1 PB2 PD6 PD7>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins = <PA4 PA11 PA14>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins = <PA5>; + function = "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins = <PA6>; + function = "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins = <PA7>; + function = "gpio"; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..59edd8157221 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Milk-V Titan"; + compatible = "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-wakeup-0 { + label = "Wake-Up"; + gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-1 { + label = "Power"; + gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-2 { + label = "Wake-Up-by-USB"; + interrupts-extended = <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins>; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "uart0-mux"; + }; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + label = "eth-link"; + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_INDICATOR; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + + led@2 { + label = "eth-activity"; + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++++++++++++++++++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile index 454d849a6ce4..dfd15c064d07 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..7a812e40a249 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + io_pins: io-pins { + pins = <PA10 PA15 PB0 PB1 PB2 PD6 PD7>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins = <PA4 PA11 PA14>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins = <PA5>; + function = "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins = <PA6>; + function = "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins = <PA7>; + function = "gpio"; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..59edd8157221 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Milk-V Titan"; + compatible = "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-wakeup-0 { + label = "Wake-Up"; + gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-1 { + label = "Power"; + gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-2 { + label = "Wake-Up-by-USB"; + interrupts-extended = <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins>; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "uart0-mux"; + }; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + label = "eth-link"; + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_INDICATOR; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + + led@2 { + label = "eth-activity"; + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree @ 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 0 siblings, 0 replies; 28+ messages in thread From: Xincheng Ji via B4 Relay @ 2026-10-13 10:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Jia Wang, Xincheng Ji, Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt, Conor Dooley, linux-riscv From: Jia Wang <wangjia@ultrarisc.com> Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++++++++++++++++++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile index 454d849a6ce4..dfd15c064d07 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..7a812e40a249 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + io_pins: io-pins { + pins = <PA10 PA15 PB0 PB1 PB2 PD6 PD7>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins = <PA4 PA11 PA14>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins = <PA5>; + function = "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins = <PA6>; + function = "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins = <PA7>; + function = "gpio"; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..59edd8157221 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Milk-V Titan"; + compatible = "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-wakeup-0 { + label = "Wake-Up"; + gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-1 { + label = "Power"; + gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-2 { + label = "Wake-Up-by-USB"; + interrupts-extended = <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins>; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "uart0-mux"; + }; +}; + +ðernet { + phy-handle = <&phy0>; + /* + * The PCB does not add RGMII TX or RX clock delays. The DP1000 + * integration adds fixed delays in both directions. + */ + phy-mode = "rgmii-id"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + label = "eth-link"; + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_INDICATOR; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + + led@2 { + label = "eth-activity"; + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree 2026-10-13 10:21 ` Xincheng Ji via B4 Relay (?) (?) @ 2026-10-13 10:31 ` sashiko-bot 2026-10-13 17:34 ` Conor Dooley -1 siblings, 1 reply; 28+ messages in thread From: sashiko-bot @ 2026-10-13 10:31 UTC (permalink / raw) To: Xincheng Ji; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] dts: incorrect RGMII phy-mode causes double clock delay -- commit 471320732fb47362c8b5d5e16472052117a95204 Author: Jia Wang <wangjia@ultrarisc.com> riscv: dts: ultrarisc: Add Milk-V Titan board device tree This commit introduces the device tree for the Milk-V Titan board, an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts > new file mode 100644 > index 0000000000000..59edd8157221a > --- /dev/null > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts [ ... ] > +ðernet { > + phy-handle = <&phy0>; > + /* > + * The PCB does not add RGMII TX or RX clock delays. The DP1000 > + * integration adds fixed delays in both directions. > + */ > + phy-mode = "rgmii-id"; [Severity: Medium] The comment notes that the DP1000 integration already adds fixed delays in both directions. When the MAC or SoC natively provides the RGMII delays, shouldn't phy-mode be set to "rgmii" instead of "rgmii-id"? Setting it to "rgmii-id" instructs the PHY to insert its own internal delays as well, which might result in a double-delayed link. This combination could shift the clock outside the valid data window, leading to link failures or dropped packets. > + > + status = "okay"; > + -- Sashiko AI review · https://sashiko.dev/#/patchset/20261013-ultrarisc-dts-v3-0-5ff3ebb2a90d@ultrarisc.com?part=7 ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree 2026-10-13 10:31 ` sashiko-bot @ 2026-10-13 17:34 ` Conor Dooley 2026-10-13 18:08 ` Andrew Lunn 0 siblings, 1 reply; 28+ messages in thread From: Conor Dooley @ 2026-10-13 17:34 UTC (permalink / raw) To: sashiko-reviews; +Cc: Xincheng Ji, devicetree, robh, conor+dt, Andrew Lunn [-- Attachment #1: Type: text/plain, Size: 1931 bytes --] +CC Andrew Lunn <andrew@lunn.ch> On Tue, Oct 13, 2026 at 10:31:35AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] dts: incorrect RGMII phy-mode causes double clock delay > -- > > commit 471320732fb47362c8b5d5e16472052117a95204 > Author: Jia Wang <wangjia@ultrarisc.com> > > riscv: dts: ultrarisc: Add Milk-V Titan board device tree > > This commit introduces the device tree for the Milk-V Titan board, an ITX > motherboard based on the UltraRISC DP1000 SoC. > > Link: https://milkv.io/docs/titan/overview > > > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts > > new file mode 100644 > > index 0000000000000..59edd8157221a > > --- /dev/null > > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts > > [ ... ] > > > +ðernet { > > + phy-handle = <&phy0>; > > + /* > > + * The PCB does not add RGMII TX or RX clock delays. The DP1000 > > + * integration adds fixed delays in both directions. > > + */ > > + phy-mode = "rgmii-id"; > > [Severity: Medium] > The comment notes that the DP1000 integration already adds fixed delays in > both directions. When the MAC or SoC natively provides the RGMII delays, > shouldn't phy-mode be set to "rgmii" instead of "rgmii-id"? > > Setting it to "rgmii-id" instructs the PHY to insert its own internal delays > as well, which might result in a double-delayed link. This combination could > shift the clock outside the valid data window, leading to link failures or > dropped packets. You previously commented on this stuff, are you okay with what's currently here? Thanks, Conor. > > > + > > + status = "okay"; > > + > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20261013-ultrarisc-dts-v3-0-5ff3ebb2a90d@ultrarisc.com?part=7 [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree 2026-10-13 17:34 ` Conor Dooley @ 2026-10-13 18:08 ` Andrew Lunn 0 siblings, 0 replies; 28+ messages in thread From: Andrew Lunn @ 2026-10-13 18:08 UTC (permalink / raw) To: Conor Dooley; +Cc: sashiko-reviews, Xincheng Ji, devicetree, robh, conor+dt On Tue, Oct 13, 2026 at 06:34:28PM +0100, Conor Dooley wrote: > +CC Andrew Lunn <andrew@lunn.ch> > > On Tue, Oct 13, 2026 at 10:31:35AM +0000, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > > - [Medium] dts: incorrect RGMII phy-mode causes double clock delay > > -- > > > > commit 471320732fb47362c8b5d5e16472052117a95204 > > Author: Jia Wang <wangjia@ultrarisc.com> > > > > riscv: dts: ultrarisc: Add Milk-V Titan board device tree > > > > This commit introduces the device tree for the Milk-V Titan board, an ITX > > motherboard based on the UltraRISC DP1000 SoC. > > > > Link: https://milkv.io/docs/titan/overview > > > > > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts > > > new file mode 100644 > > > index 0000000000000..59edd8157221a > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts > > > > [ ... ] > > > > > +ðernet { > > > + phy-handle = <&phy0>; > > > + /* > > > + * The PCB does not add RGMII TX or RX clock delays. The DP1000 > > > + * integration adds fixed delays in both directions. > > > + */ > > > + phy-mode = "rgmii-id"; If the PCB does not add delays, rgmii-id is correct. What is important is how the MAC driver handles this, it needs to mask the value passed to the PHY. Assuming this has been tested on real hardware, it probably does. Andrew ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2026-10-13 18:08 UTC | newest] Thread overview: 28+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-13 10:21 [PATCH v3 0/7] riscv: Add device tree support for UltraRISC DP1000 Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 1/7] dt-bindings: vendor-prefixes: Add shenrongda Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:36 ` sashiko-bot 2026-10-13 10:21 ` [PATCH v3 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:21 ` [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan " Xincheng Ji via B4 Relay 2026-10-13 10:21 ` Xincheng Ji 2026-10-13 10:21 ` Xincheng Ji via B4 Relay 2026-10-13 10:31 ` sashiko-bot 2026-10-13 17:34 ` Conor Dooley 2026-10-13 18:08 ` Andrew Lunn
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