* [PATCH v2 0/2] Manage the PCIe supplies with pwrctrl @ 2026-10-29 2:40 ` Shawn Lin 0 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin The Rockchip PCIe host controller describes a single vpcie3v3 supply on the controller node to power whatever is plugged into the slot. That is enough for a board that only ever has one device there, but it cannot express per-device supplies, and it does not fit boards where the slot power is owned by a separate power sequencing or switch device. This series switches the pcie-dw-rockchip driver to the generic PCI pwrctrl framework, which lets the supplies of the devices below a host controller be described in their own DT nodes and be enabled before the PHY is initialized. Patch 1 makes the driver create and power on the pwrctrl devices below the controller ahead of the PHY init. The controller level vpcie3v3 supply is kept for backward compatibility, so existing boards keep working unchanged. Patch 2 moves the supply of the RK3588 EVB1 slot into a child node that describes the slot as a PCI bridge. Changes in v2: - Select PCI_PWRCTRL_GENERIC from PCIE_ROCKCHIP_DW, so that the built-in controller driver cannot end up with undefined pci_pwrctrl_* references when the pwrctrl core is a module(sashiko) - Do not destroy the pwrctrl devices on -EPROBE_DEFER, so that the deferred child devices can still bind and retrigger the probe(sashiko) Shawn Lin (2): PCI: dw-rockchip: Power on devices below the RC using pwrctrl arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply .../boot/dts/rockchip/rk3588-evb1-v10.dts | 14 +++++++- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 32 ++++++++++++++++--- 3 files changed, 42 insertions(+), 5 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 0/2] Manage the PCIe supplies with pwrctrl @ 2026-10-29 2:40 ` Shawn Lin 0 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin The Rockchip PCIe host controller describes a single vpcie3v3 supply on the controller node to power whatever is plugged into the slot. That is enough for a board that only ever has one device there, but it cannot express per-device supplies, and it does not fit boards where the slot power is owned by a separate power sequencing or switch device. This series switches the pcie-dw-rockchip driver to the generic PCI pwrctrl framework, which lets the supplies of the devices below a host controller be described in their own DT nodes and be enabled before the PHY is initialized. Patch 1 makes the driver create and power on the pwrctrl devices below the controller ahead of the PHY init. The controller level vpcie3v3 supply is kept for backward compatibility, so existing boards keep working unchanged. Patch 2 moves the supply of the RK3588 EVB1 slot into a child node that describes the slot as a PCI bridge. Changes in v2: - Select PCI_PWRCTRL_GENERIC from PCIE_ROCKCHIP_DW, so that the built-in controller driver cannot end up with undefined pci_pwrctrl_* references when the pwrctrl core is a module(sashiko) - Do not destroy the pwrctrl devices on -EPROBE_DEFER, so that the deferred child devices can still bind and retrigger the probe(sashiko) Shawn Lin (2): PCI: dw-rockchip: Power on devices below the RC using pwrctrl arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply .../boot/dts/rockchip/rk3588-evb1-v10.dts | 14 +++++++- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 32 ++++++++++++++++--- 3 files changed, 42 insertions(+), 5 deletions(-) -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/2] PCI: dw-rockchip: Power on devices below the RC using pwrctrl 2026-10-29 2:40 ` Shawn Lin @ 2026-10-29 2:40 ` Shawn Lin -1 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin Devices below the Rockchip PCIe host controller may need resources (regulators, clocks) enabled before they can be detected on the bus. So far the driver only enabled a single vpcie3v3 supply described by the controller node itself, which cannot express per-device or per-slot supplies. Use the PCI pwrctrl framework: before initializing the PHY, create the pwrctrl devices for the DT nodes below the controller and power them on. The supplies of the slot must be up before PHY init, so this has to run ahead of rockchip_pcie_phy_init(). The controller node supply is kept for backward compatibility: boards that still describe vpcie3v3 on the controller keep working, and boards that move the supply into a child node get it enabled by pwrctrl. Only the RC mode is affected, the endpoint does not own the supplies of the devices below it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v2: - Select PCI_PWRCTRL_GENERIC from PCIE_ROCKCHIP_DW, so that the built-in controller driver cannot end up with undefined pci_pwrctrl_* references when the pwrctrl core is a module(sashiko) - Do not destroy the pwrctrl devices on -EPROBE_DEFER, so that the deferred child devices can still bind and retrigger the probe(sashiko) drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 32 ++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0a0d56fcf0ac..8e74a756271a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -368,6 +368,7 @@ config PCIE_RCAR_GEN4_EP config PCIE_ROCKCHIP_DW bool + select PCI_PWRCTRL_GENERIC config PCIE_ROCKCHIP_DW_HOST bool "Rockchip DesignWare PCIe controller (host mode)" diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index bd86e32cc2b1..4263181f63f5 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -19,6 +19,7 @@ #include <linux/of.h> #include <linux/of_irq.h> #include <linux/phy/phy.h> +#include <linux/pci-pwrctrl.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -841,16 +842,33 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Power on the devices described below this controller before the PHY + * is initialized: the slot supplies must be up before PHY init. + */ + if (data->mode == DW_PCIE_RC_TYPE) { + ret = pci_pwrctrl_create_devices(dev); + if (ret) + return dev_err_probe(dev, ret, + "failed to create pwrctrl devices\n"); + + ret = pci_pwrctrl_power_on_devices(dev); + if (ret) { + if (ret != -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(dev); + return dev_err_probe(dev, ret, + "failed to power on pwrctrl devices\n"); + } + } + /* DON'T MOVE ME: must be enable before PHY init */ ret = devm_regulator_get_enable_optional(dev, "vpcie3v3"); if (ret < 0 && ret != -ENODEV) - return dev_err_probe(dev, ret, - "failed to enable vpcie3v3 regulator\n"); + goto err_pwrctrl_off; ret = rockchip_pcie_phy_init(rockchip); if (ret) - return dev_err_probe(dev, ret, - "failed to initialize the phy\n"); + goto err_pwrctrl_off; ret = reset_control_deassert(rockchip->rst); if (ret) @@ -883,6 +901,12 @@ static int rockchip_pcie_probe(struct platform_device *pdev) clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); deinit_phy: rockchip_pcie_phy_deinit(rockchip); +err_pwrctrl_off: + if (data->mode == DW_PCIE_RC_TYPE) { + pci_pwrctrl_power_off_devices(dev); + if (ret != -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(dev); + } return ret; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 1/2] PCI: dw-rockchip: Power on devices below the RC using pwrctrl @ 2026-10-29 2:40 ` Shawn Lin 0 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin Devices below the Rockchip PCIe host controller may need resources (regulators, clocks) enabled before they can be detected on the bus. So far the driver only enabled a single vpcie3v3 supply described by the controller node itself, which cannot express per-device or per-slot supplies. Use the PCI pwrctrl framework: before initializing the PHY, create the pwrctrl devices for the DT nodes below the controller and power them on. The supplies of the slot must be up before PHY init, so this has to run ahead of rockchip_pcie_phy_init(). The controller node supply is kept for backward compatibility: boards that still describe vpcie3v3 on the controller keep working, and boards that move the supply into a child node get it enabled by pwrctrl. Only the RC mode is affected, the endpoint does not own the supplies of the devices below it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v2: - Select PCI_PWRCTRL_GENERIC from PCIE_ROCKCHIP_DW, so that the built-in controller driver cannot end up with undefined pci_pwrctrl_* references when the pwrctrl core is a module(sashiko) - Do not destroy the pwrctrl devices on -EPROBE_DEFER, so that the deferred child devices can still bind and retrigger the probe(sashiko) drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 32 ++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0a0d56fcf0ac..8e74a756271a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -368,6 +368,7 @@ config PCIE_RCAR_GEN4_EP config PCIE_ROCKCHIP_DW bool + select PCI_PWRCTRL_GENERIC config PCIE_ROCKCHIP_DW_HOST bool "Rockchip DesignWare PCIe controller (host mode)" diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index bd86e32cc2b1..4263181f63f5 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -19,6 +19,7 @@ #include <linux/of.h> #include <linux/of_irq.h> #include <linux/phy/phy.h> +#include <linux/pci-pwrctrl.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -841,16 +842,33 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Power on the devices described below this controller before the PHY + * is initialized: the slot supplies must be up before PHY init. + */ + if (data->mode == DW_PCIE_RC_TYPE) { + ret = pci_pwrctrl_create_devices(dev); + if (ret) + return dev_err_probe(dev, ret, + "failed to create pwrctrl devices\n"); + + ret = pci_pwrctrl_power_on_devices(dev); + if (ret) { + if (ret != -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(dev); + return dev_err_probe(dev, ret, + "failed to power on pwrctrl devices\n"); + } + } + /* DON'T MOVE ME: must be enable before PHY init */ ret = devm_regulator_get_enable_optional(dev, "vpcie3v3"); if (ret < 0 && ret != -ENODEV) - return dev_err_probe(dev, ret, - "failed to enable vpcie3v3 regulator\n"); + goto err_pwrctrl_off; ret = rockchip_pcie_phy_init(rockchip); if (ret) - return dev_err_probe(dev, ret, - "failed to initialize the phy\n"); + goto err_pwrctrl_off; ret = reset_control_deassert(rockchip->rst); if (ret) @@ -883,6 +901,12 @@ static int rockchip_pcie_probe(struct platform_device *pdev) clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); deinit_phy: rockchip_pcie_phy_deinit(rockchip); +err_pwrctrl_off: + if (data->mode == DW_PCIE_RC_TYPE) { + pci_pwrctrl_power_off_devices(dev); + if (ret != -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(dev); + } return ret; } -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] PCI: dw-rockchip: Power on devices below the RC using pwrctrl 2026-10-29 2:40 ` Shawn Lin (?) @ 2026-10-29 2:46 ` sashiko-bot -1 siblings, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-10-29 2:46 UTC (permalink / raw) To: Shawn Lin; +Cc: linux-pci > Devices below the Rockchip PCIe host controller may need resources > (regulators, clocks) enabled before they can be detected on the bus. So > far the driver only enabled a single vpcie3v3 supply described by the > controller node itself, which cannot express per-device or per-slot > supplies. > > Use the PCI pwrctrl framework: before initializing the PHY, create the > pwrctrl devices for the DT nodes below the controller and power them on. > The supplies of the slot must be up before PHY init, so this has to run > ahead of rockchip_pcie_phy_init(). > > The controller node supply is kept for backward compatibility: boards > that still describe vpcie3v3 on the controller keep working, and boards > that move the supply into a child node get it enabled by pwrctrl. > > Only the RC mode is affected, the endpoint does not own the supplies of > the devices below it. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Sashiko has reviewed this patch and found no issues. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261029024006.3483210-1-shawn.lin@rock-chips.com?part=1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply 2026-10-29 2:40 ` Shawn Lin @ 2026-10-29 2:40 ` Shawn Lin -1 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin Move the vpcie3v3 supply of the PCIe3x4 controller into a child node describing the slot, so that the PCI pwrctrl framework manages it. The child node is modelled as a PCI bridge, which is what dtc expects for a node below a PCI host bridge, and carries the regulator that powers the devices in the slot. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- (no changes since v1) arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 8969b56f3063..80eb36e783e0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -569,8 +569,20 @@ &pcie3x4 { pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; + + pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x000000 0x0 0x0 0x0 0x0>; + bus-range = <0x00 0x0f>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + vpcie3v3-supply = <&vcc3v3_pcie30>; + }; }; &pd_gpu { -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply @ 2026-10-29 2:40 ` Shawn Lin 0 siblings, 0 replies; 8+ messages in thread From: Shawn Lin @ 2026-10-29 2:40 UTC (permalink / raw) To: Bjorn Helgaas, Manivannan Sadhasivam, Heiko Stuebner Cc: linux-pci, linux-rockchip, Shawn Lin Move the vpcie3v3 supply of the PCIe3x4 controller into a child node describing the slot, so that the PCI pwrctrl framework manages it. The child node is modelled as a PCI bridge, which is what dtc expects for a node below a PCI host bridge, and carries the regulator that powers the devices in the slot. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- (no changes since v1) arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 8969b56f3063..80eb36e783e0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -569,8 +569,20 @@ &pcie3x4 { pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; + + pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x000000 0x0 0x0 0x0 0x0>; + bus-range = <0x00 0x0f>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + vpcie3v3-supply = <&vcc3v3_pcie30>; + }; }; &pd_gpu { -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply 2026-10-29 2:40 ` Shawn Lin (?) @ 2026-10-29 2:49 ` sashiko-bot -1 siblings, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-10-29 2:49 UTC (permalink / raw) To: Shawn Lin; +Cc: linux-pci > Move the vpcie3v3 supply of the PCIe3x4 controller into a child node > describing the slot, so that the PCI pwrctrl framework manages it. > > The child node is modelled as a PCI bridge, which is what dtc expects > for a node below a PCI host bridge, and carries the regulator that > powers the devices in the slot. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Sashiko has reviewed this patch and found no issues. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261029024006.3483210-1-shawn.lin@rock-chips.com?part=2 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-10-29 2:49 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-29 2:40 [PATCH v2 0/2] Manage the PCIe supplies with pwrctrl Shawn Lin 2026-10-29 2:40 ` Shawn Lin 2026-10-29 2:40 ` [PATCH v2 1/2] PCI: dw-rockchip: Power on devices below the RC using pwrctrl Shawn Lin 2026-10-29 2:40 ` Shawn Lin 2026-10-29 2:46 ` sashiko-bot 2026-10-29 2:40 ` [PATCH v2 2/2] arm64: dts: rockchip: rk3588-evb1: describe the PCIe3x4 slot supply Shawn Lin 2026-10-29 2:40 ` Shawn Lin 2026-10-29 2:49 ` sashiko-bot
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