* [PATCH v5 0/2] Add PCIe support for Qualcomm Nord platform
@ 2026-10-29 6:10 ` Krishna Chaitanya Chundru
0 siblings, 0 replies; 8+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-29 6:10 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, shengchao.guo, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-pci,
Krzysztof Kozlowski, Konrad Dybcio
This series adds PCIe support for the Qualcomm Nord (SA8797P) platform.
Nord has a single Gen5-capable QMP PCIe PHY block split into four
independently-clocked and independently-resettable ports (A/B/C/D).
Firmware selects the active lane topology at boot via a TCSR
configuration register, and the same PHY block can appear as a single
x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This
is similar in spirit to the Glymur multi-PHY support already posted,
except Nord's PHY registers are programmed by Linux rather than by
firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init
tables along with the power-up/power-down/soft-reset sequencing needed
to bring each port up.
The series also documents and wires up the qcom,nord-pcie compatible
(reusing the existing SA8775P PCIe controller binding), and adds a
CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing
convergence issue in the PCIe power domain.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kwilczynski@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Bjorn Andersson <andersson@kernel.org>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: shengchao.guo@oss.qualcomm.com
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: shengchao.guo@oss.qualcomm.com
---
Changes in v5:
- Rebased to the tip and removed already applied patches.
- Link to v4: https://patch.msgid.link/20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com
Changes in v4:
- Couple of nits in dt binding & phy driver (shawn, Mani)
- Add proper description for link-mode & phy-cells
- Remove soc node and address cells from example (Mani)
- change cgc_dis_workaround to disable_cgc (Mani)
- Split common changes and nord changes (Mani)
- Link to v3: https://patch.msgid.link/20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com
Changes in v3:
- change the name to quadfurcated phy (Konrad).
- remove min items and change clocks order (Krzysztof).
- Factor out the common config and create overlays & try to use common
symbols for glymur and nord (Konrad).
- create qphy_setbit and qphy_clrbit (Qiang Yu).
- and in qmp_pcie_exit() apply settings only when nocsr is present (Qiang Yu).
- Link to v2: https://patch.msgid.link/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com
Changes in v2:
- Fix dtbinding errors (Krzysztof)
- Link to v1: https://patch.msgid.link/20260825-nord-v1-0-7c02f2b8765a@oss.qualcomm.com
---
Krishna Chaitanya Chundru (2):
dt-bindings: pci: qcom: add Nord PCIe controller compatible
PCI: qcom: Add Nord PCIe controller support
.../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
---
base-commit: c339f4010dea8b0d754f84ace70cd1b089878ef8
change-id: 20260810-nord-461809f1d5ae
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v5 1/2] dt-bindings: pci: qcom: add Nord PCIe controller compatible
2026-10-29 6:10 ` Krishna Chaitanya Chundru
@ 2026-10-29 6:10 ` Krishna Chaitanya Chundru
-1 siblings, 0 replies; 8+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-29 6:10 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, shengchao.guo, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-pci,
Krzysztof Kozlowski
Add the qcom,nord-pcie compatible string to the Qualcomm PCIe
controller binding.
The Nord PCIe controller is compatible with the SA8775P PCIe
controller implementation and reuses the same binding definition.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 63630a814f28..b8ba2c4449b7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -20,6 +20,7 @@ properties:
- const: qcom,pcie-sa8775p
- items:
- enum:
+ - qcom,nord-pcie
- qcom,pcie-qcs8300
- const: qcom,pcie-sa8775p
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 1/2] dt-bindings: pci: qcom: add Nord PCIe controller compatible
@ 2026-10-29 6:10 ` Krishna Chaitanya Chundru
0 siblings, 0 replies; 8+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-29 6:10 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, shengchao.guo, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-pci,
Krzysztof Kozlowski
Add the qcom,nord-pcie compatible string to the Qualcomm PCIe
controller binding.
The Nord PCIe controller is compatible with the SA8775P PCIe
controller implementation and reuses the same binding definition.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 63630a814f28..b8ba2c4449b7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -20,6 +20,7 @@ properties:
- const: qcom,pcie-sa8775p
- items:
- enum:
+ - qcom,nord-pcie
- qcom,pcie-qcs8300
- const: qcom,pcie-sa8775p
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 1/2] dt-bindings: pci: qcom: add Nord PCIe controller compatible
2026-10-29 6:10 ` Krishna Chaitanya Chundru
(?)
@ 2026-10-29 6:12 ` sashiko-bot
-1 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-10-29 6:12 UTC (permalink / raw)
To: Krishna Chaitanya Chundru; +Cc: linux-pci
> Add the qcom,nord-pcie compatible string to the Qualcomm PCIe
> controller binding.
>
> The Nord PCIe controller is compatible with the SA8775P PCIe
> controller implementation and reuses the same binding definition.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-nord-v5-0-1a13c214e89d@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 2/2] PCI: qcom: Add Nord PCIe controller support
2026-10-29 6:10 ` Krishna Chaitanya Chundru
@ 2026-10-29 6:10 ` Krishna Chaitanya Chundru
-1 siblings, 0 replies; 8+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-29 6:10 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, shengchao.guo, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-pci, Konrad Dybcio
Add the Nord PCIe controller configuration and the platform-specific
settings required for correct operation.
Nord requires the NO_SNOOP override and L0s to be disabled. It also
requires a clock-gating-control (CGC) workaround to address a PCIe
power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and
AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
The SLV_ACLK_CGC_DIS bit is already configured by hardware reset.
This behavior is documented in the private QCTDD11972446 erratum,
which is not publicly available.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d903f10211c2..c62abfc7a446 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -300,6 +300,7 @@ struct qcom_pcie_cfg {
bool override_no_snoop;
bool firmware_managed;
bool no_l0s;
+ bool disable_cgc;
};
struct qcom_pcie_perst {
@@ -1138,11 +1139,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
+ u32 val;
if (pcie_cfg->override_no_snoop)
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
+ if (pcie_cfg->disable_cgc) {
+ val = readl(pcie->parf + PARF_SYS_CTRL);
+ val |= CORE_CLK_CGC_DIS | AUX_PWR_DET;
+ writel(val, pcie->parf + PARF_SYS_CTRL);
+ }
+
qcom_pcie_set_slot_cap(pcie->pci);
qcom_pcie_init_outbound_blocker(pcie);
@@ -1725,6 +1733,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
.ops = &ops_2_9_0,
};
+static const struct qcom_pcie_cfg cfg_nord = {
+ .ops = &ops_1_9_0,
+ .override_no_snoop = true,
+ .no_l0s = true,
+ .disable_cgc = true,
+};
+
static const struct qcom_pcie_cfg cfg_sc8280xp = {
.ops = &ops_1_21_0,
.no_l0s = true,
@@ -2586,6 +2601,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,nord-pcie", .data = &cfg_nord },
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 2/2] PCI: qcom: Add Nord PCIe controller support
@ 2026-10-29 6:10 ` Krishna Chaitanya Chundru
0 siblings, 0 replies; 8+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-29 6:10 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Bjorn Helgaas, Bjorn Andersson,
Maxime Chevallier, Philipp Zabel
Cc: Krishna Chaitanya Chundru, shengchao.guo, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-pci, Konrad Dybcio
Add the Nord PCIe controller configuration and the platform-specific
settings required for correct operation.
Nord requires the NO_SNOOP override and L0s to be disabled. It also
requires a clock-gating-control (CGC) workaround to address a PCIe
power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and
AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
The SLV_ACLK_CGC_DIS bit is already configured by hardware reset.
This behavior is documented in the private QCTDD11972446 erratum,
which is not publicly available.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d903f10211c2..c62abfc7a446 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -300,6 +300,7 @@ struct qcom_pcie_cfg {
bool override_no_snoop;
bool firmware_managed;
bool no_l0s;
+ bool disable_cgc;
};
struct qcom_pcie_perst {
@@ -1138,11 +1139,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
+ u32 val;
if (pcie_cfg->override_no_snoop)
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
+ if (pcie_cfg->disable_cgc) {
+ val = readl(pcie->parf + PARF_SYS_CTRL);
+ val |= CORE_CLK_CGC_DIS | AUX_PWR_DET;
+ writel(val, pcie->parf + PARF_SYS_CTRL);
+ }
+
qcom_pcie_set_slot_cap(pcie->pci);
qcom_pcie_init_outbound_blocker(pcie);
@@ -1725,6 +1733,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
.ops = &ops_2_9_0,
};
+static const struct qcom_pcie_cfg cfg_nord = {
+ .ops = &ops_1_9_0,
+ .override_no_snoop = true,
+ .no_l0s = true,
+ .disable_cgc = true,
+};
+
static const struct qcom_pcie_cfg cfg_sc8280xp = {
.ops = &ops_1_21_0,
.no_l0s = true,
@@ -2586,6 +2601,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,nord-pcie", .data = &cfg_nord },
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 2/2] PCI: qcom: Add Nord PCIe controller support
2026-10-29 6:10 ` Krishna Chaitanya Chundru
(?)
@ 2026-10-29 6:13 ` sashiko-bot
-1 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-10-29 6:13 UTC (permalink / raw)
To: Krishna Chaitanya Chundru; +Cc: linux-pci
> Add the Nord PCIe controller configuration and the platform-specific
> settings required for correct operation.
>
> Nord requires the NO_SNOOP override and L0s to be disabled. It also
> requires a clock-gating-control (CGC) workaround to address a PCIe
> power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and
> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
> The SLV_ACLK_CGC_DIS bit is already configured by hardware reset.
>
> This behavior is documented in the private QCTDD11972446 erratum,
> which is not publicly available.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-nord-v5-0-1a13c214e89d@oss.qualcomm.com?part=2
^ permalink raw reply [flat|nested] 8+ messages in thread