Re: [PATCH 09/12] pinctrl: airoha: an7583: use force GPIO mode for GPIO requests

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] pinctrl: airoha: an7583: hsuart and hsuart_cts_rts mux
  conflict
- [Low] pinctrl: airoha: an7583: redundant regmap[2] in PWM_EXT_SEC and
  unused macros
--

commit f7d089a2abc89c3f0877be6d6eb92f87952452c6
Author: Zhengping Zhang <zhengping.zhang@airoha.com>

pinctrl: airoha: an7583: use force GPIO mode for GPIO requests

This commit enables per-pad force GPIO overrides, shared GPIO request
handling, and mux conflict checking on AN7583, while updating peripheral,
PWM, and PON pinmux groups accordingly.

> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> index 74628a03ca909..e2f629d9d43cd 100644
> --- a/drivers/pinctrl/airoha/pinctrl-an7583.c
> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c

[ ... ]

> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val, force_reg, force_mask) \
>  	{							\
>  		.name = (gpio),					\
>  		.regmap[0] = {					\
> @@ -299,10 +308,14 @@
>  			(smux_val),				\
>  			(smux_val)				\
>  		},						\
> -		.regmap_size = 2,				\
> +		.regmap[2] = {					\
> +			AIROHA_FUNC_MUX, (force_reg),		\
> +			(force_mask), (force_mask)			\
> +		},						\
> +		.regmap_size = 3,				\
>  	}

[Severity: Low]
This isn't a bug, but AIROHA_PINCTRL_PWM_EXT_SEC() already sets the
per-pad GPIO selector bit (smux_val) in REG_GPIO_PON_MODE via regmap[1],
and all 13 callers (gpio39 through gpio51 in pwm_func_group) pass 0 for
force_mask, making regmap[2] a no-op entry.  In addition, replacing the
entries in gpio_func_group with AN7583_GPIO_GROUP() leaves
AIROHA_PINCTRL_GPIO() and AIROHA_PINCTRL_GPIO_EXT() unused.

[ ... ]

> @@ -745,7 +840,14 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
>  			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>  			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>  		},
> -		.regmap_size = 1,
> +		.regmap[1] = {
> +			AIROHA_FUNC_MUX,
> +			REG_FORCE_GPIO_EN,
> +			BIT(30) |
> +			BIT(31),
> +			0
> +		},
> +		.regmap_size = 2,
>  	}, {
>  		.name = "hsuart",
>  		.regmap[0] = {
> @@ -754,7 +856,14 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
>  			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>  			GPIO_HSUART_MODE_MASK
>  		},
> -		.regmap_size = 1,
> +		.regmap[1] = {
> +			AIROHA_FUNC_MUX,
> +			REG_FORCE_GPIO_EN,
> +			BIT(28) |
> +			BIT(29),
> +			0
> +		},
> +		.regmap_size = 2,
>  	},
>  	{
>  		.name = "hsuart_cts_rts",
> @@ -764,7 +873,14 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
>  			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>  			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>  		},
> -		.regmap_size = 1,
> +		.regmap[1] = {
> +			AIROHA_FUNC_MUX,
> +			REG_FORCE_GPIO_EN,
> +			BIT(26) |
> +			BIT(27),
> +			0
> +		},
> +		.regmap_size = 2,
>  	}, {

[Severity: Medium]
Does enabling check_mux_conflicts in pinctrl_match_data cause selecting
both "hsuart" and "hsuart_cts_rts" to fail with -EBUSY?

On AN7583, hsuart_pins covers only the TX/RX pins (30 and 31) and
hsuart_cts_rts_pins covers only the CTS/RTS pins (28 and 29), and their
regmap[1] entries clear the force-GPIO bits for those disjoint pin sets
(BIT(28) | BIT(29) vs BIT(26) | BIT(27)).  Enabling HSUART with flow
control therefore requires selecting both groups, just like "uart2" and
"uart2_cts_rts".  However, unlike "uart2" (whose regmap[0].mask is only
GPIO_UART2_MODE_MASK), "hsuart" includes GPIO_HSUART_CTS_RTS_MODE_MASK in
regmap[0].mask with value 0 while "hsuart_cts_rts" sets that bit to 1, so
airoha_pinmux_check_conflicts() rejects combining them.  Conversely,
selecting "hsuart_cts_rts" alone leaves the TX/RX pins unclaimed and their
force-GPIO overrides (BIT(28) | BIT(29)) uncleared.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110094339.749110-1-zhengping.zhang@airoha.com?part=9