Re: [PATCH 2/3] drm/msm/mdss: reset all block resets described in DT

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] drm/msm/mdss: inaccurate INT2 reset description in commit
  message
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commit 216edbc98463c8e657023589d0ec19367667e829
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

drm/msm/mdss: reset all block resets described in DT

This commit switches msm_mdss_reset() to devm_reset_control_array_get() so
that all resets listed in the MDSS device node are asserted and released
together.

>     msm_mdss_reset() acquires only the first reset listed in the MDSS
>     device node.  Platforms can describe more than one MDSS block reset: the
>     SM8750 display clock controller also provides a reset for the MDSS core
>     INT2 interrupt controller, which is left out of reset when the
>     bootloader hands over with the display block still running.

[Severity: Low]
As reported by Dmitry Baryshkov on v3 [1], is the commit message accurate
about DISP_CC_MDSS_CORE_INT2_BCR being an interrupt controller reset, and
what is the side effect of leaving it out of reset?

In drivers/clk/qcom/dispcc-sm8750.c, DISP_CC_MDSS_CORE_INT2_BCR at offset
0xa000 is the block reset for the second MDSS core clock and GDSC domain
(mdss_int2_gdsc and the disp_cc_mdss_*1_clk clocks), rather than an
interrupt controller.  The commit message of the follow-up device tree
patch in this series was updated in v4 to describe the second MDSS core
domain and the cold-boot symptom, but this commit message was left
unchanged.

[1] https://lore.kernel.org/r/awb7bslhrhemsgvu7ubaejvurk6fecotgvqlwtvsoe2benqdgq@tvh2sfjbuzyu

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Sashiko AI review · https://sashiko.dev/#/patchset/20261113155635.1677541-1-xiaqinghuan@mail.ustc.edu.cn?part=2