Re: [PATCH 1/3] dt-bindings: display: msm: mdss-common: describe additional block resets

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: display: msm: misdescribed MDSS_CORE_INT2 reset in
  mdss-common
--

commit 0f5d0a5d3c7e47f59b13ac8f16fb077159d613cd
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

dt-bindings: display: msm: mdss-common: describe additional block resets

This commit updates the MDSS common Device Tree binding and the SM8750 MDSS
example to allow a second reset for the MDSS hardware block.

> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> index c6305a6e03346..51ef4cc74e818 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> @@ -84,8 +84,10 @@ properties:
>            - const: cpu-cfg
>  
>    resets:
> +    minItems: 1
>      items:
> -      - description: MDSS_CORE reset
> +      - description: MDSS core reset
> +      - description: MDSS core INT2 interrupt controller reset

[Severity: Low]
Is "MDSS core INT2 interrupt controller reset" an accurate description of
this reset (and in the commit message)?

In drivers/clk/qcom/dispcc-sm8750.c (and sibling Qualcomm DISP_CC drivers),
DISP_CC_MDSS_CORE_INT2_BCR at 0xa000 is paired with MDSS_INT2_GDSC at 0xb000
and resets the secondary internal MDSS core clock domain
(disp_cc_mdss_mdp1_clk, disp_cc_mdss_mdp_lut1_clk, disp_cc_mdss_vsync1_clk,
and disp_cc_mdss_ahb1_clk), rather than an interrupt controller.  The MDSS
top-level interrupt status register (HW_INTR_STATUS) is part of the primary
MDSS core MMIO space.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261113155635.1677541-1-xiaqinghuan@mail.ustc.edu.cn?part=1